summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: c1f4345)
raw | patch | inline | side by side (parent: c1f4345)
author | Tinku Mannan <tmannan@ti.com> | |
Tue, 7 Jan 2014 19:18:28 +0000 (14:18 -0500) | ||
committer | Tinku Mannan <tmannan@ti.com> | |
Tue, 7 Jan 2014 19:18:28 +0000 (14:18 -0500) |
12 files changed:
index 8a34d461251d6224d209d3bc967bc306fca807c7..78f24ad60cec574e70414eda2bb41acf97cdbee9 100755 (executable)
CSL_NETCP_CFG_REGS,
CSL_NETCP_CFG_SA_CFG_REGS,
CSL_QMSS_CFG_BASE,
+ CSL_QMSS_DATA_BASE,
NWAL_PA_NUM_CPPI_RX_CHANNELS_NSS_GEN1,
NWAL_PA_NUM_CPPI_TX_CHANNELS_NSS_GEN1
};
index 8ef386f38deab16618187bdc3a221eafd93398c8..3aedcc5f24d6d7bf2d25203ca1d1d6e92c7dec97 100755 (executable)
CSL_NETCP_CFG_REGS,
CSL_NETCP_CFG_SA_CFG_REGS,
CSL_QMSS_CFG_BASE,
+ CSL_QMSS_DATA_BASE,
NWAL_PA_NUM_CPPI_RX_CHANNELS_NSS_GEN2,
NWAL_PA_NUM_CPPI_TX_CHANNELS_NSS_GEN2
};
index 02cf34b54e9f2dde981ddd7165abf9165fb5d4ef..4ee14989d12c994c6a17209fd903292378e2ce62 100755 (executable)
CSL_NETCP_CFG_REGS,
CSL_NETCP_CFG_SA_CFG_REGS,
CSL_QMSS_CFG_BASE,
+ CSL_QMSS_DATA_BASE,
NWAL_PA_NUM_CPPI_RX_CHANNELS_NSS_GEN1,
NWAL_PA_NUM_CPPI_TX_CHANNELS_NSS_GEN1
};
index c1ec5709eb43d8e394da430b9f46d346abaa3bb1..9f448d1e25a5b206802fc867a577a5033e2a7f37 100755 (executable)
CSL_NETCP_CFG_REGS,
CSL_NETCP_CFG_SA_CFG_REGS,
CSL_QMSS_CFG_BASE,
+ CSL_QMSS_DATA_BASE,
NWAL_PA_NUM_CPPI_RX_CHANNELS_NSS_GEN1,
NWAL_PA_NUM_CPPI_TX_CHANNELS_NSS_GEN1
index 8b809dd3912e3e8d471b081764bff7f183ae7bf9..8a0ed8ee281e6ef0535d022eeb57a8cd8d24913e 100755 (executable)
CSL_NETCP_CFG_REGS,
CSL_NETCP_CFG_SA_CFG_REGS,
CSL_QMSS_CFG_BASE,
+ CSL_QMSS_DATA_BASE,
NWAL_PA_NUM_CPPI_RX_CHANNELS_NSS_GEN2,
NWAL_PA_NUM_CPPI_TX_CHANNELS_NSS_GEN2
diff --git a/ti/drv/nwal/nwal.h b/ti/drv/nwal/nwal.h
index bac67170b8751960941ebedcd7104cad9d47f9c2..03a5e155bd547cfa76c6c0bcb6857d5758fee5de 100755 (executable)
--- a/ti/drv/nwal/nwal.h
+++ b/ti/drv/nwal/nwal.h
uint32_t cslPscLpscSA; /**< PSC LPSC Module Assignment for SASS */
uint32_t cslNetCpCfgRegs; /**< Base address of NETCP configuration Registers */
uint32_t cslNetCpCfgSaCfgRegs; /**< Base address of SASS configuration Registers */
- uint32_t cslQMssCfgBase; /**< Base address of QMSS configuration Registers */
+ uint32_t cslQmssCfgBase; /**< Base address of QMSS configuration Registers */
+ uint32_t cslQmssDataBase; /**< Base address of QMSS Data Registers */
uint32_t cppiMaxNumRxCpdmaChan; /**< Maximum number of RX CPDMA channels */
uint32_t cppiMaxNumTxCpdmaChan; /**< Maximum number of TX CPDMA channels */
} nwalGlobalDeviceConfigParams_t;
index 956411d0e20c2a3d0e5c8905ca1a5e9d538440e3..08cff66be8dc88dedef1d4fe0d9d6dcc72bcae89 100755 (executable)
--- a/ti/drv/nwal/nwal_util.h
+++ b/ti/drv/nwal/nwal_util.h
/**
* @ingroup nwal_fast_send_macros
- * @brief nwal_mCmdSetL4CkSumCrypPort Update L4 checksum,Crypto and
+ * @brief nwal_mCmdSetL4CkSumCrypPort2 Update L4 checksum,Crypto and
* outgoing EMAC port to NetCP command for Network Subsystem 2
*
* @details Inline macro API can be used to do dynamic update for Crypto
diff --git a/ti/drv/nwal/src/nwal.c b/ti/drv/nwal/src/nwal.c
index 8237db47c5827d1906f8e2add20e0bf079da5d5e..0f61c9214b09b46cf0a71ad74efcf1b4bb1f9d6f 100755 (executable)
--- a/ti/drv/nwal/src/nwal.c
+++ b/ti/drv/nwal/src/nwal.c
return (nwal_ERR_INVALID_PARAM);
}
- pLocContext->transInfo.transId = transId;
- retVal = nwal_prepCmdBuf(pIhandle,
- &cmdSize,
- &cmdReply,
- &pLocContext->transInfo,
- &pHd);
- if(retVal != nwal_OK)
- {
- return retVal;
- }
+
if(pIhandle->cfg.pDeviceCfg->nssGen == NWAL_CFG_NSS_GEN2)
{
else
{
int cmdDest;
+ pLocContext->transInfo.transId = transId;
+ retVal = nwal_prepCmdBuf(pIhandle,
+ &cmdSize,
+ &cmdReply,
+ &pLocContext->transInfo,
+ &pHd);
+ if(retVal != nwal_OK)
+ {
+ return retVal;
+ }
netCPRet = Pa_requestStats (pIhandle->memSizeInfo.pahandle,
doClear,
(paCmd_t) pHd->buffPtr,
diff --git a/ti/drv/nwal/test/common/armv7/linux/fw_main.c b/ti/drv/nwal/test/common/armv7/linux/fw_main.c
index 44f32e4e495f115944bd958d2665a68f062d3eea..379f3608fba8f99f3f3fc18bf4b015aea9b0142a 100755 (executable)
#include <pthread.h>
#include <string.h>
+#if defined(DEVICE_K2H)
+#include <ti/runtime/hplib/device/k2h/src/hplib_device.c>
+#elif defined (DEVICE_K2K)
+#include <ti/runtime/hplib/device/k2k/src/hplib_device.c>
+#elif defined (DEVICE_K2L)
+#include <ti/runtime/hplib/device/k2l/src/hplib_device.c>
+#elif defined (DEVICE_K2E)
+#include <ti/runtime/hplib/device/k2e/src/hplib_device.c>
+#else /*Default */
+#include <ti/runtime/hplib/device/k1/src/hplib_device.c>
+#endif /* Device */
extern void *nwalTest(void *args);
void topLevelTest (void);
diff --git a/ti/drv/nwal/test/common/armv7/linux/pdkv2/fw_pdk.c b/ti/drv/nwal/test/common/armv7/linux/pdkv2/fw_pdk.c
index ec8e4b413801b82f54e490fbd6e6af9e894fa35f..f611e9b64e6a588bf80d4c121b6c4e7df4b68ae8 100755 (executable)
#include <ti/drv/cppi/device/k2h/src/cppi_device.c>
#endif /* Device */
+extern nwalGlobalDeviceConfigParams_t nwalDeviceGblCfgParam;
/* Global variables to hold virtual address of various subsystems */
extern void *fw_qmssCfgVaddr;
for (i=0; i<CPPI_MAX_CPDMA; i++)
fw_cppiGblCfgParams[i] = cppiGblCfgParams[i];
- /* SRIO CPDMA regs */
- fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CONFIG_REGS,
- (uint32_t)fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs);
-
- fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CONFIG_REGS,
- (uint32_t)fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs);
-
- fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CONFIG_REGS,
- (uint32_t)fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs);
-
- fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CONFIG_REGS,
- (uint32_t)fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs);
-
- fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CONFIG_REGS,
- (uint32_t)fw_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs);
-
/* PASS CPDMA regs */
fw_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
FW_GET_REG_VADDR(fw_netcpCfgVaddr,
diff --git a/ti/drv/nwal/test/common/armv7/linux/pdkv3/fw_pdk.c b/ti/drv/nwal/test/common/armv7/linux/pdkv3/fw_pdk.c
index d3fd23eba3bbf9e24763ade7c2158face617e30d..78e7572f1ce16a96fe7df4123800683ac60a7204 100755 (executable)
fw_cppiGblCfgParams = cppiGblCfgParams;
/* Convert Physical address to Virtual address for LLD access */
- /* SRIO CPDMA regs */
- fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CFG_REGS,
- (uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs);
-
- fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txChRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CFG_REGS,
- (uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txChRegs);
-
- fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CFG_REGS,
- (uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxChRegs);
-
- fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CFG_REGS,
- (uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txSchedRegs);
-
- fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
- FW_GET_REG_VADDR(fw_srioCfgVaddr,
- CSL_SRIO_CFG_REGS,
- (uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs);
-
/* PASS CPDMA regs */
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
FW_GET_REG_VADDR(fw_netcpCfgVaddr,
- CSL_NETCP_CFG_REGS,
+ //CSL_NETCP_CFG_REGS,
+ nwalDeviceGblCfgParam.cslNetCpCfgRegs,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].gblCfgRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txChRegs =
FW_GET_REG_VADDR(fw_netcpCfgVaddr,
- CSL_NETCP_CFG_REGS,
+ nwalDeviceGblCfgParam.cslNetCpCfgRegs,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txChRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxChRegs =
FW_GET_REG_VADDR(fw_netcpCfgVaddr,
- CSL_NETCP_CFG_REGS,
+ nwalDeviceGblCfgParam.cslNetCpCfgRegs,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxChRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
FW_GET_REG_VADDR(fw_netcpCfgVaddr,
- CSL_NETCP_CFG_REGS,
+ nwalDeviceGblCfgParam.cslNetCpCfgRegs,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txSchedRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
FW_GET_REG_VADDR(fw_netcpCfgVaddr,
- CSL_NETCP_CFG_REGS,
+ nwalDeviceGblCfgParam.cslNetCpCfgRegs,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxFlowRegs);
/* QMSS CPDMA regs */
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- QMSS_CFG_BASE_ADDR,
+ //CSL_QMSS_CFG_BASE,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txChRegs =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- QMSS_CFG_BASE_ADDR,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txChRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- QMSS_CFG_BASE_ADDR,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxChRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- QMSS_CFG_BASE_ADDR,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txSchedRegs);
fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- QMSS_CFG_BASE_ADDR,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs);
result = Cppi_init (&fw_cppiGblCfgParams);
if (result != CPPI_SOK) {
fw_qmssGblCfgParams.groupRegs[count].qmConfigReg =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmConfigReg);
fw_qmssGblCfgParams.groupRegs[count].qmDescReg =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmDescReg);
fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtReg =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtReg);
fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyReg =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyReg);
fw_qmssGblCfgParams.groupRegs[count].qmQueStatReg =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmQueStatReg);
fw_qmssGblCfgParams.groupRegs[count].qmStatusRAM =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmStatusRAM);
fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtDataReg =
FW_GET_REG_VADDR(fw_qmssDataVaddr,
- QMSS_DATA_BASE_ADDR,
+ nwalDeviceGblCfgParam.cslQmssDataBase,
(uint32_t)fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtDataReg);
fw_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyDataReg = NULL;
{
fw_qmssGblCfgParams.regs.qmQueIntdReg[count] =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.regs.qmQueIntdReg[count]);
}
{
fw_qmssGblCfgParams.regs.qmPdspCmdReg[count] =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.regs.qmPdspCmdReg[count]);
fw_qmssGblCfgParams.regs.qmPdspCtrlReg[count] =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.regs.qmPdspCtrlReg[count]);
fw_qmssGblCfgParams.regs.qmPdspIRamReg[count] =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.regs.qmPdspIRamReg[count]);
}
fw_qmssGblCfgParams.regs.qmLinkingRAMReg =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.regs.qmLinkingRAMReg);
fw_qmssGblCfgParams.regs.qmBaseAddr =
FW_GET_REG_VADDR(fw_qmssCfgVaddr,
- nwalDeviceGblCfgParam.cslQMssCfgBase,
+ nwalDeviceGblCfgParam.cslQmssCfgBase,
(uint32_t)fw_qmssGblCfgParams.regs.qmBaseAddr);
result = Qmss_init (&qmssInitConfig, &fw_qmssGblCfgParams);
index 70a971c5091ffd3a1aa965aae6cb8f4ec9ca0489..fa90d5d876dbe0004df5d3c5196a0815228c4e4b 100755 (executable)
#endif
memset(&testNwGlobContext.paStats,0,sizeof(paSysStats_t));
nwal_getPAStats(testNwGlobContext.nwalInstHandle,
- NULL,
+ NWAL_TRANSID_SPIN_WAIT,
&testNwGlobContext.paStats,
0);
testNWALCmdDispPaStats();