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raw | patch | inline | side by side (parent: 276c330)
raw | patch | inline | side by side (parent: 276c330)
author | Ming Wei <mwei@ti.com> | |
Thu, 27 Jun 2019 15:55:41 +0000 (10:55 -0500) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Mon, 8 Jul 2019 00:55:14 +0000 (19:55 -0500) |
Signed-off-by: Ming Wei <mwei@ti.com>
index 4d0eb04cc5e9120e71615a2aa6537a493cf8833d..5fc1309c25a48a4e1325d41f7a83a757f47c6d58 100644 (file)
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
/* Default configurations for DSP core */
CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */
- 0U, /* TBD */
- 0U /* TBD */
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 1 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER1_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 2 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER2_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 3 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER3_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 4 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER4_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 5 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER5_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 6 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER6_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 7 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER7_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 8 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER8_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 9 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER9_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 10 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER10_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 11 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER11_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 12 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER12_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 13 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER13_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 14 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER14_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 15 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER15_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 16 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER16_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 17 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER17_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 18 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER18_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
},
/* Timer ID 19 */
TIMERP_EVENT_NOT_AVAILABLE
#endif
#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
- CSL_TIMER0_CFG_BASE,
- 0U, /* TBD */
- 0U /* TBD */
+ CSL_TIMER19_CFG_BASE,
+ TIMERP_INTR_USER_CONFIGURE, /* User Confugure */
+ TIMERP_EVENT_USER_CONFIGURE /* User Confugure */
#endif
}
};
index afb72e2d35cd4746202f0c970a7ddab3985f2760..cb73869a686f5e2f6e203460a2792165c6fc04d1 100644 (file)
--- a/src/nonos/Nonos_config.h
+++ b/src/nonos/Nonos_config.h
#endif
#define TIMERP_EVENT_NOT_AVAILABLE (-(int32_t) (1u))
+#define TIMERP_INTR_USER_CONFIGURE (-(int32_t) (2u))
+#define TIMERP_EVENT_USER_CONFIGURE (-(int32_t) (3u))
/*
* @brief TimerP Information structure
index 8265bca9a499262a747a9be4d63f46fdca3e7ef2..5d1da5fb5008460c87faf6b6f1d3f09faa715199 100644 (file)
#ifdef __TI_ARM_V7R4__
interruptRegParams->corepacConfig.priority=0x15U; /* Default */
#else
-#ifdef __C7100__
+#if defined(__C7100__) || defined(BUILD_DSP_1) || defined(BUILD_DSP_2)
interruptRegParams->corepacConfig.priority=0x01U; /* Default */
#else
interruptRegParams->corepacConfig.priority=0x20U; /* Default */
index 81432770fb05255474e79c18920c276f432e5934..47c7cebd16607b2114cabd694788ca7863c50191 100755 (executable)
#define OSAL_TEST_TIMER_ID2 (3U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#elif defined (BUILD_C66X_2)
- #define OSAL_TEST_TIMER_ID (1U)
- #define OSAL_TEST_TIMER_ID2 (2U)
+ #define OSAL_TEST_TIMER_ID (2U)
+ #define OSAL_TEST_TIMER_ID2 (3U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#elif defined (BUILD_C7X_1)
#define OSAL_TEST_TIMER_ID (1U)
#if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) || defined(BUILD_C7X_1)
id = OSAL_TEST_TIMER_ID;
#endif
-
volatile int32_t i;
uint32_t prevCount, ctrlBitmap = OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE ;
bool ret = true;
timerParams.periodType = TimerP_PeriodType_MICROSECS;
timerParams.period = OSAL_TEST_TIMER_PERIOD;
+#if defined(SOC_J721E)
#if defined(BUILD_C66X_1)
+ /* the Eevnt 21 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
+ timerParams.eventId = 22;
+ /* the Interrupt 14 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
timerParams.intNum = 15;
OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
#endif
#if defined(BUILD_C66X_2)
- timerParams.intNum = 12;
+ /* the Eevnt 20 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
+ timerParams.eventId = 22;
+ /* the Interrupt 14 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
+ timerParams.intNum = 15;
#endif
#if defined(BUILD_C7X_1)
timerParams.intNum = 15;
OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
#endif
+#endif
#if !defined(SOC_J721E)
#if defined(_TMS320C6X)
* intr_router[12] corresponds to output event #21, which is what we
* set eventId to in .cfg file.
* - bit 16 enables the entry
- * - lower bits define input event (#0 for dmtimer #0)
+ * - lower bits define input event (#1 for dmtimer #0)
+ * intr_router[13] corresponds to output event #22, which is what we
+ * set eventId to in this file.
+ * - bit 16 enables the entry
+ * - lower bits define input event (#3 for dmtimer #2)
*/
#ifdef BUILD_C66X_1
intr_router[12] = 0x00010001;
intr_router[13] = 0x00010003;
#endif
+ /*
+ * intr_router[11] corresponds to output event #20, which is what we
+ * set eventId to in .cfg file.
+ * - bit 16 enables the entry
+ * - lower bits define input event (#1 for dmtimer #0)
+ * intr_router[13] corresponds to output event #22, which is what we
+ * set eventId to in this file.
+ * - bit 16 enables the entry
+ * - lower bits define input event (#3 for dmtimer #2)
+ */
#ifdef BUILD_C66X_2
- intr_router[11] = 0x00010002;
+ intr_router[11] = 0x00010001;
+ intr_router[13] = 0x00010003;
#endif
}
index a27a59a1a94c7d0392c680034d7ad5f4c81e109a..e497fdcaa573a452d478cb29e96e21db7d408086 100755 (executable)
EXTERNAL_LNKCMD_FILE = $(PDK_INSTALL_PATH)/ti/build/j721e/linker_c66.lds
endif
-ifeq ($(CORE),$(filter $(CORE), c7x))
+ifeq ($(CORE),$(filter $(CORE), c7x_1))
# Enable XDC build for application by providing XDC CFG File per core
XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/j721e/sysbios_c7x.cfg
EXTERNAL_LNKCMD_FILE = $(PDK_INSTALL_PATH)/ti/build/j721e/linker_c7x.lds