PRSDK-5246: support SMP mode for application so that appropriate cache includes are...

Signed-off-by: Aravind Batni <aravindbr@ti.com>

diff --git a/package.xs b/package.xs
index 9a3ca1c57112dda23a0ff2e30b867b1d894aee2e..09c57a6f087ddd3ed86b352dfe94779f42c8f98b 100644 (file)
--- a/package.xs
+++ b/package.xs
@@ -128,6 +128,7 @@ function getLibs(prog)
 \r
 function init() {\r
     xdc.loadPackage("ti.csl");\r
+    xdc.loadPackage("ti.sysbios");\r
 }\r
 \r
 /*\r

diff --git a/src/tirtos/CacheP_tirtos.c b/src/tirtos/CacheP_tirtos.c
index 26a1c877791e69e55bfbe6f2b60d36b36f7cbbd2..5282386c4c7ef64fae1dc4f2b4b05c84481d0db1 100644 (file)
--- a/src/tirtos/CacheP_tirtos.c
+++ b/src/tirtos/CacheP_tirtos.c
@@ -35,27 +35,7 @@
 
 #include <ti/osal/CacheP.h>
 #include <ti/sysbios/BIOS.h>
-
-#if defined (SOC_AM335x) 
-#include <ti/sysbios/family/arm/a8/Cache.h>
-#elif defined (SOC_AM437x)
-#include <ti/sysbios/family/arm/a9/Cache.h>
-#elif defined (__ARM_ARCH_7A__)
-#include <ti/sysbios/family/arm/a15/Cache.h>
-#elif defined (__TI_ARM_V7M4__)
-#include <ti/sysbios/hal/unicache/Cache.h>
-#elif defined (__TI_ARM_V7R4__)
-#include <ti/sysbios/family/arm/v7r/Cache.h>
-#elif defined (__TI_ARM_V5__)  
-#include <ti/sysbios/family/arm/arm9/Cache.h>
-#elif defined (_TMS320C6X) && !(defined (SOC_OMAPL137) || defined (SOC_OMAPL138))
-#include <ti/sysbios/family/c66/Cache.h>
-#elif defined(__aarch64__)
-#include <ti/sysbios/family/arm/v8a/Cache.h>
-#else
 #include <ti/sysbios/hal/Cache.h>
-#endif
-
 
 void CacheP_wb(const void * addr, int32_t size)
 {