index 007ec0a982d1b6294df4cca5e258fad26c86895d..b79a304229912568c86293b90d9c566e92b2204d 100644 (file)
--- a/pa.h
+++ b/pa.h
#include <stdint.h>
#include <stdlib.h>
+/*
+ * Shut off: remark #880-D: parameter "descType" was never referenced
+ *
+ * This is better than removing the argument since removal would break
+ * backwards compatibility
+ */
+#ifdef _TMS320C6X
+#pragma diag_suppress 880
+#pragma diag_suppress 681
+#elif defined(__GNUC__)
+/* Same for GCC:
+ * warning: unused parameter descType [-Wunused-parameter]
+ * expectation is all these catch up with some other intelligent
+ * tools like coverity, Klocwork etc, instead of dump GNU
+ * warnings
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wmaybe-uninitialized"
+#endif
+
+
#include <ti/drv/pa/paver.h>
/* ============================================================= */
* @brief Packet Accelerator (PA) sub-system LLD API and Data Definitions
*
* ============================================================================
- * Copyright (c) Texas Instruments Incorporated 2009-2013
+ * Copyright (c) Texas Instruments Incorporated 2009-2014
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* provides the following functionalities:
* - Ethernet and SRIO packet classification
* - Stateless L3/L4 Firewall (ACL)
- * - Outer and inner IP packet classification
+ * - Outer and Inner IP packet classification
+ * - Ethernet OAM classification
* - Outer and inner IP reassembly
* - TCP/UDP/GTPU based LUT2 classification
* - IPv4 and TCP/UDP checksum generation and verification
* can also be routed between PASS and SASS (Security Accelerator sub-system) multiple times to perform encryption,
* decryption and authentication operation.
* - Ingress 0 (2 PDSPs and 2 256-entry LUT1 engines):
- * - PDSP0 and LUT1_0: SRIO/MAC header parsing and classification
- * - PDSP1 and LUT1_1: L3/L4 header parsing and pre-IPSEC firewall (ACL) lookup
+ * - PDSP0 and LUT1_0: SRIO/MAC header parsing and classification
+ * - PDSP1 and LUT1_1 (normal mode): L3/L4 header parsing and pre-IPSEC firewall (ACL) lookup
+ * - PDSP1 and LUT1_1 (Eoam mode): L2 header parsing and Ethernet OAM lookup.
* - Ingress 1 (2 PDSPs and 2 256-entry LUT1 engines):
* - PDSP0 and LUT1_0: Outer IP or custom header parsing and classification
* - PDSP1 and LUT1_1: IPSEC NAT-T detection, IPSEC header parsing and classification
#define pa_MAX_NUM_LUT1_ENTRIES pa_MAX_NUM_LUT1_ENTRIES_GEN2
#endif
-/**
- * @def pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES
- * The maximum number of emac port entries. Each emac port can be configured
- * for multiple featuers.
- *
- */
-#define pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES 17
-
/**
* @defgroup ReturnValues Function Return Values
* @ingroup palld_api_constants
*/
#define pa_API_UNSUPPORTED -39
+/**
+ * @def pa_INVALID_INPUT_POINTER
+ * Some of required input pointers are null
+ */
+#define pa_INVALID_INPUT_POINTER -40
+
+/**
+ * @def pa_ACL_BUSY
+ * PASS ACL is busy and can not accept new operations, please retry after the time
+ * as specified by the @ref Pa_addAcl API
+ */
+#define pa_ACL_BUSY -41
+
+/**
+ * @def pa_SUB_SYSTEM_BASE_ADDR_NULL
+ * PASS Base address configured in PA LLD is NULL - serious error
+ */
+#define pa_SUB_SYSTEM_BASE_ADDR_NULL -42
+
+
+/**
+ * @def pa_LUT2_TABLE_FULL
+ * PASS LUT2 Table is full, no more entries can be added unless an
+ * entry is deleted to create a room to a next entry
+ */
+#define pa_LUT2_TABLE_FULL -43
+
+
/*@}*/
/** @} */
* The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_SYS_CONFIG) function to perform PASS
* global configuration.
*/
-#define pa_GLOBAL_CONFIG_MIN_CMD_BUF_SIZE_BYTES 72
+#define pa_GLOBAL_CONFIG_MIN_CMD_BUF_SIZE_BYTES 108
/**
* @def pa_802_1ag_DET_MIN_CMD_BUF_SIZE_BYTES
*/
#define pa_GTPU_CONFIG_MIN_CMD_BUF_SIZE_BYTES 24
+/**
+ * @def pa_EMAC_PORT_MIRROR_CONFIG_MIN_CMD_BUF_SIZE_BYTES
+ * The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_EMAC_PORT_CONFIG, pa_EMAC_PORT_CFG_MIRROR)
+ * function to configure EMAC Mirror operation with the maxmium number of EMAC ports.
+ * The size of command packet is calculated as 24 + (number of configured EMAC ports) * 12.
+ *
+ */
+#define pa_EMAC_PORT_MIRROR_CONFIG_MIN_CMD_BUF_SIZE_BYTES 120
+#define pa_EMAC_PORT_MIRROR_CONFIG_PACKET_SIZE(numPorts) (24 + (numPorts)*12)
+
+/**
+ * @def pa_EMAC_PORT_PKT_CAPTURE_CONFIG_MIN_CMD_BUF_SIZE_BYTES
+ * The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_EMAC_PORT_CONFIG, pa_EMAC_PORT_CFG_PKT_CAPTURE)
+ * function to configure EMAC packet capture operation with the maxmium number of CPSW ports.
+ * The size of command packet is calculated as 24 + (number of configured CPSW ports) * 12.
+ *
+ * @note CPPI port (CPSW port 0) packet capture is only applicable at the egress direction.
+ *
+ */
+#define pa_EMAC_PORT_PKT_CAPTURE_CONFIG_MIN_CMD_BUF_SIZE_BYTES 136
+#define pa_EMAC_PORT_PKT_CAPTURE_CONFIG_PACKET_SIZE(numPorts) (24 + (numPorts)*12)
+
+/**
+ * @def pa_EMAC_PORT_DEFAULT_ROUTE_CONFIG_MIN_CMD_BUF_SIZE_BYTES
+ * The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_EMAC_PORT_CONFIG, pa_EMAC_PORT_CFG_DEFAULT_ROUTE)
+ * function to configure EMAC default routes with the maxmium number of EMAC ports.
+ * The size of command packet is calculated as 24 + (number of configured EMAC ports) * 52.
+ *
+ */
+#define pa_EMAC_PORT_DEFAULT_ROUTE_CONFIG_MIN_CMD_BUF_SIZE_BYTES 440
+#define pa_EMAC_PORT_DEFAULT_ROUTE_CONFIG_PACKET_SIZE(numPorts) (24 + (numPorts)*52)
+
+/**
+ * @def pa_EMAC_PORT_EQoS_MODE_CONFIG_MIN_CMD_BUF_SIZE_BYTES
+ * The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_EMAC_PORT_CONFIG, pa_EMAC_PORT_CFG_EQoS_MODE)
+ * function to configure EMAC default routes with the maxmium number of EMAC ports.
+ * The size of command packet is calculated as 24 + (number of configured EMAC ports) * 152.
+ *
+ */
+#define pa_EMAC_PORT_EQoS_MODE_CONFIG_MIN_CMD_BUF_SIZE_BYTES 1240
+#define pa_EMAC_PORT_EQoS_MODE_CONFIG_PACKET_SIZE(numPorts) (24 + (numPorts)*152)
+
/**
* @def pa_EMAC_PORT_CONFIG_MIN_CMD_BUF_SIZE_BYTES
* The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_EMAC_PORT_CONFIG) function to configure
- * the ethernet port configuration operations.
+ * the ethernet port configuration operations with the maxmium number of EMAC EQoS ports.
+ *
*/
-#define pa_EMAC_PORT_CONFIG_MIN_CMD_BUF_SIZE_BYTES 424
-
+#define pa_EMAC_PORT_CONFIG_MIN_CMD_BUF_SIZE_BYTES pa_EMAC_PORT_EQoS_MODE_CONFIG_MIN_CMD_BUF_SIZE_BYTES
/**
* @def pa_MAX_CMD_BUF_SIZE_BYTES
*/
typedef void* paHandleAcl_t;
+/**
+ * @ingroup palld_api_structures
+ * @brief PA handle specification for EOAM (LUT1) handles.
+ *
+ * @details This type is used to reference EOAM (LUT1) entry with the EOAM table. The module
+ * user is responsible for storing the handle and using it to refer to EOAM entry already
+ * created through calls to @ref Pa_addEoamFlow.
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ */
+typedef void* paHandleEoam_t;
+
/**
* @ingroup palld_api_structures
* @brief PA handle specification for Flow Cache (LUT1) handles
paHandleL2L3_t l2l3Handle; /**< Level 2 or level 3 handle created by @ref Pa_addMac @ref Pa_addSrio, @ref Pa_addCustomLUT1 or @ref Pa_addIp */
paHandleAcl_t aclHandle; /**< ACL handle created by @ref Pa_addAcl (Gen2 only) */
+ paHandleEoam_t eoamHandle; /**< EOAM handle created by @ref Pa_addEoamFlow (Gen2 only) */
paHandleFc_t fclHandle; /**< Flow Cache handle created by @ref Pa_addFc (Gen2 only) */
paHandleL4_t l4Handle; /**< Level 4 handle created by @ref Pa_addPort or @ref Pa_addCustomLUT2 */
*/
#define pa_FC_HANDLE 11
+/**
+ * @def pa_EOAM_HANDLE
+ * EOAM (Ethernet OAM) handle
+ */
+#define pa_EOAM_HANDLE 12
+
/**
* @def pa_INVALID_HANDLE
* Invalid handle type
/* @} */
/** @} */
-
/**
* @defgroup ErouteTypes Exception Route Types
* @ingroup palld_api_constants
/**
* @def pa_EROUTE_GTPU_MESSAGE_TYPE_254
- * GTP-U End Markr packet
+ * GTP-U End Marker packet
*/
#define pa_EROUTE_GTPU_MESSAGE_TYPE_254 20
int nMaxVlnk; /**< Maximum number of virtual links supported */
int nMaxAcl; /**< Maximum number of Stateless ACL handles supported (Gen2 only)*/
int nMaxFc; /**< Maximum number of Flow Cache Hanndles supported (Gen2 only) */
+ int nMaxEoam; /**< Maximum number of EOAM Hanndles supported (Gen2 only). Please refer to @ref appendix8 for details about EOAM mode. */
} paSizeInfo_t;
/**
int numCxts; /**< Total number of contexts the RA handles. This value affects
the amount of heap memory that needs to be allocated. This
value must be between 0x1 and 0x400 (1k). If set to 0, all
- fragments will be discarded. The default value is 0x400. */
+ fragments will be discarded. The default value is 0x400.
+ Note: Each context requires 65kB heap memory */
int cxtDiscardThresh; /**< Number of concurrent contexts that, once reached, causes the
oldest current context to be forcibly timed out. To prevent
this behavior, this value should be programmed to be equal to
uint64_t heapBase[pa_RA_MAX_HEAP_REGIONS]; /**< Reassembly Heap addresses which should be 64-byte aligned */
} paRaConfig_t;
+/**
+ * @ingroup palld_api_structures
+ * @brief PA LUT1 Information Structure
+ *
+ * @details LLD can return the LUT1 information using @ref Pa_getLUT1Info API calls.
+ */
+typedef struct {
+ int lut1Inst; /**< which LUT1 (0-2) Instance is used */
+ int lut1Index; /**< which LUT1 entry (0-63) is used */
+} paLUT1Info_t;
/**
* @ingroup palld_api_structures
/**
- * @defgroup pktControlInfo PA Packet Control Bit Definitions
+ * @defgroup paPktControlInfo PA Packet Control Bit Definitions
* @ingroup palld_api_constants
* @{
*
* @name PA Packet Control Bit Definitions
*
- * Bitmap definition of the ctrlBitMap in @ref paPacketControlConfig_t.
- *
+ * Bitmap definition of the ctrlBitMap in @ref paPacketControlConfig_t
+ * and @ref paPacketControl2Config_t.
*/
/*@{*/
/**
* @def pa_PKT_CTRL_EMAC_IF_IGRESS_CLONE
* Control Info -- Set: Enable EMAC interface-based packet capture/mirror for ingress ethernet traffic
* Clear: disable EMAC interface-based packet capture/mirror (default) for ingress ethernet traffic
+ * @note This definition is only vaild at @ref paPacketControl2Config_t.
*/
#define pa_PKT_CTRL_EMAC_IF_IGRESS_CLONE 0x0020
* @def pa_PKT_CTRL_EMAC_IF_EGRESS_CLONE
* Control Info -- Set: Enable EMAC interface-based packet capture/mirror for egress ethernet traffic
* Clear: disable EMAC interface-based packet capture/mirror (default) for egress ethernet traffic
+ * @note This definition is only vaild at @ref paPacketControl2Config_t.
*/
#define pa_PKT_CTRL_EMAC_IF_EGRESS_CLONE 0x0040
* @def pa_PKT_CTRL_EMAC_IF_INGRESS_DEFAULT_ROUTE
* Control Info -- Set: Enable EMAC interface-based ingress packet default route
* Clear: disable EMAC interface-based ingress packet default route
+ * @note This definition is only vaild at @ref paPacketControl2Config_t.
*/
#define pa_PKT_CTRL_EMAC_IF_INGRESS_DEFAULT_ROUTE 0x0080
/**
- * @def pa_PKT_CTRL_EMAC_IF_EQoS_MODE
- * Control Info -- Set: Enable EMAC interface-based enhanced QoS Mode to support L2 Shappers
- * Clear: Disable EMAC interface-based enhanced QoS Mode
+ * @def pa_PKT_CTRL_EMAC_IF_EGRESS_EQoS_MODE
+ * Control Info -- Set: Enable EMAC interface-based enhanced QoS Mode for egress ethernet traffic
+ * Clear: Disable EMAC interface-based enhanced QoS Mode for egress ethernet traffic
+ * @note This definition is only vaild at @ref paPacketControl2Config_t.
*/
-#define pa_PKT_CTRL_EMAC_IF_EQoS_MODE 0x0100
-
+#define pa_PKT_CTRL_EMAC_IF_EGRESS_EQoS_MODE 0x0100
/*@}*/
/** @} */
* - TTL is not 0
*
* @note refer to the @ref ErouteTypes for the corresponding exception routes.
+ * @note This data structure will be depreciated and replaced with paPacketControl2Config_t due to its limitation that
+ * all desired control bits and other parameters must be provided when it is invoked every time.
*/
typedef struct {
- uint16_t ctrlBitMap; /**< Packet control bit as defined at @ref pktControlInfo */
+ uint16_t ctrlBitMap; /**< Packet control bit as defined at @ref paPktControlInfo */
uint16_t rxPaddingErrStatsIndex; /**< Specify the user statistics index of Rx padding error counter */
uint16_t txPaddingStatsIndex; /**< Specify the user statistics index of Tx MAC padding counter */
} paPacketControlConfig_t;
/**
- * @defgroup paPacketControl2ValidBits PA packet control2 Valid Bit Definitions
+ * @defgroup paPktControlValidBits PA Packet Control Valid Bit Definitions
* @ingroup palld_api_constants
* @{
*
- * @name PA packet control Valid Bit Definitions
+ * @name PA Packet Control Valid Bit Definitions
*
* Bitmap definition of the validBitmap in @ref paPacketControl2Config_t.
*/
#define pa_PKT_CTRL2_VALID_L3_OFFSET pa_PKT_CTRL_L3OFFSET_TO_INNER_IP
/**
- * @def pa_PKT_CTRL2_VALID_EMAC_IF_IGRESS_CAPTURE
+ * @def pa_PKT_CTRL2_VALID_EMAC_IF_IGRESS_CLONE
* - Valid Ingress packet capture/mirror configuration is present in the configuration
*/
#define pa_PKT_CTRL2_VALID_EMAC_IF_IGRESS_CLONE pa_PKT_CTRL_EMAC_IF_IGRESS_CLONE
/**
- * @def pa_PKT_CTRL2_VALID_EMAC_IF_EGRESS_CAPTURE
+ * @def pa_PKT_CTRL2_VALID_EMAC_IF_EGRESS_CLONE
* - Valid Egress packet capture/mirror configuration is present in the configuration
*/
#define pa_PKT_CTRL2_VALID_EMAC_IF_EGRESS_CLONE pa_PKT_CTRL_EMAC_IF_EGRESS_CLONE
#define pa_PKT_CTRL2_VALID_EMAC_IF_INGRESS_DEFAULT_ROUTE pa_PKT_CTRL_EMAC_IF_INGRESS_DEFAULT_ROUTE
/**
- * @def pa_PKT_CTRL2_VALID_EMAC_IF_ENHANCED_QoS_MODE
- * - Valid emac interface enhanced QoS mode is present to support L2 Shapping
+ * @def pa_PKT_CTRL2_VALID_EMAC_IF_EGRESS_EQoS_MODE
+ * - Valid emac interface egress enhanced QoS mode is present
*/
-#define pa_PKT_CTRL2_VALID_EMAC_IF_ENHANCED_QoS_MODE pa_PKT_CTRL_EMAC_IF_EQoS_MODE
+#define pa_PKT_CTRL2_VALID_EMAC_IF_EGRESS_EQoS_MODE pa_PKT_CTRL_EMAC_IF_EGRESS_EQoS_MODE
+
+/**
+ * @def pa_PKT_CTRL2_VALID_PADDING_STATS_INDEX
+ * - Valid rxPaddingErrStatsIndex and txPaddingStatsIndex are present
+ */
+#define pa_PKT_CTRL2_VALID_PADDING_STATS_INDEX 0x8000
/* @} */
/** @} */
*
* @brief Enhanced Packet Control configuration structure
*
- * @details paPacketControl2Config_t is the upgraded version of paPacketControlConfig_t to support additional packet control
- * parameters over time while still maintaining backward compatibility. Future feature
- * enhancements will be supported through this API data structure only.
- *
- * The validBitMap is used to specify which field is used for packet control configuration.
+ * @details paPacketControl2Config_t is the upgraded version of paPacketControlConfig_t to support
+ * individual feature control without affecting the other feature operations. It is achieved
+ * by introducing the parameter validBitMap where only the valid control bits and their
+ * associated parameters will be processed by PASS and the other feature operations will
+ * not be affected.
*/
typedef struct {
- uint16_t validBitMap; /**< Valid bitmap corresponding to each optional field as defined at @ref paPacketControl2ValidBits */
- uint16_t ctrlBitMap; /**< Packet control bit as defined at @ref pktControlInfo */
- uint16_t rxPaddingErrStatsIndex; /**< Specify the user statistics index of Rx padding error counter */
- uint16_t txPaddingStatsIndex; /**< Specify the user statistics index of Tx MAC padding counter */
+ uint16_t validBitMap; /**< Valid control bits as defined at @ref paPktControlValidBits */
+ uint16_t ctrlBitMap; /**< Packet control bit as defined at @ref paPktControlInfo */
+ uint16_t rxPaddingErrStatsIndex; /**< Specify the user statistics index of Rx padding error counter
+ note This parameter is valid only if pa_PKT_CTRL2_VALID_PADDING_STATS_INDEX is set.*/
+ uint16_t txPaddingStatsIndex; /**< Specify the user statistics index of Tx MAC padding counter
+ note This parameter is valid only if pa_PKT_CTRL2_VALID_PADDING_STATS_INDEX is set.*/
+ uint8_t egressDefPri; /**< Specify the global default priority for untagged non IP egress traffic
+ for enhanced QoS mode (refer to @ref appendix7)
+ @note This parameter is valid only if both pa_PKT_CTRL2_VALID_EMAC_IF_EGRESS_EQoS_MODE
+ and the corresponding enable bit are set. */
+
} paPacketControl2Config_t;
/* @} */
/** @} */
+/**
+ * @defgroup paAclInsertModes PA ACL insert modes
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA ACL Insert Modes
+ * @brief Define the ACL insert mode types.
+ *
+ * @details ACL entries are ordered entries, each entry having a priority associated with it.
+ *
+ * When application has a prior knowledge about the
+ * new (latest) entry being inserted typically has highest priority against the
+ * entries already done OR
+ * new (latest) entry being inserted typically has lowest priority against the
+ * entries already done OR
+ * has no prior information on the priority of the new entry, it can indicate it
+ * in the ACL insert mode parameter during the ACL configuration @ref paAclConfig_t
+ *
+ * This information can be used inside LLD to minimize the manual re-score operations as a result of
+ * inserting ordered entries
+ */
+/* @{ */
+/**
+ * @def pa_ACL_INSERT_TOP
+ * Application adds new ACL entry to the top of the ACL table typically (typically new entry that is going to be inserted has highest priority).
+ */
+#define pa_ACL_INSERT_TOP 2
+
+/**
+ * @def pa_ACL_INSERT_BOTTOM
+ * Application adds new ACL entry to the bottom of the ACL table typically (typically new entry that is going to be inserted has lowest priority).
+ */
+#define pa_ACL_INSERT_BOTTOM 1
+
+/**
+ * @def pa_ACL_INSERT_RANDOM
+ * Application adds new ACL entry in any order (application has no prior knowledge on the priority of the new entries that are going to be inserted).
+ */
+#define pa_ACL_INSERT_RANDOM 0
+
+/* @} */
+/** @} */
+
+
/**
* @ingroup palld_api_structures
* @brief Stateless ACL Configuration Information.
(valid only if action = pa_ACL_ACTION_HOST) */
uint16_t destQueue; /**< Destination host queue where PASS will deliver the packets if no ACL matches found
(valid only if action = pa_ACL_ACTION_HOST) */
+ int insertMode; /**< Typical insert order (Top/Bottom/Random) as specified at @ref paAclInsertModes */
} paAclConfig_t;
/**
*/
typedef struct {
- int dest; /**< (TBD:) Packet destination as defined at @ref pktDest */
+ int dest; /**< Packet destination as defined at @ref pktDest (Host and Discard only) */
uint8_t flowId; /**< Specifies CPPI flow which defines free queues are used for receiving packets */
uint16_t queue; /**< Specifies the destination host queue */
} paRaERouteInfo_t;
paRaERouteInfo_t genErrER; /**< Specify exception route for packets with non-critical error*/
} paRaGroupConfig_t;
+/**
+ * @ingroup palld_api_constants
+ * @brief Define the maximum number ethernet protocol types to be excluded from EOAM classification
+ *
+ * @details The application can specify the list of ethernet types to be excluded from EOAM classification
+ * i.e., the target flow statistics count would not be incremented even though the match happens
+ * when the packet ethernet type matches the list.
+ *
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ */
+#define pa_MAX_ETH_PROTO_EOAM_EXCLUSION 8
+
+/**
+ * @ingroup palld_api_structures
+ * @brief PA time offset correction.
+ *
+ * @details paSetTimeOffset_t is used to set the 1588 time offsets at PASS time 0
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ */
+typedef struct {
+ uint32_t offset_sec; /**< 1588 Time offset in seconds (needed for features like EOAM) */
+ uint32_t offset_ns; /**< 1588 Time offset in nano seconds (needed for features like EOAM) */
+}paSetTimeOffset_t;
+
+/**
+ @defgroup paInputFreq Packet Accelerator PLL Frequencies
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name Packet Accelerator PLL input frequency (Gen2 only)
+ *
+ * paInputFreq_e is used to provide the input frequency to PASS programmed either through PA clock or
+ * system clock in MHz. This parameter is useful in converting the ticks to seconds and nano seconds.
+ *
+ * @details This information is required for firmware to convert the time ticks to seconds and nano
+ * seconds. The mathematical operations and the scheme involved in such conversion
+ * requires the input frequency. Hence, not all possible frequencies are supported.
+ * The converted time can be used to patch the time in the message using
+ * @ref pa_CMD_PATCH_TIME. The mathematical operations
+ * in firmware are optimized for these frequency lists.
+ *
+ * @note This parameter can be ignored if EOAM mode is not enabled and the message is not patched
+ * for time.
+ */
+/** @ingroup paInputFreq */
+/*@{*/
+typedef enum {
+ pa_INPUT_FREQ_1000MHZ = 1, /**< PASS Input frequency is 1000 MHz */
+ pa_INPUT_FREQ_1050MHZ, /**< PASS Input frequency is 1050 MHz */
+ pa_INPUT_FREQ_1049p6MHZ /**< PASS Input frequency is 1049.6 MHz */
+} paInputFreq_e;
+
+/*@}*/
+/** @} */
+
+/**
+ * @ingroup palld_api_structures
+ * @brief PA Ethernet OAM target flow match Statistics control configuration Information.
+ *
+ * @details paEoamTfExcCtrlConfig_t is used to exclude few ethernet types from EOAM target classification
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ */
+typedef struct {
+ uint8_t numProtoExcl; /**< Number of protocol to be excluded from EOAM target classifiation */
+ uint16_t exclEthTypes[pa_MAX_ETH_PROTO_EOAM_EXCLUSION]; /**< maximum number of ethernet types to be excluded from EOAM target classification */
+} paEoamTfExcCtrlConfig_t;
+
+/**
+ * @defgroup paEoamGlobalValidInfo PA EOAM Global Configuration Valid Bit Definitions
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Global Config Valid Bit Definitions
+ *
+ * Bitmap definition of the validBitmap in @ref paEoamGlobalConfig_t.
+ */
+/*@{*/
+/**
+ * @def pa_EOAM_VALID_STATS_CTRL
+ * - Control to increment the Ethernet OAM target flow matches is present
+ */
+#define pa_EOAM_VALID_STATS_CTRL (1<<0)
+
+/* @} */ /* ingroup */
+/** @} */
+
+
+/**
+ * @ingroup palld_api_structures
+ * @brief PA Ethernet OAM Global Configuration Information.
+ *
+ * @details paEoamGlobalConfig_t is used to configure the Ethernet OAM parameters.
+ *
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ * @warning EOAM mode can not co-exist with Outer ACL firewall operations. Please make sure
+ * Outer ACL is not configured during EOAM system configuration. There is no dynamic
+ * switching between the original mode and EOAM mode.
+ */
+typedef struct {
+ uint32_t validBitMap; /**< Valid control bits as defined at @ref paEoamGlobalValidInfo */
+ uint32_t enable; /**< Enable/Disable EOAM feature, As Outer ACL and EOAM can not co-exist, make sure Outer ACL
+ entries are all removed before adding the EOAM entries in the LUT table */
+ paInputFreq_e freq; /**< Mandatory: PA Input Frequency in MHz as defined at @ref paInputFreq_e */
+ paEoamTfExcCtrlConfig_t statsCtrl; /**< Ethernet OAM target flow exclusion protocol control @ref paEoamTfExcCtrlConfig_t */
+} paEoamGlobalConfig_t;
+
+/**
+ * @defgroup paQueueBounceRoutingClass PA Queue Bounce Routing Class
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Queue Bounce Routing Class
+ *
+ * Definition of PA Queue Bounce Routing Classes
+ */
+/** @ingroup paQueueBounceRoutingClass */
+/*@{*/
+typedef enum {
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_CMD_RET = 0, /**< Command Return */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_QoS, /**< Ingress QoS Packets */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_CAPTURE, /**< Packet Capture */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_IP_REASSEMBLY, /**< IP Reassembly-assisted packets */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_MISC, /**< All other Traffic */
+ PA_MAX_QUEUE_BOUNCE_ROUTING_CLASSES
+}paQueueBounceRoutingClass_e ;
+/*@}*/
+/** @} */
+
+/**
+ * @defgroup paQueueBounceOperationTypes PA Queue Bounce operation modes
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Queue Bounce operation modes
+ * @brief Define the Queue Bounce operation modes.
+ */
+/* @{ */
+/**
+ * @def pa_QUEUE_BOUNCE_OP_NONE
+ * No bounce, use the user specified destination queue as it is
+ */
+#define pa_QUEUE_BOUNCE_OP_NONE 0
+
+/**
+ * @def pa_QUEUE_BOUNCE_OP_DDR
+ * Add control bits to indicate bouncing to the DDR Queue
+ */
+#define pa_QUEUE_BOUNCE_OP_DDR 1
+
+/**
+ * @def pa_QUEUE_BOUNCE_OP_MSMC
+ * Add control bits to indicate bouncing to the MSMC queue
+ */
+#define pa_QUEUE_BOUNCE_OP_MSMC 2
+
+
+/**
+ * @def pa_QUEUE_BOUNCE_OP_MAX
+ * Number of Queue Bounce Operation modes
+ */
+#define pa_QUEUE_BOUNCE_OP_MAX pa_QUEUE_BOUNCE_OP_MSMC
+/*@}*/
+/** @} */
+
+/**
+ * @ingroup palld_api_structures
+ * @brief PA Queue Bounce Configuration Information.
+ *
+ * @details paQueueBounceConfig_t is used to configure the PA Queue Bounce operation as described at @ref appendix9.
+ *
+ * @note The Queue Bounce Configuration should be specified at PA system initialization and only once. The dynamic
+ * re-configuration is not supported and may cause undefined behaviors.
+ */
+typedef struct {
+
+ uint32_t enable; /**< Enable/Disable(1/0) Queue Bounce operation, default = 0 (disable) */
+ uint16_t ddrQueueId; /**< Bounce queue where PASS will deliver the host-routed packet with DDR bit set */
+ uint16_t msmcQueueId; /**< Bounce queue where PASS will deliver the host-routed packet with MSMC bit set */
+ uint16_t hwQueueBegin; /**< Queue number of the first NetCP hardware queue */
+ uint16_t hwQueueEnd; /**< Queue number of the last NetCP hardware queue */
+ uint16_t defOp[PA_MAX_QUEUE_BOUNCE_ROUTING_CLASSES]; /**< Default Queue Bounce operations per class */
+
+} paQueueBounceConfig_t;
+
+/**
+ * @defgroup paQueueBounceControlBits PA Queue Bounce Control Bits and related definitions
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Queue Bounce Control Bits
+ * @brief PA Queue Bounce Control Bits and related definitions
+ */
+/* @{ */
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_DEFAULT
+ * Use default rule
+ */
+#define pa_QUEUE_BOUNCE_CTRL_DEFAULT 0
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_DDR
+ * Bounce to the DDR Queue
+ */
+#define pa_QUEUE_BOUNCE_CTRL_DDR 1
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_MSMC
+ * Bounce to the MSMC queue
+ */
+#define pa_QUEUE_BOUNCE_CTRL_MSMC 2
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_NONE
+ * No bounce, clear the control bits
+ */
+#define pa_QUEUE_BOUNCE_CTRL_NONE 3
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_LOC
+ * Bit location of the queue bounce control bits
+ */
+#define pa_QUEUE_BOUNCE_CTRL_LOC 14
+
+/**
+ * @def pa_QUEUE_BOUNCE_QUEUE_MASK
+ * Actual queue number mask
+ */
+#define pa_QUEUE_BOUNCE_QUEUE_MASK 0x3FFF
+
+/*@}*/
+/** @} */
+
+/**
+ * @defgroup PA_queue_bounce_op_macros PA Queue Bounce Operation Macros
+ * @ingroup palld_api_macros
+ * @{
+ * @name PA Queue Bounce Operation Macros
+ * Macros used by the PA Queue Bounce Operation to insert/clear control bits
+ */
+/*@{*/
+#define PA_BOUNCE_QUEUE_DDR(queueId) (((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) | (pa_QUEUE_BOUNCE_CTRL_DDR << pa_QUEUE_BOUNCE_CTRL_LOC)) /**< Insert control bits to indicate DDR queue bouncing */
+#define PA_BOUNCE_QUEUE_MSMC(queueId) (((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) | (pa_QUEUE_BOUNCE_CTRL_MSMC << pa_QUEUE_BOUNCE_CTRL_LOC)) /**< Insert control bits to indicate MSMC queue bouncing */
+#define PA_BOUNCE_QUEUE_NONE(queueId) (((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) | (pa_QUEUE_BOUNCE_CTRL_NONE << pa_QUEUE_BOUNCE_CTRL_LOC)) /**< Incert control bits to indicate no queue bouncing */
+#define PA_BOUNCE_QUEUE_DEFAULT(queueId) ((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) /**< Clear control bits to indicate default operation */
+
+/*@}*/ /* PA_queue_bounce_op_macros */
+/** @}*/ /* PA Queue Bounce Operation Macros */
+
/**
* @ingroup palld_api_structures
* @brief PA System Configuration Information structure
paUsrStatsConfig_t* pUsrStatsConfig; /**< Pointer to the user-defined statistics configuration structure */
paQueueDivertConfig_t* pQueueDivertConfig; /**< Pointer to the queue-diversion configuration structure */
paPacketControlConfig_t* pPktControl; /**< Pointer to the packet control configuration structure */
+ paQueueBounceConfig_t* pQueueBounceConfig; /**< Pointer to the Queue Bounce configuration structure */
paAclConfig_t* pOutAclConfig; /**< Pointer to the outer ACL configuration structure */
paAclConfig_t* pInAclConfig; /**< Pointer to the inner ACL configuration structure */
paRaGroupConfig_t* pOutIpRaGroupConfig; /**< Poimter to the outer IP Reassembly group configuration structure */
paRaGroupConfig_t* pInIpRaGroupConfig; /**< Poimter to the inner IP Reassembly group configuration structure */
- paPacketControl2Config_t* pPktControl2; /**< Pointer to the packet control 2 configuration structure */
+ paPacketControl2Config_t* pPktControl2; /**< Pointer to the packet control 2 configuration structure */
+ paEoamGlobalConfig_t* pEoamConfig; /**< Pointer to the EOAM Global configuration structure */
} paSysConfig_t;
/**
* (Outer IP and IPSEC) processing stage to avoid the re-entry operation. However, the detector
* is also implemented at the Ingress4 (LUT2) stage to maintain backward compatibility.
* It is recommended to set this flag to one to enable the IPSEC ESP NAT-T detector at Ingress 1
- * stage to maintain the maxmium PASS throughput.
+ * stage to maintain the maximum PASS throughput.
*
* @note: This feature is only supported by the second generation of PASS and this control bit will be
* ignored at the device which uses the first generation of PASS.
* Clear: GTU-U classification vector consists of the 32-bit of tunnel ID only (Default)
*/
#define pa_GTPU_CTRL_USE_LINK 0x0001
+
+/**
+ * @def pa_GTPU_CTRL_ROUTE_END_MARKER_AS_GPDU
+ * Control Info -- Set: Configures the GTP-U message routing rule such that the packets with message type 254 (end markers)
+ * are routed the same way as message type 255 (G-PDU), meaning GTPU TEID would be recovered and routed for
+ * LUT2 match.
+ * Clear: End message routing send to a configured flow/exception route (Default)
+ */
+#define pa_GTPU_CTRL_ROUTE_END_MARKER_AS_GPDU 0x0002
+
/*@}*/
/** @} */
*
*/
#define pa_N_BUFS_GEN1 5
-#define pa_N_BUFS_GEN2 7
+#define pa_N_BUFS_GEN2 8
#define pa_N_BUFS pa_N_BUFS_GEN2
*/
#define pa_BUF_FC_TABLE 6
+/**
+ * @def pa_BUF_EOAM_TABLE
+ * PA LLD match table of EOAM entries such as Y1731
+ * Please refer to @ref appendix8 for details about EOAM mode.*
+ * @note This definition is valid for the second generation PASS only.
+ */
+#define pa_BUF_EOAM_TABLE 7
+
/* @} */
/** @} */
*
* @param[in] handle The PA LLD instance identifier
* @param[in] startCfg PA start configuration
- * @retval None
+ * @retval Value (@ref ReturnValues)
*/
-void Pa_startCfg (Pa_Handle handle, paStartCfg_t *startCfg);
+paReturn_t Pa_startCfg (Pa_Handle handle, paStartCfg_t *startCfg);
/**
* @ingroup palld_api_functions
#define pa_CMD_PATCH_MSG_LEN 15
/* @def pa_CMD_VERIFY_PKT_ERROR
- * Verify the packet error based on the CPPI error flags as specified at @ref Appendix2 and forward
+ * Verify the packet error based on the CPPI error flags as specified at @ref appendix2 and forward
* the error packet to the specified destination
* @note This packet error verification is not applicable to the CRC verification operation within the same
* command set.
*/
#define pa_CMD_EF_OP 18
+/* @def pa_CMD_PATCH_TIME
+ * Patch the time values in packets (Gen 2 support only)
+ */
+#define pa_CMD_PATCH_TIME 19
+
+/* @def pa_CMD_PATCH_COUNT
+ * Patch the time values in packets (Gen 2 support only)
+ */
+#define pa_CMD_PATCH_COUNT 20
+
+/* @def pa_CMD_EMAC_CRC_VERIFY
+ * Perfrom the Ethernet CRC verification for egress traffic. (Applicable only for Gen1)
+ * Refer to the description of data structure @ref paCmdEmacCrcVerify_t for details.
+ */
+
+#define pa_CMD_EMAC_CRC_VERIFY 21
/* @} */
/** @} */
*/
#define pa_NEXT_ROUTE_PROC_USR_STATS 0x0010
+/**
+ * @def pa_NEXT_ROUTE_RPT_TX_TIMESTAMP
+ * Control Info -- Set: Instruct switch to report the transmit timestamp with the associated CPTS domain, message type and
+ * sequence number encoded in the swInfo0.
+ * Clear: swInfo0 is invalid
+ * @note: This option is only valid in the egress (to-network) direction on NSS_GEN2 devices when dest is set to pa_DEST_EMAC.
+ */
+#define pa_NEXT_ROUTE_RPT_TX_TIMESTAMP 0x0020
+
/*@}*/
/** @} */
+/**
+ * @ingroup palld_api_macros
+ * @brief pa_FORMAT_REPORT_TIMESTAMP_INFO is used to format the CPTS report timestamp information at swInfo0
+ *
+ * @details This macro is used to construct the swInfo0 with associated CPTS domain, message type and sequence id where
+ * swInfo0 is used to instruct the CPSW to report transmit timestamp as a CPTS event
+ *
+ */
+#define pa_FORMAT_REPORT_TIMESTAMP_INFO(domain, msgType, seqId) 0x80000000UL | \
+ (((domain) & 0xFF) << 20) | \
+ (((msgType) & 0x0F) << 16)| \
+ ((seqId & 0xFFFF))
+
/**
* @ingroup palld_api_structures
* @brief Next Route Command
} paTxChksum_t;
+/**
+ * @ingroup palld_api_structures
+ * @brief patch time in EOAM packet configuration
+ *
+ * @details paPatchTime_t is used in the call @ref Pa_formatTxCmd to create a tx
+ * command header that instructs the packet accelerator sub-system to patch the
+ * time bytes in the specified offset of the packet.
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ */
+typedef struct {
+ uint16_t startOffset; /**< Byte location, from SOP, to insert 8 bytes time values 4 byte second, 4 byte nano second */
+} paPatchTime_t;
+
+/**
+ * @ingroup palld_api_structures
+ * @brief patch Count in EOAM packet configuration
+ *
+ * @details paPatchCount_t is used in the call @ref Pa_formatTxCmd to create a tx
+ * command header that instructs the packet accelerator sub-system to patch the
+ * specified user stats counter bytes in the specified offset of the packet.
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ */
+typedef struct {
+
+ uint16_t startOffset; /**< Byte location, from SOP, to insert count values */
+ uint16_t countIndex; /**< Counter index to insert */
+} paPatchCount_t;
/**
* @defgroup copyCtrlInfo PA Copy Command Control Info Bit Definitions
* @details paCmdTxTimestamp_t specifies the tx timestamp reporting information. The report tx timestamp command is used to instruct
* the PASS to report the PA timestamp when the packet is transmitting out of PASS in a return (null) packet to the specified
* host queue. The transmit timestamp may be used for the Precision Timing Protocol (PTP). The reported tx timestamp will be
- * a 48 bit value, with the lower 32 bits stored in timestamp field, and the upper 16 bits stored in swInfo1.
+ * a 64-bit value, with the lower 32 bits stored in timestamp field, and the upper 32 bits stored in swInfo1.
*
* @pre API @ref Pa_configTimestamp() should be called to enable PASS system timestamp.
*/
uint32_t swInfo0; /**< Placed in SwInfo0 for packets to host */
} paCmdVerifyPktErr_t;
+/**
+ * @ingroup palld_api_structures
+ * @brief EMAC CRC Verification information
+ *
+ * @details paCmdEmacCrcVerify_t is used to create the EMAC CRC verification command which is used to instruct the PASS to
+ * perform Ethernet CRC verification for forwarding to-network traffic. The egress packet with this command is
+ * expected to be a forwarding Ethernet packet with CRC. PASS will perform CRC verification against the CRC
+ * value at the packet, if CRC is good, the packet will be forwarded to the desired EMAC port and if CRC
+ * is bad, then the packet will be dropped.
+ * Application should invoke Pa_configCrcEngine() API to format the CRC configuration packet for Ethernet CRC and
+ * then forward configuration packet to Tx command prtocessing PDSP (PDSP5) before this command is used.
+ *
+ * This command is used to provide a workaround for following GbE errata at some keystone devices:
+ *
+ * The GbE switch may drop packets in TX path when:
+ * - full gigabit speeds are sustained and
+ * - the packet size is not a 32 bit multiple (1499, 1498, 1497, 1495, etc.) and
+ * - Ethernet CRC is included in the last 4 bytes of the packet sent to the switch
+ *
+ * @note The Ethernet CRC Verify command can not be combined with any other tx commands, all other commands will be ignored
+ * by PASS when this command is processed.
+ *
+ */
+
+typedef struct {
+ uint16_t emacPort; /**< Specify the output EMAC port number as define at @ref paEmacPort. */
+} paCmdEmacCrcVerify_t;
+
/**
* @defgroup efOpCtrlInfo PA Egress Flow Command Control Info Bit Definitions
* @ingroup palld_api_constants
paPatchMsgLenInfo_t patchMsgLen; /**< Specify Patch Message Length command specific parameters */
paCmdVerifyPktErr_t verifyPktErr; /**< Specify Packet error Verification command specific parameters */
paCmdSplitOp_t split; /**< Specify Split command sepcific parameters */
+ paCmdEmacCrcVerify_t emacCrc;/**< Specify the EMAC CRC Verify command specific parameters */
paCmdEfOp_t efOp; /**< Specify Egress Flow operation command specific parameters (PASS Gen2 only) */
+ paPatchTime_t patchTime; /**< Specify insert time in the messages like Ethernet OAM packets (PASS Gen2 only)*/
+ paPatchCount_t patchCount; /**< Specify insert count in the messages like Ethernet OAM packets (PASS Gen2 only)*/
}params; /**< Contain the command specific parameters */
} paCmdInfo_t;
*/
#define pa_ETH_INFO_VALID_INPORT (1<<5)
+/**
+ * @def pa_ETH_INFO_VALID_VLAN_PRI
+ * - Input VLAN PRI is present
+ */
+#define pa_ETH_INFO_VALID_VLAN_PRI (1<<6)
+
+
/* @} */ /* ingroup */
/** @} */
uint32_t validBitMap; /**< 32-bit valid Bitmap corresponding to each optional field as defined at @ref paEthInfoValidBits */
paMacAddr_t src; /**< Source MAC addresss */
paMacAddr_t dst; /**< Destination MAC address */
- uint16_t vlan; /**< VLAN tag VID field, 12 lsbs */
+ uint16_t vlan; /**< VLAN tag VID field, 12 lsbs
+ @note: Both untagged packets and priority marked packets (i.e. packets with VID = 0)
+ will be matched when vlan is set to 0 */
uint16_t ethertype; /**< Ethertype field. */
uint32_t mplsTag; /**< MPLS tag. Only the outer tag is examined */
uint16_t inport; /**< Input EMAC port number as specified by @ref paEmacPort */
+ uint8_t vlanPri; /**< VLAN tag PCP field, 3 bits showing priority */
} paEthInfo2_t;
+
+/**
+ * @ingroup palld_api_structures
+ * @brief EOAM look up information
+ *
+ * @details paEoamFlowInfo_t is used to specify the flow parameters used in EOAM packet classification.
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ */
+typedef struct {
+ uint16_t validBitMap; /**< Valid bit map reserved for future enhancements */
+ uint8_t flowId; /**< Specifies the packet DMA flow ID, which defines the free queuese are
+ used for receiving EOAM control packets */
+ uint16_t destQueue; /**< Specifies the destination queue used for receiving EOAM control packets */
+ uint32_t swInfo0; /**< Placed in SwInfo0 for EOAM control packets to host */
+ uint16_t statsIndex; /**< user defined counter index binded with an EOAM target flow */
+ uint8_t megLevel; /**< Maintenance Entity Group Level threshold to decide need statistics or not.
+ MEG Level is a 3-bit field. It contains an integer value that identifies MEG
+ level of OAM PDU. Value ranges from 0 to 7 */
+} paEoamFlowInfo_t;
+
/**
* @defgroup paAclInfoValidBit PA ACL Matching Info Valid Bit Definitions
* @ingroup palld_api_constants
* or interface-based routing.
* PASS forwards the matched packets to the desired QoS queue which is equal
* to the base queue plus an offset specified by the VLAN priority or DSCP value
- * in prority-based routing.
+ * in prority-based routing such as pa_ROUTE_PRIORITY_VLAN or pa_ROUTE_PRIORITY_DSCP.
* PASS forwards the matched packets to the desired host queue which is equal
* to the base queue plus an offset as the EMAC port (interface) number with the CPPI
* flow which is equal to the base flow number plus the EMAC port (interface) number
- * optionally in interface-based routing.
+ * optionally in interface-based routing such as pa_ROUTE_INTF or pa_ROUTE_INTF_W_FLOW.
+ * PASS forwards the matched packets to the derived QoS queue with derived CPPI flow
+ * based on the algorithm specified at @ref appendix6 in EQoS routing
*
* @note: There is some use cases where output packets from QoS are delivered to
* PASS for pre-routing operation such as tx timestamp report and both
/** @ingroup paPriIntfRouteMode */
/*@{*/
typedef enum {
- pa_ROUTE_PRIORITY_VLAN = 1, /**< Route by using VLAN bits as priority */
+ pa_ROUTE_PRIORITY_VLAN = 1, /**< Route by using VLAN P bits as priority */
pa_ROUTE_PRIORITY_DSCP, /**< Route by using DSCP bits as priority */
pa_ROUTE_INTF, /**< Route by using EMAC port (interface) number as destination queue offset */
pa_ROUTE_INTF_W_FLOW, /**< Route by using EMAC port (interface) number as both
*/
#define pa_ROUTE_INFO_VALID_PRIORITY_TYPE (1<<3)
+/**
+ * @def pa_ROUTE_INFO_VALID_CTRLBITMAP
+ * - Optional parameter ctrlBitMap is valid
+ */
+#define pa_ROUTE_INFO_VALID_CTRLBITMAP (1<<4)
+
+
/* @} */ /* ingroup */
/** @} */
+/**
+ * @defgroup paRouteInfoCtrlBits PA Route Info Control Bits Definitions
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Route Info Control Bits Definitions
+ *
+ * @brief Bitmap definition of the ctrlBitMap in @ref paRouteInfo2_t
+ *
+ */
+/* @{ */
+/**
+ * @def pa_ROUTE_INFO_L2_PKT_CAPTURE
+ * Control Info -- Set: Duplicate and forward the matched L2 packet to the capture queue
+ *
+ * This flag will be check only if the destination is set to pa_DEST_CONTINUE_PARSE_LUT1.
+ * In this case, the parameter flowId, queue and swInfo0 are used to deliver the captured
+ * packet.
+ *
+ * @note: This feature is supported only on PASS Gen2 device. For PASS Gen1 devices, the L2
+ * packet capture can be implemented with host multi-route feature where the packet
+ * should be duplicated and routed to the capture queue and the queue 641 for continuous
+ * classification on PASS Gen1 devices.
+ */
+#define pa_ROUTE_INFO_L2_PKT_CAPTURE 0x0001
+
+/* @} */
+/** @} */
+
/**
* @ingroup palld_api_structures
* @brief Enhanced Packet routing configuration
uint8_t priorityType; /**< validBitMap[t3]: For Host only, specify priority-based and/or interfcae-based routing mode as
* defined at @ref paRoutePriIntf_e
*/
- paEfOpInfo_t *efOpInfo; /**< For EFLOW only, egress flow operation info (PAGG Gen2 only) */
+ paEfOpInfo_t *efOpInfo; /**< For EFLOW only, egress flow operation info (PASS Gen2 only) */
+ uint32_t ctrlBitMap; /**< validBitMap[t4]: 32-bit control bitmap as defined at @ref paRouteInfoCtrlBits */
} paRouteInfo2_t;
/**
- * @defgroup PaPktCloneCtrlCode_e PA Packet capture/port mirror control Code
+ * @defgroup paPktCloneCtrlBits PA Packet Capture/Port Mirror Control Bit Definitions
* @ingroup palld_api_constants
* @{
*
- * @name PA EMAC packet capture/port mirror Code
+ * @name PA Packet Capture/Port Mirror Control Bit Definitions
*
- * @brief Define the PA LLD EMAC packet capture/port mirror code
+ * @brief Bitmap definition of the ctrlBitMap in @ref paPortMirrorConfig_t and @ref paPktCaptureConfig_t.
*
*/
-/** @ingroup PaEmacPortCfgCode_e */
/* @{ */
/**
* @def pa_PKT_CLONE_ENABLE
- * port mirror/packet capture configuration
- * please refer to appendix for details about this mode.
+ * port mirror/packet capture control
+ * please refer to @ref appendix5 for details about this mode.
*/
#define pa_PKT_CLONE_ENABLE 1
/**
* @ingroup palld_api_structures
- * @brief PA Interface based Packet Capture Configuration Information.
+ * @brief PA Interface based Port Mirror Configuration Information.
*
* @details paPortMirrorConfig_t is used to specify the port mirror configuration parameters of the PASS.
*
* For the Ingress configuration:
- * All the ingress MAC packets entering PDSP0 will be duplicated and forwarded to the
+ * All the ingress MAC packets entering PDSP0 (Ingress0) will be duplicated and forwarded to the
* specified EMAC port to simulate Ethernet SW port mirroring operation prior to the classification
* (lookup) operation based on the IF based configuration.
*
* For the Egress configuration:
* All the egress packets directed to EMAC port will be duplicated and forwarded
- * to another specified EMAC port to simulate Ethernet SW port mirroring operation
+ * to specified mirror port to simulate Ethernet SW port mirroring operation
* as part of the nextRoute command processing based on the IF based configuration.
*/
typedef struct {
- uint32_t ctrlBitMap; /**< Specifies the control packet capture as defined in @ref PaPktCloneCtrlCode_e */
+ uint32_t ctrlBitMap; /**< Specifies various port mirror control bits as defined in @ref paPktCloneCtrlBits */
uint8_t portToBeMirrored; /**< Specifies port to be mirrored */
uint8_t mirrorPort; /**< The mirror port */
} paPortMirrorConfig_t;
* @details paPktCaptureConfig_t is used to specify the packet capture configuration parameters of the PASS.
*
* For the Ingress configuration:
- * All the ingress MAC packets entering PDSP0 will be duplicated and forwarded to the
+ * All the ingress MAC packets entering PDSP0 (Ingress0) will be duplicated and forwarded to the
* specified host queue for packet capturing prior to the classification (lookup)
* operation based on the IF based configuration.
*
* For the Egress configuration:
* All the egress packets directed to EMAC port will be duplicated and forwarded
- * to another pecified host queue for packet capturing as part of the nextRoute
+ * to the pecified host queue for packet capturing as part of the nextRoute
* command processing based on the IF based configuration.
*/
typedef struct {
- uint32_t ctrlBitMap; /**< Specifies the control packet capture as defined in @ref PaPktCloneCtrlCode_e */
+ uint32_t ctrlBitMap; /**< Specifies various packet capture control bits as defined in @ref paPktCloneCtrlBits */
uint8_t portToBeCaptured; /**< Specifies port to be captured */
- uint32_t swInfo0; /**< Specifies Software Info0 to be returned */
- uint8_t flowId; /**< Specifies CPPI flow which defines free queues are used for receiving packets */
- uint16_t queue; /**< Specifies the destination host queue */
+ uint32_t swInfo0; /**< Placed in SwInfo0 for packets to host */
+ uint8_t flowId; /**< Specifies CPPI flow which defines free queues to be used for receiving packets */
+ uint16_t queue; /**< Specifies the destination host queue */
} paPktCaptureConfig_t;
/**
- * @defgroup PaDefRouteCtrlCode_e PA Interface-based Ingress packet Capture default route Control Bit Definitions
- * for multicast and broadcast packets and for packets which does not match any
- * specified MAC entry.
+ * @defgroup paDrouteTypes PA Default Route Types
* @ingroup palld_api_constants
* @{
*
- * @name PA Interface-based Ingress packet default route Control Bit Definitions
+ * @name PA Default Route Types
+ *
+ * @brief These values are used to define interface-based ingress default route types.
*
- * Bitmap definition of the ctrlBitMap in @ref PaDefRouteCtrlCode_e
+ * @details The interface-based ingress default route defines the global routing information for the
+ * packet types such as multicast packet, broadcast packet and non-matched unicast packet.
+ */
+/* @{ */
+/**
+ *
+ * @def pa_DROUTE_MULTICAST
+ * Multicast packet default route index
+ */
+#define pa_DROUTE_MULTICAST 0
+
+/**
+ *
+ * @def pa_DROUTE_BROADCAST
+ * Broadcast packet default route index
+ */
+#define pa_DROUTE_BROADCAST 1
+
+/**
+ *
+ * @def pa_DROUTE_NO_MATCH
+ * Non-matched unicast packet default route index
+ */
+#define pa_DROUTE_NO_MATCH 2
+
+
+/**
+ * @def pa_DROUTE_MAX
+ * The maximum number of global default route types
+ */
+#define pa_DROUTE_MAX 3
+
+/* @} */
+/** @} */
+
+/**
+ * @defgroup paDefRouteCtrlBits PA Interface-based Ingress Packet Default Route Control Bit Definitions
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Interface based Ingress Packet Default Route Control Bit Definitions
+ *
+ * Bitmap definition of the ctrlBitMap in @ref paDefRouteConfig_t
*
*/
/*@{*/
/**
- * @def pa_EMAC_IF_INGRESS_DEFAULT_ROUTE_MC_ENABLE
+ * @def pa_EMAC_IF_DEFAULT_ROUTE_MC_ENABLE
* Control Info -- Set: Multicast default route enable
* Clear: Multicast default route disable
*/
#define pa_EMAC_IF_DEFAULT_ROUTE_MC_ENABLE 0x0001
/**
- * @def pa_EMAC_IF_INGRESS_DEFAULT_ROUTE_BC_ENABLE
+ * @def pa_EMAC_IF_DEFAULT_ROUTE_BC_ENABLE
* Control Info -- Set: Broadcast default route enable
* Clear: Broadcast default route disable
*/
#define pa_EMAC_IF_DEFAULT_ROUTE_BC_ENABLE 0x0002
+/**
+ * @def pa_EMAC_IF_DEFAULT_ROUTE_UC_ENABLE
+ * Control Info -- Set: unicast packet no match default route enable
+ * Clear: unicast packet no match default route disable
+ */
+#define pa_EMAC_IF_DEFAULT_ROUTE_UC_ENABLE 0x0004
/**
- * @def pa_EMAC_IF_INGRESS_DEFAULT_ROUTE_POST_CLASSIFICATION_ENABLE
- * Control Info -- Set: post classification enable
- * Clear: Pre classification enable
+ * @def pa_EMAC_IF_DEFAULT_ROUTE_MC_PRE_CLASSIFY_ENABLE
+ * Control Info -- Set: default route for multicast pre classification enable
+ * Clear: default route for multicast post classification disable
*/
-#define pa_EMAC_IF_DEFAULT_ROUTE_POST_CLASSIFY_ENABLE 0x0004
+#define pa_EMAC_IF_DEFAULT_ROUTE_MC_PRE_CLASSIFY_ENABLE 0x0008
/**
- * @def pa_EMAC_IF_INGRESS_DEFAULT_ROUTE_UC_ENABLE
- * Control Info -- Set: unicast packet no match default route enable
- * Clear: unicast packet no match default route disable
+ * @def pa_EMAC_IF_DEFAULT_ROUTE_BC_PRE_CLASSIFY_ENABLE
+ * Control Info -- Set: default route for broadcast pre classification enable
+ * Clear: default route for broadcast post classification disable
*/
-#define pa_EMAC_IF_DEFAULT_ROUTE_UC_ENABLE 0x0008
+#define pa_EMAC_IF_DEFAULT_ROUTE_BC_PRE_CLASSIFY_ENABLE 0x0010
+
/*@}*/
/** @} */
*
* @details paDefRouteConfig_t is used to specify the ingress default routing
* configuration parameters of the PASS.
- * Default Route corresponds to no match conditions for unicast packets not targetted for SoC,
- * and also for multicast and broadcast packets
+ * Refer to @ref appendix6 for details
+ *
*/
typedef struct {
- uint32_t ctrlBitMap; /**< Specifies the control for ingress default packets that do not match L2 lUT rule @ref PaDefRouteCtrlCode_e */
- uint8_t port; /**< Ingress port ID */
- paRouteInfo2_t bcRouteInfo; /**< Broadcast default route information */
- paRouteInfo2_t mcRouteInfo; /**< Multicast default route information */
- paRouteInfo2_t ucRouteInfo; /**< No match routing information for the unicast packets */
+ uint32_t ctrlBitMap; /**< Specifies various ingress default route control bits as defined at @ref paDefRouteCtrlBits */
+ uint8_t port; /**< Specifies the ingress EMAC port number (1-based) */
+ paRouteInfo2_t dRouteInfo[pa_DROUTE_MAX]; /**< Specifies the default route information for each packet type as defined at @ref paDrouteTypes */
} paDefRouteConfig_t;
/**
- * @defgroup PaEQoSCtrlCode_e PA Enhanced QoS control code
+ * @defgroup paEQoSCtrlBits PA Enhanced QoS Control Bits Definitions
* @ingroup palld_api_constants
* @{
*
- * @name PA enhanced QoS control Code
+ * @name PA enhanced QoS Control Bits Definitions
*
- * @brief Define the PA LLD Enhanced QoS control code
+ * @brief Bitmap definition of the ctrlBitMap in @ref paEQosModeConfig_t
*
*/
-/** @ingroup PaEQoSCtrlCode_e */
/* @{ */
/**
- * @def pa_IF_EQoS_ROUTE_DSCP_DP_ENABLE
- * Control Info -- Set: DSCP mode enable
- * Clear: DP-bit mode disable
+ * @def pa_IF_EQoS_ROUTE_DP_BIT_MODE
+ * Control Info -- Set: DP-bit mode
+ * Clear: DSCP mode
*/
-#define pa_IF_EQoS_ROUTE_DSCP_DP_ENABLE 0x0001
+#define pa_IF_EQoS_ROUTE_DP_BIT_MODE 0x0001
/**
* @def pa_IF_EQoS_PRIORITY_OVERRIDE_ENABLE
/**
* @ingroup palld_api_structures
- * @brief Enhanced QoS Mode Route offset information. This is per dscp or vlan priority bits
+ * @brief Enhanced QoS Mode Route offset information. This is per dscp or priority bits
*
- * @details paRouteOffset_t specifies the offset for queue and flow
- * with respect to a base Flow and base QoS Queue.
+ * @details paRouteOffset_t specifies the offset for flow and queue
+ * with respect to a base CPPI flow and base QoS Queue.
*/
typedef struct {
- uint8_t flowOffset; /**< Specifies CPPI flow offset for enhanced QoS mode support */
- uint8_t queueOffset; /**< Specifies the destination host queue offset for enhanced QoS mode Support */
+ uint8_t flowOffset; /**< Specifies CPPI flow offset */
+ uint8_t queueOffset; /**< Specifies the destination host queue offset */
} paRouteOffset_t;
/**
* @ingroup palld_api_structures
- * @brief PA emac port configuration parameters.
+ * @brief PA Interfcae based Enhanced QoS mode information
*
- * @details paEmacPortConfig_t is used to configure the emac port for either port mirror Or packet capture, default ingress packet route and
- * enhanced QoS mode. Please refer to individual elements for further details.
+ * @details paEQosModeConfig_t is used to specify the EQoS mode global configuration
+ * parameters of the PASS. Refer to @ref appendix7 for details.
*/
typedef struct {
- uint32_t ctrlBitMap; /**< Specifies the control for egress interface based route as defined in @ref PaEQoSCtrlCode_e */
- union {
- paRouteOffset_t dscpMap[64]; /**< Specifies the DSCP-to-flow/queue offset mapping */
- paRouteOffset_t pbitMap[8]; /**< Specifies the P bit-to-flow/queue offset mapping */
- }u;
+ uint32_t ctrlBitMap; /**< Specifies various EQoS mode control bits as defined in @ref paEQoSCtrlBits */
+ paRouteOffset_t pbitMap[8]; /**< Specifies the Pbit-to-flow/queue offset mapping */
+ paRouteOffset_t dscpMap[64]; /**< Specifies the DSCP-to-flow/queue offset mapping */
+ uint8_t port; /**< Specifies the EMAC port number (1-based) for the EQoS configuration*/
uint8_t ingressDefPri; /**< ingress port default priority */
- uint8_t vlan; /**< Specifies the VLAN to be used/replaced at the output packet */
- uint8_t flowBase; /* Applicable for egress (SoC generated packets) */
- uint16_t queueBase; /* Applicable for egress (SoC generated packets) */
+ uint16_t vlanId; /**< Specifies the VLAN ID to be used/replaced at the egress packet */
+ uint8_t flowBase; /**< Specifies the CPPI flow base for egress (SoC generated) packets */
+ uint16_t queueBase; /**< Specifies the QoS queue base for egress (SoC generated) packets */
} paEQosModeConfig_t;
-
/**
- * @defgroup PaEmacPortCfgCode_e PA EMAC Port config Code
+ * @defgroup paEmacPortCfgType PA EMAC Port Configuration Type
* @ingroup palld_api_constants
* @{
*
- * @name PA EMAC PORT Config Code
+ * @name PA EMAC Port Configuration Type
*
- * @brief Define the PA LLD EMAC PORT config code
+ * @brief Define the PA EMAC port configuration types used at @ref paEmacPortConfig_t
*
*/
-/** @ingroup PaEmacPortCfgCode_e */
/* @{ */
/**
* @def pa_EMAC_PORT_CFG_MIRROR
* port mirror configuration
- * please refer to appendix for details about this mode.
+ * Please refer to @ref appendix5 for details about this operation.
*/
#define pa_EMAC_PORT_CFG_MIRROR 0
/**
* @def pa_EMAC_PORT_CFG_PKT_CAPTURE
* packet capture configuration
- * please refer to appendix for details about this mode.
+ * Please refer to @ref appendix5 for details about this operation.
*/
#define pa_EMAC_PORT_CFG_PKT_CAPTURE 1
/**
* @def pa_EMAC_PORT_CFG_DEFAULT_ROUTE
- * ingress packet default route configuration when there is no L2 match
- * please refer to appendix for details about this mode.
+ * ingress packet default route configuration
+ * Please refer to @ref appendix6 for details about this operation.
*/
#define pa_EMAC_PORT_CFG_DEFAULT_ROUTE 2
/**
- * @def pa_EMAC_PORT_CFG_EQOS_MODE
- * enhanced QoS mode configuration, please refer to appendix for details
- * about this mode.
+ * @def pa_EMAC_PORT_CFG_EQoS_MODE
+ * enhanced QoS mode configuration
+ * please refer to @ref appendix7 for details about this operation.
*/
-#define pa_EMAC_PORT_CFG_EQOS_MODE 3
+#define pa_EMAC_PORT_CFG_EQoS_MODE 3
/* @} */
/** @} */
+/**
+ * @def pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES
+ * The maximum number of emac port configuration entries for interfcae-based EMAC operations.
+ * Please note that this number is limited by the PASS internal memory size and therefore it
+ * may be smaller than the number of available EMAC ports.
+ */
+#define pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES_GEN1 5
+#define pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES_GEN2 9
+
+#ifndef NSS_GEN2
+#define pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES_GEN1
+#else
+#define pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES pa_MAX_NUM_EMAC_PORT_CONFIG_ENTRIES_GEN2
+#endif
/**
* @ingroup palld_api_structures
- * @brief PA emac port configuration parameters.
+ * @brief PA emac port configuration information.
+ *
+ * @details paEmacPortConfig_t is used to specify the interfcae based EMAC port configuration parameters
+ * for the following operations respectively
+ * - EMAC Port Mirroring
+ * - Packet Capture
+ * - Ingress Default Route
+ * - Enhanced QoS Mode
+ *
+ * Please refer to individual operation as described at @ref appendix5, @ref appendix6 and @ref appendix7 for further details.
+ * @note All entries of the port mirror or packet capture array should be in the same direction. The PA LLD will extract the
+ * direction information of the first entry only.
*
- * @details paEmacPortConfig_t is used to configure the emac port for either port mirror Or packet capture, default ingress packet route and
- * enhanced QoS mode. Please refer to individual elements for further details.
*/
typedef struct {
- uint16_t ctrlType; /**< Control type as defined under @ref PaEmacPortCfgCode_e to specify which structure to use under the union */
- uint8_t numEntries; /**< number of port entries to be configured */
- uint8_t egressDefPri; /**< global default priority for untagged non IP egress traffic for enhanced QoS mode */
+ uint16_t cfgType; /**< Specify the EMAC port configuration type as defined at @ref paEmacPortCfgType
+ to specify which structure to use under the union */
+ uint16_t numEntries; /**< Specify number of port entries to be configured */
union {
- paPortMirrorConfig_t *mirrorCfg; /**< pointer to port mirror configuration */
- paPktCaptureConfig_t *pktCapCfg; /**< pointer to packet capture configuration */
- paDefRouteConfig_t *defRouteCfg; /**< pointer to default ingress route configuration structure */
- paEQosModeConfig_t *eQoSModeCfg; /**< pointer to enhanced QoS Mode configuration structure */
+ paPortMirrorConfig_t *mirrorCfg; /**< pointer to port mirror configuration array */
+ paPktCaptureConfig_t *pktCapCfg; /**< pointer to packet capture configuration array */
+ paDefRouteConfig_t *defRouteCfg; /**< pointer to default ingress route configuration array */
+ paEQosModeConfig_t *eQoSModeCfg; /**< pointer to enhanced QoS Mode configuration arary */
}u; /**< Contain the port configuration specific parameters */
} paEmacPortConfig_t;
-
/**
* @defgroup paCtrlCode PA Control Code
* @ingroup palld_api_constants
/**
* @def pa_CONTROL_EMAC_PORT_CONFIG
- * Global EMAC_PORT_CONFIG_configuration
+ * EMAC_PORT_CONFIG configuration
*/
#define pa_CONTROL_EMAC_PORT_CONFIG 4
/**
* @def pa_CONTROL_RA_CONFIG
- * Global RA_configuration
+ * RA configuration
*/
#define pa_CONTROL_RA_CONFIG 5
+/**
+ * @def pa_CONTROL_TIME_OFFSET_CONFIG
+ * This control provides a provision to correct the initial values set for time offsets
+ * during Ethernet Operations And maintenance support
+ */
+#define pa_CONTROL_TIME_OFFSET_CONFIG 6
+
/**
* @def pa_CONTROL_MAX_CONFIG_GEN1
- * maximum pa_CONTROL_CONFIG_GEN1_configuration
+ * Maximum global configuration types on NSS Gen1 devices
*/
#define pa_CONTROL_MAX_CONFIG_GEN1 pa_CONTROL_EMAC_PORT_CONFIG
/**
* @def pa_CONTROL_MAX_CONFIG_GEN2
- * maximum pa_CONTROL_CONFIG_GEN2_configuration
+ * Maximum global configuration types on NSS Gen2 devices
*/
-#define pa_CONTROL_MAX_CONFIG_GEN2 pa_CONTROL_RA_CONFIG
+#define pa_CONTROL_MAX_CONFIG_GEN2 pa_CONTROL_TIME_OFFSET_CONFIG
/* @} */
/** @} */
pa802p1agDetConfig_t pa802p1agDetCfg; /**< Specify 802.1ag Detector configuration parameters */
paIpsecNatTConfig_t ipsecNatTDetCfg; /**< Specify IPSEC NAT-T Detector configuration parameters */
paGtpuConfig_t gtpuCfg; /**< Specify GTP-U configuration parameters */
- paRaConfig_t raCfg; /**< Specify RA global configuration information (PASS Gen2 only) */
paEmacPortConfig_t emacPortCfg; /**< Specify interface based port configuration information */
+ paRaConfig_t raCfg; /**< Specify RA global configuration information (PASS Gen2 only)
+ @note RA global configuration does not require command buffer. */
+ paSetTimeOffset_t tOffsetCfg; /**< Specify Ethernet OAM time stamp offset information (PASS Gen2 only) */
}params; /**< Contain the control operation specific parameters */
} paCtrlInfo_t;
} paAclStats_t;
-
/**
* @ingroup palld_api_structures
* @brief PA Timestamp Structure
*
- * This structure defines the 48-bit timestamp provided upon request with @ref Pa_getTimestamp ().
+ * This structure defines the 64-bit system timestamp provided upon request with @ref Pa_getTimestamp ().
+ * ---------------------------------------
+ * | 16 bits | 32 bits | 16 bits |
+ * | hi_hi | hi | lo |
+ * ---------------------------------------
+ *@note: The structure is updated to have upper 16 bit (hi_hi) to be backwards compatible with 48-bit
+ * timestamp support
*/
typedef struct {
- uint32_t hi; /**< Upper 32 bits of the 48-bit PASS timestamp */
- uint16_t lo; /**< Lower 16 bits of the 48-bit PASS timestamp */
+ uint16_t hi_hi; /**< Upper Upper 16 bits of the 64-bit PASS timestamp */
+ uint32_t hi; /**< Upper 32 bits of the 64-bit PASS timestamp */
+ uint16_t lo; /**< Lower 16 bits of the 64-bit PASS timestamp */
} paTimestamp_t;
-
/**
* @defgroup paApiParamValidBits PA API Parameter Valid Bit Definitions
* @ingroup palld_api_constants
*/
#define pa_PARAM_VALID_NEXTLINK (1<<3)
+/**
+ * @def pa_PARAM_VALID_CTRLBITMAP
+ * - Set: there is a valid control bit map
+ * - Clear: control bit map is not valid
+ * @note: this is applicable for Gen1 only since LUT1 ordering is no longer a problem in Gen2
+ */
+#define pa_PARAM_VALID_CTRLBITMAP (1<<4)
+
/* @} */ /* ingroup */
/** @} */
+/**
+ * @defgroup paApiParamCtrlBits PA API Parameter Control Bit Definitions
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA API Parameter Control Bit Definitions
+ *
+ * Bitmap definition of the ctrlBitMap in @ref paParamDesc.
+ */
+/*@{*/
+
+/**
+ * @def pa_PARAM_CTRL_REPLACE
+ * - Set: Application specifies the replace index for LUT1 entry (0-63).
+ * - Clear: No replace action
+ * @note: applicable for Gen1 only
+ */
+#define pa_PARAM_CTRL_REPLACE (1<<0)
+
+/* @} */ /* ingroup */
+/** @} */
/**
* @ingroup palld_api_structures
* @brief PA API parameters structure
*
- * @details This structure define the common parameters of the next generation APIs such as
+ * @details This structure defines the common parameters of the next generation APIs such as
* @ref Pa_addMac2 and @ref Pa_addIp2. This structure includes a validBitMap of
* optional parameters so that it can evolve while maintaining backward-compatibility.
*
*/
typedef struct {
uint32_t validBitMap; /**< 32-bit bitmap corresponding to usage of each optional field */
+ uint32_t ctrlBitMap; /**< 32-bit bitmap corresponding to usage of each control field */
int lutInst; /**< validBitMap[t0] Specify which LUT1 (0-2) should be used. */
int index; /**< validBitMap[t1] Specify the index of the LUT1 entry (0-63).*/
paLnkHandle_t prevLink; /**< validBitMap[t2] An optional L2 or L3 handle, or virtual link handle */
* @param[in] iHandle The driver instance handle
* @param[in] ethInfo Value @ref paEthInfo2_t
* @param[in] params Common API parameters @ref paParamDesc
- * @param[out] retHandle Pointer to L2 Handle
+ * @param[in,out] retHandle Pointer to L2 Handle. LLD puts the allocated L2 handle in this location. During
+ * L2 replace operation, this parameter would point to the L2 handle to be replaced.
* @param[out] cmd Where the created command is placed
* @param[in,out] cmdSize Input the size of cmd buffer, on output the actual size used. @ref cmdMinBufSize
* @param[in] reply Where the sub-system sends the command reply
paCmd_t cmd,
uint16_t *cmdSize,
paCmdReply_t *reply,
- int *cmdDest
- );
+ int *cmdDest);
+
+/**
+ * @ingroup palld_api_functions
+ * @brief Pa_addEoamFlow adds an Ethernet OAM target flow entry to the EOAM table
+ *
+ * @details A new entry is added if the EOAM flow configuration info is unique in the modules handle table. If
+ * the value is not unique then the routing information for the existing entry is changed to
+ * the values provided in the function.
+ *
+ * On return the command buffer (cmd) contains a formatted command for the sub-system. The
+ * destination for the command is provided in cmdDest. The module user must send the formatted
+ * command to the sub-system. The sub-system will generate a reply
+ * and this reply must be sent back to this module through the @ref Pa_forwardResult API.
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ * @param[in] iHandle The driver instance handle
+ * @param[in] ethInfo Value @ref paEthInfo2_t
+ * @param[in] eoamInfo Ethernet OAM target flow information
+ * @param[out] handle Pointer to EOAM Handle. LLD puts the allocated EOAM handle in this location.
+ * @param[out] cmd Where the created command is placed
+ * @param[in,out] cmdSize Input the size of cmd buffer, on output the actual size used. @ref cmdMinBufSize
+ * @param[in] reply Where the sub-system sends the command reply
+ * @param[out] cmdDest Value (@ref cmdTxDest)
+ * @retval Value (@ref ReturnValues)
+ * @pre A driver instance must be created and tables initialized, Ethernet OAM System Configuration
+ * and EOAM timer offset configurations are complete.
+ *
+ */
+
+paReturn_t Pa_addEoamFlow (Pa_Handle iHandle,
+ paEthInfo2_t *ethInfo,
+ paEoamFlowInfo_t *eoamInfo,
+ paHandleEoam_t *handle,
+ paCmd_t cmd,
+ uint16_t *cmdSize,
+ paCmdReply_t *reply,
+ int *cmdDest);
+
/**
* @ingroup palld_api_functions
paCmdReply_t *reply,
int *cmdDest );
+/**
+ * @ingroup palld_api_functions
+ * @brief Pa_delEoamHandle deletes an EOAM handle
+ *
+ * @details This function is used to remove an entry from the LUT1-EOAM lookup
+ * Please refer to @ref appendix8 for details about EOAM mode.
+ *
+ * @param[in] iHandle The driver instance handle
+ * @param[in] handle Pointer to the EOAM handle to delete
+ * @param[out] cmd Where the created command is placed
+ * @param[in] cmdSize The size of the cmd buffer
+ * @param[in] reply Where the sub-system sends the command reply
+ * @param[out] cmdDest Value (@ref cmdTxDest)
+ * @retval Value (@ref ReturnValues)
+ * @pre A driver instance must be created and tables initialized
+ */
+paReturn_t Pa_delEoamHandle (Pa_Handle iHandle,
+ paHandleEoam_t *handle,
+ paCmd_t cmd,
+ uint16_t *cmdSize,
+ paCmdReply_t *reply,
+ int *cmdDest );
+
+
/**
* @ingroup palld_api_functions
* @brief Pa_addIp adds an IP address to the L3 table
* @retval Value (@ref ReturnValues)
* @pre A driver instance must be created and tables initialized
*
- * @note No table entry validation will be proformed if the LUT1 index is specified at this function
+ * @note No table entry validation will be proformed if the LUT1 index is specified at this function.
+ *
+ * @note When ipInfo (@ref paIpInfo_t) has only SPI, prevLink parameter is recommended
+ * to be set for Gen1 and mandatory for Gen2 due to hardware limitations.
*
*/
paReturn_t Pa_addIp ( Pa_Handle iHandle,
* @param[in] iHandle The driver instance handle
* @param[in] ipInfo Value @ref paIpInfo2_t
* @param[in] params Common API parameters @ref paParamDesc
- * @param[out] retHandle Pointer to L3 Handle
+ * @param[in,out] retHandle Pointer to L3 Handle. LLD puts the allocated L3 handle in this location. During
+ * L3 replace operation(Gen1 only), this parameter would point to the L3 handle to be replaced.
* @param[out] cmd Where the created command is placed
* @param[in,out] cmdSize Input the size of cmd buffer, on output the actual size used. @ref cmdMinBufSize
* @param[in] reply Where the sub-system sends the command reply
* @param[out] cmdDest Value (@ref cmdTxDest)
* @retval Value (@ref ReturnValues)
* @pre A driver instance must be created and tables initialized
+ *
+ * @note When ipInfo (@ref paIpInfo2_t) has only SPI, prevLink parameter in @ref paParamDesc is recommended
+ * to be set for Gen1 and mandatory for Gen2 due to hardware limitations.
*/
paReturn_t Pa_addIp2 ( Pa_Handle iHandle,
paIpInfo2_t *ipInfo,
* @param[in] cmdSize The size of the cmd buffer
* @param[in] reply Where the response to the PASS command is routed
* @param[out] cmdDest Value (@ref cmdTxDest)
+ * @param[out] timeToNextCall Time in microseconds to indicate that this API is not available until this time elapses
* @retval Value (@ref ReturnValues)
* @pre A driver instance must be created and tables initialized
*
paCmd_t cmd,
uint16_t *cmdSize,
paCmdReply_t *reply,
- int *cmdDest );
+ int *cmdDest,
+ uint32_t *timeToNextCall);
/**
* @defgroup paLut2PortSize LUT2 Port Size Values
/**
* @ingroup palld_api_functions
- * @brief Pa_getTimestamp returns the 48-bit system timestamp
+ * @brief Pa_getTimestamp returns the 64-bit system timestamp
*
- * @details This function is called to retrieve the current value of 48-bit PASS system timestamp.
+ * @details This function is called to retrieve the current value of 64-bit PASS system timestamp.
*
* @param[in] iHandle The driver instance handle
- * @param[out] pTimestamp Pointer to the 48-bit timestamp
+ * @param[out] pTimestamp Pointer to the 64-bit timestamp
* @retval Value (@ref ReturnValues)
* @pre A driver instance must be created and tables initialized
*
*/
paReturn_t Pa_getDbgpInfo(Pa_Handle iHandle, paSnapShotDebugInfo_t *dbgInfo);
+
+/**
+ * @ingroup palld_api_functions
+ * @brief Pa_getVirtualLinkId provides the hooks to get the virtual link id
+ *
+ * @details This function is used to get the virtual link ID information from the handle
+ *
+ * @param[in] iHandle The driver instance handle
+ * @param[in] vlinkHdl Pointer to the virtual link handle
+ * @param[out] lnkId virtual link ID from the virtual link handle
+ * @retval Value (@ref ReturnValues)
+ * @pre A driver instance must be created and tables initialized
+ *
+ * @note: This API provides the snap shot information only, the actual values may differ
+ * after the snap shot
+ */
+paReturn_t Pa_getVirtualLinkId(Pa_Handle iHandle, paLnkHandle_t vlinkHdl, int8_t* lnkId);
+
/**
* @ingroup palld_api_functions
* @brief Pa_formatStatsReply formats the stats reply from the PA (PASS Gen1 only)
*/
const char* Pa_getVersionStr (void);
+/**
+ * @ingroup palld_api_functions
+ * @brief Pa_getLUT1Info returns the LUT1 information.
+ *
+ * @details This function is used to get the lut1 information associated with the L2L3handle
+ *
+ * @param[in] iHandle The driver instance handle
+ * @param[in] l2l3handle LLD l2l3handle
+ * @param[out] lut1Info The pointer to lut1Information structure
+ * @retval Value (@ref ReturnValues)
+ * @pre The PDSP image should be downloaded successfully.
+ *
+ */
+paReturn_t Pa_getLUT1Info ( Pa_Handle iHandle,
+ paHandleL2L3_t l2l3handle,
+ paLUT1Info_t *lut1Info);
+
+
/**
* @ingroup palld_api_macros
* @brief pa_RESET_SUBSYSTEM is used to reset the Sub-system
/**
* @page appendix5 Port Mirror and Packet Capture Operation
*
- * The current version of PASS supports port mirroring OR packet capture feature.
+ * The current version of CPSW within NetCP does not support port mirroring feature. The PA LLD and the PASS firmware have been
+ * enhnaced to support EMAC port mirroring operation OR EMAC port packet capture feature.
*
- * When Port Mirror configuration is enabled, one of the ethernet ports can be configured as mirror port. Mirror port receives and transmits
- * ethernet traffic as normal and other non-mirror ports can be configured to have its traffic mirrored or not. A port that has its
- * traffic \93mirrored\94 means that all traffic to and from this port can also be transmitted (mirrored) to the mirror port. PA supports
- * individual ingress and egress control of the directions to be mirrored. The mirror port can never be mirrored. It is the responsibility of the
- * higher level software to take care of this condition to avoid recursion and undesired effects.
- * Packets are mirrored excatly as they are received/transmitted. No additional mac header or
+ * When Port Mirror configuration is enabled, some of the ethernet ports can be configured as mirror ports. Mirror port receives
+ * and transmits ethernet traffic as normal and other non-mirror ports can be configured to have its traffic mirrored to any
+ * mirror port. A port that has its traffic mirrored means that all traffic to and/or from this port can also be transmitted
+ * (mirrored) to its mirror port. PA supports individual ingress and egress control of the EMAC port to be mirrored. The mirror port
+ * itself can never be mirrored. It is the responsibility of the higher level software to take care of this condition to avoid
+ * recursion and undesired effects. Packets are mirrored excatly as they are received/transmitted. No additional mac header or
* equivalent is placed on these packets.
*
- * In addition, a releated feature to support packet capture is also supported for ingress and egress packets. This feature is valid only if port
- * mirroring is not in use and if it is enabled on an interface. The feature works in a similar fashion to port mirroring except that the captured
- * packet will be copied and sent to a configured hardware queue.
+ * In addition, PASS also supports the packet capture feature which is valid only if port mirroring is not in use and if it is enabled
+ * on an interface. The feature works in a similar fashion to port mirroring except that the captured packet will be copied and sent to
+ * a configured hardware queue instead of the mirror port.
*
- * The host software should enable either the port mirror or packet capture on that interface using @ref Pa_control API. A global system configuration
- * is required to enable the feature system wide.
- *
- * @note The design assumes that the port mirroring feature is not required when the device is operating with the CPSW switch active (i.e., bypass disabled)
- * or in a NETCP bridge or s/w bridge mode.
+ * The host software should enable and configure either the port mirror or packet capture operation on that interface using @ref Pa_control API.
+ * And global system configuration is required to enable those features system wide.
*
+ * @note The design assumes that the port mirroring feature is not required when the device is operating with the CPSW switch active
+ * (i.e., ALE bypass disabled) or in a NETCP bridge or s/w bridge mode.
*/
/**
* @page appendix6 Ingress Default Route Operation
- * This rule provides the default route configurations for ingress packets that do not match L2 look up. These features can be globally enabled or disabled using @ref paPacketControl2Config_t configuration.
- * - This rule preceeds the exception route rule.
- * - When the default route configuration is added, it provides the default routes for multicast, broadcast and no match unicast packets.
- * and no match unicast packets.
- * - The rule does not kick into effect if there is a L2 entry to look up multicast/broadcast packets.
+ * The feature allows the host to configure PASS to send all packets with broadcast bit set (bit 0 of 1st mac header byte) from ingress port X
+ * to a corresponding route before or after the LUT look up. The ingress default route provides the route configurations for ingress broadcast(BC)
+ * and multicast(MC) packets and the unicast packets that do not match L2 entries on an EMAC interface as described below.
+ * - Route BC/MC traffics prior to LUT1 lookup if configured as pre-classification route
+ * - Route unmatched BC/MC traffics from EMAC port X if configured as post-classification route
+ * - Route unmatched unicast traffic from EMAC port X if configured
+ * - This rule precedes the exception route rule.
* - These features can be globally enabled or disabled using @ref paPacketControl2Config_t configuration along with per interface configurations.
*
- * @note When this feature is enabled, the exception route multicast/broadcast/unicast packets is no longer handled.
+ * @note When this feature is enabled, the exception routes for multicast/broadcast/unicast packets will not be used..
*
*/
/**
- * @page appendix7 Enhanced QoS Mode2 Operation
- * This feature supports the packet forwarding algorithm per egress ethernet interface port in the PASS to support QoS routing scheme using either packet VLAN p-bits or IP DSCP to index
- * off a base shaper queue and flow numbers. These features can be globally enabled or disabled using @ref paPacketControl2Config_t configuration.
+ * @page appendix7 Enhanced QoS Mode Operation
+ * Enhanced QoS mode is an advanced priority-based routing algorithm where VLAN P-bit, IP DSCP or the EMAC port-based default priority
+ * is used to determine the destination QoS queue and CPPI flow. This routing algorithm is required to support egress L2 shaper and is
+ * described in details here.
*
- * The algorithm to support the enhanced QoS Mode2 is as below:
- *
- * Case 1: Support egress interface based routing for ingress packets
- * @li Maintain configurations per egress port - refer to ctrlBitMap of @ref TBD structure
+ * For each EMAC interface, PASS will be configured for:
+ * - Base queue (egress only)
+ * - Base flow (egress only
+ * - DSCP_MAP[] {one entry (= flow offset /queue offset) for each DSCP value, 64 total}
+ * - VLAN_PRIORITY_MAP[] { one entry (= flow offset/queue offset) for each P-bit value, 8 total}
+ * - Default priority to use per the ingress interface
+ * - Routing mode: P-bit or DSCP
+ * - PriorityOverride: True/False
*
* Routing algorithm supports two modes and is described as below:
- * - DP-bit mode:
- * - If VLAN exists, set priority to the VLAN DP-bit
- * - Else if IP exists and the priority override bit is not set, set priority to dscpPriMap[dscp]
- * - Else set priority to defPri
- * - Forward the packet based on the routing parameters specified by routeTbl[priority].
- * - DSCP mode:
- * - If IP exists, set priority to dscpPriMap[dscp]
- * - Else set priority to defPri
- * - Forward the packet based on the routing parameters specified by routeTbl[priority].
- *
- * Case 2: Support egress interface based routing for egress (SoC-generated) packets.
- * @li Maintain the configuration per egress port
- * @li The routing algorithm requires configuration for NETCP to include offset to VLAN header (if present or NULL), offset to DSCP bits (or NULL if not IP), egress port
- * ingress port (or special value for SoC generated packets), command label indicating enhanced QoS mode2 to be performed on the packet.
*
- * Routing algorithm supports two modes:
* - DP-bit mode:
- * - If frame has VLAN tag, use p-bits to lookup shaper input queue # from the VLAN_PRIORITY_MAP[] for the frame\92s egress port
- * - If frame is un-tagged, but is an IP packet, use the DSCP value to lookup the shaper input queue from the DSCP_MAP[] for the frame\92s egress port unless priority override is set for the egress port (see last bullet below).
- * - If frame is un-tagged, and non-ip , then use the default priority for the frame\92s ingress port to look up the shaper input queue from the egress port\92s VLAN_PRIORITY_MAP[]. For SOC-generated traffic, the default priority is a separate configuration item.
- * - If priority override is set and the packet is IP then do as in un-tagged/non-ip ( above bullet).
+ * - If frame has VLAN tag, use p-bits to lookup shaper input queue # from the VLAN_PRIORITY_MAP[] for the frame's egress port
+ * - If frame is un-tagged, but is an IP packet, use the DSCP value to lookup the shaper input queue # from the DSCP_MAP[]
+ * for the frame's egress port unless priority override is set for the egress port (see last bullet below).
+ * - If frame is un-tagged, and non-ip , then use the default priority for the frame's ingress port to look up the shaper input queue from
+ * the egress port's VLAN_PRIORITY_MAP[]. For SOC-generated traffic, the default priority is a separate global configuration item.
+ * - If priority override is set and the packet is IP then do as in un-tagged/non-ip (above bullet).
* - DSCP mode:
- * - IP packets: use the packet DSCP bits and the DSCP_MAP [] for the egress port as above to determine the L2 shaper queue to use
- * - Non-ip packets: use the default priority for the frame\92s ingress port to look up the shaper input queue from the egress port\92s VLAN_PRIORITY_MAP[]. For SOC-generated traffic, the default priority is a separate configuration item.
+ * - If frame is an IP packet, use the DSCP value and the DSCP_MAP [] for the egress port as above to determine the L2 shaper queue to use
+ * - For non-ip packets, use the default priority for the frame's ingress port to look up the shaper input queue from the egress port's
+ * VLAN_PRIORITY_MAP[]. For SOC-generated traffic, the default priority is a separate global configuration item.
* - Priority override setting is not applicable in this mode.
*
*/
-
+/**
+ * @page appendix8 Ethernet OAM (EOAM) Mode Operation
+ * EOAM mode is a new mode of operation that includes the EOAM classification and new packet flow as described below.
+ * The Ingress0-PDSP1 LUT1, is utilized to support Ethernet OAM (EOAM) target flow classification instead of the
+ * firewall of outer IP and Ingress3-PDSP0, is enhanced to filter both outer IP/UDP and inner IP/UDP.
+ *
+ * During EOAM classification, packets are inspected for a specific target flow match based on any group
+ * of Destination MAC address, Source MAC address, VLAN priority, VLAN ID and Ethernet PORT id.
+ * Each target flow is associated with the corresponding "user defined statistics counter".
+ * When the target flow match happens, a statistics update happens as per the "statistics update algorithm" described as below.
+ * Further, during the match if the message type/PDU found to be 1DM/DMM/DMR/LMM/LMR PALLD provides configurations to forward that packet to a
+ * host queue.
+ *
+ * - For IPSec transport mode, Ingress 3 would filter the IP/UDP header
+ * - For IPSec tunnel mode, Ingress 3 would filter the inner IP/UDP header
+ * - For a non-cipher packet, Ingress 3 would filter the IP/UDP header
+ * - IP over IP is NOT supported during this mode.
+ *
+ * The above feature can be utilized to compute the "delay measurements" and/or "Ethernet loss measurements" on 1DM/DMM/DMR/LMM/LMR PDU types as
+ * defined in protocols such as Y.1731 (Please refer to ITU-T specification "http://www.itu.int/rec/T-REC-Y.1731-200605-S/en" for further details on Y.1731)
+ *
+ * - PASS actions for 1DM/DMM/DMR PDU types
+ * - Send Direction
+ * - Patches the 8 bytes of 1588 formatted timestamp information to the specified field of the message as per the Tx command initiated by the upper layer and forward the packet to configured destination
+ * - Receive Direction
+ * - Checks for valid measurement to route to specified queue for this flow and puts the 64 bit PA time stamp in the PSINFO fields of the message
+ *
+ * - PASS actions for LMM/LMR PDU types
+ * - Send Direction
+ * - Patches the 4 bytes of specified 32-bit user defined counter values to the specified filed of message as per the Tx command initiated by the upper layer and forward the packet to configured destination
+ * - Receive Direction
+ * - Checks for valid measurement to route to specified queue for this flow and puts the 64 bit PA time stamp in the PSINFO fields of the message
+ * - Also, provide the 4 byte receive packet counter associated with this target flow to PS_INFO fields of the message
+ *
+ * - Statistics update algorithm in Rx direction
+ *
+ * PA LLD along with firmware for GEN2 supports upto 8 protocols to be excluded from EOAM target flow statistics even though the match happens. The pseudo code showing the packet statistics update is as below.
+ *
+ * @code
+ * decision statsUpdateDecision(rxEthType, rxMEGLevel, rxPktOpcode, pktExcludeProtolist, TabMEGLevel)
+ * {
+ * if (rxEthType in pktExcludeProtolist)
+ * {
+ * return (noStatisticsUpdate);
+ * }
+ * if (rxEthType is 0x8902)
+ * {
+ * if (rxMEGLevel > TabMEGLevel)
+ * {
+ * return (needStatisticsUpdate);
+ * }
+ * else if (rxMEGLevel < TabMEGLevel)
+ * {
+ * return (noStatisticsUpdate);
+ * }
+ * else
+ * {
+ * if (rxPktOpcode is (Y1731_APS_OPCODE OR Y1731_OPCODE_CCM) )
+ * {
+ * return (needStatisticsUpdate);
+ * }
+ *
+ * return (noStatisticsUpdate);
+ * }
+ * }
+ * }
+ * @endcode
+ *
+ * The new packet flow during EOAM mode is as described in below table.
+ *
+ * \image html packetflow.gif
+ *
+ */
+
+
+/**
+ * @page appendix9 Destination Queue Bounce Operation
+ *
+ * There is a hardware deficiency identified at the Keystone2 devices where memory consistency is not guaranteed for
+ * IO coherent A15 and PktDMA masters at some rare conditions. Therefore it is possible that the data arrival signal
+ * to the ARM (i.e., presence of a descriptor in QMSS queue) may occur prior to the data arriving properly in the
+ * ARM cache. Thus, the ARM core may access stale data.
+ * To ensure ARM Cache consistency, one of the QMSS PDSP is enhanced to provide a DMA barrier function. Packets destined
+ * to ARM queues may be delivered first to one of the QMSS "bounce" queues serviced by this function. The QMSS PDSP f/w
+ * will pop packets from these queues, perform the necessary barrier operation (that will cause the ARM cache to get
+ * invalidated for the descriptor and buffer locations), and then will relay the packet to the final destination queue.\r
+ *
+ * The Destination Queue Bounce Operation is designed to enable the QMSS proxy bounce on packets PA sends to queues
+ * served by ARM user space by embedding 2 control bits into the destination queue ID to instruct the PASS firmware
+ * to re-route the packets to the specified QMSS bounce queues.
+ *
+ * This operation can be enabled and configured by a global configuration message including the following parameters:
+ * - Enable/Disable
+ * - QMSS Bounce Queue IDs
+ * - DDR Queue: All PktMDA descriptors and buffers use DDR memory only
+ * - MSMC Queue: PktDMA descriptor and buffers may use MSMC memory and/or DDR memory
+ * - Default Behavior map []: Specify the default queue bounce operation for each traffic class such as Command Response
+ * and ingress QoS routing
+ * - NetCP hardware queue info
+ * - Number of NetCP queue
+ * - NetCP queue base
+ *
+ * The Destination Queue Bounce operation is described below in details:
+ * - When the queue bounce feature is disabled, all PA LLD APIs work as before and the two control bits of the destination
+ * queue ID will be cleared.
+ * - When the queue bounce feature is enabled, the application may invoke the following PA Macros to specify the
+ * queue ID in PA LLD APIs:
+ * - PA_BOUNCE_QUEUE_DDR(queueId): Bounce to DDR queue
+ * - PA_BOUNCE_QUEUE_MSMC(queueId): Bounce to MSMC queue
+ * - PA_BOUNCE_QUEUE_NONE(queueId): No Bounce
+ * Or the application may allow the LLD to specify the embedded destination queue ID based on the default behavior map
+ * by invoking the following PA Macro optionally
+ * - PA_BOUNCE_QUEUE_DEFAULT(queueId): Use default behavior map by cleraing the two control bits
+ *
+ * @note PA_BOUNCE_QUEUE_DEFAULT() is a no-operation, so if queueid is used as is, then default behavior rule will be applied automatically
+ * @note For any SOC h/w queues (as indicated to PA in global configuration), all bounce settings are ignored so that packets to these queues
+ * will never be bounced to the barrier function.
+ */
+
#ifdef __cplusplus
}
#endif