--- a/pa.h
+++ b/pa.h
*/
#define pa_SUB_SYSTEM_BASE_ADDR_NULL -42
+
+/**
+ * @def pa_LUT2_TABLE_FULL
+ * PASS LUT2 Table is full, no more entries can be added unless an
+ * entry is deleted to create a room to a next entry
+ */
+#define pa_LUT2_TABLE_FULL -43
+
+
/*@}*/
/** @} */
* The minmium command buffer size allowed when using the @ref Pa_control (pa_CONTROL_SYS_CONFIG) function to perform PASS
* global configuration.
*/
-#define pa_GLOBAL_CONFIG_MIN_CMD_BUF_SIZE_BYTES 104
+#define pa_GLOBAL_CONFIG_MIN_CMD_BUF_SIZE_BYTES 108
/**
* @def pa_802_1ag_DET_MIN_CMD_BUF_SIZE_BYTES
paEoamTfExcCtrlConfig_t statsCtrl; /**< Ethernet OAM target flow exclusion protocol control @ref paEoamTfExcCtrlConfig_t */
} paEoamGlobalConfig_t;
+/**
+ * @defgroup paQueueBounceRoutingClass PA Queue Bounce Routing Class
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Queue Bounce Routing Class
+ *
+ * Definition of PA Queue Bounce Routing Classes
+ */
+/** @ingroup paQueueBounceRoutingClass */
+/*@{*/
+typedef enum {
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_CMD_RET = 0, /**< Command Return */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_QoS, /**< Ingress QoS Packets */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_CAPTURE, /**< Packet Capture */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_IP_REASSEMBLY, /**< IP Reassembly-assisted packets */
+ pa_QUEUE_BOUNCE_ROUTING_CLASS_MISC, /**< All other Traffic */
+ PA_MAX_QUEUE_BOUNCE_ROUTING_CLASSES
+}paQueueBounceRoutingClass_e ;
+/*@}*/
+/** @} */
+
+/**
+ * @defgroup paQueueBounceOperationTypes PA Queue Bounce operation modes
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Queue Bounce operation modes
+ * @brief Define the Queue Bounce operation modes.
+ */
+/* @{ */
+/**
+ * @def pa_QUEUE_BOUNCE_OP_NONE
+ * No bounce, use the user specified destination queue as it is
+ */
+#define pa_QUEUE_BOUNCE_OP_NONE 0
+
+/**
+ * @def pa_QUEUE_BOUNCE_OP_DDR
+ * Add control bits to indicate bouncing to the DDR Queue
+ */
+#define pa_QUEUE_BOUNCE_OP_DDR 1
+
+/**
+ * @def pa_QUEUE_BOUNCE_OP_MSMC
+ * Add control bits to indicate bouncing to the MSMC queue
+ */
+#define pa_QUEUE_BOUNCE_OP_MSMC 2
+
+
+/**
+ * @def pa_QUEUE_BOUNCE_OP_MAX
+ * Number of Queue Bounce Operation modes
+ */
+#define pa_QUEUE_BOUNCE_OP_MAX pa_QUEUE_BOUNCE_OP_MSMC
+/*@}*/
+/** @} */
+
+/**
+ * @ingroup palld_api_structures
+ * @brief PA Queue Bounce Configuration Information.
+ *
+ * @details paQueueBounceConfig_t is used to configure the PA Queue Bounce operation as described at @ref appendix9.
+ *
+ * @note The Queue Bounce Configuration should be specified at PA system initialization and only once. The dynamic
+ * re-configuration is not supported and may cause undefined behaviors.
+ */
+typedef struct {
+
+ uint32_t enable; /**< Enable/Disable(1/0) Queue Bounce operation, default = 0 (disable) */
+ uint16_t ddrQueueId; /**< Bounce queue where PASS will deliver the host-routed packet with DDR bit set */
+ uint16_t msmcQueueId; /**< Bounce queue where PASS will deliver the host-routed packet with MSMC bit set */
+ uint16_t hwQueueBegin; /**< Queue number of the first NetCP hardware queue */
+ uint16_t hwQueueEnd; /**< Queue number of the last NetCP hardware queue */
+ uint16_t defOp[PA_MAX_QUEUE_BOUNCE_ROUTING_CLASSES]; /**< Default Queue Bounce operations per class */
+
+} paQueueBounceConfig_t;
+
+/**
+ * @defgroup paQueueBounceControlBits PA Queue Bounce Control Bits and related definitions
+ * @ingroup palld_api_constants
+ * @{
+ *
+ * @name PA Queue Bounce Control Bits
+ * @brief PA Queue Bounce Control Bits and related definitions
+ */
+/* @{ */
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_DEFAULT
+ * Use default rule
+ */
+#define pa_QUEUE_BOUNCE_CTRL_DEFAULT 0
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_DDR
+ * Bounce to the DDR Queue
+ */
+#define pa_QUEUE_BOUNCE_CTRL_DDR 1
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_MSMC
+ * Bounce to the MSMC queue
+ */
+#define pa_QUEUE_BOUNCE_CTRL_MSMC 2
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_NONE
+ * No bounce, clear the control bits
+ */
+#define pa_QUEUE_BOUNCE_CTRL_NONE 3
+
+/**
+ * @def pa_QUEUE_BOUNCE_CTRL_LOC
+ * Bit location of the queue bounce control bits
+ */
+#define pa_QUEUE_BOUNCE_CTRL_LOC 14
+
+/**
+ * @def pa_QUEUE_BOUNCE_QUEUE_MASK
+ * Actual queue number mask
+ */
+#define pa_QUEUE_BOUNCE_QUEUE_MASK 0x3FFF
+
+/*@}*/
+/** @} */
+
+/**
+ * @defgroup PA_queue_bounce_op_macros PA Queue Bounce Operation Macros
+ * @ingroup palld_api_macros
+ * @{
+ * @name PA Queue Bounce Operation Macros
+ * Macros used by the PA Queue Bounce Operation to insert/clear control bits
+ */
+/*@{*/
+#define PA_BOUNCE_QUEUE_DDR(queueId) (((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) | (pa_QUEUE_BOUNCE_CTRL_DDR << pa_QUEUE_BOUNCE_CTRL_LOC)) /**< Insert control bits to indicate DDR queue bouncing */
+#define PA_BOUNCE_QUEUE_MSMC(queueId) (((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) | (pa_QUEUE_BOUNCE_CTRL_MSMC << pa_QUEUE_BOUNCE_CTRL_LOC)) /**< Insert control bits to indicate MSMC queue bouncing */
+#define PA_BOUNCE_QUEUE_NONE(queueId) (((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) | (pa_QUEUE_BOUNCE_CTRL_NONE << pa_QUEUE_BOUNCE_CTRL_LOC)) /**< Incert control bits to indicate no queue bouncing */
+#define PA_BOUNCE_QUEUE_DEFAULT(queueId) ((queueId) & pa_QUEUE_BOUNCE_QUEUE_MASK) /**< Clear control bits to indicate default operation */
+
+/*@}*/ /* PA_queue_bounce_op_macros */
+/** @}*/ /* PA Queue Bounce Operation Macros */
+
/**
* @ingroup palld_api_structures
* @brief PA System Configuration Information structure
paUsrStatsConfig_t* pUsrStatsConfig; /**< Pointer to the user-defined statistics configuration structure */
paQueueDivertConfig_t* pQueueDivertConfig; /**< Pointer to the queue-diversion configuration structure */
paPacketControlConfig_t* pPktControl; /**< Pointer to the packet control configuration structure */
+ paQueueBounceConfig_t* pQueueBounceConfig; /**< Pointer to the Queue Bounce configuration structure */
paAclConfig_t* pOutAclConfig; /**< Pointer to the outer ACL configuration structure */
paAclConfig_t* pInAclConfig; /**< Pointer to the inner ACL configuration structure */
paRaGroupConfig_t* pOutIpRaGroupConfig; /**< Poimter to the outer IP Reassembly group configuration structure */
paRaGroupConfig_t* pInIpRaGroupConfig; /**< Poimter to the inner IP Reassembly group configuration structure */
- paPacketControl2Config_t* pPktControl2; /**< Pointer to the packet control 2 configuration structure */
+ paPacketControl2Config_t* pPktControl2; /**< Pointer to the packet control 2 configuration structure */
paEoamGlobalConfig_t* pEoamConfig; /**< Pointer to the EOAM Global configuration structure */
} paSysConfig_t;
*/
#define pa_CMD_PATCH_COUNT 20
+/* @def pa_CMD_EMAC_CRC_VERIFY
+ * Perfrom the Ethernet CRC verification for egress traffic. (Applicable only for Gen1)
+ * Refer to the description of data structure @ref paCmdEmacCrcVerify_t for details.
+ */
+
+#define pa_CMD_EMAC_CRC_VERIFY 21
/* @} */
/** @} */
uint32_t swInfo0; /**< Placed in SwInfo0 for packets to host */
} paCmdVerifyPktErr_t;
+/**
+ * @ingroup palld_api_structures
+ * @brief EMAC CRC Verification information
+ *
+ * @details paCmdEmacCrcVerify_t is used to create the EMAC CRC verification command which is used to instruct the PASS to
+ * perform Ethernet CRC verification for forwarding to-network traffic. The egress packet with this command is
+ * expected to be a forwarding Ethernet packet with CRC. PASS will perform CRC verification against the CRC
+ * value at the packet, if CRC is good, the packet will be forwarded to the desired EMAC port and if CRC
+ * is bad, then the packet will be dropped.
+ * Application should invoke Pa_configCrcEngine() API to format the CRC configuration packet for Ethernet CRC and
+ * then forward configuration packet to Tx command prtocessing PDSP (PDSP5) before this command is used.
+ *
+ * This command is used to provide a workaround for following GbE errata at some keystone devices:
+ *
+ * The GbE switch may drop packets in TX path when:
+ * - full gigabit speeds are sustained and
+ * - the packet size is not a 32 bit multiple (1499, 1498, 1497, 1495, etc.) and
+ * - Ethernet CRC is included in the last 4 bytes of the packet sent to the switch
+ *
+ * @note The Ethernet CRC Verify command can not be combined with any other tx commands, all other commands will be ignored
+ * by PASS when this command is processed.
+ *
+ */
+
+typedef struct {
+ uint16_t emacPort; /**< Specify the output EMAC port number as define at @ref paEmacPort. */
+} paCmdEmacCrcVerify_t;
+
/**
* @defgroup efOpCtrlInfo PA Egress Flow Command Control Info Bit Definitions
* @ingroup palld_api_constants
paPatchMsgLenInfo_t patchMsgLen; /**< Specify Patch Message Length command specific parameters */
paCmdVerifyPktErr_t verifyPktErr; /**< Specify Packet error Verification command specific parameters */
paCmdSplitOp_t split; /**< Specify Split command sepcific parameters */
+ paCmdEmacCrcVerify_t emacCrc;/**< Specify the EMAC CRC Verify command specific parameters */
paCmdEfOp_t efOp; /**< Specify Egress Flow operation command specific parameters (PASS Gen2 only) */
paPatchTime_t patchTime; /**< Specify insert time in the messages like Ethernet OAM packets (PASS Gen2 only)*/
paPatchCount_t patchCount; /**< Specify insert count in the messages like Ethernet OAM packets (PASS Gen2 only)*/
uint32_t validBitMap; /**< 32-bit valid Bitmap corresponding to each optional field as defined at @ref paEthInfoValidBits */
paMacAddr_t src; /**< Source MAC addresss */
paMacAddr_t dst; /**< Destination MAC address */
- uint16_t vlan; /**< VLAN tag VID field, 12 lsbs */
+ uint16_t vlan; /**< VLAN tag VID field, 12 lsbs
+ @note: Both untagged packets and priority marked packets (i.e. packets with VID = 0)
+ will be matched when vlan is set to 0 */
uint16_t ethertype; /**< Ethertype field. */
uint32_t mplsTag; /**< MPLS tag. Only the outer tag is examined */
uint16_t inport; /**< Input EMAC port number as specified by @ref paEmacPort */
*/
paReturn_t Pa_getDbgpInfo(Pa_Handle iHandle, paSnapShotDebugInfo_t *dbgInfo);
+
+/**
+ * @ingroup palld_api_functions
+ * @brief Pa_getVirtualLinkId provides the hooks to get the virtual link id
+ *
+ * @details This function is used to get the virtual link ID information from the handle
+ *
+ * @param[in] iHandle The driver instance handle
+ * @param[in] vlinkHdl Pointer to the virtual link handle
+ * @param[out] lnkId virtual link ID from the virtual link handle
+ * @retval Value (@ref ReturnValues)
+ * @pre A driver instance must be created and tables initialized
+ *
+ * @note: This API provides the snap shot information only, the actual values may differ
+ * after the snap shot
+ */
+paReturn_t Pa_getVirtualLinkId(Pa_Handle iHandle, paLnkHandle_t vlinkHdl, int8_t* lnkId);
+
/**
* @ingroup palld_api_functions
* @brief Pa_formatStatsReply formats the stats reply from the PA (PASS Gen1 only)
*
*/
+
+/**
+ * @page appendix9 Destination Queue Bounce Operation
+ *
+ * There is a hardware deficiency identified at the Keystone2 devices where memory consistency is not guaranteed for
+ * IO coherent A15 and PktDMA masters at some rare conditions. Therefore it is possible that the data arrival signal
+ * to the ARM (i.e., presence of a descriptor in QMSS queue) may occur prior to the data arriving properly in the
+ * ARM cache. Thus, the ARM core may access stale data.
+ * To ensure ARM Cache consistency, one of the QMSS PDSP is enhanced to provide a DMA barrier function. Packets destined
+ * to ARM queues may be delivered first to one of the QMSS "bounce" queues serviced by this function. The QMSS PDSP f/w
+ * will pop packets from these queues, perform the necessary barrier operation (that will cause the ARM cache to get
+ * invalidated for the descriptor and buffer locations), and then will relay the packet to the final destination queue.\r
+ *
+ * The Destination Queue Bounce Operation is designed to enable the QMSS proxy bounce on packets PA sends to queues
+ * served by ARM user space by embedding 2 control bits into the destination queue ID to instruct the PASS firmware
+ * to re-route the packets to the specified QMSS bounce queues.
+ *
+ * This operation can be enabled and configured by a global configuration message including the following parameters:
+ * - Enable/Disable
+ * - QMSS Bounce Queue IDs
+ * - DDR Queue: All PktMDA descriptors and buffers use DDR memory only
+ * - MSMC Queue: PktDMA descriptor and buffers may use MSMC memory and/or DDR memory
+ * - Default Behavior map []: Specify the default queue bounce operation for each traffic class such as Command Response
+ * and ingress QoS routing
+ * - NetCP hardware queue info
+ * - Number of NetCP queue
+ * - NetCP queue base
+ *
+ * The Destination Queue Bounce operation is described below in details:
+ * - When the queue bounce feature is disabled, all PA LLD APIs work as before and the two control bits of the destination
+ * queue ID will be cleared.
+ * - When the queue bounce feature is enabled, the application may invoke the following PA Macros to specify the
+ * queue ID in PA LLD APIs:
+ * - PA_BOUNCE_QUEUE_DDR(queueId): Bounce to DDR queue
+ * - PA_BOUNCE_QUEUE_MSMC(queueId): Bounce to MSMC queue
+ * - PA_BOUNCE_QUEUE_NONE(queueId): No Bounce
+ * Or the application may allow the LLD to specify the embedded destination queue ID based on the default behavior map
+ * by invoking the following PA Macro optionally
+ * - PA_BOUNCE_QUEUE_DEFAULT(queueId): Use default behavior map by cleraing the two control bits
+ *
+ * @note PA_BOUNCE_QUEUE_DEFAULT() is a no-operation, so if queueid is used as is, then default behavior rule will be applied automatically
+ * @note For any SOC h/w queues (as indicated to PA in global configuration), all bounce settings are ignored so that packets to these queues
+ * will never be bounced to the barrier function.
+ */
+
#ifdef __cplusplus
}
#endif