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raw | patch | inline | side by side (parent: c340d79)
raw | patch | inline | side by side (parent: c340d79)
author | Eric Ruei <e-ruei1@ti.com> | |
Tue, 25 Nov 2014 20:25:36 +0000 (15:25 -0500) | ||
committer | Eric Ruei <e-ruei1@ti.com> | |
Tue, 25 Nov 2014 20:25:36 +0000 (15:25 -0500) |
example/emacExample/src/c66x/bios/cpsw_mgmt.c | patch | blob | history | |
example/emacExample/src/c66x/bios/framework.c | patch | blob | history | |
test/PAUnitTest/src/tests/test3.c | patch | blob | history |
diff --git a/example/emacExample/src/c66x/bios/cpsw_mgmt.c b/example/emacExample/src/c66x/bios/cpsw_mgmt.c
index 88c69d717d0424d18a5f7c64134a9dd284f59091..860c4c9bac031d686aae53624ac6394a1358bd85 100755 (executable)
#define PA_EMAC_EXAMPLE_REF_CLK_KHZ SERDES_REF_CLK_156250_KHZ\r
#endif\r
\r
+#ifdef NSS_GEN2\r
+\r
+/* CSL related definition: will be moved to CSL at the next drop */\r
+\r
+/** @brief \r
+ *\r
+ * Defines CPTS timestamp output bits\r
+ */ \r
+typedef enum {\r
+ CPTS_TS_OUTPUT_BIT_DISABLED = 0,\r
+ CPTS_TS_OUTPUT_BIT_17,\r
+ CPTS_TS_OUTPUT_BIT_18,\r
+ CPTS_TS_OUTPUT_BIT_19,\r
+ CPTS_TS_OUTPUT_BIT_20,\r
+ CPTS_TS_OUTPUT_BIT_21,\r
+ CPTS_TS_OUTPUT_BIT_22,\r
+ CPTS_TS_OUTPUT_BIT_23,\r
+ CPTS_TS_OUTPUT_BIT_24,\r
+ CPTS_TS_OUTPUT_BIT_25,\r
+ CPTS_TS_OUTPUT_BIT_26,\r
+ CPTS_TS_OUTPUT_BIT_27,\r
+ CPTS_TS_OUTPUT_BIT_28,\r
+ CPTS_TS_OUTPUT_BIT_29,\r
+ CPTS_TS_OUTPUT_BIT_30,\r
+ CPTS_TS_OUTPUT_BIT_31\r
+} CSL_CPTS_TS_OUTPUT_BIT;\r
+\r
+/** @brief \r
+ *\r
+ * Holds the CPTS control register info. \r
+ */ \r
+typedef struct {\r
+ /** Time Sync Enable: When disabled (cleared to zero), the RCLK domain is\r
+ held in reset. */ \r
+ Uint32 cptsEn;\r
+\r
+ /** Interrupt Test: When set, this bit allows the raw interrupt to be written to\r
+ facilitate interrupt test. */ \r
+ Uint32 intTest;\r
+\r
+ /** TS_COMP Polarity: 0 - TS_COMP is asserted low; 1: TS_COMP is asserted high */ \r
+ Uint32 tsCompPolarity;\r
+\r
+ /** Host Receive Timestamp Enable: When set, Timestamps enabled on received packets to host */ \r
+ Uint32 tstampEn;\r
+\r
+ /** Sequence Enable:\r
+ 0: The timestamp value increments with the selected RFTCLK\r
+ 1: The timestamp for received packets is the sequence number of the received packet\r
+ */ \r
+ Uint32 seqEn;\r
+ \r
+ /** 64-bit mode:\r
+ 0: The timestamp is 32-bits with the upper 32-bits forced to zero.\r
+ 1: The timestamp is 64-bits.\r
+ */ \r
+ Uint32 ts64bMode;\r
+ \r
+ /** Hardware push 1-8 enable */\r
+ Uint32 tsHwPushEn[8];\r
+ \r
+ /** TS_SYNC output timestamp counter bit select */ \r
+ CSL_CPTS_TS_OUTPUT_BIT tsOutputBitSel;\r
+\r
+} CSL_CPTS_CONTROL;\r
+\r
+/** ============================================================================\r
+ * @n@b CSL_CPTS_setCntllReg\r
+ *\r
+ * @b Description\r
+ * @n This function sets up the contents of CPTS control register \r
+ *\r
+ * @b Arguments\r
+ @verbatim\r
+ pCntlCfg CSL_CPTS_CONTROL contain settings for \r
+ CPTS control register.\r
+ * @endverbatim\r
+ *\r
+ * <b> Return Value </b>\r
+ * @n None\r
+ *\r
+ * <b> Pre Condition </b>\r
+ * @n None\r
+ *\r
+ * <b> Post Condition </b>\r
+ * @n None\r
+ *\r
+ * @b Writes\r
+ * @n CPTS_CONTROL_REG_CPTS_EN\r
+ * CPTS_CONTROL_REG_INT_TEST \r
+ * CPTS_CONTROL_REG_TS_COMP_POLARITY\r
+ * CPTS_CONTROL_REG_TSTAMP_EN\r
+ * CPTS_CONTROL_REG_SEQUENCE_EN\r
+ * CPTS_CONTROL_REG_MODE\r
+ * CPTS_CONTROL_REG_HW1_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW2_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW3_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW4_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW5_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW6_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW7_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_HW8_TS_PUSH_EN\r
+ * CPTS_CONTROL_REG_TS_SYNC_SEL\r
+ *\r
+ * @b Example\r
+ * @verbatim\r
+ CSL_CPTS_CONTROL cntlCfg;\r
+ \r
+ CSL_CPTS_setCntlReg (&cntlCfg);\r
+\r
+ @endverbatim\r
+ * =============================================================================\r
+ */\r
+CSL_IDEF_INLINE void CSL_CPTS_setCntlReg (\r
+ CSL_CPTS_CONTROL* pCntlCfg \r
+)\r
+{\r
+ Uint32 value = 0;\r
+ \r
+ CSL_FINS (value, CPTS_CONTROL_REG_CPTS_EN, pCntlCfg->cptsEn);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_INT_TEST, pCntlCfg->intTest);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_TS_COMP_POLARITY, pCntlCfg->tsCompPolarity);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_TSTAMP_EN, pCntlCfg->tstampEn);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_SEQUENCE_EN, pCntlCfg->seqEn);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_MODE, pCntlCfg->ts64bMode);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW1_TS_PUSH_EN, pCntlCfg->tsHwPushEn[0]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW2_TS_PUSH_EN, pCntlCfg->tsHwPushEn[1]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW3_TS_PUSH_EN, pCntlCfg->tsHwPushEn[2]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW4_TS_PUSH_EN, pCntlCfg->tsHwPushEn[3]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW5_TS_PUSH_EN, pCntlCfg->tsHwPushEn[4]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW6_TS_PUSH_EN, pCntlCfg->tsHwPushEn[5]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW7_TS_PUSH_EN, pCntlCfg->tsHwPushEn[6]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_HW8_TS_PUSH_EN, pCntlCfg->tsHwPushEn[7]);\r
+ CSL_FINS (value, CPTS_CONTROL_REG_TS_SYNC_SEL, (Uint32)pCntlCfg->tsOutputBitSel);\r
+ hCptsRegs->CONTROL_REG = value;\r
+ \r
+ return;\r
+}\r
+\r
+#endif\r
+\r
void cpsw_getStats(CSL_CPSW_STATS* stats, int clear)\r
{\r
\r
*/\r
int Init_MAC (UInt32 macPortNum, UInt8 macAddress[6], UInt32 mtu)\r
{\r
+\r
+#ifdef NSS_GEN2\r
+ CSL_CPSW_TSCNTL tsCtrl;\r
+ \r
+ memset(&tsCtrl, 0, sizeof(CSL_CPSW_TSCNTL));\r
+#endif \r
+\r
+\r
/* Reset MAC Sliver 0 */\r
CSL_CPGMAC_SL_resetMac (macPortNum);\r
while (CSL_CPGMAC_SL_isMACResetDone (macPortNum) != TRUE);\r
*/\r
CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu);\r
\r
+#ifdef NSS_GEN2 \r
+ /*\r
+ * Enable Port Time sync transmit host timestamp\r
+ */\r
+ tsCtrl.tsTxHostEnable = 1;\r
+ tsCtrl.tsMsgTypeEnable = 0xFFFF;\r
+ \r
+ CSL_CPSW_setPortTimeSyncCntlReg (macPortNum+1, &tsCtrl);\r
+#endif \r
+ \r
/* Done setting up the MAC port */\r
return 0;\r
}\r
return;\r
}\r
\r
+/** ============================================================================\r
+ * @n@b Init_CPTS\r
+ *\r
+ * @b Description\r
+ * @n Init and configure CPTS module\r
+ *\r
+ * @param[in]\r
+ * @n None\r
+ *\r
+ * @return\r
+ * @n None\r
+ * =============================================================================\r
+ */\r
+Void Init_CPTS (Void)\r
+{\r
+#ifdef NSS_GEN2\r
+ CSL_CPTS_CONTROL ctrl;\r
+ uint32_t refClockSelect = 0;\r
+ \r
+ memset(&ctrl, 0, sizeof(CSL_CPTS_CONTROL));\r
+ ctrl.cptsEn = 1;\r
+ ctrl.tstampEn = 1;\r
+ ctrl.seqEn = 0;\r
+ ctrl.ts64bMode = 1;\r
+ \r
+ CSL_CPTS_disableCpts();\r
+ \r
+ CSL_CPTS_setRFTCLKSelectReg (refClockSelect); \r
+ \r
+ CSL_CPTS_setCntlReg(&ctrl);\r
+ \r
+#endif\r
+\r
+ /* Return success. */\r
+ return;\r
+}\r
+\r
+\r
/** ============================================================================\r
* @n@b Init_Switch\r
*\r
\r
/* Initialize the SERDES modules */\r
Init_SGMII_SERDES();\r
-\r
+ \r
/* Initialize the SGMII/Sliver submodules for the\r
* two corresponding MAC ports.\r
*/\r
\r
/* Setup the Phys by initializing the MDIO */\r
Init_MDIO ();\r
+ \r
+ Init_CPTS ();\r
\r
/* Setup the Ethernet switch finally. */\r
Init_Switch (mtu);\r
diff --git a/example/emacExample/src/c66x/bios/framework.c b/example/emacExample/src/c66x/bios/framework.c
index 8007622d3e802d1239a89430a673e5d912d7ee87..37acc7cdb17b30db000b674ca169df0eed4c4055 100755 (executable)
#include <ti/csl/csl_psc.h>\r
#include <ti/csl/csl_pscAux.h>\r
\r
-//#define PASS_TEST_TX_CMD\r
+#define PASS_TEST_TX_CMD\r
/* High Priority Accumulation Interrupt Service Handler for this application */\r
void Cpsw_RxISR (void);\r
\r
uint16_t cmdSize = sizeof(cmdBuf);\r
\r
paCmdNextRoute_t routeCmdEth = {\r
+ #ifndef NSS_GEN2\r
0, /* ctrlBitfield */\r
+ #else\r
+ pa_NEXT_ROUTE_RPT_TX_TIMESTAMP,\r
+ #endif\r
pa_DEST_EMAC, /* Route - host */\r
0, /* pktType don't care */\r
0, /* flow Id */\r
}; \r
\r
routeCmdEth.pktType_emacCtrl = psFlags;\r
+#ifdef NSS_GEN2\r
+ routeCmdEth.swInfo0 = pa_FORMAT_REPORT_TIMESTAMP_INFO(0x88, 0x5, (uint16_t)gTxCounter); \r
+#endif \r
\r
/* Command : Next route */\r
cmdInfo.cmd = pa_CMD_NEXT_ROUTE;\r
int32_t VerifyPacket (Cppi_Desc* pCppiDesc, int emac_dest_port)\r
{\r
Cppi_HostDesc *pHostDesc;\r
- uint8_t *pDataBuffer;\r
- int32_t i;\r
- uint32_t infoLen;\r
+ uint8_t *pDataBuffer;\r
+ int32_t i;\r
+ uint32_t infoLen;\r
pasahoLongInfo_t *pinfo;\r
- uint8_t portNum;\r
+ uint8_t portNum;\r
\r
pHostDesc = (Cppi_HostDesc *)pCppiDesc;\r
\r
return -1;\r
}\r
}\r
+ \r
+#if defined(NSS_GEN2) && defined(PASS_TEST_TX_CMD) \r
+ {\r
+ uint32_t rxTimestamp, rxTimestampMSW;\r
+ CSL_CPTS_EVENTINFO cptsEventInfo;\r
+ \r
+ /* Extract Rx timestamps from the packet */\r
+ Cppi_getTimeStamp (Cppi_DescType_HOST, (Cppi_Desc *)pHostDesc, &rxTimestamp);\r
+ rxTimestampMSW = PASAHO_LINFO_READ_TSTAMP_MSB(pinfo); \r
+ \r
+ /* Extract Tx Timestamp from CPTS event */\r
+ CSL_CPTS_getEventInfo(&cptsEventInfo);\r
+ CSL_CPTS_popEvent(); \r
+ \r
+ System_printf ("pkt %d: Rx timestamp 0x%08x%08x; Tx timestamp 0x%08x%08x\n", cptsEventInfo.seqId, rxTimestampMSW, rxTimestamp, cptsEventInfo.timeStampHi, cptsEventInfo.timeStamp);\r
+ } \r
+#endif \r
\r
//System_printf ("Packet Received Verified Successfully!\n");\r
\r
index 63098e87b947a03f0017af869a974c1a0ac0792c..8f18a5c7815650e9d3e7e128888fce3fa452c246 100644 (file)
uint32_t cmdStack[5][(sizeof(pasahoNextRoute_t) + (3 * sizeof(pasahoComChkCrc_t)) + sizeof(pasahoReportTimestamp_t)) / sizeof (uint32_t)];
uint16_t cmdStackSize[5] = {CMD_BUF_SIZE, CMD_BUF_SIZE, CMD_BUF_SIZE, CMD_BUF_SIZE, CMD_BUF_SIZE};
uint32_t rxTimestamp[5], txTimestamp[5];
- uint16_t rxTimestampMSW[5], txTimestampMSW[5];
+ uint32_t rxTimestampMSW[5], txTimestampMSW[5];
paTimestamp_t timestamp[5];
paCmdInfo_t cmdInfo[5];
uint32_t *swinfo;
Qmss_Queue q;
uint16_t tsQueue;
- /* We stored upper 16 bit of RX timestamp in pinfo->word4 upper 16 bits*/
+ /* We stored upper 32 bit of RX timestamp in pinfo->word6 */
pasahoLongInfo_t *pinfo;
uint32_t infoLen;
Cppi_getTimeStamp (Cppi_DescType_HOST, (Cppi_Desc *)hd, &txTimestamp[i]);
txTimestampMSW[i] = swinfo[1];
+#ifndef NSS_GEN2
if (txTimestamp[i] > rxTimestamp[i])
{
System_printf ("%s (%s:%d): Rx timestamp 0x%08x is ealier than Tx timestamp 0x%08x\n", tfName, __FILE__, __LINE__, rxTimestamp[i],txTimestamp[i]);
return (PA_TEST_FAILED);
}
+#endif
testCommonRecycleLBDesc (tf, hd);
}
-#ifdef PA_T3_SHOW_TIMESTAMP
+#if defined(PA_T3_SHOW_TIMESTAMP) && !defined(NSS_GEN2)
for (i = 0; i < 5; i++) {
- //System_printf ("pkt %d: System Timestamp 0x%08x%04x; Rx timestamp 0x%x; Tx timestamp 0x%x\n", i, timestamp[i].hi, timestamp[i].lo, (rxTimestamp[i]>>32)&0xffff, rxTimestamp[i], (txTimestamp[i]>>32), txTimestamp[i]);
- System_printf ("pkt %d: System Timestamp 0x%08x%04x; Rx timestamp 0x%04x%08x; Tx timestamp 0x%04x%08x\n", i, timestamp[i].hi, timestamp[i].lo, rxTimestampMSW[i], rxTimestamp[i], txTimestampMSW[i], txTimestamp[i]);
+ System_printf ("pkt %d: System Timestamp 0x%04x%08x%04x; Rx timestamp 0x%08x%08x; Tx timestamp 0x%08x%08x\n", i, timestamp[i].hi_hi, timestamp[i].hi, timestamp[i].lo, rxTimestampMSW[i], rxTimestamp[i], txTimestampMSW[i], txTimestamp[i]);
System_flush();
}
#endif