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raw | patch | inline | side by side (parent: c22b669)
raw | patch | inline | side by side (parent: c22b669)
author | Aravind Batni <aravindbr@ti.com> | |
Fri, 19 Jul 2013 00:23:46 +0000 (20:23 -0400) | ||
committer | Aravind Batni <aravindbr@ti.com> | |
Fri, 19 Jul 2013 00:23:46 +0000 (20:23 -0400) |
38 files changed:
index 407488affd18f0a1681c01a3b77e29dad0a4c165..fe75795ec3e57ba29f5070528abde50c0a7ec2c9 100755 (executable)
Binary files a/docs/ReleaseNotes_PA_LLD.doc and b/docs/ReleaseNotes_PA_LLD.doc differ
Binary files a/docs/ReleaseNotes_PA_LLD.doc and b/docs/ReleaseNotes_PA_LLD.doc differ
index 850560a8fc47b3186d871734ce4a87356e6ad71b..5723f11ae21dccbd929fb33d6d865df40fe91f96 100755 (executable)
c) EMAC MAC Adress Port 0: other\r
EMAC_MAC_ADDR_PORT0: 10-11-12-13-14-15\r
\r
-2. Execute \r
+2. Execute using CCS\r
\r
Launch the CCS Debugger and go to the Debug Perspective.\r
\r
To execute the project ensure the following is done:-\r
- a) System reset (EVM only)\r
- b) Run EVM specific GEL scripts (EVM only)\r
+ a) System reset (applicable for EVM under NO_BOOT mode only)\r
+ b) Run EVM specific GEL scripts (applicable for EVM under NO_BOOT mode only)\r
b) Load Program\r
c) Once the project is loaded; Run to execute it.\r
\r
+NOTE:\r
+If EVM is *NOT* running in NO_BOOT mode, the below assumptions are made\r
+2a. The PDSPs are downloaded for QMSS and PA outside the example\r
+2b. CPSW Switch is configured outside the example\r
+2c. To disable the auto detect logic, please set 'autodetectLogic' variable to '0' using CCS. When this is done, the all the steps as mentioned in 'Execute' section are mandatory.\r
+ \r
3. Result\r
\r
The application will output to the console its status progress and the number of sent/received packets\r
and declare pass/fail.\r
+\r
+4. Loading and Executing the project using MPM Client Utility\r
+ a) Bring up linux\r
+ b) copy the DSP executable (e.g., PA_emacExample_K2HC66BiosExampleProject.out) to the filesystemExecute \r
+ c) Execute below command to reset core0\r
+ root@keystone-evm:~#mpmcl reset dsp0 \r
+ d) Execute below command to load the DSP image to core 0\r
+ root@keystone-evm:~#mpmcl load dsp0 PA_emacExample_K2HC66BiosExampleProject.out\r
+ e) Execute below command to run the DSP image from core 0\r
+ root@keystone-evm:~#mpmcl run dsp0\r
+ f) Execute below command to view System_printf() outputs from core0 trace/log message from Linux \r
+ root@keystone-evm:~#cat /debug/remoteproc/remoteproc0/trace0\r
\r
\r
\r
diff --git a/example/emacExample/k2h/c66/bios/PA_emacExample_K2HC66BiosExampleProject.txt b/example/emacExample/k2h/c66/bios/PA_emacExample_K2HC66BiosExampleProject.txt
index 59168fd531d6ec74a87e1675e61fa2d2c68baa1b..42922105f7245ae7917dff46c2bc864318f6e312 100755 (executable)
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/c66x/bios/cpsw_mgmt.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2h/c66/bios/singlecore_osal.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cppi_qmss_mgmt.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/setuprm.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/view_ale_table.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/c66x/bios/framework.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/fw/classify1_bin.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/fw/classify2_bin.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/fw/pam_bin.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/rm/device/k2h/policy_dsp-only.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/rm/device/k2h/policy_dsp_arm.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/rm/device/k2h/global-resource-list.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2h/src/cppi_device.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2h/src/qmss_device.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2h/c66/bios/cpsw_linker.cmd"
diff --git a/example/emacExample/k2h/c66/bios/cpsw_example.cfg b/example/emacExample/k2h/c66/bios/cpsw_example.cfg
/* Load the PA package */
var Pa = xdc.loadPackage('ti.drv.pa');
+/* Load the RM package */
+var Rm = xdc.loadPackage('ti.drv.rm');
+
var System = xdc.useModule('xdc.runtime.System');
SysStd = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;
+/* Below configuration is needed if the DSP executable needs to be loaded from MPM client from ARM */
+/*
+ * The SysMin used here vs StdMin, as trace buffer address is required for
+ * Linux trace debug driver, plus provides better performance.
+ */
+Program.global.sysMinBufSize = 0x8000;
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize = Program.global.sysMinBufSize;
+
+/* Configure resource table for trace only.
+ Note that, it traceOnly parameter should not
+ be set if application is using MessageQ based IPC
+ to communicate between cores.
+ */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = Program.platform.dataMemory;
+Resource.traceOnly = true;
+
+/* end MPM Client Configurations */
/* Create a default system heap using ti.bios.HeapMem. */
var heapMemParams1 = new HeapMem.Params;
Program.sectMap[".const"] = "L2SRAM";
Program.sectMap[".qmss"] = "L2SRAM";
Program.sectMap[".cppi"] = "L2SRAM";
-
+/* Section not to be loaded by remoteproc loader */
+Program.sectMap[".noload_section"].type = "NOLOAD";
diff --git a/example/emacExample/k2h/c66/bios/cpsw_linker.cmd b/example/emacExample/k2h/c66/bios/cpsw_linker.cmd
SECTIONS
{
.init_array > L2SRAM
+ .sharedGRL: load >> L2SRAM
+ .sharedPolicy: load >> L2SRAM
+ .rm: load >> MSMCSRAM
}
diff --git a/example/emacExample/k2h/c66/bios/singlecore_osal.c b/example/emacExample/k2h/c66/bios/singlecore_osal.c
UInt32 cpswCppiFreeCounter = 0;
UInt32 cpswQmssMallocCounter = 0;
UInt32 cpswQmssFreeCounter = 0;
-
+uint32_t rmMallocCounter = 0;
+uint32_t rmFreeCounter = 0;
UInt32 coreKey [MAX_NUM_CORES];
/**********************************************************************
CSL_semReleaseSemaphore (PA_HW_SEM);
}
+/**
+ * @b Description
+ * @n
+ * The function is used to allocate a memory block of the specified size.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @retval
+ * Allocated block address
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ rmMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to free a memory block of the specified size.
+ *
+ * @param[in] ptr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] size
+ * Size of the memory block to be cleaned up.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ /* Increment the free counter. */
+ rmFreeCounter++;
+ Memory_free(NULL, ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_cppiCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ *
+ * @retval
+ * Allocated task blocking object
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to block a task whose context a
+ * RM instance is running within.
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to unblock a task whose context a
+ * RM instance is running within.
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to delete a task blocking object
+ * provided to a RM instance
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is the RM OSAL Logging API which logs
+ * the messages on the console.
+ *
+ * @param[in] fmt
+ * Formatted String.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
+
diff --git a/example/emacExample/k2k/c66/bios/PA_emacExample_K2KC66BiosExampleProject.txt b/example/emacExample/k2k/c66/bios/PA_emacExample_K2KC66BiosExampleProject.txt
index 20b4c7606cf99de4d47f07a0b22085bbfdf773a8..c84c5cd63f0e8babb37b8832e75182e131ae21a0 100755 (executable)
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/c66x/bios/cpsw_mgmt.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2k/c66/bios/singlecore_osal.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/cppi_qmss_mgmt.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/setuprm.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/view_ale_table.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/src/c66x/bios/framework.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/fw/classify1_bin.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/fw/classify2_bin.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/fw/pam_bin.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/rm/device/k2k/policy_dsp-only.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/rm/device/k2k/policy_dsp_arm.c"
+-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/rm/device/k2k/global-resource-list.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2k/src/cppi_device.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2k/src/qmss_device.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/emacExample/k2k/c66/bios/cpsw_linker.cmd"
diff --git a/example/emacExample/k2k/c66/bios/cpsw_example.cfg b/example/emacExample/k2k/c66/bios/cpsw_example.cfg
/* Load the PA package */
var Pa = xdc.loadPackage('ti.drv.pa');
+/* Load the RM package */
+var Rm = xdc.loadPackage('ti.drv.rm');
+
var System = xdc.useModule('xdc.runtime.System');
SysStd = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;
+/* Below configuration is needed if the DSP executable needs to be loaded from MPM client from ARM */
+/*
+ * The SysMin used here vs StdMin, as trace buffer address is required for
+ * Linux trace debug driver, plus provides better performance.
+ */
+Program.global.sysMinBufSize = 0x8000;
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize = Program.global.sysMinBufSize;
+
+/* Configure resource table for trace only.
+ Note that, it traceOnly parameter should not
+ be set if application is using MessageQ based IPC
+ to communicate between cores.
+ */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = Program.platform.dataMemory;
+Resource.traceOnly = true;
+
+/* end MPM Client Configurations */
/* Create a default system heap using ti.bios.HeapMem. */
var heapMemParams1 = new HeapMem.Params;
Program.sectMap[".const"] = "L2SRAM";
Program.sectMap[".qmss"] = "L2SRAM";
Program.sectMap[".cppi"] = "L2SRAM";
-
+/* Section not to be loaded by remoteproc loader */
+Program.sectMap[".noload_section"].type = "NOLOAD";
diff --git a/example/emacExample/k2k/c66/bios/cpsw_linker.cmd b/example/emacExample/k2k/c66/bios/cpsw_linker.cmd
SECTIONS
{
.init_array > L2SRAM
+ .sharedGRL: load >> L2SRAM
+ .sharedPolicy: load >> L2SRAM
+ .rm: load >> MSMCSRAM
}
diff --git a/example/emacExample/k2k/c66/bios/singlecore_osal.c b/example/emacExample/k2k/c66/bios/singlecore_osal.c
UInt32 cpswCppiFreeCounter = 0;
UInt32 cpswQmssMallocCounter = 0;
UInt32 cpswQmssFreeCounter = 0;
-
+uint32_t rmMallocCounter = 0;
+uint32_t rmFreeCounter = 0;
UInt32 coreKey [MAX_NUM_CORES];
/**********************************************************************
CSL_semReleaseSemaphore (PA_HW_SEM);
}
+/**
+ * @b Description
+ * @n
+ * The function is used to allocate a memory block of the specified size.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @retval
+ * Allocated block address
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ rmMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to free a memory block of the specified size.
+ *
+ * @param[in] ptr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] size
+ * Size of the memory block to be cleaned up.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ /* Increment the free counter. */
+ rmFreeCounter++;
+ Memory_free(NULL, ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_cppiCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ *
+ * @retval
+ * Allocated task blocking object
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to block a task whose context a
+ * RM instance is running within.
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to unblock a task whose context a
+ * RM instance is running within.
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to delete a task blocking object
+ * provided to a RM instance
+ *
+ * @param[in] handle
+ * Task blocking object handle.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is the RM OSAL Logging API which logs
+ * the messages on the console.
+ *
+ * @param[in] fmt
+ * Formatted String.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
+
diff --git a/example/emacExample/src/c66x/bios/cpsw_mgmt.c b/example/emacExample/src/c66x/bios/cpsw_mgmt.c
#define PA_EMAC_EXAMPLE_REF_CLK_KHZ SERDES_REF_CLK_156250_KHZ\r
#endif\r
\r
+\r
+void cpsw_getStats(CSL_CPSW_5GF_STATS* stats)\r
+{\r
+\r
+ int numBlocks;\r
+ CSL_CPSW_nGF_getStats(stats);\r
+ for (numBlocks = 0; numBlocks < CSL_CPSW_5GF_NUMSTATBLOCKS; numBlocks++)\r
+ {\r
+ System_printf ("Stats for port number: %d \n", numBlocks);\r
+ System_printf ("********************************************\n");\r
+ System_printf(" Good Frames Received %d\n", stats->RxGoodFrames);\r
+\r
+ System_printf(" Good Broadcast Frames Received %d\n", stats->RxBCastFrames);\r
+\r
+ System_printf(" Good Multicast Frames Received %d\n", stats->RxMCastFrames);\r
+\r
+ System_printf(" PauseRx Frames Received %d\n", stats->RxPauseFrames);\r
+\r
+ System_printf(" Frames Received with CRC Errors %d\n", stats->RxCRCErrors);\r
+\r
+ System_printf(" Frames Received with Alignment/Code Errors%d\n", stats->RxAlignCodeErrors);\r
+\r
+ System_printf(" Oversized Frames Received %d\n", stats->RxOversized);\r
+\r
+ System_printf(" Jabber Frames Received %d\n", stats->RxJabber);\r
+\r
+ System_printf(" Undersized Frames Received %d\n", stats->RxUndersized);\r
+\r
+ System_printf(" Rx Frame Fragments Received %d\n", stats->RxFragments);\r
+\r
+ System_printf(" Reserved %d\n", stats->reserved);\r
+\r
+ System_printf(" Reserved %d\n", stats->reserved2);\r
+\r
+ System_printf(" Total Received Bytes in Good Frames %d\n", stats->RxOctets);\r
+\r
+ System_printf(" Good Frames Sent %d\n", stats->TxGoodFrames);\r
+\r
+ System_printf(" Good Broadcast Frames Sent %d\n", stats->TxBCastFrames);\r
+\r
+ System_printf(" Good Multicast Frames Sent %d\n", stats->TxMCastFrames);\r
+\r
+ System_printf(" PauseTx Frames Sent %d\n", stats->TxPauseFrames);\r
+\r
+ System_printf(" Frames Where Transmission was Deferred %d\n", stats->TxDeferred);\r
+\r
+ System_printf(" Total Frames Sent With Collision %d\n", stats->TxCollision);\r
+\r
+ System_printf(" Frames Sent with Exactly One Collision %d\n", stats->TxSingleColl);\r
+\r
+ System_printf(" Frames Sent with Multiple Colisions %d\n", stats->TxMultiColl);\r
+\r
+ System_printf(" Tx Frames Lost Due to Excessive Collisions%d\n", stats->TxExcessiveColl);\r
+\r
+ System_printf(" Tx Frames Lost Due to a Late Collision %d\n", stats->TxLateColl);\r
+\r
+ System_printf(" Tx Frames Lost with Tx Underrun Error %d\n", stats->TxUnderrun);\r
+\r
+ System_printf(" Tx Frames Lost Due to Carrier Sense Loss %d\n", stats->TxCarrierSLoss);\r
+\r
+ System_printf(" Total Transmitted Bytes in Good Frames %d\n", stats->TxOctets);\r
+\r
+ System_printf(" Total Tx&Rx with Octet Size of 64 %d\n", stats->Frame64);\r
+\r
+ System_printf(" Total Tx&Rx with Octet Size of 65 to 127 %d\n", stats->Frame65t127);\r
+\r
+ System_printf(" Total Tx&Rx with Octet Size of 128 to 255 %d\n", stats->Frame128t255);\r
+\r
+ System_printf(" Total Tx&Rx with Octet Size of 256 to 511 %d\n", stats->Frame256t511);\r
+\r
+ System_printf(" Total Tx&Rx with Octet Size of 512 to 1023 %d\n", stats->Frame512t1023);\r
+\r
+ System_printf(" Total Tx&Rx with Octet Size of >=1024 %d\n", stats->Frame1024tUp);\r
+\r
+ System_printf(" Sum of all Octets Tx or Rx on the Network %d\n", stats->NetOctets);\r
+\r
+ System_printf(" Total Rx Type1 Overruns %d\n", stats->OverrunType1);\r
+\r
+ System_printf(" Total Rx Type2 Overruns %d\n", stats->OverrunType2);\r
+\r
+ System_printf(" Total Rx Type3 Overruns %d\n", stats->OverrunType3);\r
+ System_printf ("********************************************\n");\r
+ stats++;\r
+ }\r
+\r
+}\r
/** ============================================================================\r
* @n@b Init_SGMII\r
*\r
diff --git a/example/emacExample/src/c66x/bios/framework.c b/example/emacExample/src/c66x/bios/framework.c
index c07c9806a163968c8e62cd0b556a060f8798eccf..7189e543390eb0344d3547a16c5c7dc14df9581e 100755 (executable)
#include <ti/csl/csl_psc.h>\r
#include <ti/csl/csl_pscAux.h>\r
\r
-/* High Priority QM Rx Interrupt Threshold */\r
-#define RX_INT_THRESHOLD 1u\r
-\r
-/* Accumulator channel to use */\r
-#define PA_ACC_CHANNEL_NUM 0u\r
-\r
/* High Priority Accumulation Interrupt Service Handler for this application */\r
void Cpsw_RxISR (void);\r
\r
Qmss_AccCmdCfg accCfg;\r
uint16_t numAccEntries, intThreshold;\r
uint8_t isAllocated;\r
- int32_t result;\r
+ Qmss_Result result;\r
int32_t eventId, vectId;\r
uint8_t coreNum = (uint8_t) CSL_chipReadReg(CSL_CHIP_DNUM);\r
extern Qmss_QueueHnd gRxQHnd;\r
\r
- /* Open a Receive (Rx) queue.\r
- *\r
- * This queue will be used to hold all the packets received by PASS/CPSW\r
- *\r
- * Open the next available High Priority Accumulation queue for Rx.\r
- */\r
- if ((gRxQHnd = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
- {\r
- System_printf ("Error opening a High Priority Accumulation Rx queue \n");\r
- return -1;\r
- }\r
- *rxQInfo = Qmss_getQueueNumber (gRxQHnd);\r
-\r
- /* Setup high priority accumulation interrupts on the Rx queue.\r
- *\r
- * Let's configure the accumulator with the following settings:\r
- * (1) Interrupt pacing disabled.\r
- * (2) Interrupt on every received packet\r
- */\r
- intThreshold = RX_INT_THRESHOLD;\r
- numAccEntries = (intThreshold + 1) * 2;\r
- accChannelNum = PA_ACC_CHANNEL_NUM + coreNum;\r
-\r
- /* Initialize the accumulator list memory */\r
- memset ((void *) gHiPriAccumList, 0, numAccEntries * 4);\r
-\r
- /* Ensure that the accumulator channel we are programming is not\r
- * in use currently.\r
- */\r
- result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, accChannelNum);\r
- if (result != QMSS_ACC_SOK && result != QMSS_ACC_CHANNEL_NOT_ACTIVE)\r
- {\r
- System_printf ("Error Disabling high priority accumulator for channel : %d error code: %d\n",\r
- accChannelNum, result);\r
- return -1;\r
- }\r
-\r
- /* Setup the accumulator settings */\r
- accCfg.channel = accChannelNum;\r
- accCfg.command = Qmss_AccCmd_ENABLE_CHANNEL;\r
- accCfg.queueEnMask = 0;\r
- accCfg.listAddress = Convert_CoreLocal2GlobalAddr((uint32_t) gHiPriAccumList);\r
- accCfg.queMgrIndex = gRxQHnd;\r
- accCfg.maxPageEntries = (intThreshold + 1); /* Add an extra entry for holding the entry count */\r
- accCfg.timerLoadCount = 0;\r
- accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;\r
- accCfg.listEntrySize = Qmss_AccEntrySize_REG_D;\r
- accCfg.listCountMode = Qmss_AccCountMode_ENTRY_COUNT;\r
- accCfg.multiQueueMode = Qmss_AccQueueMode_SINGLE_QUEUE;\r
-\r
- /* Program the accumulator */\r
- if ((result = Qmss_programAccumulator (Qmss_PdspId_PDSP1, &accCfg)) != QMSS_ACC_SOK)\r
- {\r
- System_printf ("Error Programming high priority accumulator for channel : %d queue : %d error code : %d\n",\r
+ //if (linuxBoot == FALSE)\r
+ if (1)\r
+ {\r
+\r
+ /* Open a Receive (Rx) queue.\r
+ *\r
+ * This queue will be used to hold all the packets received by PASS/CPSW\r
+ *\r
+ * Open the next available High Priority Accumulation queue for Rx.\r
+ */\r
+ if ((gRxQHnd = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
+ {\r
+ System_printf ("Error opening a High Priority Accumulation Rx queue \n");\r
+ return -1;\r
+ }\r
+ *rxQInfo = Qmss_getQueueNumber (gRxQHnd);\r
+\r
+ /* Setup high priority accumulation interrupts on the Rx queue.\r
+ *\r
+ * Let's configure the accumulator with the following settings:\r
+ * (1) Interrupt pacing disabled.\r
+ * (2) Interrupt on every received packet\r
+ */\r
+ intThreshold = RX_INT_THRESHOLD;\r
+ numAccEntries = (intThreshold + 1) * 2;\r
+ accChannelNum = PA_ACC_CHANNEL_NUM + coreNum;\r
+ \r
+ /* Initialize the accumulator list memory */\r
+ memset ((void *) gHiPriAccumList, 0, numAccEntries * 4);\r
+\r
+ /* Setup the accumulator settings */\r
+ accCfg.channel = accChannelNum;\r
+ accCfg.command = Qmss_AccCmd_ENABLE_CHANNEL;\r
+ accCfg.queueEnMask = 0;\r
+ accCfg.listAddress = Convert_CoreLocal2GlobalAddr((uint32_t) gHiPriAccumList);\r
+ accCfg.queMgrIndex = Qmss_getQIDFromHandle(gRxQHnd);\r
+ accCfg.maxPageEntries = (intThreshold + 1); /* Add an extra entry for holding the entry count */\r
+ accCfg.timerLoadCount = 0;\r
+ accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;\r
+ accCfg.listEntrySize = Qmss_AccEntrySize_REG_D;\r
+ accCfg.listCountMode = Qmss_AccCountMode_ENTRY_COUNT;\r
+ accCfg.multiQueueMode = Qmss_AccQueueMode_SINGLE_QUEUE;\r
+\r
+ /* Program the accumulator */\r
+ if ((result = Qmss_programAccumulator (Qmss_PdspId_PDSP1, &accCfg)) != QMSS_ACC_SOK)\r
+ {\r
+ System_printf ("Error Programming high priority accumulator for channel : %d queue : %d error code : %d\n",\r
accCfg.channel, accCfg.queMgrIndex, result);\r
- return -1;\r
- }\r
- /* Register interrupts for the system event corresponding to the\r
- * accumulator channel we are using.\r
- */\r
- /* System event 48 - Accumulator Channel 0 */\r
- eventId = 48;\r
-\r
- /* Pick a interrupt vector id to use */\r
- vectId = 7;\r
-\r
- /* Register our ISR handle for this event */\r
- EventCombiner_dispatchPlug (eventId, (EventCombiner_FuncPtr)Cpsw_RxISR, (UArg)NULL, TRUE);\r
-\r
- /* Map the combiner's output event id (evevtId/32) to hardware interrupt 8. */\r
- /* The HW int 8 is slected via CM.eventGroupHwiNum[] specified at cpsw_example.cfg */\r
- Hwi_eventMap(vectId, 1);\r
-\r
- /* Enable interrupt 8. */\r
- Hwi_enableInterrupt(vectId);\r
+ return -1;\r
+ }\r
+\r
+ /* Register interrupts for the system event corresponding to the\r
+ * accumulator channel we are using.\r
+ */\r
+ /* System event 48 - Accumulator Channel 0 */\r
+ eventId = 48;\r
+ \r
+ /* Pick a interrupt vector id to use */\r
+ vectId = 7;\r
+ \r
+ /* Register our ISR handle for this event */\r
+ EventCombiner_dispatchPlug (eventId, (EventCombiner_FuncPtr)Cpsw_RxISR, (UArg)NULL, TRUE);\r
+ \r
+ /* Map the combiner's output event id (evevtId/32) to hardware interrupt 8. */\r
+ /* The HW int 8 is slected via CM.eventGroupHwiNum[] specified at cpsw_example.cfg */\r
+ Hwi_eventMap(vectId, 1);\r
+ \r
+ /* Enable interrupt 8. */\r
+ Hwi_enableInterrupt(vectId);\r
+ }\r
+ else {\r
+ /* Open a Receive (Rx) queue.\r
+ *\r
+ * This queue will be used to hold all the packets received by PASS/CPSW\r
+ *\r
+ * Open the next available High Priority Accumulation queue for Rx.\r
+ */\r
+ if ((gRxQHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, RX_QUEUE_NUM_INIT, &isAllocated)) < 0)\r
+ {\r
+ System_printf ("Error opening a High Priority Accumulation Rx queue \n");\r
+ return -1;\r
+ }\r
+ *rxQInfo = Qmss_getQueueNumber (gRxQHnd); \r
+ }\r
\r
return (0);\r
\r
);\r
Cppi_setPacketLen (Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, dataBufferSize);\r
\r
+\r
if (cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
{\r
- /* Force the packet to the specific EMAC port if loopback is enabled */\r
- Cppi_setPSFlags(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, psFlags);\r
+ /* Force the packet to the specific EMAC port if loopback is enabled */\r
+ Cppi_setPSFlags(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, psFlags);\r
}\r
else\r
{\r
- Cppi_setPSFlags(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, 0);\r
+ Cppi_setPSFlags(Cppi_DescType_HOST, (Cppi_Desc *)pCppiDesc, 0); \r
}\r
+ \r
/* Send the packet out the mac. It will loop back to PA if the mac/switch\r
* have been configured properly\r
*/\r
- Qmss_queuePush (gPaTxQHnd[8], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ if (linuxBoot == FALSE)\r
+ Qmss_queuePush (gPaTxQHnd[8], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ else {\r
+ Qmss_queuePush (gPaTxQHnd[0], pCppiDesc, dataBufferSize, SIZE_HOST_DESC, Qmss_Location_TAIL);\r
+ }\r
\r
/* Increment the application transmit counter */\r
gTxCounter ++;\r
\r
return 0;\r
}\r
+\r
+/** ============================================================================\r
+ * @n@b ReceivePacket\r
+ *\r
+ * @b Description\r
+ * @n This API is called to Receive packets.\r
+ *\r
+ * @param[in] \r
+ * @n None\r
+ * \r
+ * @return int32_t\r
+ * -1 - Error\r
+ * 0 - Success\r
+ * =============================================================================\r
+ */\r
+int32_t ReceivePacket (void)\r
+{\r
+ Cppi_Desc *hd;\r
+ int32_t j;\r
+ int32_t status=0;\r
+ extern Qmss_QueueHnd gRxQHnd;\r
+ \r
+ /* Wait for a data packet from PA */\r
+ for (j = 0; j < 100; j++) \r
+ {\r
+ CycleDelay (1000);\r
+ if (Qmss_getQueueEntryCount (gRxQHnd) > 0) \r
+ {\r
+ hd = (Cppi_Desc *)(((uint32_t)Qmss_queuePop (gRxQHnd)) & ~0xf);\r
+ if(VerifyPacket(hd) != 0)\r
+ status=-1;\r
+ }\r
+ } \r
+ \r
+ return (status);\r
+}\r
+\r
/** ============================================================================\r
* @n@b VerifyPacket\r
*\r
}\r
else if(!cpswSimTest)\r
{\r
- /* Verify the input port number */\r
- portNum = PASAHO_LINFO_READ_INPORT(pinfo);\r
- \r
- if (portNum != pa_EMAC_PORT_1)\r
+ /* do not check the port number if linux boot is true */\r
+ if (linuxBoot == FALSE)\r
{\r
- System_printf ("VerifyPacket: receive packet from unexpected EMAC PORT %d (expected %d)\n", portNum - 1, pa_EMAC_PORT_1 - 1);\r
- System_flush();\r
+ /* Verify the input port number */\r
+ portNum = PASAHO_LINFO_READ_INPORT(pinfo);\r
+ \r
+ if (portNum != pa_EMAC_PORT_1)\r
+ {\r
+ System_printf ("VerifyPacket: receive packet from unexpected EMAC PORT %d (expected %d)\n", portNum - 1, pa_EMAC_PORT_1 - 1);\r
+ System_flush();\r
+ }\r
}\r
}\r
\r
diff --git a/example/emacExample/src/c66x/bios/fw_main.c b/example/emacExample/src/c66x/bios/fw_main.c
index da6cdf4e7a5bfb27faf3618fdbe198163e2dd976..b9a42138eb7bfb363741183accb4430076dcc896 100755 (executable)
*/
#include <cpsw_singlecore.h>
#include <stdio.h>
+#include "ti/csl/csl_bootcfgAux.h"
+#ifdef SIMULATOR_SUPPORT
+uint32_t autodetectLogic = FALSE;
+#else
+uint32_t autodetectLogic = TRUE;
+#endif
int32_t main (void)
{
Task_Params cpswTaskParams;
+ uint32_t bootMode;
/* Init internal cycle counter */
TSCL = 1;
+ if (autodetectLogic == TRUE)
+ {
+ bootMode = CSL_BootCfgGetBootMode();
+
+ if (bootMode == 0)
+ no_bootMode = TRUE;
+ else
+ no_bootMode = FALSE;
+ }
+ else {
+ no_bootMode = TRUE;
+ }
+
if (!cpswSimTest)
{
- passPowerUp();
+ if (no_bootMode == TRUE)
+ {
+ passPowerUp();
+ }
}
/* Initialize the task params */
index 1a128ef4438581551657c1eb7fb094eb51867d1b..ee23d807f4a6f3b5e1376c1ead7d1b43e31e27c2 100755 (executable)
/* Bypass hardware initialization as it is done within Kernel */\r
qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;\r
#else\r
- qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;\r
+ if (no_bootMode == TRUE)\r
+ {\r
+ qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;\r
#ifdef _LITTLE_ENDIAN \r
- qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;\r
- qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);\r
+ qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;\r
+ qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);\r
#else\r
- qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;\r
- qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);\r
-#endif \r
+ qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;\r
+ qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ /* Bypass hardware initialization as it is done within Kernel */\r
+ qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;\r
+ }\r
+#endif\r
+\r
+#if RM\r
+ if (rmServiceHandle)\r
+ qmssGblCfgParams.qmRmServiceHandle = rmServiceHandle;\r
#endif\r
/* Initialize the Queue Manager */\r
fw_qmssGblCfgParams = &qmssGblCfgParams;\r
Cppi_TxChInitCfg txChCfg;\r
Cppi_RxChInitCfg rxChInitCfg;\r
Cppi_GlobalConfigParams fw_cppiGblCfgParams;\r
+#if RM\r
+ Cppi_StartCfg cppiStartCfg;\r
+#endif\r
\r
fw_cppiGblCfgParams = cppiGblCfgParams;\r
/* Initialize CPPI LLD */\r
return -1;\r
}\r
\r
+#if RM\r
+ if (rmServiceHandle)\r
+ {\r
+ cppiStartCfg.rmServiceHandle = rmServiceHandle;\r
+ Cppi_startCfg(&cppiStartCfg);\r
+ }\r
+#endif\r
/* Initialize PASS CPDMA */\r
memset (&cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));\r
cpdmaCfg.dmaNum = Cppi_CpDma_PASS_CPDMA;\r
\r
if ((gPaTxQHnd[i] = Qmss_queueOpen (Qmss_QueueType_PASS_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
{\r
- System_printf ("Error opening PA Tx queue \n");\r
+ System_printf ("Error opening PA Tx queue, err:%d \n", gPaTxQHnd[i]);\r
return -1;\r
} \r
}\r
*/\r
if ((gTxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_STARVATION_COUNTER_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
{\r
- System_printf ("Error opening Tx Free descriptor queue \n");\r
+ System_printf ("Error opening Tx Free descriptor queue, err: %d \n", gTxFreeQHnd);\r
return -1;\r
} \r
\r
}\r
\r
/* Empty the remaining queues */\r
+ Qmss_queueEmpty(gGlobalFreeQHnd);\r
+ Qmss_queueClose(gGlobalFreeQHnd);\r
+\r
Qmss_queueEmpty (gTxFreeQHnd);\r
Qmss_queueEmpty (gRxFreeQHnd);\r
Qmss_queueEmpty (gPaCfgCmdRespQHnd);\r
}\r
\r
/* The QM/CPDMA are cleared */\r
-int clearQm(void)\r
+int freeAttachedBufs(void)\r
{\r
- int result, i;\r
+ int i;\r
+ uint8_t *bufaddr;\r
+ uint32_t buflen;\r
+ void* pCppiDesc;\r
\r
/* Free Attached Buffers associated with Rx descriptors\r
* Note that there are no attached buffers for the Tx Descriptors\r
*/\r
for (i = 0; i < NUM_RX_DESC; i++) {\r
\r
- uint8_t *bufaddr;\r
- uint32_t buflen;\r
- void* pCppiDesc;\r
/* Get a free descriptor from the global free queue we setup\r
* during initialization.\r
*/\r
DataBufFree((void*)bufaddr, buflen);\r
}\r
\r
- /* clear the flows */\r
- if ((result = Cppi_closeRxFlow (gRxFlowHnd)) != CPPI_SOK) {\r
- return (-1);\r
- }\r
-\r
- /* Close the queues that were setup */\r
- closeAllOpenedQueues();\r
-\r
- /* Close the cpDma setup */\r
- for (i = 0; i < NUM_PA_RX_CHANNELS; i++) {\r
- if ((result = Cppi_channelClose (gCpdmaRxChanHnd[i])) != CPPI_SOK) {\r
- return (result);\r
- }\r
- }\r
- for (i = 0; i < NUM_PA_TX_QUEUES; i++) {\r
- if ((result = Cppi_channelClose (gCpdmaTxChanHnd[i])) != CPPI_SOK) {\r
- return (result);\r
- }\r
- }\r
-\r
- /* Free the memory regions */\r
- if ((result = Qmss_removeMemoryRegion (Qmss_MemRegion_MEMORY_REGION0, 0)) != QMSS_SOK)\r
- {\r
- System_printf ("Error Core : Remove memory region error code : %d\n", result);\r
- }\r
-\r
return (0);\r
-\r
}\r
\r
int clearFramework(void)\r
{\r
-\r
+ Qmss_Result qmss_result;\r
+ Cppi_Result cppi_result;\r
+ int i, accChannelNum;\r
+#ifdef __LINUX_USER_SPACE\r
+ uint8_t coreNum = 0;\r
+#else\r
+ uint8_t coreNum = (uint8_t) CSL_chipReadReg(CSL_CHIP_DNUM);\r
+#endif\r
/* Delete the MAC Address added */\r
if (Del_Port() < 0)\r
{\r
System_printf ("Failed to clean up the MAC address\n");\r
}\r
\r
- /* The QM/CPDMA are cleared */\r
- if (clearQm() < 0)\r
+\r
+ /* clear the flows */\r
+ if ((cppi_result = Cppi_closeRxFlow (gRxFlowHnd)) != CPPI_SOK) {\r
+ return (-1);\r
+ }\r
+\r
+ /* Free Attached Bufs */\r
+ freeAttachedBufs();\r
+\r
+ /* Close the Accumulator Channel programmed */\r
+ accChannelNum = PA_ACC_CHANNEL_NUM + coreNum;\r
+ qmss_result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, accChannelNum);\r
+ if (qmss_result != QMSS_ACC_SOK && qmss_result != QMSS_ACC_CHANNEL_NOT_ACTIVE)\r
{\r
- System_printf(" Failed to clean qm/cppi\n");\r
- return (-1);\r
+ System_printf ("Error Disabling high priority accumulator for channel : %d error code: %d\n",\r
+ accChannelNum, qmss_result);\r
+ return -1;\r
}\r
\r
+ /* Close the queues that were setup */\r
+ closeAllOpenedQueues();\r
+\r
+ /* Close the cpDma setup */\r
+ for (i = 0; i < NUM_PA_RX_CHANNELS; i++) {\r
+ if ((cppi_result = Cppi_channelClose (gCpdmaRxChanHnd[i])) != CPPI_SOK) {\r
+ return (cppi_result);\r
+ }\r
+ }\r
+ for (i = 0; i < NUM_PA_TX_QUEUES; i++) {\r
+ if ((cppi_result = Cppi_channelClose (gCpdmaTxChanHnd[i])) != CPPI_SOK) {\r
+ return (cppi_result);\r
+ }\r
+ }\r
+\r
+ /* Free the memory regions */\r
+ if ((qmss_result = Qmss_removeMemoryRegion (Qmss_MemRegion_MEMORY_REGION0, 0)) != QMSS_SOK)\r
+ {\r
+ System_printf ("Error Core : Remove memory region error code : %d\n", qmss_result);\r
+ }\r
+\r
+ while ((qmss_result = Qmss_exit()) != QMSS_SOK)\r
+ {\r
+ for (i=0; i<100; i++); /* Wait for QM Exit */\r
+ }\r
return (0);\r
\r
}\r
index 1bda8f4c8c62e80351404acb2522ff0fda8cb6e9..9b46ca721cdfa725572d189833053b0a4900c31f 100755 (executable)
* (1) Initializes:\r
* (a) Queue Manager (QM) Subsystem \r
* (b) Packet Accelerator (PA) CPPI DMA \r
- * (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO)\r
- * (d) PA Subsystem + PDSP\r
+ * (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO) - (Note: Applicable only for NO_BOOT mode)\r
+ * (d) PA Subsystem + PDSP - (Note: PDSP is initialized only during NO_BOOT mode)\r
*\r
* (2) Sets up the CPPI descriptors and Queues required for sending and\r
* receiving data using Ethernet.\r
void mdebugHaltPdsp (int pdspNum);\r
volatile int mdebugWait = 1;\r
\r
+uint32_t no_bootMode = TRUE;\r
+\r
/**************************************************************\r
**************** EXAMPLE APP FUNCTIONS ************************\r
***************************************************************/\r
extern void view_ale_table(void);\r
int32_t i;\r
int ct_show_ale = 0;\r
+ CSL_CPSW_5GF_STATS stats [2];\r
\r
System_printf ("**************************************************\n");\r
System_printf ("******* Ethernet Single Core Example Start *******\n");\r
System_printf ("**************************************************\n");\r
\r
+#if RM\r
+ if (setupRm ())\r
+ {\r
+ System_printf ("Function setupRm failed\n");\r
+ return;\r
+ }\r
+#endif\r
/* Initialize the components required to run the example:\r
* (1) QMSS\r
* (2) CPPI\r
System_printf ("PASS successfully initialized \n");\r
}\r
#ifndef __LINUX_USER_SPACE\r
- /* Initialize the CPSW switch */\r
- if (Init_Cpsw () != 0)\r
- {\r
- System_printf ("Ethernet subsystem init failed \n");\r
- APP_exit (-1);\r
- }\r
- else\r
+ if (no_bootMode == TRUE)\r
{\r
- System_printf ("Ethernet subsystem successfully initialized \n");\r
+ /* Initialize the CPSW switch */\r
+ if (Init_Cpsw () != 0)\r
+ {\r
+ System_printf ("Ethernet subsystem init failed \n");\r
+ APP_exit (-1);\r
+ }\r
+ else\r
+ {\r
+ System_printf ("Ethernet subsystem successfully initialized \n");\r
+ }\r
}\r
#endif\r
\r
System_printf ("PASS setup successfully done \n");\r
}\r
\r
- if (!cpswSimTest)\r
+ if (no_bootMode == TRUE)\r
{\r
- System_printf("Following is the ALE table before transmits.\n");\r
- view_ale_table(); // Added by Atsushi\r
+ if (!cpswSimTest)\r
+ {\r
+ System_printf("Following is the ALE table before transmits.\n");\r
+ view_ale_table(); // Added by Atsushi\r
+ }\r
}\r
+\r
+#ifndef __LINUX_USER_SPACE\r
+ System_printf ("CSL_CPSW_nGF Status before Packet Transmission ...\n");\r
+ memset(stats, 0, sizeof(stats));\r
+ cpsw_getStats(stats);\r
+#endif\r
\r
/* Run some data through and verify transfer worked */\r
System_printf ("Packet Transmission Start ... \n");\r
}\r
}\r
\r
- if (!cpswSimTest)\r
+ if (no_bootMode == TRUE)\r
{\r
- System_printf("Following is the ALE table after transmits.\n");\r
- view_ale_table(); \r
+ if (!cpswSimTest)\r
+ {\r
+ System_printf("Following is the ALE table after transmits.\n");\r
+ view_ale_table();\r
+ }\r
}\r
\r
/* Wait until all packet reception is done */\r
{\r
System_printf("Verififcation Failed for Received %d packets so far...\n", gRxCounter);\r
}\r
-#endif\r
+#endif \r
CycleDelay (10000);\r
\r
if (!cpswSimTest)\r
System_printf ("Function getPaStats failed\n");\r
}\r
\r
-\r
+#ifndef __LINUX_USER_SPACE\r
+ System_printf ("CSL_CPSW_nGF Status after Packet Transmission ...\n");\r
+ cpsw_getStats(stats);\r
+#endif\r
System_printf ("**************************************************\n");\r
System_printf ("******** Ethernet Single Core Example End ********\n");\r
System_printf ("**************************************************\n");\r
System_printf ("Failed to Clean the example application \n");\r
}\r
\r
+#if (RM) && !defined(__LINUX_USER_SPACE)\r
+ {\r
+ int32_t rmResult;\r
+\r
+ if ((rmResult = Rm_resourceStatus(rmHandle, FALSE)) != 0)\r
+ {\r
+ System_printf ("Error : Number of unfreed resources : %d\n", rmResult);\r
+ }\r
+ else\r
+ {\r
+ System_printf ("All resources freed successfully\n");\r
+ }\r
+ }\r
+#endif\r
/* Example application done. Return success */\r
APP_exit (0);\r
\r
index 403f22001ce2c25c79f50cee0d05e4eb55c9f429..0f47c244486839d9f14c6bd28c14199617b54c15 100755 (executable)
/** Number of PA Rx channels available */\r
#define NUM_PA_RX_CHANNELS 24\r
\r
+/* Initial RX queue number */\r
+#define RX_QUEUE_NUM_INIT 900\r
+\r
+/* High Priority QM Rx Interrupt Threshold */\r
+#define RX_INT_THRESHOLD 1u\r
+\r
+/* Accumulator channel to use */\r
+#define PA_ACC_CHANNEL_NUM 0u\r
+\r
#define CACHE_LINESZ 128\r
#define SYS_ROUND_UP(x,y) ((x) + ((y) -1))/(y)*(y)\r
\r
/* Define the Receive Data Buffer size */\r
#define PA_EMAC_EX_RXBUF_SIZE 1518\r
\r
+/* Resource manager */\r
+#ifdef __LINUX_USER_SPACE\r
+#define RM 0\r
+#else\r
+#define RM 1\r
+#endif\r
+\r
+#if RM\r
+extern int setupRm (void);\r
+extern Rm_Handle rmHandle;\r
+extern Rm_ServiceHandle *rmServiceHandle;\r
+#endif\r
extern int cpswLpbkMode;\r
extern int cpswSimTest;\r
extern Cppi_FlowHnd gRxFlowHnd;\r
extern Qmss_QueueHnd gPaTxQHnd [NUM_PA_TX_QUEUES], gTxFreeQHnd, gRxFreeQHnd;\r
extern volatile uint32_t gTxCounter, gRxCounter;\r
extern uint8_t pktMatch[];\r
+extern uint32_t no_bootMode;\r
\r
extern int32_t Cpsw_SwitchOpen (void);\r
extern int32_t Mdio_Open (void);\r
extern void* Cpsw_SingleCoreApp (void *args);\r
#else\r
extern int32_t Init_Cpsw (void);\r
+extern void cpsw_getStats(CSL_CPSW_5GF_STATS* stats);\r
extern void Cpsw_SingleCoreApp (void);\r
extern int32_t Download_PAFirmware (void);\r
extern void CycleDelay (int32_t count);\r
index 046f1ff554dd524f444e99bd0d84d8a92830b2d9..cdd7199ff6adbb9ea6f6b0dcc30920e9db088dc6 100755 (executable)
/* PASS RL file */\r
#include <ti/csl/cslr_device.h>\r
#include <ti/csl/cslr_pa_ss.h>\r
+#include <ti/csl/csl_pscAux.h>\r
\r
#ifdef __LINUX_USER_SPACE\r
#include "armv7/linux/fw_test.h"\r
* The simulator does not record the ingress port number.\r
* Therefore, we need to remove inport configuration for simulator operation\r
*/\r
- if (cpswSimTest)\r
+ if ((cpswSimTest) || (no_bootMode == FALSE))\r
{\r
- ethInfo.inport = 0;\r
+ ethInfo.inport = pa_EMAC_PORT_NOT_SPECIFIED;\r
}\r
#endif\r
retVal = Pa_addMac (gPAInstHnd,\r
int32_t sizes[pa_N_BUFS];\r
int32_t aligns[pa_N_BUFS];\r
void* bases[pa_N_BUFS];\r
- \r
+\r
memset(&paSize, 0, sizeof(paSizeInfo_t));\r
memset(&paCfg, 0, sizeof(paConfig_t));\r
memset(bases, 0, sizeof(bases));\r
#else\r
paCfg.baseAddr = CSL_NETCP_CFG_REGS;\r
#endif\r
+\r
+#if RM\r
+ paCfg.rmServiceHandle = rmServiceHandle;\r
+#endif\r
+\r
paCfg.sizeCfg = &paSize;\r
if ((retVal = Pa_create (&paCfg, bases, &gPAInstHnd)) != pa_OK) \r
{\r
System_printf ("Pa_create returned with error code %d\n", retVal);\r
return -1;\r
}\r
- /* Download of PASS PDSP firmware being skipped for linux user mode as this is already taken care by Kernel*/\r
+\r
#ifndef __LINUX_USER_SPACE\r
- /* Download the PASS PDSP firmware */\r
- if (Download_PAFirmware ())\r
+ /* Download the PASS PDSP firmware only if no boot mode is set*/\r
+ if (no_bootMode == TRUE)\r
{\r
- return -1;\r
+ if (Download_PAFirmware ())\r
+ {\r
+ return -1;\r
+ }\r
}\r
#endif\r
-\r
/* Open a PA Command Response Queue.\r
*\r
* This queue will be used to hold responses from the PA PDSP for all the\r
index dbcb3d8fc9ea12791518e0a65aa38dafb8008fcb..f2b7589821348426322e2c5514b6ef5c5bb9e39e 100755 (executable)
This example also demonstrates the normal CPSW configuration as CPSW_LOOPBACK_NONE mode. In this configuration, it is up to the user\r
to modify PASS configuration to receive desired ingress packets.\r
\r
--------------------------\r
-Steps to run the example\r
--------------------------\r
+-------------------------------------\r
+Steps to run the example on DSP\r
+-------------------------------------\r
1. Simulator configuration\r
\r
In order for the example to work in external loopback mode successfully, i.e. to be able to send/receive data packets from the wire, \r
@@ -51,11 +51,17 @@ Once the number of cores is set, select the project in CCS, clean it (Project->c
3. Execute\r
\r
To execute the project ensure the following is done:\r
- a) Reset the cores (EVM only)\r
- b) Run EVM specific GEL scripts (EVM only)\r
+ a) Reset the cores (applicable for EVM under NO_BOOT mode only)\r
+ b) Run EVM specific GEL scripts (applicable for EVM under NO_BOOT mode only)\r
c) Load the program into the cores (0 - NUM_CORES) before running any core. \r
d) Run the cores (0 - NUM_CORES).\r
\r
+NOTE:\r
+If EVM is *NOT* running in NO_BOOT mode, the below assumptions are made\r
+3a. The PDSPs are downloaded for QMSS and PA outside the example\r
+3b. CPSW Switch is configured outside the example\r
+3c. To disable the auto detect logic, please set 'autodetectLogic' variable to '0' using CCS. When this is done, the all the steps as mentioned in 'Execute' section are mandatory.\r
+\r
4. Result\r
\r
Each core will output to the console its status progress and the number of sent/received packets.\r
diff --git a/example/multicoreExample/k2h/c66/bios/PA_multicoreExample_K2HC66BiosExampleProject.txt b/example/multicoreExample/k2h/c66/bios/PA_multicoreExample_K2HC66BiosExampleProject.txt
index 7fbf4732dea6486de7568d80cc051b93e8907dee..f2b54a5c9d532b75db92e4e78d85b18e241d3100 100755 (executable)
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/multicoreExample/k2h/c66/bios/multicore_linker.cmd"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2h/global-resource-list.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2h/policy_dsp-only.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2h/policy_dsp_arm.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_transport_setup.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/multicoreExample/k2h/c66/bios/multicore_example.cfg"
-ccs.setCompilerOptions "-D -mv64+ -g -DDEVICE_K2H --diag_warning=225 --mem_model:data=far -I${PASS_INSTALL_PATH} -I${PASS_INSTALL_PATH}/ti/drv/pa/example/multicoreExample/src -I${PDK_INSTALL_PATH}/ti/drv/cppi -I${PDK_INSTALL_PATH}/ti/drv/qmss" -rtsc.enableRtsc
diff --git a/example/multicoreExample/k2h/c66/bios/multicore_example.cfg b/example/multicoreExample/k2h/c66/bios/multicore_example.cfg
index 51cf3752f6c609ead2a7b43fa6176113593865b4..6423a96050d0e12a8746218b3fda600804f07f85 100755 (executable)
SysStd = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;
+/* Below configuration is needed if the DSP executable needs to be loaded from MPM client from ARM */
+/*
+ * The SysMin used here vs StdMin, as trace buffer address is required for
+ * Linux trace debug driver, plus provides better performance.
+ */
+Program.global.sysMinBufSize = 0x8000;
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize = Program.global.sysMinBufSize;
+
+/* Configure resource table for trace only.
+ Note that, it traceOnly parameter should not
+ be set if application is using MessageQ based IPC
+ to communicate between cores.
+ */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = Program.platform.dataMemory;
+Resource.traceOnly = true;
+
+/* end MPM Client Configurations */
/* Create a default system heap using ti.bios.HeapMem. */
var heapMemParams1 = new HeapMem.Params;
Program.sectMap["systemHeap"] = Program.platform.stackMemory;
+var heapMemParams2 = new HeapMem.Params;
+heapMemParams2.size = 16384;
+heapMemParams2.align = 8;
+heapMemParams2.sectionName = "cppiSharedHeap";
+Program.global.cppiSharedHeap = HeapMem.create(heapMemParams2);
+
/* Enable BIOS Task Scheduler */
BIOS.taskEnabled = true;
Program.sectMap[".sharedDDR"] = "MSMCSRAM";
Program.sectMap[".cppiMemTX"] = "MSMCSRAM";
Program.sectMap[".cppiMemRX"] = "MSMCSRAM";
-
+/* Section not to be loaded by remoteproc loader */
+Program.sectMap[".noload_section"].type = "NOLOAD";
/* Add init function, make sure the shared memory is created well in advance */
Startup.lastFxns.$add('&fw_shmCreate');
diff --git a/example/multicoreExample/k2h/c66/bios/multicore_linker.cmd b/example/multicoreExample/k2h/c66/bios/multicore_linker.cmd
index 8c8b513397ccd353d50a263fc9f64f0d220298ca..9d3c2680aa6728f6b814ca9b51a375ff3fb062bf 100755 (executable)
.sharedGRL: load >> L2SRAM
.sharedPolicy: load >> L2SRAM
.rm: load >> MSMCSRAM
+ cppiSharedHeap: load >> MSMCSRAM
}
diff --git a/example/multicoreExample/k2h/c66/bios/multicore_osal.c b/example/multicoreExample/k2h/c66/bios/multicore_osal.c
index a0a1932dd718c9cf15d0913930a6c34d2ccad00d..f8a677b6ea2b2c66382d149250101e233c8b19f7 100755 (executable)
cpswCppiMallocCounter++;
/* Allocate memory. */
- return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+ return Memory_alloc(cppiHeap, num_bytes, 0, &errorBlock);
}
/**
/* Convert the global address to local address since
* thats what the heap understands.
*/
- Memory_free(NULL, dataPtr, num_bytes);
+ Memory_free(cppiHeap, dataPtr, num_bytes);
}
}
diff --git a/example/multicoreExample/k2k/c66/bios/PA_multicoreExample_K2KC66BiosExampleProject.txt b/example/multicoreExample/k2k/c66/bios/PA_multicoreExample_K2KC66BiosExampleProject.txt
index 3193d148ed161fa9a3b4057ca3f9415c5f6ca842..209da433fde2a0aba413563949652884aa223ed6 100755 (executable)
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/multicoreExample/k2k/c66/bios/multicore_linker.cmd"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2k/global-resource-list.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2k/policy_dsp-only.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/k2k/policy_dsp_arm.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_transport_setup.c"
-ccs.linkFile "PASS_INSTALL_PATH/ti/drv/pa/example/multicoreExample/k2k/c66/bios/multicore_example.cfg"
-ccs.setCompilerOptions "-D -mv64+ -g -DDEVICE_K2K --diag_warning=225 --mem_model:data=far -I${PASS_INSTALL_PATH} -I${PASS_INSTALL_PATH}/ti/drv/pa/example/multicoreExample/src -I${PDK_INSTALL_PATH}/ti/drv/cppi -I${PDK_INSTALL_PATH}/ti/drv/qmss" -rtsc.enableRtsc
diff --git a/example/multicoreExample/k2k/c66/bios/multicore_example.cfg b/example/multicoreExample/k2k/c66/bios/multicore_example.cfg
index 05c5f25d21b1d320cb742fcc9e5d599c0faa3418..a3d120acc74a5f78d890e9240ad569b8146d5440 100755 (executable)
SysStd = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;
+/* Below configuration is needed if the DSP executable needs to be loaded from MPM client from ARM */
+/*
+ * The SysMin used here vs StdMin, as trace buffer address is required for
+ * Linux trace debug driver, plus provides better performance.
+ */
+Program.global.sysMinBufSize = 0x8000;
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize = Program.global.sysMinBufSize;
+
+/* Configure resource table for trace only.
+ Note that, it traceOnly parameter should not
+ be set if application is using MessageQ based IPC
+ to communicate between cores.
+ */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = Program.platform.dataMemory;
+Resource.traceOnly = true;
+
+/* end MPM Client Configurations */
/* Create a default system heap using ti.bios.HeapMem. */
var heapMemParams1 = new HeapMem.Params;
Program.sectMap["systemHeap"] = Program.platform.stackMemory;
+var heapMemParams2 = new HeapMem.Params;
+heapMemParams2.size = 16384;
+heapMemParams2.align = 8;
+heapMemParams2.sectionName = "cppiSharedHeap";
+Program.global.cppiSharedHeap = HeapMem.create(heapMemParams2);
+
/* Enable BIOS Task Scheduler */
BIOS.taskEnabled = true;
Program.sectMap[".sharedDDR"] = "MSMCSRAM";
Program.sectMap[".cppiMemTX"] = "MSMCSRAM";
Program.sectMap[".cppiMemRX"] = "MSMCSRAM";
-
+/* Section not to be loaded by remoteproc loader */
+Program.sectMap[".noload_section"].type = "NOLOAD";
/* Add init function, make sure the shared memory is created well in advance */
Startup.lastFxns.$add('&fw_shmCreate');
diff --git a/example/multicoreExample/k2k/c66/bios/multicore_linker.cmd b/example/multicoreExample/k2k/c66/bios/multicore_linker.cmd
index 8c8b513397ccd353d50a263fc9f64f0d220298ca..9d3c2680aa6728f6b814ca9b51a375ff3fb062bf 100755 (executable)
.sharedGRL: load >> L2SRAM
.sharedPolicy: load >> L2SRAM
.rm: load >> MSMCSRAM
+ cppiSharedHeap: load >> MSMCSRAM
}
diff --git a/example/multicoreExample/k2k/c66/bios/multicore_osal.c b/example/multicoreExample/k2k/c66/bios/multicore_osal.c
index a0a1932dd718c9cf15d0913930a6c34d2ccad00d..f8a677b6ea2b2c66382d149250101e233c8b19f7 100755 (executable)
cpswCppiMallocCounter++;
/* Allocate memory. */
- return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+ return Memory_alloc(cppiHeap, num_bytes, 0, &errorBlock);
}
/**
/* Convert the global address to local address since
* thats what the heap understands.
*/
- Memory_free(NULL, dataPtr, num_bytes);
+ Memory_free(cppiHeap, dataPtr, num_bytes);
}
}
diff --git a/example/multicoreExample/src/armv7/linux/framework.c b/example/multicoreExample/src/armv7/linux/framework.c
index 25d490a3193b776ff97da33d18930ba58483cf7b..804e6a89ec2274cbefec3acfbebad9ad9b6c3864 100755 (executable)
\r
}\r
\r
+void APP_waitSlaveTestStatus(void)\r
+{\r
+ uint32_t testRxCnt;\r
+\r
+ do {\r
+ testRxCnt = (uint32_t) fw_shmGetEntry(allPktRxCntAddr);\r
+ yield();\r
+ } while (testRxCnt != (pa_MC_EXAMPLE_NUM_CORES-1));\r
+\r
+}\r
+\r
void APP_waitTestStatus(void)\r
{\r
uint32_t testRxCnt;\r
diff --git a/example/multicoreExample/src/c66x/bios/framework.c b/example/multicoreExample/src/c66x/bios/framework.c
index d68cca71aac73394306498da69a595431715503a..98b6f6ede7c5ac341448f3d0083ce8247f91c8dd 100755 (executable)
} while (localCfgDone != pa_MC_EXAMPLE_NUM_CORES);\r
}\r
\r
+void APP_waitSlaveTestStatus(void)\r
+{\r
+ uint32_t testRxCnt;\r
+\r
+ do {\r
+ testRxCnt = (uint32_t) fw_shmGetEntry(allPktRxCntAddr);\r
+ yield();\r
+ } while (testRxCnt != (pa_MC_EXAMPLE_NUM_CORES-1));\r
+\r
+}\r
+\r
void APP_waitTestStatus(void)\r
{\r
uint32_t testRxCnt;\r
diff --git a/example/multicoreExample/src/c66x/bios/fw_main.c b/example/multicoreExample/src/c66x/bios/fw_main.c
index 8ba6d7bb99349ae1d619c433ac2a99fcb6242938..1a7927a52ae03458bdc5b26a95512e281d5fc1e6 100755 (executable)
#pragma DATA_SECTION (isRmInitialized, ".rm");
volatile uint32_t isRmInitialized;
+#ifdef SIMULATOR_SUPPORT
+uint32_t autodetectLogic = FALSE;
+#else
+uint32_t autodetectLogic = TRUE;
+#endif
+
+
/** ============================================================================
* @n@b main
*
#else
Task_Params cpswTaskParams;
#endif
-
+ uint32_t bootMode;
/* Init internal cycle counter */
TSCL = 1;
+ if (autodetectLogic == TRUE)
+ {
+ bootMode = CSL_BootCfgGetBootMode();
+
+ if (bootMode == 0)
+ no_bootMode = TRUE;
+ else
+ no_bootMode = FALSE;
+ }
+ else {
+ no_bootMode = TRUE;
+ }
+
+
/* Get the core number. */
coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
/* Power up PASS from Master process/core */
- if (coreNum == SYSINIT)
+ if ( (coreNum == SYSINIT) && (no_bootMode == TRUE) )
{
/* Enable PASS power domain */
passPowerUp();
System_sprintf (rmInstName, "RM_Server");
rmInitCfg.instName = rmInstName;
rmInitCfg.instType = Rm_instType_SERVER;
- rmInitCfg.instCfg.serverCfg.globalResourceList = (void *)rmGlobalResourceList;
- rmInitCfg.instCfg.serverCfg.globalPolicy = (void *)rmDspOnlyPolicy;
+
+ if (no_bootMode == TRUE) {
+ rmInitCfg.instCfg.serverCfg.globalResourceList = (void *)rmGlobalResourceList;
+ rmInitCfg.instCfg.serverCfg.globalPolicy = (void *)rmDspOnlyPolicy;
+ }
+ else {
+ rmInitCfg.instCfg.serverCfg.globalResourceList = (void *)rmGlobalResourceList;
+ rmInitCfg.instCfg.serverCfg.globalPolicy = (void *)rmDspPlusArmPolicy;
+ }
rmHandle = Rm_init(&rmInitCfg, &rmResult);
if (rmResult != RM_OK)
{
diff --git a/example/multicoreExample/src/cppi_qmss_mgmt.c b/example/multicoreExample/src/cppi_qmss_mgmt.c
index 508ba9138bc4e181ab7ced9fcd4dc2e97d394a49..f502c1582c461c2040163a39470b3ea42edb3e8f 100755 (executable)
uint8_t cppiMemRX[NUM_RX_DESC][RX_BUF_SIZE];\r
#endif\r
\r
+#ifndef __LINUX_USER_SPACE\r
+/**\r
+ * @b Description\r
+ * @n\r
+ * The function is used to get the handle to the CPPI memory heap.\r
+ * If the application is run on a multiple cores then place the CPPI global\r
+ * variables in shared memory.\r
+ *\r
+ * @retval\r
+ * Not Applicable\r
+ */\r
+static void cppiHeapInit ()\r
+{\r
+ cppiHeap = HeapMem_Handle_upCast (cppiSharedHeap);\r
+}\r
+#endif\r
/** ============================================================================\r
* @n@b Init_Qmss\r
*\r
/* Bypass hardware initialization as it is done within Kernel */\r
qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;\r
#else\r
- qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;\r
+ if (no_bootMode == TRUE)\r
+ {\r
+ qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;\r
#ifdef _LITTLE_ENDIAN \r
- qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;\r
- qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);\r
+ qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;\r
+ qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);\r
#else\r
- qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;\r
- qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);\r
-#endif \r
+ qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;\r
+ qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ /* Bypass hardware initialization as it is done within Kernel */\r
+ qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;\r
+ }\r
#endif\r
\r
#if RM\r
qmssGblCfgParams.qmRmServiceHandle = rmClientServiceHandle;\r
#endif\r
+\r
+#ifndef __LINUX_USER_SPACE\r
+ /* Initialize the heap in shared memory for CPPI data structures */\r
+ cppiHeapInit ();\r
+#endif\r
+\r
/* Initialize the Queue Manager */\r
fw_qmssGblCfgParams = &qmssGblCfgParams;\r
get_qmssGblCfgParamsRegsPhy2Virt(fw_qmssGblCfgParams);\r
{\r
if ((gPaTxQHnd[i] = Qmss_queueOpen (Qmss_QueueType_PASS_QUEUE, pa_tx_queues, &isAllocated)) < 0)\r
{\r
- System_printf ("Error opening PA Tx queue \n");\r
+ System_printf ("Error opening PA Tx queue (slaves), err:%d \n", gPaTxQHnd[i]);\r
APP_exit(-1);\r
}\r
}\r
*/\r
if ((gTxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_STARVATION_COUNTER_QUEUE, txFreeQInfo.qNum, &isAllocated)) < 0)\r
{\r
- System_printf ("Error opening Tx Free descriptor queue \n");\r
+ System_printf ("Error opening Tx Free descriptor queue(slaves), err:%d \n", gTxFreeQHnd);\r
APP_exit (-1);\r
} \r
\r
\r
if ((gPaTxQHnd[i] = Qmss_queueOpen (Qmss_QueueType_PASS_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
{\r
- System_printf ("Error opening PA Tx queue \n");\r
+ System_printf ("Error opening PA Tx queue (master) err: %d\n", gPaTxQHnd[i]);\r
return -1;\r
} \r
}\r
*/\r
if ((gTxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_STARVATION_COUNTER_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)\r
{\r
- System_printf ("Error opening Tx Free descriptor queue \n");\r
+ System_printf ("Error opening Tx Free descriptor queue (master), err: %d \n", gTxFreeQHnd);\r
return -1;\r
} \r
\r
/* Reenable Interrupts. */\r
Hwi_restore(key);\r
#endif \r
+\r
+#ifndef __LINUX_USER_SPACE\r
/* Send the packet out the mac. It will loop back to PA if the mac/switch \r
* have been configured properly \r
- */ \r
-#ifndef __LINUX_USER_SPACE \r
- Qmss_queuePushDescSize (gPaTxQHnd[8], pCppiDesc, SIZE_HOST_DESC);\r
+ */\r
+ if (no_bootMode == TRUE)\r
+ Qmss_queuePushDescSize (gPaTxQHnd[8], pCppiDesc, SIZE_HOST_DESC);\r
+ else\r
+ Qmss_queuePushDescSize (gPaTxQHnd[0], pCppiDesc, SIZE_HOST_DESC); /* internal loop back */\r
#else\r
Qmss_queuePushDescSize (gPaTxQHnd[0], pCppiDesc, SIZE_HOST_DESC);\r
#endif\r
extern Qmss_QueueHnd gPaCfgCmdRespQHnd;\r
\r
/* The 10 PA transmit queues (corresponding to the 10 tx cdma channels */\r
- if (procId == SYSINIT) {\r
- for (i = 0; i < NUM_PA_TX_QUEUES; i++) {\r
- Qmss_queueEmpty (gPaTxQHnd[i]);\r
- Qmss_queueClose (gPaTxQHnd[i]);\r
- }\r
+ for (i = 0; i < NUM_PA_TX_QUEUES; i++) {\r
+ Qmss_queueEmpty (gPaTxQHnd[i]);\r
+ Qmss_queueClose (gPaTxQHnd[i]);\r
+ }\r
\r
- /* Empty the remaining queues */\r
- Qmss_queueEmpty (gTxFreeQHnd);\r
- Qmss_queueEmpty (gRxFreeQHnd);\r
- Qmss_queueEmpty (gPaCfgCmdRespQHnd);\r
- }\r
- \r
- Qmss_queueEmpty (gRxQHnd);\r
-\r
- /* Close the remaining queues */\r
- if (procId == SYSINIT) { \r
- Qmss_queueClose (gTxFreeQHnd);\r
- Qmss_queueClose (gRxFreeQHnd);\r
- Qmss_queueClose (gPaCfgCmdRespQHnd);\r
- }\r
- \r
- Qmss_queueClose (gRxQHnd);\r
+ if (procId == SYSINIT)\r
+ {\r
+ Qmss_queueEmpty(gGlobalFreeQHnd);\r
+ Qmss_queueClose(gGlobalFreeQHnd); \r
+\r
+ /* Empty the remaining queues */\r
+ Qmss_queueEmpty (gTxFreeQHnd);\r
+ Qmss_queueEmpty (gRxFreeQHnd);\r
+ }\r
+\r
+ Qmss_queueClose (gTxFreeQHnd);\r
+ Qmss_queueClose (gRxFreeQHnd); \r
+\r
+ Qmss_queueEmpty (gPaCfgCmdRespQHnd); \r
+ Qmss_queueEmpty (gRxQHnd);\r
+ Qmss_queueClose (gPaCfgCmdRespQHnd);\r
+ Qmss_queueClose (gRxQHnd);\r
\r
- return;\r
+ return;\r
\r
}\r
\r
-/* The QM/CPDMA are cleared */\r
-int clearQm(uint32_t procId)\r
+int clearFramework(uint32_t procId)\r
{\r
- int result, i;\r
-\r
- if (procId == SYSINIT) {\r
+ int i;\r
+ Qmss_Result qmss_result;\r
+ Cppi_Result cppi_result;\r
+ \r
+ \r
/* clear the flows */\r
- if ((result = Cppi_closeRxFlow (gRxFlowHnd)) != CPPI_SOK) {\r
- return (-1);\r
- }\r
+ if ((cppi_result = Cppi_closeRxFlow (gRxFlowHnd)) != CPPI_SOK) {\r
+ return (-1);\r
}\r
\r
/* Close the queues that were setup */\r
closeAllOpenedQueues(procId);\r
\r
- if (procId == SYSINIT) {\r
+ if (procId == SYSINIT) {\r
/* Close the cpDma setup */\r
for (i = 0; i < NUM_PA_RX_CHANNELS; i++) {\r
- if ((result = Cppi_channelClose (gCpdmaRxChanHnd[i])) != CPPI_SOK) {\r
- return (result);\r
+ if ((cppi_result = Cppi_channelClose (gCpdmaRxChanHnd[i])) != CPPI_SOK) {\r
+ return (cppi_result);\r
}\r
}\r
for (i = 0; i < NUM_PA_TX_QUEUES; i++) {\r
- if ((result = Cppi_channelClose (gCpdmaTxChanHnd[i])) != CPPI_SOK) {\r
- return (result);\r
+ if ((cppi_result = Cppi_channelClose (gCpdmaTxChanHnd[i])) != CPPI_SOK) {\r
+ return (cppi_result);\r
}\r
}\r
- \r
- /* Free the memory regions */\r
- if ((result = Qmss_removeMemoryRegion (Qmss_MemRegion_MEMORY_REGION0, 0)) != QMSS_SOK)\r
- {\r
- System_printf ("Error Core : Remove memory region error code : %d\n", result);\r
- }\r
}\r
\r
- return (0);\r
-\r
-}\r
-\r
-int clearFramework(uint32_t procId)\r
-{\r
-\r
- /* Delete the port added */\r
- if (Del_Port() < 0)\r
- {\r
- System_printf ("Failed to delete the L2 entry for the MAC address for procId: %d\n", procId);\r
- }\r
-\r
+#ifndef __LINUX_USER_SPACE\r
if (procId == SYSINIT)\r
+#endif\r
{\r
- /* Delete the Ip Address added */\r
- if (Del_IPAddress() < 0)\r
- {\r
- System_printf ("Failed to delete the L2 entry for IP address for procId: %d\n", procId);\r
- }\r
- \r
- /* Delete the MAC Address added */\r
- if (Del_MACAddress() < 0)\r
- {\r
- System_printf ("Failed to clean up the MAC address for procId: %d\n", procId);\r
- }\r
+ /* Close CPPI CPDMA instance */\r
+ if ((cppi_result = Cppi_close (gCpdmaHnd)) != CPPI_SOK)\r
+ {\r
+ errorCount++;\r
+ System_printf ("Error Core %d : Closing CPPI CPDMA error code : %d\n", coreNum, cppi_result);\r
+ }\r
+ else \r
+ {\r
+ System_printf ("Core %d : CPPI CPDMA closed successfully\n", coreNum);\r
+ }\r
+\r
+ /* Deinitialize CPPI LLD */\r
+ if ((cppi_result = Cppi_exit ()) != CPPI_SOK)\r
+ {\r
+ errorCount++;\r
+ System_printf ("Error Core %d : Exiting CPPI error code : %d\n", coreNum, cppi_result);\r
+ }\r
+ else \r
+ {\r
+ System_printf ("Core %d : CPPI exit successful\n", coreNum);\r
+ }\r
+ }\r
+\r
+ /* Free the memory regions */\r
+ if (procId == SYSINIT) {\r
+ if ((qmss_result = Qmss_removeMemoryRegion (Qmss_MemRegion_MEMORY_REGION0, 0)) != QMSS_SOK)\r
+ {\r
+ System_printf ("Error Core : Remove memory region error code : %d\n", qmss_result);\r
+ }\r
}\r
\r
- /* The QM/CPDMA are cleared, wait until all PA configuration clean up happens */\r
- if (clearQm(procId) < 0)\r
+ /* Exit QMSS */\r
+#ifdef __LINUX_USER_SPACE\r
+ System_printf ("Core %d: exit QMSS\n", coreNum);\r
+ if ((qmss_result = Qmss_exit ()))\r
{\r
- System_printf(" Failed to clean qm/cppi for procId: %d\n", procId);\r
- return (-1);\r
- } \r
-\r
+ errorCount++;\r
+ System_printf ("Error Core %d : exit error code : %d\n", coreNum, qmss_result);\r
+ }\r
+#else\r
+ if (procId == SYSINIT)\r
+ {\r
+ System_printf ("Core %d: exit QMSS\n", coreNum);\r
+ while ((qmss_result = Qmss_exit()) != QMSS_SOK)\r
+ {\r
+ yield(); /* Wait for other cores to close their queues */\r
+ }\r
+ }\r
+#endif\r
return (0);\r
-\r
}\r
\r
\r
diff --git a/example/multicoreExample/src/local_variables.c b/example/multicoreExample/src/local_variables.c
index 5b4aaec4a64723b38ff163b50b997b17dfbdf4bb..5308a29979153d1b867ab83b63d7879f8fe8fa0a 100755 (executable)
Int cpswLpbkMode = CPSW_LOOPBACK_INTERNAL;\r
#endif\r
\r
+/* Default test configuration for the silicon\r
+ * \r
+ * To run the test at the CCS (with no boot mode, using GEL files) - Default\r
+ * no_bootMode = TRUE\r
+ * To run the test at the CCS (with other boot modes when linux is up)\r
+ * no_bootMode = FALSE \r
+ */\r
+int no_bootMode = TRUE;\r
+\r
void mdebugHaltPdsp (Int pdspNum);\r
volatile Int mdebugWait = 1;\r
\r
/* Indicates the core or logical task ID test is running on */\r
uint32_t coreNum;\r
\r
+/* Indicate the test status */\r
+char test_stat[50];\r
+\r
+#ifndef __LINUX_USER_SPACE\r
+/* Handle to CPPI heap */\r
+IHeap_Handle cppiHeap;\r
+#endif\r
+\r
+\r
diff --git a/example/multicoreExample/src/multicore_example.c b/example/multicoreExample/src/multicore_example.c
index 578877195da162459bd6160e7dd1f8565d3afb87..36a9ef90689161b7f22c5974179062019b787a0c 100755 (executable)
* (1) Initializes:\r
* (a) Queue Manager (QM) Subsystem \r
* (b) Packet Accelerator (PA) CPPI DMA \r
- * (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO)\r
- * (d) PA Subsystem + PDSP\r
+ * (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO) - (Note: Applicable only for NO_BOOT mode)\r
+ * (d) PA Subsystem + PDSP (Note: PDSP is initialized only during NO_BOOT mode)\r
*\r
* (2) Sets up the CPPI descriptors and Queues required for sending and\r
* receiving data using Ethernet.\r
#endif\r
{\r
int32_t i;\r
- int32_t rxStatus=TEST_NOT_COMPLETED;\r
- volatile uint32_t testComplete=FALSE;\r
+ volatile uint32_t testComplete=FALSE;\r
\r
#ifdef __LINUX_USER_SPACE\r
#else\r
System_printf ("PASS successfully initialized \n"); \r
}\r
#ifndef __LINUX_USER_SPACE\r
- /* Initialize the CPSW switch */\r
- if (Init_Cpsw () != 0)\r
- {\r
- System_printf ("Ethernet subsystem init failed \n");\r
- APP_exit (-1);\r
- }\r
- else\r
+\r
+ if (no_bootMode == TRUE)\r
{\r
- System_printf ("Ethernet subsystem successfully initialized \n");\r
+ /* Initialize the CPSW switch */\r
+ if (Init_Cpsw () != 0)\r
+ {\r
+ System_printf ("Ethernet subsystem init failed \n");\r
+ APP_exit (-1);\r
+ }\r
+ else\r
+ {\r
+ System_printf ("Ethernet subsystem successfully initialized \n");\r
+ }\r
}\r
#endif\r
/* Setup Tx */\r
APP_waitAllLocalCfgDone();\r
\r
/* Send data towards switch */\r
- System_printf ("Packet Transmission Start ... core id: %d \n", coreNum);\r
+ System_printf ("\n\nPacket Transmission Start ... core id: %d \n", coreNum);\r
for (i = 0; i < MAX_NUM_PACKETS; i ++)\r
{\r
if (SendPacket () != 0)\r
\r
/* Wait until all packet reception is done */\r
System_printf ("Packet Transmission Done.\nWait for all packets to be Received ... core num: %d\n", coreNum);\r
- rxStatus = TEST_PASSED;\r
+ strcpy(test_stat, "TEST_PASSED");\r
while (gRxCounter < gTxCounter)\r
{\r
if(ReceivePacket() != 0) {\r
- rxStatus= TEST_FAILED;\r
+ strcpy(test_stat, "TEST_FAILED"); \r
System_printf ("Test failed on core %d\n",coreNum); \r
}\r
}\r
\r
System_printf ("Core %d: Packets Sent\t\t=\t%d \nCore %d: Packets Received\t=\t%d \n",coreNum, gTxCounter, coreNum, gRxCounter);\r
\r
- /* The global variable is a shared resource which is being accessed from multiple cores. \r
- * So here we need to protect it and ensure that there is only 1 core which is accessing \r
- * it at a time. We use a Hardware Semaphore to protect this. */\r
- System_printf ("Updating the Test Status core: %d, status:%d\n", coreNum, rxStatus); \r
- APP_publishTestStatus();\r
-\r
- /* Clean up for slave process/cores */\r
- if (coreNum != SYSINIT)\r
- clearFramework(coreNum); \r
+ /* Delete the port added */\r
+ if (Del_Port() < 0)\r
+ {\r
+ System_printf ("Failed to delete the L2 entry for the MAC address for procId: %d\n", coreNum);\r
+ } \r
\r
/* Core 0 collects all the results and declare PASS or Fail */\r
if(coreNum == SYSINIT)\r
{\r
System_printf ("Wait for all packets to be Received in all cores... \n");\r
- APP_waitTestStatus();\r
- /* Final Clean up on the Master core */\r
- clearFramework(SYSINIT);\r
+ /* The global variable is a shared resource which is being accessed from multiple cores. \r
+ * So here we need to protect it and ensure that there is only 1 core which is accessing \r
+ * it at a time. We use a Hardware Semaphore to protect this. */\r
+ System_printf ("Updating the Test Status core: %d, status:%s\n", coreNum, test_stat); \r
+ APP_waitSlaveTestStatus();\r
+ }\r
+ else\r
+ {\r
+\r
+ /* Clean up for Qmss/CPPI from slave cores */\r
+ clearFramework(coreNum);\r
+\r
+ /* The global variable is a shared resource which is being accessed from multiple cores. \r
+ * So here we need to protect it and ensure that there is only 1 core which is accessing \r
+ * it at a time. We use a Hardware Semaphore to protect this. */\r
+ System_printf ("Updating the Test Status core: %d, status:%s\n", coreNum, test_stat); \r
+ /* Indicate that the test is complete from slave processes */\r
+ APP_publishTestStatus();\r
+ \r
+ }\r
+\r
+ if (coreNum == SYSINIT) \r
+ {\r
+ /* Delete the Ip Address added */\r
+ if (Del_IPAddress() < 0)\r
+ {\r
+ System_printf ("Failed to delete the L2 entry for IP address for procId: %d\n", coreNum);\r
+ }\r
+ \r
+ /* Delete the MAC Address added */\r
+ if (Del_MACAddress() < 0)\r
+ {\r
+ System_printf ("Failed to clean up the MAC address for procId: %d\n", coreNum);\r
+ }\r
+\r
+ /* Freeup Firmware */\r
\r
+ /* Clean up for Qmss/CPPI from master core */\r
+ clearFramework(coreNum);\r
+\r
+ APP_publishTestStatus(); \r
+ }\r
+\r
+ /* Wait for all test completion from all processes before deleting the shared memory*/\r
+ APP_waitTestStatus();\r
+\r
+ if (coreNum == SYSINIT)\r
+ {\r
/* Delete the Shared memory */\r
fw_shmClose();\r
fw_shmDelete();\r
- \r
+\r
#ifdef __LINUX_USER_SPACE\r
/* Delete the Semaphore */\r
fw_SemDestroy();\r
- #endif \r
+ #endif\r
}\r
+ System_printf (" Done...\n"); \r
\r
System_printf ("**********************************************\n");\r
System_printf ("*** PA Multi Core Example Ended on Core %d ***\n",coreNum);\r
diff --git a/example/multicoreExample/src/multicore_example.h b/example/multicoreExample/src/multicore_example.h
index a0a37bf59c5dae5cfd0e898d2f5deefdf26c0523..851e3aa6edfc6984c61c466bb7286d4a9ee0c874 100755 (executable)
#define TEST_NOT_COMPLETED 0\r
#define TEST_PASSED 1\r
#define TEST_FAILED 2\r
+extern char test_stat[50];\r
+extern int no_bootMode;\r
\r
/* Number of PA internal buffers to allocate */\r
#define PA_NUM_BUFFERS 3\r
extern const char rmGlobalResourceList[];\r
/* RM test Global Policy provided to RM Server */\r
extern const char rmDspOnlyPolicy[];\r
+extern const char rmDspPlusArmPolicy[];\r
/* RM instance transport code */\r
extern int setupRmTransConfig(uint32_t numTestCores, uint32_t systemInitCore, Task_FuncPtr testTask);\r
extern volatile uint32_t isRmInitialized;\r
#endif /* RM */\r
+/* Handle to CPPI heap */\r
+extern IHeap_Handle cppiHeap;\r
#endif /* __LINUX_USER_SPACE */\r
\r
/* Define LoopBack modes */ \r
extern void Setup_Tx_local(void);\r
extern void APP_publishTestStatus(void);\r
extern void APP_waitTestStatus(void);\r
+extern void APP_waitSlaveTestStatus(void);\r
\r
#ifdef __LINUX_USER_SPACE\r
extern void MultiCoreApp(void *args);\r
index 1d8e37bb72d4b25d08a265242177101c2f971e3e..1a81589c8178f8506a9979860099d85df9e2f9d6 100755 (executable)
\r
SYS_CACHE_WB( (void *)gPAInst, BUFSIZE_PA_INST, CACHE_WAIT);\r
#ifndef __LINUX_USER_SPACE \r
- /* Download the PASS PDSP firmware */\r
- if (Download_PAFirmware ())\r
+ /* Download the PASS PDSP firmware only if no boot mode is set */\r
+ if (no_bootMode == TRUE)\r
{\r
- return -1;\r
+ if (Download_PAFirmware ())\r
+ {\r
+ return -1;\r
+ }\r
}\r
#endif\r
/* Open a PA Command Response Queue.\r
index 8b1b6b36c0d2fb7f076735547853abd95e21452b..3240850233700fd0dc0b34b59527b3c821eb226b 100755 (executable)
--- a/pa.h
+++ b/pa.h
*/
#define pa_VIRTUAL_LINK_TABLE_FULL -32
+/**
+ * @def pa_VIRTUAL_LINK_TABLE_FULL
+ * Virtual link table is full
+ */
+#define pa_RESOURCE_FREE_DENIED -33
+
+
/*@}*/
/** @} */
*/
#define pa_STATE_ENABLE_FAILED 5 /**< The Sub-system did not respond after restart */
+/**
+ * @def pa_STATE_RESOURCE_USE_DENIED
+ * Resource manager denied the firmware use
+ */
+#define pa_STATE_RESOURCE_USE_DENIED 6 /**< Resource manager denied the firmware use */
+
/* @} */
/** @} */
diff --git a/package.xdc b/package.xdc
index 7a1afc1ee12df80e4523369f0d82421b25d592ae..a10d87c00119eb0ed4485e5b71a79c389555599f 100755 (executable)
--- a/package.xdc
+++ b/package.xdc
* Copyright (C) 2009-2013, Texas Instruments, Inc.
*****************************************************************************/
-package ti.drv.pa[02,00,01,00] {
+package ti.drv.pa[02,00,01,01] {
module Settings;
}
index 6127557c8f784597e6eb1572c60398cca22fd39a..c12c663574618cfae961e96e1d131fb905af9eab 100755 (executable)
--- a/paver.h
+++ b/paver.h
* format:
* 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
*/
-#define PA_LLD_VERSION_ID (0x02000100)
+#define PA_LLD_VERSION_ID (0x02000101)
/**
* @brief This is the version string which describes the PA LLD along with the
* date and build information.
*/
-#define PA_LLD_VERSION_STR "PA LLD Revision: 02.00.01.00"
+#define PA_LLD_VERSION_STR "PA LLD Revision: 02.00.01.01"
#ifdef __cplusplus
diff --git a/src/pa.c b/src/pa.c
index 31b0d693d2bf2e0b62109a5bc04ac70fc78a17f9..b68302c5748a9c5d9a16fd945f680138de7d82bd 100755 (executable)
--- a/src/pa.c
+++ b/src/pa.c
\r
if (!pa_rmService (Rm_service_RESOURCE_ALLOCATE_USE, rmLut, &dstPdsp)) {\r
return pa_RESOURCE_USE_DENIED;\r
+ }\r
+\r
+ /* we use RM only for permission check, so freeing up immediately */\r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmLut, &dstPdsp)) {\r
+ return pa_RESOURCE_FREE_DENIED;\r
}\r
}\r
\r
if (!pa_rmService (Rm_service_RESOURCE_ALLOCATE_USE, rmLut, &dstPdsp)) {\r
return pa_RESOURCE_USE_DENIED;\r
}\r
+ /* we use RM only for permission check, so freeing up immediately */\r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmLut, &dstPdsp)) {\r
+ return pa_RESOURCE_FREE_DENIED;\r
+ } \r
}\r
\r
/* Sanity chek the LUT1 index */\r
ret = pa_RESOURCE_USE_DENIED;\r
goto Pa_addIp2_end;\r
}\r
+ /* we use RM only for permission check, so freeing up immediately */\r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmLut, cmdDest)) {\r
+ ret = pa_RESOURCE_FREE_DENIED;\r
+ goto Pa_addIp2_end;\r
+ } \r
} \r
\r
if (ret != pa_DUP_ENTRY)\r
paL3Entry_t *l3Table = (paL3Entry_t *)pa_CONV_OFFSET_TO_BASE(paLObj.cfg.instPoolBaseAddr, paInst->paBufs[PA_BUFFNUM_L3_TABLE].base);\r
paVirtualLnk_t *vlnkTable = (paVirtualLnk_t *)pa_CONV_OFFSET_TO_BASE(paLObj.cfg.instPoolBaseAddr, paInst->paBufs[PA_BUFFNUM_VIRTUAL_LNK_TABLE].base);\r
\r
+ /* Future enhancement for RM protection of LUT2 entries */\r
+ #if 0\r
if (paLObj.cfg.rmServiceHandle) {\r
int32_t dstPdsp = pa_CMD_TX_DEST_3;\r
\r
return pa_RESOURCE_USE_DENIED;\r
}\r
}\r
+ #endif\r
\r
/* Verify that there is enough room to create the command */\r
csize = sizeof(pafrmCommand_t) + sizeof(pafrmCommandAddLut2_t) - sizeof(uint32_t);\r
ret = pa_RESOURCE_USE_DENIED;\r
goto Pa_addCustomLUT1_end;\r
}\r
+ /* we use RM only for permission check, so freeing up immediately */\r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmLut, cmdDest)) {\r
+ ret = pa_RESOURCE_FREE_DENIED;\r
+ goto Pa_addCustomLUT1_end;\r
+ } \r
} \r
}\r
\r
if (!pa_rmService (Rm_service_RESOURCE_ALLOCATE_USE, rmLut, &dstPdsp)) {\r
return pa_RESOURCE_USE_DENIED;\r
}\r
+ /* we use RM only for permission check, so freeing up immediately */\r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmLut, &dstPdsp)) {\r
+ return pa_RESOURCE_FREE_DENIED;\r
+ } \r
}\r
\r
/* Sanity check: custom index range check */\r
CSL_Pa_ssRegs *passRegs;\r
paSSstate_t ret = pa_STATE_INVALID_REQUEST;\r
uint32_t mtCsKey; \r
- \r
+\r
+ /* Check permission */\r
+ if ( (newState == pa_STATE_RESET) ||\r
+ (newState == pa_STATE_ENABLE) )\r
+ {\r
+ if (paLObj.cfg.rmServiceHandle) {\r
+ int32_t fw = 0;\r
+\r
+ if (!pa_rmService (Rm_service_RESOURCE_ALLOCATE_USE, rmFirmware, &fw)) {\r
+ return pa_RESOURCE_USE_DENIED;\r
+\r
+ }\r
+ if (!pa_rmService (Rm_service_RESOURCE_ALLOCATE_INIT, rmFirmware, &fw)) {\r
+ /* Use but don't init - Check firmware revision */\r
+ \r
+ /* if check reveals different revision - return PA_FIRMWARE_REVISION_DIFFERENCE; */\r
+ } \r
+ /* we use RM only for permission check, so freeing up immediately */\r
+ \r
+ /* Release firmware "use" */ \r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmFirmware, &fw)) {\r
+ return pa_RESOURCE_USE_DENIED;\r
+ } \r
+ \r
+ /* Release firmware "init" */ \r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmFirmware, &fw)) {\r
+ return pa_RESOURCE_INIT_DENIED;\r
+ } \r
+ }\r
+ }\r
+ \r
/* Refresh PA Instance for read only */\r
Pa_osalMtCsEnter(&mtCsKey);\r
Pa_osalBeginMemAccess (paInst, sizeof(paInst_t));\r
@@ -5393,6 +5449,18 @@ paReturn_t Pa_downloadImage (Pa_Handle iHandle, int modId, void* image, int size
\r
/* if check reveals different revision - return PA_FIRMWARE_REVISION_DIFFERENCE; */\r
} \r
+ /* we use RM only for permission check, so freeing up immediately */\r
+\r
+ /* Release firmware "use" */ \r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmFirmware, &fw)) {\r
+ return pa_RESOURCE_USE_DENIED;\r
+ } \r
+\r
+ /* Release firmware "init" */ \r
+ if (!pa_rmService (Rm_service_RESOURCE_FREE, rmFirmware, &fw)) {\r
+ return pa_RESOURCE_INIT_DENIED;\r
+ } \r
+ \r
}\r
\r
passRegs = (CSL_Pa_ssRegs *)paLObj.cfg.baseAddr;\r