1 /*\r
2 *\r
3 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/\r
4 *\r
5 *\r
6 * Redistribution and use in source and binary forms, with or without\r
7 * modification, are permitted provided that the following conditions\r
8 * are met:\r
9 *\r
10 * Redistributions of source code must retain the above copyright\r
11 * notice, this list of conditions and the following disclaimer.\r
12 *\r
13 * Redistributions in binary form must reproduce the above copyright\r
14 * notice, this list of conditions and the following disclaimer in the\r
15 * documentation and/or other materials provided with the\r
16 * distribution.\r
17 *\r
18 * Neither the name of Texas Instruments Incorporated nor the names of\r
19 * its contributors may be used to endorse or promote products derived\r
20 * from this software without specific prior written permission.\r
21 *\r
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
33 *\r
34 */\r
35 \r
36 #ifndef _PCIE_H\r
37 #define _PCIE_H\r
38 \r
39 #ifdef __cplusplus\r
40 extern "C" {\r
41 #endif\r
42 \r
43 /* System level header files */\r
44 #include <stdint.h>\r
45 #include <stdlib.h>\r
46 #include "pciever.h"\r
47 \r
48 /* ============================================================== */\r
49 /**\r
50 * @file ti/drv/pcie/pcie.h\r
51 *\r
52 * @brief PCIe sub-system API and Data Definitions\r
53 *\r
54 */\r
55 \r
56 /** @mainpage PCIe Low Level Driver\r
57 *\r
58 * @section intro Introduction\r
59 *\r
60 *\r
61 * This document describes the Low Level Driver (LLD) for the Peripheral Component Interconnect Express (PCIe).\r
62 *\r
63 * The PCI Express module supports dual operation mode: End Point (EP or Type0) or Root Complex (RC or Type1).\r
64 * This driver focuses on EP mode but it also provides access to some basic RC configuration/functionalities.\r
65 *\r
66 * The PCIe userguide can be found at <http://www.ti.com/lit/sprugs6a>.\r
67 *\r
68 * The PCIe subsystem has two address spaces. The first (Address Space 0)\r
69 * is dedicated for local application registers, local configuration accesses and remote\r
70 * configuration accesses. The second (Address Space 1) is dedicated for data transfer.\r
71 *\r
72 * The PCIe driver focuses on the registers for Address Space 0.\r
73 *\r
74 * Throughout the LLD, the registers/APIs are grouped into the following:\n\n\r
75 * -# PCIe Application Registers/APIs\n\n\r
76 * -# PCIe Configuration Registers/APIs (Local and Remote)\n\r
77 * 2.1 Type0 and Type1 Common Registers/APIs\n\r
78 * 2.2 Type0 Registers/APIs\n\r
79 * 2.3 Type1 Registers/APIs\n\r
80 * 2.4 MSI Registers/APIs\n\r
81 * 2.5 Capabylity Registers/APIs\n\r
82 * 2.6 Extended Capability Registers/APIs\n\r
83 * 2.7 Port Logic Registers/APIs\n\r
84 *\r
85 * The normal sequence of events to enable the peripheral is listed below.\n\r
86 * There is a C code example in ti/drv/pcie/example/sample.\n\n\r
87 *\r
88 * -# Set up the SERDES PLL, reference clock\r
89 * -# Set up the peripheral mode (EP/RC)\r
90 * -# Power up the peripheral\r
91 * -# Disable link training\r
92 * -# Configure the peripheral, including BAR masks\r
93 * -# Configure Inbound Address Translation\r
94 * -# Configure Outbound Address Translation\r
95 * -# Enable Link Training\r
96 * -# Insure Link Training completion\n\r
97 * PCIe link is up and ready to be used.\r
98 *\r
99 * In order to check that all values are within bounds, the LLD can be\r
100 * recompiled with the -Dpcie_DEBUG compiler flag. This will ensure that\r
101 * all values passed to writes fit within their assigned bitfields.\r
102 */\r
103 \r
104 /* Define pcie LLD Module as a master group in Doxygen format and add all PCIE LLD API\r
105 definitions to this group. */\r
106 \r
107 /** @defgroup pcielld_module PCIE LLD Module API\r
108 * @{\r
109 */\r
110 /** @} */\r
111 \r
112 /** @defgroup pcielld_api_functions PCIE LLD Functions\r
113 * @ingroup pcielld_module\r
114 */\r
115 \r
116 /** @defgroup pcielld_api_macros PCIE LLD Macros\r
117 * @ingroup pcielld_module\r
118 */\r
119 \r
120 /** @defgroup pcielld_api_structures PCIE LLD API Data Structures\r
121 * @ingroup pcielld_module\r
122 */\r
123 \r
124 /** @defgroup pcielld_reg_structures PCIE LLD Register Definitions\r
125 * @ingroup pcielld_module\r
126 */\r
127 \r
128 /** @defgroup pcielld_reg_app_structures PCIE LLD Application Register Definitions\r
129 * @ingroup pcielld_reg_structures\r
130 */\r
131 \r
132 /** @defgroup pcielld_reg_cfg_structures PCIE LLD Configuration Register Definitions\r
133 * @ingroup pcielld_reg_structures\r
134 */\r
135 \r
136 /** @defgroup pcielld_reg_cfg_com_structures PCIE LLD Common (Type0/Type1) Register Definitions\r
137 * @ingroup pcielld_reg_cfg_structures\r
138 */\r
139 \r
140 /** @defgroup pcielld_reg_cfg_type0_structures PCIE LLD Type0 (endpoint) Register Definitions\r
141 * @ingroup pcielld_reg_cfg_structures\r
142 */\r
143 \r
144 /** @defgroup pcielld_reg_cfg_type1_structures PCIE LLD Type1 (root) Register Definitions\r
145 * @ingroup pcielld_reg_cfg_structures\r
146 */\r
147 \r
148 /** @defgroup pcielld_reg_cfg_pwr_structures PCIE LLD Power Management Register Definitions\r
149 * @ingroup pcielld_reg_cfg_structures\r
150 */\r
151 \r
152 /** @defgroup pcielld_reg_cfg_msi_structures PCIE LLD Message Signaled Interrupt Capabilities Register Definitions\r
153 * @ingroup pcielld_reg_cfg_structures\r
154 */\r
155 \r
156 /** @defgroup pcielld_reg_cfg_cap_structures PCIE LLD Capabilities Register Definitions\r
157 * @ingroup pcielld_reg_cfg_structures\r
158 */\r
159 \r
160 /** @defgroup pcielld_reg_cfg_cap_ext_structures PCIE LLD Extended Capabilities Register Definitions\r
161 * @ingroup pcielld_reg_cfg_structures\r
162 */\r
163 \r
164 /** @defgroup pcielld_reg_cfg_pl_structures PCIE LLD Port Logic Register Definitions\r
165 * @ingroup pcielld_reg_cfg_structures\r
166 */\r
167 \r
168 /** @defgroup pcielld_api_constants PCIE LLD Constants (enum's and define's)\r
169 * @ingroup pcielld_module\r
170 */\r
171 \r
172 /** These are the possible values for PCIe mode */\r
173 typedef enum\r
174 {\r
175 pcie_EP_MODE = 0, /**< Required when setting the PCIe Mode to End Point using the @ref Pcie_setInterfaceMode function */\r
176 pcie_LEGACY_EP_MODE, /**< Required when setting the PCIe Mode to Legacy End Point using the @ref Pcie_setInterfaceMode function */\r
177 pcie_RC_MODE /**< Required when setting the PCIe Mode to Root Complex using the @ref Pcie_setInterfaceMode function */\r
178 } pcieMode_e;\r
179 /* @} */\r
180 \r
181 \r
182 /**\r
183 * @ingroup pcielld_api_constants\r
184 *\r
185 * @{\r
186 */\r
187 /** These are the possible values for Prefetch BAR configuration */\r
188 typedef enum\r
189 {\r
190 pcie_BAR_NON_PREF = 0, /**< Non Prefetchable Region*/\r
191 pcie_BAR_PREF /**< Prefetchable Region*/\r
192 } pcieBarPref_e;\r
193 /* @} */\r
194 \r
195 /**\r
196 * @ingroup pcielld_api_constants\r
197 *\r
198 * @{\r
199 */\r
200 /** These are the possible values for Type BAR configuration */\r
201 typedef enum\r
202 {\r
203 pcie_BAR_TYPE32 = 0, /**< 32 bits BAR */\r
204 pcie_BAR_RSVD, /**< Reserved */\r
205 pcie_BAR_TYPE64 /**< 64 bits BAR */\r
206 } pcieBarType_e;\r
207 /* @} */\r
208 \r
209 /**\r
210 * @ingroup pcielld_api_constants\r
211 *\r
212 * @{\r
213 */\r
214 /** These are the possible values for Memory BAR configuration */\r
215 typedef enum\r
216 {\r
217 pcie_BAR_MEM_MEM = 0, /**< Memory BAR */\r
218 pcie_BAR_MEM_IO /**< IO BAR */\r
219 } pcieBarMem_e;\r
220 /* @} */\r
221 \r
222 /**\r
223 * @ingroup pcielld_api_constants\r
224 *\r
225 * @{\r
226 */\r
227 /** These are the possible return values from all PCIE LLD functions */\r
228 typedef enum\r
229 {\r
230 #ifdef pcie_DEBUG\r
231 /**\r
232 * The call succeeded, but the application could have leaked memory\r
233 * since a non-NULL pointer was overwritten. This only\r
234 */\r
235 pcie_RET_DBG_WRITE_OVERFLOW = -100L, /**< write value too big for bitfield */\r
236 #endif\r
237 pcie_RET_OK = 0, /**< Call succeeded */\r
238 pcie_RET_RO_CHANGED, /**< API called with RO bits changed */\r
239 pcie_RET_INV_REG, /**< readRegs/writeRegs unsupported register */\r
240 pcie_RET_INV_HANDLE, /**< Invalid handle */\r
241 pcie_RET_INV_DEVICENUM, /**< @ref Pcie_open deviceNum invalid */\r
242 pcie_RET_INV_INITCFG, /**< Invalid Pcie_InitCfg */\r
243 pcie_RET_INV_FXNPTR, /**< Top level API doesn't have dev specific fxn */\r
244 pcie_RET_NO_INIT /**< Forgot to call Pcie_init() ? */\r
245 } pcieRet_e;\r
246 /* @} */\r
247 \r
248 \r
249 /**\r
250 * @ingroup pcielld_api_constants\r
251 *\r
252 * @{\r
253 */\r
254 /** These are the possible values for the Encoding of LTSSM State in\r
255 * @ref pcieDebug0Reg_t::ltssmState (for hw rev 0) or\r
256 * @ref pcieTiConfDeviceCmdReg_t::ltssmState (for hw rev 1)\r
257 */\r
258 typedef enum\r
259 {\r
260 pcie_LTSSM_DETECT_QUIET=0, /* 0x00 */\r
261 pcie_LTSSM_DETECT_ACT, /* 0x01 */\r
262 pcie_LTSSM_POLL_ACTIVE, /* 0x02 */\r
263 pcie_LTSSM_POLL_COMPLIANCE, /* 0x03 */\r
264 pcie_LTSSM_POLL_CONFIG, /* 0x04 */\r
265 pcie_LTSSM_PRE_DETECT_QUIET, /* 0x05 */\r
266 pcie_LTSSM_DETECT_WAIT, /* 0x06 */\r
267 pcie_LTSSM_CFG_LINKWD_START, /* 0x07 */\r
268 pcie_LTSSM_CFG_LINKWD_ACEPT, /* 0x08 */\r
269 pcie_LTSSM_CFG_LANENUM_WAIT, /* 0x09 */\r
270 pcie_LTSSM_CFG_LANENUM_ACEPT, /* 0x0a */\r
271 pcie_LTSSM_CFG_COMPLETE, /* 0x0b */\r
272 pcie_LTSSM_CFG_IDLE, /* 0x0c */\r
273 pcie_LTSSM_RCVRY_LOCK, /* 0x0d */\r
274 pcie_LTSSM_RCVRY_SPEED, /* 0x0e */\r
275 pcie_LTSSM_RCVRY_RCVRCFG, /* 0x0f */\r
276 pcie_LTSSM_RCVRY_IDLE, /* 0x10 */\r
277 pcie_LTSSM_L0, /* 0x11 */\r
278 pcie_LTSSM_L0S, /* 0x12 */\r
279 pcie_LTSSM_L123_SEND_EIDLE, /* 0x13 */\r
280 pcie_LTSSM_L1_IDLE, /* 0x14 */\r
281 pcie_LTSSM_L2_IDLE, /* 0x15 */\r
282 pcie_LTSSM_L2_WAKE, /* 0x16 */\r
283 pcie_LTSSM_DISABLED_ENTRY, /* 0x17 */\r
284 pcie_LTSSM_DISABLED_IDLE, /* 0x18 */\r
285 pcie_LTSSM_DISABLED, /* 0x19 */\r
286 pcie_LTSSM_LPBK_ENTRY, /* 0x1a */\r
287 pcie_LTSSM_LPBK_ACTIVE, /* 0x1b */\r
288 pcie_LTSSM_LPBK_EXIT, /* 0x1c */\r
289 pcie_LTSSM_LPBK_EXIT_TIMEOUT, /* 0x1d */\r
290 pcie_LTSSM_HOT_RESET_ENTRY, /* 0x1e */\r
291 pcie_LTSSM_HOT_RESET, /* 0x1f */\r
292 pcie_LTSSM_RCVRY_EQ0, /* 0x20 - hw rev 1 only */\r
293 pcie_LTSSM_RCVRY_EQ1, /* 0x21 - hw rev 1 only */\r
294 pcie_LTSSM_RCVRY_EQ2, /* 0x22 - hw rev 1 only */\r
295 pcie_LTSSM_RCVRY_EQ3 /* 0x23 - hw rev 1 only */\r
296 } pcieLtssmState_e;\r
297 /* @} */\r
298 \r
299 \r
300 /**\r
301 * @ingroup pcielld_api_constants\r
302 *\r
303 * @{\r
304 */\r
305 /** Selects whether to query or modify the local or remote PCIe registers.\n\n\r
306 * Important note: PCIe registers are grouped into Application and Configuration registers.\n\r
307 * This definition of Local/Remote is only applicable to PCIe configuration registers.\n\r
308 * It is NOT applicable to PCIe application registers. For application registers, the LLD *always* accesses\r
309 * LOCAL PCIe application registers.\r
310 */\r
311 typedef enum\r
312 {\r
313 pcie_LOCATION_LOCAL, /**< Access the local PCIe peripheral */\r
314 pcie_LOCATION_REMOTE /**< Access the remote PCIe peripheral */\r
315 } pcieLocation_e;\r
316 /* @} */\r
317 \r
318 /**\r
319 * @ingroup pcielld_api_constants\r
320 *\r
321 * @{\r
322 */\r
323 /** These are the possible sizes for the PCIe Outbound translation regions */\r
324 typedef enum\r
325 {\r
326 pcie_OB_SIZE_1MB = 0, /**< Corresponds to a region size of 1MB */\r
327 pcie_OB_SIZE_2MB, /**< Corresponds to a region size of 2MB */\r
328 pcie_OB_SIZE_4MB, /**< Corresponds to a region size of 4MB */\r
329 pcie_OB_SIZE_8MB /**< Corresponds to a region size of 8MB */\r
330 } pcieObSize_e;\r
331 /* @} */\r
332 \r
333 /**\r
334 * @ingroup pcielld_api_constants\r
335 *\r
336 * @{\r
337 */\r
338 /** These are the Enable/Disable values used by the PCIe Driver */\r
339 typedef enum\r
340 {\r
341 pcie_DISABLE = 0, /**< Disable */\r
342 pcie_ENABLE /**< Enable */\r
343 } pcieState_e;\r
344 /* @} */\r
345 \r
346 \r
347 /*****************************************************************************\r
348 ********** PCIe APPLICATION REGISTERS *****************\r
349 ****************************************************************************/\r
350 \r
351 /**\r
352 * @ingroup pcielld_reg_app_structures\r
353 * @brief Specification of the PCIe Peripheral ID Register\r
354 *\r
355 * This Register contains the major and minor revisions\r
356 * for the PCIe module.\r
357 *\r
358 * This register is only used on rev 0 hw, but is very similar to rev 1's\r
359 * @ref pcieTiConfRevisionReg_t\r
360 *\r
361 * On rev 0 hw, this corresponds to PID\r
362 * On rev 1 hw, unsupported\r
363 *\r
364 * @{\r
365 */\r
366 typedef struct pciePidReg_s {\r
367 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
368 /**\r
369 * @brief [ro] Scheme\r
370 *\r
371 * On rev 0 hw, this corresponds to SCHEME\r
372 * On rev 1 hw, unsupported\r
373 *\r
374 * Field size: 2 bits\r
375 */\r
376 uint8_t scheme;\r
377 /**\r
378 * @brief [ro] Function code\r
379 *\r
380 * 0xe30 is PCIe\r
381 *\r
382 * On rev 0 hw, this corresponds to FUNC\r
383 * On rev 1 hw, unsupported\r
384 *\r
385 * Field size: 12 bits\r
386 */\r
387 uint16_t func;\r
388 /**\r
389 * @brief [ro] RTL Version\r
390 *\r
391 * On rev 0 hw, this corresponds to RTL\r
392 * On rev 1 hw, unsupported\r
393 *\r
394 * Field size: 5 bits\r
395 */\r
396 uint8_t rtl;\r
397 /**\r
398 * @brief [ro] Major revision\r
399 *\r
400 * On rev 0 hw, this corresponds to MAJOR\r
401 * On rev 1 hw, unsupported\r
402 *\r
403 * Field size: 3 bits\r
404 */\r
405 uint8_t revMaj;\r
406 /**\r
407 * @brief [ro] Customer special version\r
408 *\r
409 * On rev 0 hw, this corresponds to CUSTOM\r
410 * On rev 1 hw, unsupported\r
411 *\r
412 * Field size: 2 bits\r
413 */\r
414 uint8_t cust;\r
415 /**\r
416 * @brief [ro] Minor revision\r
417 *\r
418 * On rev 0 hw, this corresponds to MINOR\r
419 * On rev 1 hw, unsupported\r
420 *\r
421 * Field size: 6 bits\r
422 */\r
423 uint8_t revMin;\r
424 } pciePidReg_t;\r
425 /* @} */\r
426 \r
427 /**\r
428 * @ingroup pcielld_reg_app_structures\r
429 * @brief Specification of the Command Status Register\r
430 *\r
431 * This Register is used to enable address translation, link training\r
432 * and writing to BAR mask registers.\r
433 *\r
434 * On rev 0 hw, this corresponds to CMD_STATUS\r
435 * On rev 1 hw, unsupported\r
436 *\r
437 * @{\r
438 */\r
439 typedef struct pcieCmdStatusReg_s {\r
440 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
441 /**\r
442 * @brief [rw] Set to enable writing to BAR mask registers that are overlaid on BAR registers.\r
443 *\r
444 * On rev 0 hw, this corresponds to DBI_CS2\r
445 * On rev 1 hw, unsupported (but see @ref pciePlconfDbiRoWrEnReg_t::cxDbiRoWrEn)\r
446 *\r
447 * Field size: 1 bit\r
448 */\r
449 uint8_t dbi;\r
450 /**\r
451 * @brief [rw] Application retry Enable\r
452 *\r
453 * This feature can be used if initialization can take longer than PCIe\r
454 * stipulated time frame.\r
455 *\r
456 * 1 = Enable all incoming PCIe transactions to be returned with a retry response.\r
457 *\r
458 * On rev 0 hw, this corresponds to APP_RETRY_EN\r
459 * On rev 1 hw, unsupported (but see @ref pcieTiConfDeviceCmdReg_t::appReqRetryEn)\r
460 *\r
461 * Field size: 1 bit\r
462 */\r
463 uint8_t appRetryEn;\r
464 /**\r
465 * @brief [rw] Posted Write Enable\r
466 *\r
467 * Default is 0 with all internal bus master writes defaulting to non-posted.\r
468 *\r
469 * 1 = Enable the internal bus master to use posted write commands.\r
470 *\r
471 * On rev 0 hw, this corresponds to POSTED_WR_EN\r
472 * On rev 1 hw, unsupported\r
473 *\r
474 * Field size: 1 bit\r
475 */\r
476 uint8_t postedWrEn;\r
477 /**\r
478 * @brief [rw] Inbound Translation Enable\r
479 *\r
480 * 1 = Enable translation of inbound memory/IO read/write requests\r
481 * into memory read/write requests.\r
482 *\r
483 * On rev 0 hw, this corresponds to IB_XLT_EN\r
484 * On rev 1 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
485 *\r
486 * Field size: 1 bit\r
487 */\r
488 uint8_t ibXltEn;\r
489 /**\r
490 * @brief [rw] Outbound Translation Enable\r
491 *\r
492 * 1 = Enable translation of outbound memory read/write requests into\r
493 * memory/IO/configuration read/write requests.\r
494 *\r
495 * On rev 0 hw, this corresponds to OB_XLT_EN\r
496 * On rev 1 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
497 *\r
498 * Field size: 1 bit\r
499 */\r
500 uint8_t obXltEn;\r
501 /**\r
502 * @brief [rw] Link Training Enable\r
503 *\r
504 * 1 = Enable LTSSM in PCI Express core and link negotiation with\r
505 * link partner will begin.\r
506 *\r
507 * On rev 0 hw, this corresponds to LTSSM_EN\r
508 * On rev 1 hw, unsupported (but see @ref pcieTiConfDeviceCmdReg_t::ltssmEn)\r
509 *\r
510 * Field size: 1 bit\r
511 */\r
512 uint8_t ltssmEn;\r
513 } pcieCmdStatusReg_t;\r
514 /* @} */\r
515 \r
516 \r
517 /**\r
518 * @ingroup pcielld_reg_app_structures\r
519 * @brief Specification of the Configuration Transaction Setup Register\r
520 *\r
521 * On rev 0 hw, this corresponds to CFG_SETUP\r
522 * On rev 1 hw, unsupported\r
523 *\r
524 * @{\r
525 */\r
526 typedef struct pcieCfgTransReg_s {\r
527 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
528 /**\r
529 * @brief [rw] Configuration type for outbound configuration accesses\r
530 *\r
531 * 0 = Type 0 access.\r
532 * 1 = Type 1 access.\r
533 *\r
534 * On rev 0 hw, this corresponds to CFG_TYPE\r
535 * On rev 1 hw, unsupported\r
536 *\r
537 * Field size: 1 bit\r
538 */\r
539 uint8_t type;\r
540 /**\r
541 * @brief [rw] PCIe bus number for outbound configuration accesses\r
542 *\r
543 * On rev 0 hw, this corresponds to CFG_BUS\r
544 * On rev 1 hw, unsupported\r
545 *\r
546 * Field size: 8 bits\r
547 */\r
548 uint8_t bus;\r
549 /**\r
550 * @brief [rw] PCIe device number for outbound configuration accesses\r
551 *\r
552 * On rev 0 hw, this corresponds to CFG_DEVICE\r
553 * On rev 1 hw, unsupported\r
554 *\r
555 * Field size: 5 bit\r
556 */\r
557 uint8_t device;\r
558 /**\r
559 * @brief [rw] PCIe function number for outbound configuration accesses\r
560 *\r
561 * On rev 0 hw, this corresponds to CFG_FUNC\r
562 * On rev 1 hw, unsupported\r
563 *\r
564 * Field size: 3 bits\r
565 */\r
566 uint8_t func;\r
567 } pcieCfgTransReg_t;\r
568 /* @} */\r
569 \r
570 \r
571 /**\r
572 * @ingroup pcielld_reg_app_structures\r
573 * @brief Specification of the IO TLP Base Register\r
574 *\r
575 * On rev 0 hw, this corresponds to IOBASE\r
576 * On rev 1 hw, unsupported\r
577 *\r
578 * @{\r
579 */\r
580 typedef struct pcieIoBaseReg_s {\r
581 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
582 /**\r
583 * @brief [rw] outgoing IO TLP. RC mode only\r
584 *\r
585 * On rev 0 hw, this corresponds to IOBASE\r
586 * On rev 1 hw, unsupported\r
587 *\r
588 * Field size: 20 bits\r
589 *\r
590 */\r
591 uint32_t ioBase;\r
592 } pcieIoBaseReg_t;\r
593 /* @} */\r
594 \r
595 /**\r
596 * @ingroup pcielld_reg_app_structures\r
597 * @brief Specification of the TLP configuration Register\r
598 *\r
599 * On rev 0 hw, this corresponds to TLPCFG\r
600 * On rev 1 hw, unsupported\r
601 *\r
602 * @{\r
603 */\r
604 typedef struct pcieTlpCfgReg_s {\r
605 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
606 /**\r
607 * @brief [rw] Enable relaxed ordering for all outgoing TLPs\r
608 *\r
609 * On rev 0 hw, this corresponds to RELAXED\r
610 * On rev 1 hw, unsupported\r
611 *\r
612 * Field size: 1 bit\r
613 */\r
614 uint8_t relaxed;\r
615 /**\r
616 * @brief [rw] Enable No Snoop attribute on all outgoing TLPs\r
617 *\r
618 * On rev 0 hw, this corresponds to NO_SNOOP\r
619 * On rev 1 hw, unsupported\r
620 *\r
621 * Field size: 1 bit\r
622 */\r
623 uint8_t noSnoop;\r
624 } pcieTlpCfgReg_t;\r
625 /* @} */\r
626 \r
627 \r
628 /**\r
629 * @ingroup pcielld_reg_app_structures\r
630 * @brief Specification of the Reset Command Register\r
631 *\r
632 * On rev 0 hw, this corresponds to RSTCMD\r
633 * On rev 1 hw, unsupported\r
634 *\r
635 * @{\r
636 */\r
637 typedef struct pcieRstCmdReg_s {\r
638 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
639 /**\r
640 * @brief [ro] Bridge flush status\r
641 *\r
642 * Used to ensure no pending transactions prior to issuing warm reset.\r
643 * 0 = No transaction is pending.\r
644 * 1 = There are transactions pending.\r
645 *\r
646 * On rev 0 hw, this corresponds to FLUSH_N\r
647 * On rev 1 hw, unsupported\r
648 *\r
649 * Field size: 1 bit\r
650 */\r
651 uint8_t flush;\r
652 /**\r
653 * @brief [w1] Write 1 to initiate a downstream hot reset sequence on downstream.\r
654 *\r
655 * On rev 0 hw, this corresponds to INIT_RST\r
656 * On rev 1 hw, unsupported\r
657 *\r
658 * Field size: 1 bit\r
659 */\r
660 uint8_t initRst;\r
661 } pcieRstCmdReg_t;\r
662 /* @} */\r
663 \r
664 /**\r
665 * @ingroup pcielld_reg_app_structures\r
666 * @brief Specification of the Power Management Command Register\r
667 *\r
668 * On rev 0 hw, this corresponds to PMCMD\r
669 * On rev 1 hw, unsupported\r
670 *\r
671 * @{\r
672 */\r
673 typedef struct pciePmCmdReg_s {\r
674 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
675 /**\r
676 * @brief [w1] PM Turn off\r
677 *\r
678 * Write 1 to transmit a PM_TURNOFF message. Reads 0. Applicable in RC mode only.\r
679 *\r
680 * 0 = No effect\n\r
681 * 1 = Transmit a PM_TURNOFF message\r
682 *\r
683 * On rev 0 hw, this corresponds to PM_XMT_TURNOFF\r
684 * On rev 1 hw, unsupported\r
685 *\r
686 * Field size: 1 bit\r
687 */\r
688 uint8_t turnOff;\r
689 /**\r
690 * @brief [w1] Transmit PM PME message\r
691 *\r
692 * Write 1 to transmit a PM_PME message. Reads 0. Applicable to EP mode only.\r
693 *\r
694 * 0 = No effect\n\r
695 * 1 = Transmit a PM_PME message\r
696 *\r
697 * On rev 0 hw, this corresponds to PM_XMT_PME\r
698 * On rev 1 hw, unsupported\r
699 *\r
700 * Field size: 1 bit\r
701 */\r
702 uint8_t pme;\r
703 } pciePmCmdReg_t;\r
704 /* @} */\r
705 \r
706 \r
707 /**\r
708 * @ingroup pcielld_reg_app_structures\r
709 * @brief Specification of the Power Management Configuration Register\r
710 *\r
711 * On rev 0 hw, this corresponds to PMCFG\r
712 * On rev 1 hw, unsupported\r
713 *\r
714 * @{\r
715 */\r
716 typedef struct pciePmCfgReg_s {\r
717 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
718 /**\r
719 * @brief [rw] PM Turn off\r
720 *\r
721 * Write 1 to enable entry to L2/L3 ready state. Read to check L2/L3 entry readiness. Applicable to RC and EP.\r
722 *\r
723 * 0 = Disable entry to L2/L3 ready state.\n\r
724 * 1 = Enable entry to L2/L3 ready state.\r
725 *\r
726 * On rev 0 hw, this corresponds to ENTR_L23\r
727 * On rev 1 hw, unsupported\r
728 *\r
729 * Field size: 1 bit\r
730 */\r
731 uint8_t entrL23;\r
732 } pciePmCfgReg_t;\r
733 /* @} */\r
734 \r
735 /**\r
736 * @ingroup pcielld_reg_app_structures\r
737 * @brief Specification of the Activity Status Register\r
738 *\r
739 * On rev 0 hw, this corresponds to ACT_STATUS\r
740 * On rev 1 hw, unsupported\r
741 *\r
742 * @{\r
743 */\r
744 typedef struct pcieActStatusReg_s {\r
745 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
746 /**\r
747 * @brief [ro] Outbound Buffers Not Empty\r
748 *\r
749 * On rev 0 hw, this corresponds to OB_NOT_EMPTY\r
750 * On rev 1 hw, unsupported\r
751 *\r
752 * Field size: 1 bit\r
753 */\r
754 uint8_t obNotEmpty;\r
755 /**\r
756 * @brief [ro] Inbound Buffers Not Empty\r
757 *\r
758 * On rev 0 hw, this corresponds to IB_NOT_EMPTY\r
759 * On rev 1 hw, unsupported\r
760 *\r
761 * Field size: 1 bit\r
762 */\r
763 uint8_t ibNotEmpty;\r
764 } pcieActStatusReg_t;\r
765 /* @} */\r
766 \r
767 /**\r
768 * @ingroup pcielld_reg_app_structures\r
769 * @brief Specification of the Outbound Size Register\r
770 *\r
771 * On rev 0 hw, this corresponds to OB_SIZE\r
772 * On rev 1 hw, unsupported\r
773 *\r
774 * @{\r
775 */\r
776 typedef struct pcieObSizeReg_s {\r
777 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
778 /**\r
779 * @brief [rw] Set each outbound translation window size\r
780 *\r
781 * <TABLE>\r
782 * <TR><TH>@ref size</TH><TH>Window Size</TH></TR>\r
783 * <TR><TD>0</TD> <TD>1 MB</TD></TR>\r
784 * <TR><TD>1</TD> <TD>2 MB</TD></TR>\r
785 * <TR><TD>2</TD> <TD>4 MB</TD></TR>\r
786 * <TR><TD>3</TD> <TD>8 MB</TD></TR>\r
787 * <TR><TD>others</TD> <TD>reserved</TD></TR>\r
788 * </TABLE>\r
789 *\r
790 * On rev 0 hw, this corresponds to OB_SIZE\r
791 * On rev 1 hw, unsupported\r
792 *\r
793 * Field size: 3 bits\r
794 */\r
795 uint8_t size;\r
796 } pcieObSizeReg_t;\r
797 /* @} */\r
798 \r
799 /**\r
800 * @ingroup pcielld_reg_app_structures\r
801 * @brief Specification of the Diagnostic Control register\r
802 *\r
803 * On rev 0 hw, this corresponds to DIAG_CTRL\r
804 * On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t)\r
805 *\r
806 * @{\r
807 */\r
808 typedef struct pcieDiagCtrlReg_s {\r
809 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
810 /**\r
811 * @brief [rw] Force ECRC error\r
812 *\r
813 * Write 1 to force inversion of LSB of ECRC for the next one packet.\r
814 * It is self cleared when the ECRC error has been injected on one TLP.\r
815 *\r
816 * On rev 0 hw, this corresponds to INV_ECRC\r
817 * On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t::invEcrc)\r
818 *\r
819 * Field size: 1 bit\r
820 */\r
821 uint8_t invEcrc;\r
822 /**\r
823 * @brief [rw] Force LCRC error\r
824 *\r
825 * Write 1 to force inversion of LSB of LCRC for the next one packet.\r
826 * It is self cleared when the LCRC error has been injected on one TLP.\r
827 *\r
828 * On rev 0 hw, this corresponds to INV_LCRC\r
829 * On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t::invLcrc)\r
830 *\r
831 * Field size: 1 bit\r
832 */\r
833 uint8_t invLcrc;\r
834 } pcieDiagCtrlReg_t;\r
835 /* @} */\r
836 \r
837 /**\r
838 * @ingroup pcielld_reg_app_structures\r
839 * @brief Specification of the Endian Register\r
840 *\r
841 * On rev 0 hw, this corresponds to ENDIAN\r
842 * On rev 1 hw, unsupported\r
843 *\r
844 * @{\r
845 */\r
846 typedef struct pcieEndianReg_s {\r
847 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
848 /**\r
849 * @brief [rw] Endian mode.\r
850 *\r
851 * <TABLE>\r
852 * <TR><TH>@ref mode</TH><TH>Endian Swap Mode</TH></TR>\r
853 * <TR><TD>0</TD> <TD>Swap on 1 byte</TD></TR>\r
854 * <TR><TD>1</TD> <TD>Swap on 2 bytes</TD></TR>\r
855 * <TR><TD>2</TD> <TD>Swap on 4 bytes</TD></TR>\r
856 * <TR><TD>3</TD> <TD>Swap on 8 bytes</TD></TR>\r
857 * </TABLE>\r
858 *\r
859 * On rev 0 hw, this corresponds to ENDIAN_MODE\r
860 * On rev 1 hw, unsupported\r
861 *\r
862 * Field size: 2 bits\r
863 */\r
864 uint8_t mode;\r
865 } pcieEndianReg_t;\r
866 /* @} */\r
867 \r
868 /**\r
869 * @ingroup pcielld_reg_app_structures\r
870 * @brief Specification of the Transaction Priority Register\r
871 *\r
872 * On rev 0 hw, this corresponds to PRIORITY\r
873 * On rev 1 hw, unsupported\r
874 *\r
875 * @{\r
876 */\r
877 typedef struct pciePriorityReg_s {\r
878 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
879 /**\r
880 * @brief [rw] Master PRIV value on master transactions\r
881 *\r
882 * On rev 0 hw, this corresponds to MST_PRIV\r
883 * On rev 1 hw, unsupported\r
884 *\r
885 * Field size: 1 bit\r
886 */\r
887 uint8_t mstPriv;\r
888 /**\r
889 * @brief [rw] Master PRIVID value on master transactions\r
890 *\r
891 * On rev 0 hw, this corresponds to MST_PRIVID\r
892 * On rev 1 hw, unsupported\r
893 *\r
894 * Field size: 4 bits\r
895 */\r
896 uint8_t mstPrivID;\r
897 /**\r
898 * @brief [rw] Priority level for each inbound transaction on the\r
899 * internal master port\r
900 *\r
901 * On rev 0 hw, this corresponds to MST_PRIORITY\r
902 * On rev 1 hw, unsupported\r
903 *\r
904 * Field size: 3 bits\r
905 */\r
906 uint8_t mstPriority;\r
907 } pciePriorityReg_t;\r
908 /* @} */\r
909 \r
910 /**\r
911 * @ingroup pcielld_reg_app_structures\r
912 * @brief Specification of the End of Interrupt Register\r
913 *\r
914 * On rev 0 hw, this corresponds to IRQ_EOI\r
915 * On rev 1 hw, unsupported (but see @ref pcieTiConfIrqEoiReg_t)\r
916 *\r
917 * @{\r
918 */\r
919 typedef struct pcieIrqEOIReg_s {\r
920 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
921 /**\r
922 * @brief [wo] EOI for interrupts.\r
923 *\r
924 * Write to indicate end-of-interrupt for the interrupt events.\r
925 * Write 0 to mark EOI for INTA, 1 for INTB and so on.\r
926 *\r
927 * On rev 0 hw, this corresponds to EOI\r
928 * On rev 1 hw, unsupported (but see @ref pcieTiConfIrqEoiReg_t::lineNumber)\r
929 *\r
930 * Field size: 4 bits\r
931 */\r
932 uint8_t EOI;\r
933 } pcieIrqEOIReg_t;\r
934 /* @} */\r
935 \r
936 /**\r
937 * @ingroup pcielld_reg_app_structures\r
938 * @brief Specification of the MSI Interrupt IRQ Register\r
939 *\r
940 * On rev 0 hw, this corresponds to MSI_IRQ\r
941 * On rev 1 hw, unsupported\r
942 *\r
943 * @{\r
944 */\r
945 typedef struct pcieMsiIrqReg_s {\r
946 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
947 /**\r
948 * @brief [rw] To generate MSI Interrupt 0, the EP should write 0x0000_0000 to this register.\r
949 *\r
950 * On rev 0 hw, this corresponds to MSI_IRQ\r
951 * On rev 1 hw, unsupported\r
952 *\r
953 * Field size: 32 bits\r
954 */\r
955 uint32_t msiIrq;\r
956 } pcieMsiIrqReg_t;\r
957 /* @} */\r
958 \r
959 /**\r
960 * @ingroup pcielld_reg_app_structures\r
961 * @brief Specification of the Endpoint Interrupt Request Set Register\r
962 *\r
963 * On rev 0 hw, this corresponds to EP_IRQ_SET\r
964 * On rev 1 hw, unsupported\r
965 *\r
966 * @{\r
967 */\r
968 typedef struct pcieEpIrqSetReg_s {\r
969 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
970 /**\r
971 * @brief [rw] Write 1 to generate assert interrupt message\r
972 *\r
973 * If MSI is disabled, legacy interrupt assert message will\r
974 * be generated. On read, a 1 indicates currently asserted interrupt.\r
975 *\r
976 * On rev 0 hw, this corresponds to EP_IRQ_SET\r
977 * On rev 1 hw, unsupported\r
978 *\r
979 * Field size: 1 bit\r
980 */\r
981 uint8_t epIrqSet;\r
982 } pcieEpIrqSetReg_t;\r
983 /* @} */\r
984 \r
985 /**\r
986 * @ingroup pcielld_reg_app_structures\r
987 * @brief Specification of the Endpoint Interrupt Request Clear Register\r
988 *\r
989 * On rev 0 hw, this corresponds to EP_IRQ_CLR\r
990 * On rev 1 hw, unsupported\r
991 *\r
992 * @{\r
993 */\r
994 typedef struct pcieEpIrqClrReg_s {\r
995 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
996 /**\r
997 * @brief [rw] Write 1 to generate deassert interrupt message.\r
998 *\r
999 * If MSI is disabled, legacy interrupt deassert message will be generated.\r
1000 * On read, a 1 indicates currently asserted interrupt.\r
1001 *\r
1002 * On rev 0 hw, this corresponds to EP_IRQ_CLR\r
1003 * On rev 1 hw, unsupported\r
1004 *\r
1005 * Field size: 1 bit\r
1006 */\r
1007 uint8_t epIrqClr;\r
1008 } pcieEpIrqClrReg_t;\r
1009 /* @} */\r
1010 \r
1011 /**\r
1012 * @ingroup pcielld_reg_app_structures\r
1013 * @brief Specification of the Endpoint Interrupt status Register\r
1014 *\r
1015 * On rev 0 hw, this corresponds to EP_IRQ_STATUS\r
1016 * On rev 1 hw, unsupported\r
1017 *\r
1018 * @{\r
1019 */\r
1020 typedef struct pcieEpIrqStatusReg_s {\r
1021 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1022 /**\r
1023 * @brief [rw] Indicates whether interrupt for function 0 is asserted or not\r
1024 *\r
1025 * On rev 0 hw, this corresponds to EP_IRQ_STATUS\r
1026 * On rev 1 hw, unsupported\r
1027 *\r
1028 * Field size: 1 bit\r
1029 */\r
1030 uint8_t epIrqStatus;\r
1031 } pcieEpIrqStatusReg_t;\r
1032 /* @} */\r
1033 \r
1034 /**\r
1035 * @ingroup pcielld_reg_app_structures\r
1036 * @brief Specification of a General Purpose register\r
1037 *\r
1038 * On rev 0 hw, this corresponds to GPR# where # = 0..3\r
1039 * On rev 1 hw, unsupported\r
1040 *\r
1041 * @{\r
1042 */\r
1043 typedef struct pcieGenPurposeReg_s {\r
1044 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1045 /**\r
1046 * @brief [rw] Gen Purpose register value\r
1047 *\r
1048 * On rev 0 hw, this corresponds to GENERIC# where # = 0..3\r
1049 * On rev 1 hw, unsupported\r
1050 *\r
1051 * Field size: 32 bit\r
1052 */\r
1053 uint8_t genPurpose;\r
1054 } pcieGenPurposeReg_t;\r
1055 /* @} */\r
1056 \r
1057 /**\r
1058 * @ingroup pcielld_reg_app_structures\r
1059 * @brief Specification of the MSI Raw Interrupt Status Register Register\r
1060 *\r
1061 * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS_RAW where # = 0..7\r
1062 * On rev 1 hw, unsupported (but similar to @ref pciePlconfMsiCtrlIntStatusReg_t)\r
1063 *\r
1064 * @{\r
1065 */\r
1066 typedef struct pcieMsiIrqStatusRawReg_s {\r
1067 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1068 /**\r
1069 * @brief [rw] Each bit indicates raw status of MSI vectors (24, 16, 8, 0) associated with the bit\r
1070 *\r
1071 * Typically, writes to this register are only done for debug purposes.\r
1072 *\r
1073 * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS_RAW where # = 0..7\r
1074 * On rev 1 hw, unsupported\r
1075 *\r
1076 * Field size: 4 bits\r
1077 */\r
1078 uint8_t msiRawStatus;\r
1079 } pcieMsiIrqStatusRawReg_t;\r
1080 /* @} */\r
1081 \r
1082 \r
1083 /**\r
1084 * @ingroup pcielld_reg_app_structures\r
1085 * @brief Specification of the MSI Interrupt Enabled Status Register Register\r
1086 *\r
1087 * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS where # = 0..7\r
1088 * On rev 1 hw, unsupported (but similar to @ref pciePlconfMsiCtrlIntStatusReg_t)\r
1089 *\r
1090 * @{\r
1091 */\r
1092 typedef struct pcieMsiIrqStatusReg_s {\r
1093 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1094 /**\r
1095 * @brief [rw] Each bit indicates status of MSI vector (24, 16, 8, 0) associated with the bit\r
1096 *\r
1097 * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS where # = 0..7\r
1098 * On rev 1 hw, unsupported\r
1099 *\r
1100 * Field size: 4 bits\r
1101 */\r
1102 uint8_t msiIrqStatus;\r
1103 } pcieMsiIrqStatusReg_t;\r
1104 /* @} */\r
1105 \r
1106 /**\r
1107 * @ingroup pcielld_reg_app_structures\r
1108 * @brief Specification of the MSI Interrupt Enable Set Register\r
1109 *\r
1110 * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_SET where # = 0..7\r
1111 * On rev 1 hw, unsupported (but similar to @ref pcieTiConfIrqEnableSetMsiReg_t)\r
1112 *\r
1113 * @{\r
1114 */\r
1115 typedef struct pcieMsiIrqEnableSetReg_s {\r
1116 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1117 /**\r
1118 * @brief [rw] Each bit, when written to, enables the MSI interrupt (24, 16, 8, 0) associated with the bit\r
1119 *\r
1120 * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_SET where # = 0..7\r
1121 * On rev 1 hw, unsupported\r
1122 *\r
1123 * Field size: 4 bits\r
1124 */\r
1125 uint8_t msiIrqEnSet;\r
1126 } pcieMsiIrqEnableSetReg_t;\r
1127 /* @} */\r
1128 \r
1129 /**\r
1130 * @ingroup pcielld_reg_app_structures\r
1131 * @brief Specification of the MSI Interrupt Enable Clear Register\r
1132 *\r
1133 * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_CLR where # = 0..7\r
1134 * On rev 1 hw, unsupported (but similar to @ref pcieTiConfIrqEnableClrMsiReg_t)\r
1135 *\r
1136 * @{\r
1137 */\r
1138 typedef struct pcieMsiIrqEnableClrReg_s {\r
1139 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1140 /**\r
1141 * @brief [rw] Each bit, when written to, disables the MSI interrupt (24, 16, 8, 0) associated with the bit\r
1142 *\r
1143 * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_CLR where # = 0..7\r
1144 * On rev 1 hw, unsupported\r
1145 *\r
1146 * Field size: 4 bits\r
1147 */\r
1148 uint8_t msiIrqEnClr;\r
1149 } pcieMsiIrqEnableClrReg_t;\r
1150 /* @} */\r
1151 \r
1152 /**\r
1153 * @ingroup pcielld_reg_app_structures\r
1154 * @brief Specification of the Legacy Raw Interrupt Status Register\r
1155 *\r
1156 * On rev 0 hw, this corresponds to LEGACY_#_IRQ_STATUS_RAW where # = A..D (0-3)\r
1157 * On rev 1 hw, unsupported\r
1158 *\r
1159 * @{\r
1160 */\r
1161 typedef struct pcieLegacyIrqStatusRawReg_s {\r
1162 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1163 /**\r
1164 * @brief [rw] Legacy Interrupt Raw Status, RC mode only\r
1165 *\r
1166 * On rev 0 hw, this corresponds to INT_# where # = A..D\r
1167 * On rev 1 hw, unsupported\r
1168 *\r
1169 * Field size: 1 bit\r
1170 */\r
1171 uint8_t legacyRawStatus;\r
1172 } pcieLegacyIrqStatusRawReg_t;\r
1173 /* @} */\r
1174 \r
1175 \r
1176 /**\r
1177 * @ingroup pcielld_reg_app_structures\r
1178 * @brief Specification of the Legacy Interrupt Enabled Status Register\r
1179 *\r
1180 * On rev 0 hw, this corresponds to LEGACY_#_IRQ_STATUS where # = A..D (0-3)\r
1181 * On rev 1 hw, unsupported\r
1182 *\r
1183 * @{\r
1184 */\r
1185 typedef struct pcieLegacyIrqStatusReg_s {\r
1186 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1187 /**\r
1188 * @brief [rw] Legacy Interrupt status\r
1189 *\r
1190 * Set when interrupt is active. Write one to clear the interrupt event.\r
1191 * RC mode only.\r
1192 *\r
1193 * On rev 0 hw, this corresponds to INT_# where # = A..D\r
1194 * On rev 1 hw, unsupported\r
1195 *\r
1196 * Field size: 1 bit\r
1197 */\r
1198 uint8_t legacyIrqStatus;\r
1199 } pcieLegacyIrqStatusReg_t;\r
1200 /* @} */\r
1201 \r
1202 /**\r
1203 * @ingroup pcielld_reg_app_structures\r
1204 * @brief Specification of the Legacy Interrupt Enable Set Register\r
1205 *\r
1206 * On rev 0 hw, this corresponds to LEGACY_#_IRQ_ENABLE_SET where # = A..D (0-3)\r
1207 * On rev 1 hw, unsupported\r
1208 *\r
1209 * @{\r
1210 */\r
1211 typedef struct pcieLegacyIrqEnableSetReg_s {\r
1212 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1213 /**\r
1214 * @brief [rw] 0: has no effect; 1: enables the interrupt\r
1215 *\r
1216 * On rev 0 hw, this corresponds to INT_# where # = A..D\r
1217 * On rev 1 hw, unsupported\r
1218 *\r
1219 * Field size: 1 bit\r
1220 */\r
1221 uint8_t legacyIrqEnSet;\r
1222 } pcieLegacyIrqEnableSetReg_t;\r
1223 /* @} */\r
1224 \r
1225 /**\r
1226 * @ingroup pcielld_reg_app_structures\r
1227 * @brief Specification of the Legacy Interrupt Enable Clear Register\r
1228 *\r
1229 * On rev 0 hw, this corresponds to LEGACY_#_IRQ_ENABLE_CLR where # = A..D (0-3)\r
1230 * On rev 1 hw, unsupported\r
1231 *\r
1232 * @{\r
1233 */\r
1234 typedef struct pcieLegacyIrqEnableClrReg_s {\r
1235 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1236 /**\r
1237 * @brief [rw] 0 has no effect; 1 disables the interrupt\r
1238 *\r
1239 * On rev 0 hw, this corresponds to INT_# where # = A..D\r
1240 * On rev 1 hw, unsupported\r
1241 *\r
1242 * Field size: 1 bit\r
1243 */\r
1244 uint8_t legacyIrqEnClr;\r
1245 } pcieLegacyIrqEnableClrReg_t;\r
1246 /* @} */\r
1247 \r
1248 /**\r
1249 * @ingroup pcielld_reg_app_structures\r
1250 * @brief Specification of the Raw ERR Interrupt Status Register\r
1251 *\r
1252 * On rev 0 hw, this corresponds to ERR_IRQ_STATUS_RAW\r
1253 * On rev 1 hw, unsupported\r
1254 *\r
1255 * @{\r
1256 */\r
1257 typedef struct pcieErrIrqStatusRawReg_s {\r
1258 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1259 /**\r
1260 * @brief [rw] ECRC error raw status\r
1261 *\r
1262 * On rev 0 hw, this corresponds to ERR_AER\r
1263 * On rev 1 hw, unsupported\r
1264 *\r
1265 * Field size: 1 bit\r
1266 */\r
1267 uint8_t errAer;\r
1268 /**\r
1269 * @brief [rw] AXI tag lookup fatal error raw status\r
1270 *\r
1271 * On rev 0 hw, this corresponds to ERR_AXI\r
1272 * On rev 1 hw, unsupported\r
1273 *\r
1274 * Field size: 1 bit\r
1275 */\r
1276 uint8_t errAxi;\r
1277 /**\r
1278 * @brief [rw] correctable error raw status\r
1279 *\r
1280 * On rev 0 hw, this corresponds to ERR_CORR\r
1281 * On rev 1 hw, unsupported\r
1282 *\r
1283 * Field size: 1 bit\r
1284 */\r
1285 uint8_t errCorr;\r
1286 /**\r
1287 * @brief [rw] nonfatal error raw status\r
1288 *\r
1289 * On rev 0 hw, this corresponds to ERR_NONFATAL\r
1290 * On rev 1 hw, unsupported\r
1291 *\r
1292 * Field size: 1 bit\r
1293 */\r
1294 uint8_t errNonFatal;\r
1295 /**\r
1296 * @brief [rw] fatal error raw status\r
1297 *\r
1298 * On rev 0 hw, this corresponds to ERR_FATAL\r
1299 * On rev 1 hw, unsupported\r
1300 *\r
1301 * Field size: 1 bit\r
1302 */\r
1303 uint8_t errFatal;\r
1304 /**\r
1305 * @brief [rw] system error (fatal, nonfatal, correctable error) raw status\r
1306 *\r
1307 * On rev 0 hw, this corresponds to ERR_SYS\r
1308 * On rev 1 hw, unsupported\r
1309 *\r
1310 * Field size: 1 bit\r
1311 */\r
1312 uint8_t errSys;\r
1313 } pcieErrIrqStatusRawReg_t;\r
1314 /* @} */\r
1315 \r
1316 /**\r
1317 * @ingroup pcielld_reg_app_structures\r
1318 * @brief Specification of the ERR Interrupt Enabled Status Register\r
1319 *\r
1320 * On rev 0 hw, this corresponds to ERR_IRQ_STATUS\r
1321 * On rev 1 hw, unsupported\r
1322 *\r
1323 * @{\r
1324 */\r
1325 typedef struct pcieErrIrqStatusReg_s {\r
1326 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1327 /**\r
1328 * @brief [rw] ECRC error status\r
1329 *\r
1330 * On rev 0 hw, this corresponds to ERR_AER\r
1331 * On rev 1 hw, unsupported\r
1332 *\r
1333 * Field size: 1 bit\r
1334 */\r
1335 uint8_t errAer;\r
1336 /**\r
1337 * @brief [rw] AXI tag lookup fatal error status\r
1338 *\r
1339 * On rev 0 hw, this corresponds to ERR_AXI\r
1340 * On rev 1 hw, unsupported\r
1341 *\r
1342 * Field size: 1 bit\r
1343 */\r
1344 uint8_t errAxi;\r
1345 /**\r
1346 * @brief [rw] correctable error status\r
1347 *\r
1348 * On rev 0 hw, this corresponds to ERR_CORR\r
1349 * On rev 1 hw, unsupported\r
1350 *\r
1351 * Field size: 1 bit\r
1352 */\r
1353 uint8_t errCorr;\r
1354 /**\r
1355 * @brief [rw] nonfatal error status\r
1356 *\r
1357 * On rev 0 hw, this corresponds to ERR_NONFATAL\r
1358 * On rev 1 hw, unsupported\r
1359 *\r
1360 * Field size: 1 bit\r
1361 */\r
1362 uint8_t errNonFatal;\r
1363 /**\r
1364 * @brief [rw] fatal error status\r
1365 *\r
1366 * On rev 0 hw, this corresponds to ERR_FATAL\r
1367 * On rev 1 hw, unsupported\r
1368 *\r
1369 * Field size: 1 bit\r
1370 */\r
1371 uint8_t errFatal;\r
1372 /**\r
1373 * @brief [rw] system error (fatal, nonfatal, correctable error) status\r
1374 *\r
1375 * On rev 0 hw, this corresponds to ERR_SYS\r
1376 * On rev 1 hw, unsupported\r
1377 *\r
1378 * Field size: 1 bit\r
1379 */\r
1380 uint8_t errSys;\r
1381 } pcieErrIrqStatusReg_t;\r
1382 /* @} */\r
1383 \r
1384 /**\r
1385 * @ingroup pcielld_reg_app_structures\r
1386 * @brief Specification of the ERR Interrupt Enable Set Register\r
1387 *\r
1388 * On rev 0 hw, this corresponds to ERR_IRQ_ENABLE_SET\r
1389 * On rev 1 hw, unsupported\r
1390 *\r
1391 * @{\r
1392 */\r
1393 typedef struct pcieErrIrqEnableSetReg_s {\r
1394 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1395 /**\r
1396 * @brief [rw] set to enable the ECRC error interrupt\r
1397 *\r
1398 * On rev 0 hw, this corresponds to ERR_AER\r
1399 * On rev 1 hw, unsupported\r
1400 *\r
1401 * Field size: 1 bit\r
1402 */\r
1403 uint8_t errAer;\r
1404 /**\r
1405 * @brief [rw] set to enable the AXI tag lookup fatal error interrupt\r
1406 *\r
1407 * On rev 0 hw, this corresponds to ERR_AXI\r
1408 * On rev 1 hw, unsupported\r
1409 *\r
1410 * Field size: 1 bit\r
1411 */\r
1412 uint8_t errAxi;\r
1413 /**\r
1414 * @brief [rw] set to enable the correctable error interrupt\r
1415 *\r
1416 * On rev 0 hw, this corresponds to ERR_CORR\r
1417 * On rev 1 hw, unsupported\r
1418 *\r
1419 * Field size: 1 bit\r
1420 */\r
1421 uint8_t errCorr;\r
1422 /**\r
1423 * @brief [rw] set to enable the nonfatal error interrupt\r
1424 *\r
1425 * On rev 0 hw, this corresponds to ERR_NONFATAL\r
1426 * On rev 1 hw, unsupported\r
1427 *\r
1428 * Field size: 1 bit\r
1429 */\r
1430 uint8_t errNonFatal;\r
1431 /**\r
1432 * @brief [rw] set to enable the fatal error interrupt\r
1433 *\r
1434 * On rev 0 hw, this corresponds to ERR_FATAL\r
1435 * On rev 1 hw, unsupported\r
1436 *\r
1437 * Field size: 1 bit\r
1438 */\r
1439 uint8_t errFatal;\r
1440 /**\r
1441 * @brief [rw] set to enable the system error (fatal, nonfatal, correctable error) interrupt\r
1442 *\r
1443 * On rev 0 hw, this corresponds to ERR_SYS\r
1444 * On rev 1 hw, unsupported\r
1445 *\r
1446 * Field size: 1 bit\r
1447 */\r
1448 uint8_t errSys;\r
1449 } pcieErrIrqEnableSetReg_t;\r
1450 /* @} */\r
1451 \r
1452 /**\r
1453 * @ingroup pcielld_reg_app_structures\r
1454 * @brief Specification of the ERR Interrupt Enable Clear Register\r
1455 *\r
1456 * On rev 0 hw, this corresponds to ERR_IRQ_ENABLE_CLR\r
1457 * On rev 1 hw, unsupported\r
1458 *\r
1459 * @{\r
1460 */\r
1461 typedef struct pcieErrIrqEnableClrReg_s {\r
1462 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1463 /**\r
1464 * @brief [rw] set to disable the ECRC error interrupt\r
1465 *\r
1466 * On rev 0 hw, this corresponds to ERR_AER\r
1467 * On rev 1 hw, unsupported\r
1468 *\r
1469 * Field size: 1 bit\r
1470 */\r
1471 uint8_t errAer;\r
1472 /**\r
1473 * @brief [rw] set to disable the AXI tag lookup fatal error interrupt\r
1474 *\r
1475 * On rev 0 hw, this corresponds to ERR_AXI\r
1476 * On rev 1 hw, unsupported\r
1477 *\r
1478 * Field size: 1 bit\r
1479 */\r
1480 uint8_t errAxi;\r
1481 /**\r
1482 * @brief [rw] set to disable the correctable error interrupt\r
1483 *\r
1484 * On rev 0 hw, this corresponds to ERR_CORR\r
1485 * On rev 1 hw, unsupported\r
1486 *\r
1487 * Field size: 1 bit\r
1488 */\r
1489 uint8_t errCorr;\r
1490 /**\r
1491 * @brief [rw] set to disable the nonfatal error interrupt\r
1492 *\r
1493 * On rev 0 hw, this corresponds to ERR_NONFATAL\r
1494 * On rev 1 hw, unsupported\r
1495 *\r
1496 * Field size: 1 bit\r
1497 */\r
1498 uint8_t errNonFatal;\r
1499 /**\r
1500 * @brief [rw] set to disable the fatal error interrupt\r
1501 *\r
1502 * On rev 0 hw, this corresponds to ERR_FATAL\r
1503 * On rev 1 hw, unsupported\r
1504 *\r
1505 * Field size: 1 bit\r
1506 */\r
1507 uint8_t errFatal;\r
1508 /**\r
1509 * @brief [rw] set to disable the system error (fatal, nonfatal, correctable error) interrupt\r
1510 *\r
1511 * On rev 0 hw, this corresponds to ERR_SYS\r
1512 * On rev 1 hw, unsupported\r
1513 *\r
1514 * Field size: 1 bit\r
1515 */\r
1516 uint8_t errSys;\r
1517 } pcieErrIrqEnableClrReg_t;\r
1518 /* @} */\r
1519 \r
1520 /**\r
1521 * @ingroup pcielld_reg_app_structures\r
1522 * @brief Specification of the Raw Power Management and Reset Interrupt Status Register\r
1523 *\r
1524 * On rev 0 hw, this corresponds to PMRST_IRQ_STATUS_RAW\r
1525 * On rev 1 hw, unsupported\r
1526 *\r
1527 * @{\r
1528 */\r
1529 typedef struct pciePmRstIrqStatusRawReg_s {\r
1530 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1531 /**\r
1532 * @brief [rw] Link Request Reset interrupt raw status\r
1533 *\r
1534 * On rev 0 hw, this corresponds to LNK_RST_REQ\r
1535 * On rev 1 hw, unsupported\r
1536 *\r
1537 * Field size: 1 bit\r
1538 */\r
1539 uint8_t linkRstReq;\r
1540 /**\r
1541 * @brief [rw] Power management PME message received interrupt raw status\r
1542 *\r
1543 * On rev 0 hw, this corresponds to PM_PME\r
1544 * On rev 1 hw, unsupported\r
1545 *\r
1546 * Field size: 1 bit\r
1547 */\r
1548 uint8_t pmPme;\r
1549 /**\r
1550 * @brief [rw] Power mangement ACK received interrupt raw status\r
1551 *\r
1552 * On rev 0 hw, this corresponds to PM_TO_ACK\r
1553 * On rev 1 hw, unsupported\r
1554 *\r
1555 * Field size: 1 bit\r
1556 */\r
1557 uint8_t pmToAck;\r
1558 /**\r
1559 * @brief [rw] Power management turnoff messages received raw status\r
1560 *\r
1561 * On rev 0 hw, this corresponds to PM_TURNOFF\r
1562 * On rev 1 hw, unsupported\r
1563 *\r
1564 * Field size: 1 bit\r
1565 */\r
1566 uint8_t pmTurnoff;\r
1567 } pciePmRstIrqStatusRawReg_t;\r
1568 /* @} */\r
1569 \r
1570 /**\r
1571 * @ingroup pcielld_reg_app_structures\r
1572 * @brief Specification of the Power Management and Reset Interrupt Enabled Status Register\r
1573 *\r
1574 * On rev 0 hw, this corresponds to PMRST_IRQ_STATUS\r
1575 * On rev 1 hw, unsupported\r
1576 *\r
1577 * @{\r
1578 */\r
1579 typedef struct pciePmRstIrqStatusReg_s {\r
1580 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1581 /**\r
1582 * @brief [rw] Link Request Reset interrupt status\r
1583 *\r
1584 * On rev 0 hw, this corresponds to LNK_RST_REQ\r
1585 * On rev 1 hw, unsupported\r
1586 *\r
1587 * Field size: 1 bit\r
1588 */\r
1589 uint8_t linkRstReq;\r
1590 /**\r
1591 * @brief [rw] Power management PME message received interrupt status\r
1592 *\r
1593 * On rev 0 hw, this corresponds to PM_PME\r
1594 * On rev 1 hw, unsupported\r
1595 *\r
1596 * Field size: 1 bit\r
1597 */\r
1598 uint8_t pmPme;\r
1599 /**\r
1600 * @brief [rw] Power mangement ACK received interrupt status\r
1601 *\r
1602 * On rev 0 hw, this corresponds to PM_TO_ACK\r
1603 * On rev 1 hw, unsupported\r
1604 *\r
1605 * Field size: 1 bit\r
1606 */\r
1607 uint8_t pmToAck;\r
1608 /**\r
1609 * @brief [rw] Power management turnoff messages received status\r
1610 *\r
1611 * On rev 0 hw, this corresponds to PM_TURNOFF\r
1612 * On rev 1 hw, unsupported\r
1613 *\r
1614 * Field size: 1 bit\r
1615 */\r
1616 uint8_t pmTurnoff;\r
1617 } pciePmRstIrqStatusReg_t;\r
1618 /* @} */\r
1619 \r
1620 /**\r
1621 * @ingroup pcielld_reg_app_structures\r
1622 * @brief Specification of the Power Management and Reset Interrupt Enable Set Register\r
1623 *\r
1624 * On rev 0 hw, this corresponds to PMRST_ENABLE_SET\r
1625 * On rev 1 hw, unsupported\r
1626 *\r
1627 * @{\r
1628 */\r
1629 typedef struct pciePmRstIrqEnableSetReg_s {\r
1630 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1631 /**\r
1632 * @brief [rw] set to enable the Link Request Reset interrupt\r
1633 *\r
1634 * On rev 0 hw, this corresponds to LNK_RST_REQ\r
1635 * On rev 1 hw, unsupported\r
1636 *\r
1637 * Field size: 1 bit\r
1638 */\r
1639 uint8_t linkRstReq;\r
1640 /**\r
1641 * @brief [rw] set to enable the Power management PME message received interrupt\r
1642 *\r
1643 * On rev 0 hw, this corresponds to PM_PME\r
1644 * On rev 1 hw, unsupported\r
1645 *\r
1646 * Field size: 1 bit\r
1647 */\r
1648 uint8_t pmPme;\r
1649 /**\r
1650 * @brief [rw] set to enable the Power mangement ACK received interrupt\r
1651 *\r
1652 * On rev 0 hw, this corresponds to PM_TO_ACK\r
1653 * On rev 1 hw, unsupported\r
1654 *\r
1655 * Field size: 1 bit\r
1656 */\r
1657 uint8_t pmToAck;\r
1658 /**\r
1659 * @brief [rw] set to enable the Power management turnoff messages received interrupt\r
1660 *\r
1661 * On rev 0 hw, this corresponds to PM_TURNOFF\r
1662 * On rev 1 hw, unsupported\r
1663 *\r
1664 * Field size: 1 bit\r
1665 */\r
1666 uint8_t pmTurnoff;\r
1667 } pciePmRstIrqEnableSetReg_t;\r
1668 /* @} */\r
1669 \r
1670 /**\r
1671 * @ingroup pcielld_reg_app_structures\r
1672 * @brief Specification of the Power Management and Reset Interrupt Enable Clear Register\r
1673 *\r
1674 * On rev 0 hw, this corresponds to PMRST_ENABLE_CLR\r
1675 * On rev 1 hw, unsupported\r
1676 *\r
1677 * @{\r
1678 */\r
1679 typedef struct pciePmRstIrqEnableClrReg_s {\r
1680 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
1681 /**\r
1682 * @brief [rw] set to disable the Link Request Reset interrupt\r
1683 *\r
1684 * On rev 0 hw, this corresponds to LNK_RST_REQ\r
1685 * On rev 1 hw, unsupported\r
1686 *\r
1687 * Field size: 1 bit\r
1688 */\r
1689 uint8_t linkRstReq;\r
1690 /**\r
1691 * @brief [rw] set to disable the Power management PME message received interrupt\r
1692 *\r
1693 * On rev 0 hw, this corresponds to PM_PME\r
1694 * On rev 1 hw, unsupported\r
1695 *\r
1696 * Field size: 1 bit\r
1697 */\r
1698 uint8_t pmPme;\r
1699 /**\r
1700 * @brief [rw] set to disable the Power mangement ACK received interrupt\r
1701 *\r
1702 * On rev 0 hw, this corresponds to PM_TO_ACK\r
1703 * On rev 1 hw, unsupported\r
1704 *\r
1705 * Field size: 1 bit\r
1706 */\r
1707 uint8_t pmToAck;\r
1708 /**\r
1709 * @brief [rw] set to disable the Power management turnoff messages received interrupt\r
1710 *\r
1711 * On rev 0 hw, this corresponds to PM_TURNOFF\r
1712 * On rev 1 hw, unsupported\r
1713 *\r
1714 * Field size: 1 bit\r
1715 */\r
1716 uint8_t pmTurnoff;\r
1717 } pciePmRstIrqEnableClrReg_t;\r
1718 /* @} */\r
1719 \r
1720 /**\r
1721 * @ingroup pcielld_reg_app_structures\r
1722 * @brief Specification of the Outbound Translation Region Offset Low and Index Register\r
1723 *\r
1724 * On rev 0 hw, this corresponds to OB_OFFSET_INDEXn where n = 0..7\r
1725 * On rev 1 hw, unsupported (but similar to iATU\r
1726 * starting at @ref pciePlconfIatuIndexReg_t)\r
1727 *\r
1728 * @{\r
1729 */\r
1730 typedef struct pcieObOffsetLoReg_s {\r
1731 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1732 /**\r
1733 * @brief [rw] Offset bits for the translation region\r
1734 *\r
1735 * On rev 0 hw, this corresponds to OB_OFFSETn_LO (n = 0..7)\r
1736 * On rev 1 hw, unsupported\r
1737 *\r
1738 * Field size: 12 bits\r
1739 */\r
1740 uint16_t offsetLo;\r
1741 /**\r
1742 * @brief [rw] Enable translation region\r
1743 *\r
1744 * On rev 0 hw, this corresponds to OB_ENABLEn (n = 0..7)\r
1745 * On rev 1 hw, unsupported\r
1746 *\r
1747 * Field size: 1 bit\r
1748 */\r
1749 uint8_t enable;\r
1750 } pcieObOffsetLoReg_t;\r
1751 /* @} */\r
1752 \r
1753 /**\r
1754 * @ingroup pcielld_reg_app_structures\r
1755 * @brief Specification of the Outbound Translation Region Offset High Register\r
1756 *\r
1757 * On rev 0 hw, this corresponds to OB_OFFSETn_HI where n = 0..7\r
1758 * On rev 1 hw, unsupported (but similar to iATU\r
1759 * starting at @ref pciePlconfIatuIndexReg_t)\r
1760 *\r
1761 * @{\r
1762 */\r
1763 typedef struct pcieObOffsetHiReg_s {\r
1764 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1765 /**\r
1766 * @brief [rw] Offset high bits [63:32] for translation region\r
1767 *\r
1768 * On rev 0 hw, this corresponds to OB_OFFSETn_HI (n = 0..7)\r
1769 * On rev 1 hw, unsupported\r
1770 *\r
1771 * Field size: 32 bits\r
1772 */\r
1773 uint32_t offsetHi;\r
1774 } pcieObOffsetHiReg_t;\r
1775 /* @} */\r
1776 \r
1777 /**\r
1778 * @ingroup pcielld_reg_app_structures\r
1779 * @brief Specification of the Inbound Translation BAR Match Register\r
1780 *\r
1781 * On rev 0 hw, this corresponds to IB_BARn where n = 0..3\r
1782 * On rev 1 hw, unsupported (but similar to iATU\r
1783 * starting at @ref pciePlconfIatuIndexReg_t)\r
1784 *\r
1785 * @{\r
1786 */\r
1787 typedef struct pcieIbBarReg_s {\r
1788 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1789 /**\r
1790 * @brief [rw] BAR number to match for inbound translation region\r
1791 *\r
1792 * On rev 0 hw, this corresponds to IB_BARn (n = 0..3)\r
1793 * On rev 1 hw, unsupported\r
1794 *\r
1795 * Field size: 3 bits\r
1796 */\r
1797 uint8_t ibBar;\r
1798 } pcieIbBarReg_t;\r
1799 /* @} */\r
1800 \r
1801 \r
1802 /**\r
1803 * @ingroup pcielld_reg_app_structures\r
1804 * @brief Specification of the Inbound Translation Start Address Low Register\r
1805 *\r
1806 * On rev 0 hw, this corresponds to IB_STARTn_LO where n = 0..3\r
1807 * On rev 1 hw, unsupported (but similar to iATU\r
1808 * starting at @ref pciePlconfIatuIndexReg_t)\r
1809 *\r
1810 * @{\r
1811 */\r
1812 typedef struct pcieIbStartLoReg_s {\r
1813 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1814 /**\r
1815 * @brief [rw] Start address bits [31:8] for inbound translation region\r
1816 *\r
1817 * On rev 0 hw, this corresponds to IB_STARTn_LO (n = 0..3)\r
1818 * On rev 1 hw, unsupported\r
1819 *\r
1820 * Field size: 24 bits\r
1821 */\r
1822 uint32_t ibStartLo;\r
1823 } pcieIbStartLoReg_t;\r
1824 /* @} */\r
1825 \r
1826 /**\r
1827 * @ingroup pcielld_reg_app_structures\r
1828 * @brief Specification of the Inbound Translation Start Address High Register\r
1829 *\r
1830 * On rev 0 hw, this corresponds to IB_STARTn_LO where n = 0..3\r
1831 * On rev 1 hw, unsupported (but similar to iATU\r
1832 * starting at @ref pciePlconfIatuIndexReg_t)\r
1833 * @{\r
1834 */\r
1835 typedef struct pcieIbStartHiReg_s {\r
1836 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1837 /**\r
1838 * @brief [rw] Start address high bits [63:32] for inbound translation region\r
1839 *\r
1840 * On rev 0 hw, this corresponds to IB_STARTn_HI (n = 0..3)\r
1841 * On rev 1 hw, unsupported\r
1842 *\r
1843 * Field size: 32 bits\r
1844 */\r
1845 uint32_t ibStartHi;\r
1846 } pcieIbStartHiReg_t;\r
1847 /* @} */\r
1848 \r
1849 /**\r
1850 * @ingroup pcielld_reg_app_structures\r
1851 * @brief Specification of the Inbound Translation Address Offset Register\r
1852 *\r
1853 * On rev 0 hw, this corresponds to IB_OFFSETn where n = 0..3\r
1854 * On rev 1 hw, unsupported (but similar to iATU\r
1855 * starting at @ref pciePlconfIatuIndexReg_t)\r
1856 *\r
1857 * @{\r
1858 */\r
1859 typedef struct pcieIbOffsetReg_s {\r
1860 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1861 /**\r
1862 * @brief [rw] Offset address bits [31:8] for inbound translation region\r
1863 *\r
1864 * On rev 0 hw, this corresponds to IB_OFFSETn (n = 0..3)\r
1865 * On rev 1 hw, unsupported\r
1866 *\r
1867 * Field size: 24 bits\r
1868 */\r
1869 uint32_t ibOffset;\r
1870 } pcieIbOffsetReg_t;\r
1871 /* @} */\r
1872 \r
1873 /**\r
1874 * @ingroup pcielld_reg_app_structures\r
1875 * @brief Specification of the PCS Configuration 0 Register\r
1876 *\r
1877 * On rev 0 hw, this corresponds to PCS_CFG0\r
1878 * On rev 1 hw, unsupported\r
1879 *\r
1880 * @{\r
1881 */\r
1882 typedef struct pciePcsCfg0Reg_s {\r
1883 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
1884 /**\r
1885 * @brief [rw] Receiver lock/sync control.\r
1886 *\r
1887 * On rev 0 hw, this corresponds to PCS_SYNC\r
1888 * On rev 1 hw, unsupported\r
1889 *\r
1890 * Field size: 5 bits\r
1891 */\r
1892 uint8_t pcsSync;\r
1893 /**\r
1894 * @brief [rw] Receiver initialization holdoff control.\r
1895 *\r
1896 * On rev 0 hw, this corresponds to PCS_HOLDOFF\r
1897 * On rev 1 hw, unsupported\r
1898 *\r
1899 * Field size: 8 bits\r
1900 */\r
1901 uint8_t pcsHoldOff;\r
1902 /**\r
1903 * @brief [rw] Rate change delay.\r
1904 *\r
1905 * On rev 0 hw, this corresponds to PCS_RC_DELAY\r
1906 * On rev 1 hw, unsupported\r
1907 *\r
1908 * Field size: 2 bits\r
1909 */\r
1910 uint8_t pcsRCDelay;\r
1911 /**\r
1912 * @brief [rw] Detection delay.\r
1913 *\r
1914 * On rev 0 hw, this corresponds to PCS_DET_DELAY\r
1915 * On rev 1 hw, unsupported\r
1916 *\r
1917 * Field size: 4 bits\r
1918 */\r
1919 uint8_t pcsDetDelay;\r
1920 /**\r
1921 * @brief [rw] Enable short times for debug purposes.\r
1922 *\r
1923 * On rev 0 hw, this corresponds to PCS_SHRT_TM\r
1924 * On rev 1 hw, unsupported\r
1925 *\r
1926 * Field size: 1 bit\r
1927 */\r
1928 uint8_t pcsShrtTM;\r
1929 /**\r
1930 * @brief [rw] Enable PIPE Spec 1.86 for phystatus behavior.\r
1931 *\r
1932 * On rev 0 hw, this corresponds to PCS_STAT186\r
1933 * On rev 1 hw, unsupported\r
1934 *\r
1935 * Field size: 1 bit\r
1936 */\r
1937 uint8_t pcsStat186;\r
1938 /**\r
1939 * @brief [rw] Fed term output to 3'b100 during reset.\r
1940 *\r
1941 * On rev 0 hw, this corresponds to PCS_FIX_TERM\r
1942 * On rev 1 hw, unsupported\r
1943 *\r
1944 * Field size: 1 bit\r
1945 */\r
1946 uint8_t pcsFixTerm;\r
1947 /**\r
1948 * @brief [rw] Fix std output to 2'b10.\r
1949 *\r
1950 * On rev 0 hw, this corresponds to PCS_FIX_STD\r
1951 * On rev 1 hw, unsupported\r
1952 *\r
1953 * Field size: 1 bit\r
1954 */\r
1955 uint8_t pcsFixStd;\r
1956 /**\r
1957 * @brief [rw] Deassert enidl during L2 state.\r
1958 *\r
1959 * On rev 0 hw, this corresponds to PCS_L2_ENIDL_OFF\r
1960 * On rev 1 hw, unsupported\r
1961 *\r
1962 * Field size: 1 bit\r
1963 */\r
1964 uint8_t pcsL2EnidlOff;\r
1965 /**\r
1966 * @brief [rw] Deassert Rx enable in L0s state.\r
1967 *\r
1968 * On rev 0 hw, this corresponds to PCS_L0S_RX_OFF\r
1969 * On rev 1 hw, unsupported\r
1970 *\r
1971 * Field size: 1 bit\r
1972 */\r
1973 uint8_t pcsL2L0SRxOff;\r
1974 /**\r
1975 * @brief [rw] RX and TX on during reset and TX also on in P1 state.\r
1976 *\r
1977 * On rev 0 hw, this corresponds to PCS_RXTX_ON\r
1978 * On rev 1 hw, unsupported\r
1979 *\r
1980 * Field size: 1 bit\r
1981 */\r
1982 uint8_t pcsRxTxOn;\r
1983 /**\r
1984 * @brief [rw] RX and TX on during reset.\r
1985 *\r
1986 * On rev 0 hw, this corresponds to PCS_RXTX_RST\r
1987 * On rev 1 hw, unsupported\r
1988 *\r
1989 * Field size: 1 bit\r
1990 */\r
1991 uint8_t pcsRxTxRst;\r
1992 } pciePcsCfg0Reg_t;\r
1993 /* @} */\r
1994 \r
1995 /**\r
1996 * @ingroup pcielld_reg_app_structures\r
1997 * @brief Specification of the PCS Configuration 1 Register\r
1998 *\r
1999 * On rev 0 hw, this corresponds to PCS_CFG1\r
2000 * On rev 1 hw, unsupported\r
2001 *\r
2002 * @{\r
2003 */\r
2004 typedef struct pciePcsCfg1Reg_s {\r
2005 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2006 /**\r
2007 * @brief [rw] Error bit enable.\r
2008 *\r
2009 * On rev 0 hw, this corresponds to PCS_ERR_BIT\r
2010 * On rev 1 hw, unsupported\r
2011 *\r
2012 * Field size: 10 bits\r
2013 */\r
2014 uint16_t pcsErrBit;\r
2015 /**\r
2016 * @brief [rw] Error lane enable\r
2017 *\r
2018 * On rev 0 hw, this corresponds to PCS_ERR_LN\r
2019 * On rev 1 hw, unsupported\r
2020 *\r
2021 * Field size: 2 bits\r
2022 */\r
2023 uint8_t pcsErrLn;\r
2024 /**\r
2025 * @brief [rw] Error injection mode\r
2026 *\r
2027 * On rev 0 hw, this corresponds to PCS_ERR_MODE\r
2028 * On rev 1 hw, unsupported\r
2029 *\r
2030 * Field size: 2 bits\r
2031 */\r
2032 uint8_t pcsErrMode;\r
2033 } pciePcsCfg1Reg_t;\r
2034 /* @} */\r
2035 \r
2036 /**\r
2037 * @ingroup pcielld_reg_app_structures\r
2038 * @brief Specification of the PCS Status Register\r
2039 *\r
2040 * On rev 0 hw, this corresponds to PCS_STATUS\r
2041 * On rev 1 hw, unsupported\r
2042 *\r
2043 * @{\r
2044 */\r
2045 typedef struct pciePcsStatusReg_s {\r
2046 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2047 /**\r
2048 * @brief [ro] PCS RTL Revision.\r
2049 *\r
2050 * On rev 0 hw, this corresponds to PCS_REV\r
2051 * On rev 1 hw, unsupported\r
2052 *\r
2053 * Field size: 3 bits\r
2054 */\r
2055 uint8_t pcsRev;\r
2056 /**\r
2057 * @brief [ro] PCS lanes enabled status.\r
2058 *\r
2059 * On rev 0 hw, this corresponds to PCS_LN_EN\r
2060 * On rev 1 hw, unsupported\r
2061 *\r
2062 * Field size: 2 bits\r
2063 */\r
2064 uint8_t pcsLnEn;\r
2065 /**\r
2066 * @brief [ro] PCS transmitters enabled status.\r
2067 *\r
2068 * On rev 0 hw, this corresponds to PCS_TX_EN\r
2069 * On rev 1 hw, unsupported\r
2070 *\r
2071 * Field size: 2 bits\r
2072 */\r
2073 uint8_t pcsTxEn;\r
2074 /**\r
2075 * @brief [ro] PCS receivers enabled status.\r
2076 *\r
2077 * On rev 0 hw, this corresponds to PCS_RX_EN\r
2078 * On rev 1 hw, unsupported\r
2079 *\r
2080 * Field size: 2 bits\r
2081 */\r
2082 uint8_t pcsRxEn;\r
2083 } pciePcsStatusReg_t;\r
2084 /* @} */\r
2085 \r
2086 /**\r
2087 * @ingroup pcielld_reg_app_structures\r
2088 * @brief Specification of the SERDES config 0 Register\r
2089 *\r
2090 * On rev 0 hw, this corresponds to SERDES_CFG0\r
2091 * On rev 1 hw, unsupported\r
2092 *\r
2093 * @{\r
2094 */\r
2095 typedef struct pcieSerdesCfg0Reg_s {\r
2096 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
2097 /**\r
2098 * @brief [rw] Enable Tx loopback. Set both bits high to enable.\r
2099 *\r
2100 * On rev 0 hw, this corresponds to TX_LOOPBACK\r
2101 * On rev 1 hw, unsupported\r
2102 *\r
2103 * Field size: 2 bits\r
2104 */\r
2105 uint8_t txLoopback;\r
2106 /**\r
2107 * @brief [rw] Master mode for synchronization.\r
2108 *\r
2109 * On rev 0 hw, this corresponds to TX_MSYNC\r
2110 * On rev 1 hw, unsupported\r
2111 *\r
2112 * Field size: 1 bit\r
2113 */\r
2114 uint8_t txMsync;\r
2115 /**\r
2116 * @brief [rw] Enable common mode adjustment.\r
2117 *\r
2118 * On rev 0 hw, this corresponds to TX_CM\r
2119 * On rev 1 hw, unsupported\r
2120 *\r
2121 * Field size: 1 bit\r
2122 */\r
2123 uint8_t txCm;\r
2124 /**\r
2125 * @brief [rw] Invert Tx pair polarity.\r
2126 *\r
2127 * On rev 0 hw, this corresponds to TX_INVPAIR\r
2128 * On rev 1 hw, unsupported\r
2129 *\r
2130 * Field size: 1 bit\r
2131 */\r
2132 uint8_t txInvpair;\r
2133 /**\r
2134 * @brief [rw] Enable Rx loopback. Set both bits to high to enable loopback.\r
2135 *\r
2136 * On rev 0 hw, this corresponds to RX_LOOPBACK\r
2137 * On rev 1 hw, unsupported\r
2138 *\r
2139 * Field size: 2 bits\r
2140 */\r
2141 uint8_t rxLoopback;\r
2142 /**\r
2143 * @brief [rw] Enable Rx offset compensation.\r
2144 *\r
2145 * On rev 0 hw, this corresponds to RX_ENOC\r
2146 * On rev 1 hw, unsupported\r
2147 *\r
2148 * Field size: 1 bit\r
2149 */\r
2150 uint8_t rxEnoc;\r
2151 /**\r
2152 * @brief [rw] Enable Rx adaptive equalization.\r
2153 *\r
2154 * On rev 0 hw, this corresponds to RX_EQ\r
2155 * On rev 1 hw, unsupported\r
2156 *\r
2157 * Field size: 4 bits\r
2158 */\r
2159 uint8_t rxEq;\r
2160 /**\r
2161 * @brief [rw] Enable Rx clock data recovery.\r
2162 *\r
2163 * On rev 0 hw, this corresponds to RX_CDR\r
2164 * On rev 1 hw, unsupported\r
2165 *\r
2166 * Field size: 3 bits\r
2167 */\r
2168 uint8_t rxCdr;\r
2169 /**\r
2170 * @brief [rw] Enable Rx loss of signal detection.\r
2171 *\r
2172 * On rev 0 hw, this corresponds to RX_LOS\r
2173 * On rev 1 hw, unsupported\r
2174 *\r
2175 * Field size: 3 bits\r
2176 */\r
2177 uint8_t rxLos;\r
2178 /**\r
2179 * @brief [rw] Enable Rx symbol alignment.\r
2180 *\r
2181 * On rev 0 hw, this corresponds to RX_ALIGN\r
2182 * On rev 1 hw, unsupported\r
2183 *\r
2184 * Field size: 2 bits\r
2185 */\r
2186 uint8_t rxAlign;\r
2187 /**\r
2188 * @brief [rw] Invert Rx pair polarity.\r
2189 *\r
2190 * On rev 0 hw, this corresponds to RX_INVPAIR\r
2191 * On rev 1 hw, unsupported\r
2192 *\r
2193 * Field size: 1 bit\r
2194 */\r
2195 uint8_t rxInvpair;\r
2196 } pcieSerdesCfg0Reg_t;\r
2197 /* @} */\r
2198 \r
2199 /**\r
2200 * @ingroup pcielld_reg_app_structures\r
2201 * @brief Specification of the SERDES config 1 Register\r
2202 *\r
2203 * On rev 0 hw, this corresponds to SERDES_CFG1\r
2204 * On rev 1 hw, unsupported\r
2205 *\r
2206 * @{\r
2207 */\r
2208 typedef struct pcieSerdesCfg1Reg_s {\r
2209 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
2210 /**\r
2211 * @brief [rw] Enable Tx loopback. Set both bits high to enable.\r
2212 *\r
2213 * On rev 0 hw, this corresponds to TX_LOOPBACK\r
2214 * On rev 1 hw, unsupported\r
2215 *\r
2216 * Field size: 2 bits\r
2217 */\r
2218 uint8_t txLoopback;\r
2219 /**\r
2220 * @brief [rw] Master mode for synchronization.\r
2221 *\r
2222 * On rev 0 hw, this corresponds to TX_MSYNC\r
2223 * On rev 1 hw, unsupported\r
2224 *\r
2225 * Field size: 1 bit\r
2226 */\r
2227 uint8_t txMsync;\r
2228 /**\r
2229 * @brief [rw] Enable common mode adjustment.\r
2230 *\r
2231 * On rev 0 hw, this corresponds to TX_CM\r
2232 * On rev 1 hw, unsupported\r
2233 *\r
2234 * Field size: 1 bit\r
2235 */\r
2236 uint8_t txCm;\r
2237 /**\r
2238 * @brief [rw] Invert Tx pair polarity.\r
2239 *\r
2240 * On rev 0 hw, this corresponds to TX_INVPAIR\r
2241 * On rev 1 hw, unsupported\r
2242 *\r
2243 * Field size: 1 bit\r
2244 */\r
2245 uint8_t txInvpair;\r
2246 /**\r
2247 * @brief [rw] Enable Rx loopback. Set both bits to high to enable loopback.\r
2248 *\r
2249 * On rev 0 hw, this corresponds to RX_LOOPBACK\r
2250 * On rev 1 hw, unsupported\r
2251 *\r
2252 * Field size: 2 bits\r
2253 */\r
2254 uint8_t rxLoopback;\r
2255 /**\r
2256 * @brief [rw] Enable Rx offset compensation.\r
2257 *\r
2258 * On rev 0 hw, this corresponds to RX_ENOC\r
2259 * On rev 1 hw, unsupported\r
2260 *\r
2261 * Field size: 1 bit\r
2262 */\r
2263 uint8_t rxEnoc;\r
2264 /**\r
2265 * @brief [rw] Enable Rx adaptive equalization.\r
2266 *\r
2267 * On rev 0 hw, this corresponds to RX_EQ\r
2268 * On rev 1 hw, unsupported\r
2269 *\r
2270 * Field size: 4 bits\r
2271 */\r
2272 uint8_t rxEq;\r
2273 /**\r
2274 * @brief [rw] Enable Rx clock data recovery.\r
2275 *\r
2276 * On rev 0 hw, this corresponds to RX_CDR\r
2277 * On rev 1 hw, unsupported\r
2278 *\r
2279 * Field size: 3 bits\r
2280 */\r
2281 uint8_t rxCdr;\r
2282 /**\r
2283 * @brief [rw] Enable Rx loss of signal detection.\r
2284 *\r
2285 * On rev 0 hw, this corresponds to RX_LOS\r
2286 * On rev 1 hw, unsupported\r
2287 *\r
2288 * Field size: 3 bits\r
2289 */\r
2290 uint8_t rxLos;\r
2291 /**\r
2292 * @brief [rw] Enable Rx symbol alignment.\r
2293 *\r
2294 * On rev 0 hw, this corresponds to RX_ALIGN\r
2295 * On rev 1 hw, unsupported\r
2296 *\r
2297 * Field size: 2 bits\r
2298 */\r
2299 uint8_t rxAlign;\r
2300 /**\r
2301 * @brief [rw] Invert Rx pair polarity.\r
2302 *\r
2303 * On rev 0 hw, this corresponds to RX_INVPAIR\r
2304 * On rev 1 hw, unsupported\r
2305 *\r
2306 * Field size: 1 bit\r
2307 */\r
2308 uint8_t rxInvpair;\r
2309 } pcieSerdesCfg1Reg_t;\r
2310 /* @} */\r
2311 \r
2312 \r
2313 \r
2314 /*****************************************************************************\r
2315 ********** PCIe LOCAL/REMOTE CONFIG TYPE 0 and TYPE 1 REGISTERS ************\r
2316 ********** Registers that are common to both Types ************\r
2317 ****************************************************************************/\r
2318 \r
2319 /**\r
2320 * @ingroup pcielld_reg_cfg_com_structures\r
2321 * @brief Specification of the Vendor Device ID Register\r
2322 *\r
2323 * On rev 0 hw, this corresponds to VENDOR_DEVICE_ID\r
2324 * On rev 1 hw, this corresponds to DEVICE_VENDORID\r
2325 *\r
2326 * @{\r
2327 */\r
2328 typedef struct pcieVndDevIdReg_s {\r
2329 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2330 /**\r
2331 * @brief [rw] Device ID\r
2332 *\r
2333 * On rev 0 hw, this corresponds to DEVICE_ID\r
2334 * On rev 1 hw, this corresponds to DEVICEID\r
2335 *\r
2336 * Field size: 16 bits\r
2337 */\r
2338 uint16_t devId;\r
2339 /**\r
2340 * @brief [rw] Vendor ID\r
2341 *\r
2342 * On rev 0 hw, this corresponds to VENDOR_ID\r
2343 * On rev 1 hw, this corresponds to VENDORID\r
2344 *\r
2345 * Field size: 16 bits\r
2346 */\r
2347 uint16_t vndId;\r
2348 } pcieVndDevIdReg_t;\r
2349 /* @} */\r
2350 \r
2351 \r
2352 /**\r
2353 * @ingroup pcielld_reg_cfg_com_structures\r
2354 * @brief Specification of the Status Command Register\r
2355 *\r
2356 * On rev 0 hw, this corresponds to STATUS_COMMAND\r
2357 * On rev 1 hw, this corresponds to STATUS_COMMAND_REGISTER\r
2358 *\r
2359 * @{\r
2360 */\r
2361 typedef struct pcieStatusCmdReg_s {\r
2362 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2363 /**\r
2364 * @brief [rw] parity\r
2365 *\r
2366 * Set if received a poisoned TLP\r
2367 *\r
2368 * On rev 0 hw, this corresponds to PARITY_ERROR\r
2369 * On rev 1 hw, this corresponds to DETECT_PARERR\r
2370 *\r
2371 * Field size: 1 bit\r
2372 */\r
2373 uint8_t parity;\r
2374 /**\r
2375 * @brief [rw] sys error\r
2376 *\r
2377 * Set if function sends an ERR_FATAL or ERR_NONFATAL message and\r
2378 * @ref serrEn bit is set\r
2379 *\r
2380 * On rev 0 hw, this corresponds to SIG_SYS_ERROR\r
2381 * On rev 1 hw, this corresponds to SIGNAL_SYSERR\r
2382 *\r
2383 * Field size: 1 bit\r
2384 */\r
2385 uint8_t sysError;\r
2386 /**\r
2387 * @brief [rw] mst abort\r
2388 *\r
2389 * Set when a requester receives a completion with unsupported request\r
2390 * completion status\r
2391 *\r
2392 * On rev 0 hw, this corresponds to RX_MST_ABORT\r
2393 * On rev 1 hw, this corresponds to RCVD_MASTERABORT\r
2394 *\r
2395 * Field size: 1 bit\r
2396 */\r
2397 uint8_t mstAbort;\r
2398 /**\r
2399 * @brief [rw] tgt abort\r
2400 *\r
2401 * Set when a requester receives a completion with completer abort status.\r
2402 *\r
2403 * On rev 0 hw, this corresponds to RX_TGT_ABORT\r
2404 * On rev 1 hw, this corresponds to RCVD_TRGTABORT\r
2405 *\r
2406 * Field size: 1 bit\r
2407 */\r
2408 uint8_t tgtAbort;\r
2409 /**\r
2410 * @brief [rw] sig tgt abort\r
2411 *\r
2412 * Set when a function acting as a completer terminates a request by issuing\r
2413 * completer abort completion status to the requester.\r
2414 *\r
2415 * On rev 0 hw, this corresponds to SIG_TGT_ABORT\r
2416 * On rev 1 hw, this corresponds to SIGNAL_TRGTABORT\r
2417 *\r
2418 * Field size: 1 bit\r
2419 */\r
2420 uint8_t sigTgtAbort;\r
2421 /**\r
2422 * @brief [ro] DevSel Timing\r
2423 *\r
2424 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2425 *\r
2426 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2427 *\r
2428 * On rev 0 hw, unsupported\r
2429 * On rev 1 hw, this corresponds to DEVSEL_TIME\r
2430 *\r
2431 * Field size: 2 bits\r
2432 */\r
2433 uint8_t devSelTime;\r
2434 /**\r
2435 * @brief [rw] par error\r
2436 *\r
2437 * This bit is set by a requester if the @ref parError bit is set\r
2438 * in its Command register and either the condition that the requester\r
2439 * receives a poisoned completion or the condition that the\r
2440 * requester poisons a write request is true.\r
2441 *\r
2442 * On rev 0 hw, this corresponds to DAT_PAR_ERRROR\r
2443 * On rev 1 hw, this corresponds to MASTERDATA_PARERR\r
2444 *\r
2445 * Field size: 1 bit\r
2446 */\r
2447 uint8_t parError;\r
2448 /**\r
2449 * @brief [ro] Back to Back Capable\r
2450 *\r
2451 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2452 *\r
2453 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2454 *\r
2455 * On rev 0 hw, unsupported\r
2456 * On rev 1 hw, this corresponds to FAST_B2B\r
2457 *\r
2458 * Field size: 1 bit\r
2459 */\r
2460 uint8_t fastB2B;\r
2461 /**\r
2462 * @brief [ro] 66MHz Capable\r
2463 *\r
2464 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2465 *\r
2466 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2467 *\r
2468 * On rev 0 hw, unsupported\r
2469 * On rev 1 hw, this corresponds to C66MHZ_CAP\r
2470 *\r
2471 * Field size: 1 bit\r
2472 */\r
2473 uint8_t c66MhzCap;\r
2474 /**\r
2475 * @brief [ro] cap list\r
2476 *\r
2477 * For PCIe, this field must be set to 1.\r
2478 *\r
2479 * On rev 0 hw, this corresponds to CAP_LIST\r
2480 * On rev 1 hw, this corresponds to CAP_LIST\r
2481 *\r
2482 * Field size: 1 bit\r
2483 */\r
2484 uint8_t capList;\r
2485 /**\r
2486 * @brief [rw] stat\r
2487 *\r
2488 * Indicates that the function has received an interrupt.\r
2489 *\r
2490 * On rev 0 hw, this corresponds to INT_STAT\r
2491 * On rev 1 hw, this corresponds to INTX_STATUS\r
2492 *\r
2493 * Field size: 1 bit\r
2494 */\r
2495 uint8_t stat;\r
2496 /**\r
2497 * @brief [ro] dis\r
2498 *\r
2499 * Setting this bit disables generation of INTx messages.\r
2500 *\r
2501 * On rev 0 hw, this corresponds to INTX_DIS\r
2502 * On rev 1 hw, this corresponds to INTX_ASSER_DIS\r
2503 *\r
2504 * Field size: 1 bit\r
2505 */\r
2506 uint8_t dis;\r
2507 /**\r
2508 * @brief [rw] serr en\r
2509 *\r
2510 * When set, it enables generation of the appropriate PCI Express error\r
2511 * messages to the Root Complex.\r
2512 *\r
2513 * On rev 0 hw, this corresponds to SERR_EN\r
2514 * On rev 1 hw, this corresponds to SERR_EN\r
2515 *\r
2516 * Field size: 1 bit\r
2517 */\r
2518 uint8_t serrEn;\r
2519 /**\r
2520 * @brief [ro] Bit hardwired to 0 for PCIExpress\r
2521 *\r
2522 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2523 *\r
2524 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2525 *\r
2526 * On rev 0 hw, unsupported\r
2527 * On rev 1 hw, this corresponds to IDSEL_CTRL\r
2528 *\r
2529 * Field size: 1 bit\r
2530 */\r
2531 uint8_t idselCtrl;\r
2532 /**\r
2533 * @brief [rw] resp\r
2534 *\r
2535 * This bit controls whether or not the device responds to detected\r
2536 * parity errors (poisoned TLP). This error is typically reported as an\r
2537 * unsupported request and may also result in a non-fatal error\r
2538 * message if @ref serrEn = 1. If this bit is set, the PCIESS will respond\r
2539 * normally to parity errors. If this bit is cleared, the PCIESS\r
2540 * will ignore detected parity errors.\r
2541 *\r
2542 * On rev 0 hw, this corresponds to PAR_ERR_RESP\r
2543 * On rev 1 hw, this corresponds to PARITYERRRESP\r
2544 *\r
2545 * Field size: 1 bit\r
2546 */\r
2547 uint8_t resp;\r
2548 /**\r
2549 * @brief [ro] Bit hardwired to 0 for PCIExpress\r
2550 *\r
2551 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2552 *\r
2553 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2554 *\r
2555 * On rev 0 hw, unsupported\r
2556 * On rev 1 hw, this corresponds to VGA_SNOOP\r
2557 *\r
2558 * Field size: 1 bit\r
2559 */\r
2560 uint8_t vgaSnoop;\r
2561 /**\r
2562 * @brief [ro] Bit hardwired to 0 for PCIExpress\r
2563 *\r
2564 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2565 *\r
2566 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2567 *\r
2568 * On rev 0 hw, unsupported\r
2569 * On rev 1 hw, this corresponds to MEMWR_INVA\r
2570 *\r
2571 * Field size: 1 bit\r
2572 */\r
2573 uint8_t memWrInva;\r
2574 /**\r
2575 * @brief [ro] Bit hardwired to 0 for PCIExpress\r
2576 *\r
2577 * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
2578 *\r
2579 * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
2580 *\r
2581 * On rev 0 hw, unsupported\r
2582 * On rev 1 hw, this corresponds to SPEC_CYCLE_EN\r
2583 *\r
2584 * Field size: 1 bit\r
2585 */\r
2586 uint8_t specCycleEn;\r
2587 /**\r
2588 * @brief [rw] enables mastership of the bus\r
2589 *\r
2590 * On rev 0 hw, this corresponds to BUS_MS\r
2591 * On rev 1 hw, this corresponds to BUSMASTER_EN\r
2592 *\r
2593 * Field size: 1 bit\r
2594 */\r
2595 uint8_t busMs;\r
2596 /**\r
2597 * @brief [rw] enables device to respond to memory access\r
2598 *\r
2599 * On rev 0 hw, this corresponds to MEM_SP\r
2600 * On rev 1 hw, this corresponds to MEM_SPACE_EN\r
2601 *\r
2602 * Field size: 1 bit\r
2603 */\r
2604 uint8_t memSp;\r
2605 /**\r
2606 * @brief [rw] enables device to respond to IO access\r
2607 *\r
2608 * This functionality is not supported in PCIESS and therefore\r
2609 * this bit is set to 0.\r
2610 *\r
2611 * On rev 0 hw, this corresponds to IO_SP\r
2612 * On rev 1 hw, this corresponds to IO_SPACE_EN\r
2613 *\r
2614 * Field size: 1 bit\r
2615 */\r
2616 uint8_t ioSp;\r
2617 } pcieStatusCmdReg_t;\r
2618 /* @} */\r
2619 \r
2620 \r
2621 /**\r
2622 * @ingroup pcielld_reg_cfg_com_structures\r
2623 * @brief Specification of the Class code and revision ID Register\r
2624 *\r
2625 * On rev 0 hw, this corresponds to CLASSCODE_REVID\r
2626 * On rev 1 hw, this corresponds to CLASSCODE_REVISIONID\r
2627 *\r
2628 * @{\r
2629 */\r
2630 typedef struct pcieRevIdReg_s {\r
2631 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2632 /**\r
2633 * @brief [ro] Class Code\r
2634 *\r
2635 * On rev 0 hw, the register presents this as 24 bits.\r
2636 * On rev 1 hw, the register presetns as 3 8bit fields, but they will all be\r
2637 * packed/unpacked from classCode for backward/forward compatibility.\r
2638 *\r
2639 * On rev 0 hw, this corresponds to CLASSCODE\r
2640 * On rev 1 hw, this corresponds to BASE_CLS_CD, SUBCLS_CD and PROG_IF_CODE\r
2641 *\r
2642 * Field size: 24 bits\r
2643 */\r
2644 uint32_t classCode;\r
2645 /**\r
2646 * @brief [ro] Revision ID\r
2647 *\r
2648 * On rev 0 hw, this corresponds to REVID\r
2649 * On rev 1 hw, this corresponds to REVID\r
2650 *\r
2651 * Field size: 8 bits\r
2652 */\r
2653 uint8_t revId;\r
2654 } pcieRevIdReg_t;\r
2655 /* @} */\r
2656 \r
2657 \r
2658 /**\r
2659 * @ingroup pcielld_reg_cfg_type0_structures\r
2660 * @brief Specification of the Base Address Register (BAR)\r
2661 *\r
2662 * This should be used to access a BAR register.\r
2663 *\r
2664 * There are two situations when this structure should be used:\n\r
2665 * 1. When setting up a 32 bit BAR\n\r
2666 * 2. When setting up the lower 32bits of a 64bits BAR\r
2667 *\r
2668 * Refer to @ref pcieBar32bitReg_t for the other possible BAR configurations\r
2669 *\r
2670 * On rev 0 hw, this corresponds to BARn\r
2671 * On rev 1 hw, this corresponds to BARn\r
2672 *\r
2673 * @{\r
2674 */\r
2675 typedef struct pcieBarReg_s {\r
2676 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2677 /**\r
2678 * @brief [rw] Base Address\r
2679 *\r
2680 * Rev 0 hw: 28 bits are modifiable\r
2681 * Rev 1 hw: only upper 12 bits are modifyable (eg 16-27). Rest are read-only. If users tries\r
2682 * to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
2683 *\r
2684 * Field size: 28 bits\r
2685 */\r
2686 uint32_t base;\r
2687 /**\r
2688 * @brief [rw] Prefetchable region?\r
2689 *\r
2690 * For memory BARs, it indicates whether the region is prefetchable.\n\r
2691 * 0 = Non-prefetchable.\n\r
2692 * 1 = Prefetchable.\r
2693 *\r
2694 * For I/O Bars, it is used as second least significant bit (LSB)\r
2695 * of the base address.\r
2696 *\r
2697 * Field size: 1 bit\r
2698 */\r
2699 uint8_t prefetch;\r
2700 /**\r
2701 * @brief [rw] Bar Type\r
2702 *\r
2703 * For memory BARs, they determine the BAR type.\n\r
2704 * 0h = 32-bit BAR.\n\r
2705 * 2h = 64-bit BAR.\n\r
2706 * Others = Reserved.\r
2707 *\r
2708 * For I/O BARs, bit 2 is the least significant bit (LSB) of the\r
2709 * base address and bit 1 is 0.\r
2710 *\r
2711 * Field size: 2 bits\r
2712 */\r
2713 uint8_t type;\r
2714 /**\r
2715 * @brief [rw] Memory or IO BAR\r
2716 *\r
2717 * 0 = Memory BAR.\n\r
2718 * 1 = I/O BAR.\r
2719 *\r
2720 * Field size: 1 bit\r
2721 */\r
2722 uint8_t memSpace;\r
2723 } pcieBarReg_t;\r
2724 /* @} */\r
2725 \r
2726 /**\r
2727 * @ingroup pcielld_reg_cfg_type0_structures\r
2728 * @brief Specification of the Base Address Register (BAR).\r
2729 *\r
2730 * This should be used to read/write a 32bit word to the BAR register.\r
2731 *\r
2732 * There are two situations when this structure should be used:\n\r
2733 * 1. When setting up BAR masks\n\r
2734 * 2. When setting up the upper 32bits of a 64bits BAR\r
2735 *\r
2736 * Refer to @ref pcieBarReg_t for the other possible BAR configurations\r
2737 *\r
2738 * @{\r
2739 */\r
2740 typedef struct pcieBar32bitReg_s {\r
2741 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2742 /**\r
2743 * @brief [rw] 32bits word (BAR mask or BAR address)\r
2744 *\r
2745 * Field size: 32 bits\r
2746 */\r
2747 uint32_t reg32;\r
2748 } pcieBar32bitReg_t;\r
2749 /* @} */\r
2750 \r
2751 /*****************************************************************************\r
2752 ********** PCIe LOCAL/REMOTE CONFIG TYPE 0 REGISTERS **********************\r
2753 ****************************************************************************/\r
2754 \r
2755 /**\r
2756 * @ingroup pcielld_reg_cfg_type0_structures\r
2757 * @brief Specification of the BIST Header Register\r
2758 *\r
2759 * On rev 0 hw, this corresponds to BIST_HEADER\r
2760 * On rev 1 hw, this corresponds to BIST_HEAD_LAT_CACH\r
2761 *\r
2762 * @{\r
2763 */\r
2764 typedef struct pcieBistReg_s {\r
2765 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2766 /**\r
2767 * @brief [ro] Bist capability\r
2768 *\r
2769 * Returns a one for BIST capability and zero otherwise. Not supported by PCIESS.\r
2770 *\r
2771 * This field is only used on rev 0 hw. A value of 0 is returned on rev 1 hw.\r
2772 *\r
2773 * On rev 0 hw, this corresponds to BIST_CAP\r
2774 * On rev 1 hw, unsupported\r
2775 *\r
2776 * Field size: 1 bit\r
2777 */\r
2778 uint8_t bistCap;\r
2779 /**\r
2780 * @brief [ro] Start Bist\r
2781 *\r
2782 * Write a one to start BIST. Not supported by PCIESS.\r
2783 *\r
2784 * This field is only used on rev 0 hw. A value of 0 is returned on rev 1 hw.\r
2785 *\r
2786 * On rev 0 hw, this corresponds to START_BIST\r
2787 * On rev 1 hw, unsupported\r
2788 *\r
2789 * Field size: 1 bit\r
2790 */\r
2791 uint8_t startBist;\r
2792 /**\r
2793 * @brief [ro] Completion code\r
2794 *\r
2795 * Not supported by PCIESS.\r
2796 *\r
2797 * This field is only used on rev 0 hw. A value of 0 is returned on rev 1 hw.\r
2798 *\r
2799 * On rev 0 hw, this corresponds to COMP_CODE\r
2800 * On rev 1 hw, unsupported\r
2801 *\r
2802 * Field size: 4 bits\r
2803 */\r
2804 uint8_t compCode;\r
2805 /**\r
2806 * @brief [ro] hw rev 1 bist field\r
2807 *\r
2808 * This field is only used on rev 1 hw. A value of 0 is returned on rev 0 hw.\r
2809 *\r
2810 * On rev 0 hw, unsupported\r
2811 * On rev 1 hw, this corresponds to BIST\r
2812 *\r
2813 * Field size: 8 bits\r
2814 */\r
2815 uint8_t bist;\r
2816 /**\r
2817 * @brief [ro] Multifunction device\r
2818 *\r
2819 * On rev 0 hw, this corresponds to MULFUN_DEV\r
2820 * On rev 1 hw, this corresponds to MFD\r
2821 *\r
2822 * Field size: 1 bit\r
2823 */\r
2824 uint8_t mulfunDev;\r
2825 /**\r
2826 * @brief [ro] Header type\r
2827 *\r
2828 * Configuration header format.\r
2829 *\r
2830 * 0 = EP mode\n\r
2831 * 1 = RC mode\r
2832 *\r
2833 * On rev 0 hw, this corresponds to HDR_TYPE\r
2834 * On rev 1 hw, this corresponds to HEAD_TYP\r
2835 *\r
2836 * Field size: 7 bits\r
2837 */\r
2838 uint8_t hdrType;\r
2839 /**\r
2840 * @brief [ro] Not applicable in PCIe\r
2841 *\r
2842 * On rev 0 hw, this corresponds to LAT_TMR\r
2843 * On rev 1 hw, this corresponds to MSTR_LAT_TIM\r
2844 *\r
2845 * Field size: 8 bits\r
2846 */\r
2847 uint8_t latTmr;\r
2848 /**\r
2849 * @brief [ro] Not applicable in PCIe\r
2850 *\r
2851 * On rev 0 hw, this corresponds to CACHELN_SIZ\r
2852 * On rev 1 hw, this corresponds to CACH_LN_SZE\r
2853 *\r
2854 * Field size: 8 bits\r
2855 */\r
2856 uint8_t cacheLnSize;\r
2857 } pcieBistReg_t;\r
2858 /* @} */\r
2859 \r
2860 \r
2861 /**\r
2862 * @ingroup pcielld_reg_cfg_type0_structures\r
2863 * @brief @ref pcieBarReg_s register plus an index (End Point BAR)\r
2864 *\r
2865 * There are multiple instances of this register. The index is used to select which\r
2866 * instance of the register will be accessed.\r
2867 *\r
2868 * This structure is used to access an End Point BAR. For more details, please refer to @ref pcieBarReg_t\r
2869 *\r
2870 * @{\r
2871 */\r
2872 typedef struct pcieType0BarIdx_s {\r
2873 pcieBarReg_t reg; /**< @brief Register Structure */\r
2874 uint8_t idx; /**< @brief Index in the array of registers of this type */\r
2875 } pcieType0BarIdx_t;\r
2876 /* @} */\r
2877 \r
2878 /**\r
2879 * @ingroup pcielld_reg_cfg_type0_structures\r
2880 * @brief @ref pcieBar32bitReg_s register plus an index (End Point BAR)\r
2881 *\r
2882 * There are multiple instances of this register. The index is used to select which\r
2883 * instance of the register will be accessed.\r
2884 *\r
2885 * This structure is used to access an End Point BAR. For more details, please refer to @ref pcieBar32bitReg_t\r
2886 *\r
2887 * @{\r
2888 */\r
2889 typedef struct pcieType0Bar32bitIdx_s {\r
2890 pcieBar32bitReg_t reg; /**< @brief Register Structure */\r
2891 uint8_t idx; /**< @brief Index in the array of registers of this type */\r
2892 } pcieType0Bar32bitIdx_t;\r
2893 /* @} */\r
2894 \r
2895 /**\r
2896 * @ingroup pcielld_reg_cfg_type0_structures\r
2897 * @brief Specification of the Subsystem Vendor ID Register\r
2898 *\r
2899 * On rev 0 hw, unsupported\r
2900 * On rev 1 hw, this corresponds to CARDBUS_CIS_POINTER\r
2901 *\r
2902 * @{\r
2903 */\r
2904 typedef struct pcieCardbusCisPointerReg_s {\r
2905 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2906 /**\r
2907 * @brief [rw] Cardbus CIS pointer (CS)\r
2908 *\r
2909 * This register is only used in rev 1 hw. It is physically present but marked reserved\r
2910 * in rev 0 hardware, so this structure/API isn't used.\r
2911 *\r
2912 * Field size: 32 bits\r
2913 */\r
2914 uint32_t cisPointer;\r
2915 } pcieCardbusCisPointerReg_t;\r
2916 /* @} */\r
2917 \r
2918 /**\r
2919 * @ingroup pcielld_reg_cfg_type0_structures\r
2920 * @brief Specification of the Subsystem Vendor ID Register\r
2921 *\r
2922 * On rev 0 hw, this corresponds to SUBSYS_VNDR_ID\r
2923 * On rev 1 hw, this corresponds to SUBID_SUBVENDORID\r
2924 *\r
2925 * @{\r
2926 */\r
2927 typedef struct pcieSubIdReg_s {\r
2928 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2929 /**\r
2930 * @brief [ro] Subsystem ID\r
2931 *\r
2932 * On rev 0 hw, this corresponds to SUBSYS_ID\r
2933 * On rev 1 hw, this corresponds to SUBSYS_DEV_ID_N\r
2934 *\r
2935 * Field size: 16 bits\r
2936 */\r
2937 uint16_t subId;\r
2938 /**\r
2939 * @brief [ro] Subsystem Vendor ID\r
2940 *\r
2941 * On rev 0 hw, this corresponds to SUBSYS_VEN_ID\r
2942 * On rev 1 hw, this corresponds to SUBSYS_VENDOR_ID_N\r
2943 *\r
2944 * Field size: 16 bits\r
2945 */\r
2946 uint16_t subVndId;\r
2947 } pcieSubIdReg_t;\r
2948 /* @} */\r
2949 \r
2950 /**\r
2951 * @ingroup pcielld_reg_cfg_type0_structures\r
2952 * @brief Specification of the Expansion ROM Register\r
2953 *\r
2954 * On rev 0 hw, this corresponds to EXPNSN_ROM\r
2955 * On rev 1 hw, this corresponds to EXPANSION_ROM_BAR\r
2956 *\r
2957 * @{\r
2958 */\r
2959 typedef struct pcieExpRomReg_s {\r
2960 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2961 /**\r
2962 * @brief [ro] rev 0; [rw] rev 1 Address of Expansion ROM\r
2963 *\r
2964 * Rev 0 hw: entire 21 bits are r/o and are always 0.\r
2965 *\r
2966 * Rev 1 hw: only upper 16 bits are modifyable (eg 16-31). Lower 5 bits are\r
2967 * r/o. Attempt to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
2968 *\r
2969 * On rev 0 hw, this corresponds to EXP_ROM_BASE_ADDR and EXROM_ADDRESS_RO\r
2970 * On rev 1 hw, this corresponds to EXROM_ADDRESS\r
2971 *\r
2972 * Field size: 21 bits\r
2973 */\r
2974 uint32_t expRomAddr;\r
2975 /**\r
2976 * @brief [ro] rev 0; [rw] rev 1: Expansion ROM Enable\r
2977 *\r
2978 * On rev 0 hw, this corresponds to EXP_ROM_EN\r
2979 * On rev 1 hw, this corresponds to EXROM_EN\r
2980 *\r
2981 * Field size: 1 bit\r
2982 */\r
2983 uint8_t enable;\r
2984 } pcieExpRomReg_t;\r
2985 /* @} */\r
2986 \r
2987 \r
2988 /**\r
2989 * @ingroup pcielld_reg_cfg_type0_structures\r
2990 * @brief Specification of the Capability Pointer Register\r
2991 *\r
2992 * On rev 0 hw, this corresponds to CAP_PTR\r
2993 * On rev 1 hw, this corresponds to CAPPTR\r
2994 *\r
2995 * @{\r
2996 */\r
2997 typedef struct pcieCapPtrReg_s {\r
2998 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
2999 /**\r
3000 * @brief [rw] First Capability Pointer\r
3001 *\r
3002 * By default, it points to Power Management Capability structure.\r
3003 *\r
3004 * On rev 0 hw, this corresponds to CAP_PTR\r
3005 * On rev 1 hw, this corresponds to CAPPTR\r
3006 *\r
3007 * Field size: 8 bits\r
3008 */\r
3009 uint8_t ptr;\r
3010 } pcieCapPtrReg_t;\r
3011 /* @} */\r
3012 \r
3013 /**\r
3014 * @ingroup pcielld_reg_cfg_type0_structures\r
3015 * @brief Specification of the Interrupt Pin Register\r
3016 *\r
3017 * On rev 0 hw, this corresponds to INT_PIN\r
3018 * On rev 1 hw, this corresponds to INTERRUPT\r
3019 *\r
3020 * @{\r
3021 */\r
3022 typedef struct pcieIntPinReg_s {\r
3023 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3024 /**\r
3025 * @brief [ro] interrupt Pin\r
3026 *\r
3027 * It identifies the legacy interrupt message that the device uses.\r
3028 * For single function configuration, the core only uses INTA.\r
3029 *\r
3030 * <TABLE>\r
3031 * <TR><TH>@ref intPin</TH><TH>Legacy Interrupt</TH></TR>\r
3032 * <TR><TD>0</TD> <TD>none</TD></TR>\r
3033 * <TR><TD>1</TD> <TD>INTA</TD></TR>\r
3034 * <TR><TD>2</TD> <TD>INTB</TD></TR>\r
3035 * <TR><TD>3</TD> <TD>INTC</TD></TR>\r
3036 * <TR><TD>4</TD> <TD>INTD</TD></TR>\r
3037 * <TR><TD>others</TD> <TD>reserved</TD></TR>\r
3038 * </TABLE>\r
3039 *\r
3040 * On rev 0 hw, this corresponds to INT_PIN\r
3041 * On rev 1 hw, this corresponds to INT_PIN\r
3042 *\r
3043 * Field size: 8 bits\r
3044 */\r
3045 uint8_t intPin;\r
3046 /**\r
3047 * @brief [rw] interrupt line\r
3048 *\r
3049 * On rev 0 hw, this corresponds to INT_LINE\r
3050 * On rev 1 hw, this corresponds to INT_LIN\r
3051 *\r
3052 * Field size: 8 bits\r
3053 */\r
3054 uint8_t intLine;\r
3055 } pcieIntPinReg_t;\r
3056 /* @} */\r
3057 \r
3058 \r
3059 /*****************************************************************************\r
3060 ********** PCIe LOCAL/REMOTE CONFIG TYPE 1 REGISTERS **********************\r
3061 ****************************************************************************/\r
3062 \r
3063 /**\r
3064 * @ingroup pcielld_reg_cfg_type1_structures\r
3065 * @brief @ref pcieBarReg_s register plus an index (Root Complex BAR)\r
3066 *\r
3067 * There are multiple instances of this register. The index is used to select which\r
3068 * instance of the register will be accessed.\r
3069 *\r
3070 * This structure is used to access a Root Complex BAR. For more details, please refer to @ref pcieBarReg_t.\r
3071 *\r
3072 * @{\r
3073 */\r
3074 typedef struct pcieType1BarIdx_s {\r
3075 pcieBarReg_t reg; /**< @brief Register Structure */\r
3076 uint8_t idx; /**< @brief Index in the array of registers of this type */\r
3077 } pcieType1BarIdx_t;\r
3078 /* @} */\r
3079 \r
3080 /**\r
3081 * @ingroup pcielld_reg_cfg_type1_structures\r
3082 * @brief @ref pcieBar32bitReg_s register plus an index (Root Complex BAR)\r
3083 *\r
3084 * There are multiple instances of this register. The index is used to select which\r
3085 * instance of the register will be accessed.\r
3086 *\r
3087 * This structure is used to access a Root Complex BAR. For more details, please refer to @ref pcieBar32bitReg_t.\r
3088 *\r
3089 * @{\r
3090 */\r
3091 typedef struct pcieType1Bar32bitIdx_s {\r
3092 pcieBar32bitReg_t reg; /**< @brief Register Structure */\r
3093 uint8_t idx; /**< @brief Index in the array of registers of this type */\r
3094 } pcieType1Bar32bitIdx_t;\r
3095 /* @} */\r
3096 \r
3097 /**\r
3098 * @ingroup pcielld_reg_cfg_type1_structures\r
3099 * @brief Specification of the BIST, Header Type, Latency Time and Cache Line Size Regiser\r
3100 *\r
3101 * On rev 0 hw, this corresponds to BIST_HEADER\r
3102 * On rev 1 hw, this corresponds to BIST_HEAD_LAT_CACH\r
3103 *\r
3104 * @{\r
3105 */\r
3106 typedef struct pcieType1BistHeaderReg_s {\r
3107 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3108 /**\r
3109 * @brief [ro] Returns a 1 for BIST capability and 0 otherwise.\r
3110 *\r
3111 * Not supported by PCIESS.\r
3112 *\r
3113 * On rev 0 hw, this corresponds to BIST_CAP\r
3114 * On rev 1 hw, unsupported\r
3115 *\r
3116 * Field size: 1 bit\r
3117 */\r
3118 uint8_t bistCap;\r
3119 /**\r
3120 * @brief [ro] Write a one to start BIST.\r
3121 *\r
3122 * Not supported by PCIESS.\r
3123 *\r
3124 * On rev 0 hw, this corresponds to START_BIST\r
3125 * On rev 1 hw, unsupported\r
3126 *\r
3127 * Field size: 1 bit\r
3128 */\r
3129 uint8_t startBist;\r
3130 /**\r
3131 * @brief [rw] Completion Code.\r
3132 *\r
3133 * Not supported by PCIESS.\r
3134 *\r
3135 * On rev 0 hw, this corresponds to COMP_CODE\r
3136 * On rev 1 hw, unsupported\r
3137 *\r
3138 * Field size: 4 bits\r
3139 */\r
3140 uint8_t compCode;\r
3141 /**\r
3142 * @brief [ro] hw rev 1 bist field\r
3143 *\r
3144 * On rev 0 hw, unsupported\r
3145 * On rev 1 hw, this corresponds to BIST\r
3146 *\r
3147 * Field size: 8 bits\r
3148 */\r
3149 uint8_t bist;\r
3150 /**\r
3151 * @brief [rw] Returns 1 if it is a multi-function device.\r
3152 *\r
3153 * On rev 0 hw, this corresponds to MULFUN_DEV\r
3154 * On rev 1 hw, this corresponds to MFD\r
3155 *\r
3156 * Field size: 1 bit\r
3157 */\r
3158 uint8_t mulFunDev;\r
3159 /**\r
3160 * @brief [rw] Configuration Header Format.\r
3161 *\r
3162 * 0 = EP mode\n\r
3163 * 1 = RC mode\r
3164 *\r
3165 * On rev 0 hw, this corresponds to HDR_TYPE\r
3166 * On rev 1 hw, this corresponds to HEAD_TYP\r
3167 *\r
3168 * Field size: 7 bits\r
3169 */\r
3170 uint8_t hdrType;\r
3171 /**\r
3172 * @brief [ro] Not applicable in PCIe\r
3173 *\r
3174 * On rev 0 hw, this corresponds to LAT_TMR\r
3175 * On rev 1 hw, this corresponds to MSTR_LAT_TIM\r
3176 *\r
3177 * Field size: 8 bits\r
3178 */\r
3179 uint8_t latTmr;\r
3180 /**\r
3181 * @brief [ro] Not applicable in PCIe\r
3182 *\r
3183 * On rev 0 hw, this corresponds to CACHELN_SIZE\r
3184 * On rev 1 hw, this corresponds to CACH_LN_SIZE\r
3185 *\r
3186 * Field size: 8 bits\r
3187 */\r
3188 uint8_t cacheLnSize;\r
3189 } pcieType1BistHeaderReg_t;\r
3190 /* @} */\r
3191 \r
3192 /**\r
3193 * @ingroup pcielld_reg_cfg_type1_structures\r
3194 * @brief Specification of the Latency Timer and Bus Number Register\r
3195 *\r
3196 * On rev 0 hw, this corresponds to BUSNUM\r
3197 * On rev 1 hw, this corresponds to BUS_NUM_REG\r
3198 *\r
3199 * @{\r
3200 */\r
3201 typedef struct pcieType1BusNumReg_s {\r
3202 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3203 /**\r
3204 * @brief [ro] Secondary Latency Timer (N/A for PCIe)\r
3205 *\r
3206 * On rev 0 hw, this corresponds to SEC_LAT_TMR\r
3207 * On rev 1 hw, this corresponds to SEC_LAT_TIMER\r
3208 *\r
3209 * Field size: 8 bits\r
3210 */\r
3211 uint8_t secLatTmr;\r
3212 /**\r
3213 * @brief [rw] Subordinate Bus Number. This is highest bus\r
3214 * number on downstream interface.\r
3215 *\r
3216 * On rev 0 hw, this corresponds to SUB_BUS_NUM\r
3217 * On rev 1 hw, this corresponds to SUBORD_BUS_NUM\r
3218 *\r
3219 * Field size: 8 bits\r
3220 */\r
3221 uint8_t subBusNum;\r
3222 /**\r
3223 * @brief [rw] Secondary Bus Number. It is typically 1h for RC.\r
3224 *\r
3225 * On rev 0 hw, this corresponds to SEC_BUS_NUM\r
3226 * On rev 1 hw, this corresponds to SEC_BUS_NUM\r
3227 *\r
3228 * Field size: 8 bits\r
3229 */\r
3230 uint8_t secBusNum;\r
3231 /**\r
3232 * @brief [rw] Primary Bus Number. It is 0 for RC and nonzero for\r
3233 * switch devices only.\r
3234 *\r
3235 * On rev 0 hw, this corresponds to PRI_BUS_NUM\r
3236 * On rev 1 hw, this corresponds to PRIM_BUS_NUM\r
3237 *\r
3238 * Field size: 8 bits\r
3239 */\r
3240 uint8_t priBusNum;\r
3241 } pcieType1BusNumReg_t;\r
3242 /* @} */\r
3243 \r
3244 /**\r
3245 * @ingroup pcielld_reg_cfg_type1_structures\r
3246 * @brief Specification of the Secondary Status and IO Base/Limit Register\r
3247 *\r
3248 * On rev 0 hw, this corresponds to SECSTAT\r
3249 * On rev 1 hw, this corresponds to IOBASE_LIMIT_SEC_STATUS\r
3250 *\r
3251 * @{\r
3252 */\r
3253 typedef struct pcieType1SecStatReg_s {\r
3254 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3255 /**\r
3256 * @brief [rw] Detected Parity Error.\r
3257 *\r
3258 * Read 1 if received a poisoned TLP.\r
3259 * Write 1 to clear; write 0 has no effect.\r
3260 *\r
3261 * On rev 0 hw, this corresponds to DTCT_PERROR\r
3262 * On rev 1 hw, this corresponds to DET_PAR_ERR\r
3263 *\r
3264 * Field size: 1 bit\r
3265 */\r
3266 uint8_t dtctPError;\r
3267 /**\r
3268 * @brief [rw] Received System Error.\r
3269 *\r
3270 * Read 1 if received an ERR_FATAL or ERR_NONFATAL message.\r
3271 * Write 1 to clear; write 0 has no effect.\r
3272 *\r
3273 * On rev 0 hw, this corresponds to RX_SYS_ERROR\r
3274 * On rev 1 hw, this corresponds to RCVD_SYS_ERR\r
3275 *\r
3276 * Field size: 1 bit\r
3277 */\r
3278 uint8_t rxSysError;\r
3279 /**\r
3280 * @brief [rw] Received Master Abort.\r
3281 *\r
3282 * Read 1 if received a completion with unsupported request completion status.\r
3283 * Write 1 to clear; write 0 has no effect.\r
3284 *\r
3285 * On rev 0 hw, this corresponds to RX_MST_ABORT\r
3286 * On rev 1 hw, this corresponds to RCVD_MSTR_ABORT\r
3287 *\r
3288 * Field size: 1 bit\r
3289 */\r
3290 uint8_t rxMstAbort;\r
3291 /**\r
3292 * @brief [rw] Received Target Abort.\r
3293 *\r
3294 * Read 1 if received a completion with completer abort completion status.\r
3295 * Write 1 to clear; write 0 has no effect.\r
3296 *\r
3297 * On rev 0 hw, this corresponds to RX_TGT_ABORT\r
3298 * On rev 1 hw, this corresponds to RCVD_TRGT_ABORT\r
3299 *\r
3300 * Field size: 1 bit\r
3301 */\r
3302 uint8_t rxTgtAbort;\r
3303 /**\r
3304 * @brief [rw] Signaled Target Abort.\r
3305 *\r
3306 * Read 1 if sent a posted or non-posted request as a completer abort error.\r
3307 * Write 1 to clear; write 0 has no effect.\r
3308 *\r
3309 * On rev 0 hw, this corresponds to TX_TGT_ABORT\r
3310 * On rev 1 hw, this corresponds to SGNLD_TRGT_ABORT\r
3311 *\r
3312 * Field size: 1 bit\r
3313 */\r
3314 uint8_t txTgtAbort;\r
3315 /**\r
3316 * @brief [ro] DEVSEL Timing\r
3317 *\r
3318 * On rev 0 hw, unsupported\r
3319 * On rev 1 hw, this corresponds to DEVSEL_TIMING\r
3320 *\r
3321 * Field size: 2 bits\r
3322 */\r
3323 uint8_t devselTiming;\r
3324 /**\r
3325 * @brief [rw] Master Data Parity Error.\r
3326 *\r
3327 * Read 1 if the parity error enable bit\r
3328 * @ref pcieType1BridgeIntReg_s::pErrRespEn is set and either the condition\r
3329 * that the requester receives a poisoned completion or the condition\r
3330 * that the requester poisons a write request is true.\r
3331 * Write 1 to clear; write 0 has no effect.\r
3332 *\r
3333 * On rev 0 hw, this corresponds to MST_DPERR\r
3334 * On rev 1 hw, this corresponds to MSTR_DATA_PRTY_ERR\r
3335 *\r
3336 * Field size: 1 bit\r
3337 */\r
3338 uint8_t mstDPErr;\r
3339 /**\r
3340 * @brief [ro] Fast Back to Back Capable.\r
3341 *\r
3342 * On rev 0 hw, unsupported\r
3343 * On rev 1 hw, this corresponds to FAST_B2B_CAP\r
3344 *\r
3345 * Field size: 1 bit\r
3346 */\r
3347 uint8_t fastB2bCap;\r
3348 /**\r
3349 * @brief [ro] 66Mhz Capable.\r
3350 *\r
3351 * On rev 0 hw, unsupported\r
3352 * On rev 1 hw, this corresponds to C66MHZ_CAPA\r
3353 *\r
3354 * Field size: 1 bit\r
3355 */\r
3356 uint8_t c66mhzCapa;\r
3357 /**\r
3358 * @brief [rw] Upper 4 bits of 16bit IO Space Limit Address.\r
3359 *\r
3360 * On rev 0 hw, this corresponds to IO_LIMIT\r
3361 * On rev 1 hw, this corresponds to IO_SPACE_LIMIT\r
3362 *\r
3363 * Field size: 4 bits\r
3364 */\r
3365 uint8_t IOLimit;\r
3366 /**\r
3367 * @brief [rw] Indicates addressing for IO Limit Address.\r
3368 *\r
3369 * Writable from internal bus interface.\r
3370 * 0 = 16-bit IO addressing.\r
3371 * 1 = 32-bit IO addressing.\r
3372 *\r
3373 * On rev 0 hw, this corresponds to IO_LIMIT_ADDR\r
3374 * On rev 1 hw, this corresponds to IODECODE_32\r
3375 *\r
3376 * Field size: 1 bit\r
3377 */\r
3378 uint8_t IOLimitAddr;\r
3379 /**\r
3380 * @brief [rw] Upper 4 bits of 16bit IO Space Base Address.\r
3381 *\r
3382 * On rev 0 hw, this corresponds to IO_BASE\r
3383 * On rev 1 hw, this corresponds to IO_SPACE_BASE\r
3384 *\r
3385 * Field size: 4 bits\r
3386 */\r
3387 uint8_t IOBase;\r
3388 /**\r
3389 * @brief [rw] Indicates addressing for the IO Base Address.\r
3390 *\r
3391 * Writable from internal bus interface.\r
3392 * 0 = 16-bit IO addressing.\r
3393 * 1 = 32-bit IO addressing.\r
3394 *\r
3395 * On rev 0 hw, this corresponds to IO_BASE_ADDR\r
3396 * On rev 1 hw, this corresponds to IODECODE_32_0\r
3397 *\r
3398 * Field size: 1 bit\r
3399 */\r
3400 uint8_t IOBaseAddr;\r
3401 } pcieType1SecStatReg_t;\r
3402 /* @} */\r
3403 \r
3404 /**\r
3405 * @ingroup pcielld_reg_cfg_type1_structures\r
3406 * @brief Specification of the Memory Limit and Base Register\r
3407 *\r
3408 * On rev 0 hw, this corresponds to MEMSPACE\r
3409 * On rev 1 hw, this corresponds to MEM_BASE_LIMIT\r
3410 *\r
3411 * @{\r
3412 */\r
3413 typedef struct pcieType1MemspaceReg_s {\r
3414 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3415 /**\r
3416 * @brief [rw] Upper 12 bits of 32bit Memory Limit Address.\r
3417 *\r
3418 * On rev 0 hw, this corresponds to MEM_LIMIT\r
3419 * On rev 1 hw, this corresponds to MEM_LIMIT_ADDR\r
3420 *\r
3421 * Field size: 12 bits\r
3422 */\r
3423 uint16_t limit;\r
3424 /**\r
3425 * @brief [rw] Upper 12 bits of 32bit Memory Base Address.\r
3426 *\r
3427 * On rev 0 hw, this corresponds to MEM_BASE\r
3428 * On rev 1 hw, this corresponds to MEM_BASE_ADDR\r
3429 *\r
3430 * Field size: 12 bit\r
3431 */\r
3432 uint16_t base;\r
3433 } pcieType1MemspaceReg_t;\r
3434 /* @} */\r
3435 \r
3436 \r
3437 /**\r
3438 * @ingroup pcielld_reg_cfg_type1_structures\r
3439 * @brief Specification of the Prefetchable Memory Limit and Base Register\r
3440 *\r
3441 * On rev 0 hw, this corresponds to PREFETCH_MEM\r
3442 * On rev 1 hw, this corresponds to PREF_MEM_BASE_LIMIT\r
3443 *\r
3444 * @{\r
3445 */\r
3446 typedef struct pciePrefMemReg_s {\r
3447 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3448 /**\r
3449 * @brief [rw] Memory limit\r
3450 *\r
3451 * Upper 12 bits of 32bit prefetchable memory limit address (end address).\r
3452 *\r
3453 * On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
3454 * On rev 1 hw, this corresponds to PREF_MEM_ADDR\r
3455 *\r
3456 * Field size: 12 bits\r
3457 */\r
3458 uint16_t limit;\r
3459 /**\r
3460 * @brief [rw] 32 or 64 bit addressing\r
3461 *\r
3462 * Indicates addressing for prefetchable memory limit address (end address).\r
3463 *\r
3464 * 0 = 32-bit memory addressing\n\r
3465 * 1 = 64-bit memory addressing\r
3466 *\r
3467 * On rev 0 hw, this corresponds to PRE_LIMIT_ADDR\r
3468 * On rev 1 hw, this corresponds to MEMDECODE_64\r
3469 *\r
3470 * Field size: 1 bit\r
3471 */\r
3472 uint8_t limitAddr;\r
3473 /**\r
3474 * @brief [rw] Memory base\r
3475 *\r
3476 * Upper 12 bits of 32bit prefetchable memory base address (start address).\r
3477 *\r
3478 * On rev 0 hw, this corresponds to PREFETCH_BASE\r
3479 * On rev 1 hw, this corresponds to UPPPREF_MEM_ADDR\r
3480 *\r
3481 * Field size: 12 bits\r
3482 */\r
3483 uint16_t base;\r
3484 /**\r
3485 * @brief [rw] 32 or 64 bit addressing\r
3486 *\r
3487 * Indicates addressing for the prefetchable memory base address (start address).\r
3488 *\r
3489 * 0 = 32-bit memory addressing\n\r
3490 * 1 = 64-bit memory addressing\r
3491 *\r
3492 * On rev 0 hw, this corresponds to PRE_BASE_ADDR\r
3493 * On rev 1 hw, this corresponds to MEMDECODE_64_0\r
3494 *\r
3495 * Field size: 1 bit\r
3496 */\r
3497 uint8_t baseAddr;\r
3498 } pciePrefMemReg_t;\r
3499 /* @} */\r
3500 \r
3501 \r
3502 /**\r
3503 * @ingroup pcielld_reg_cfg_type1_structures\r
3504 * @brief Specification of the Prefetchable Memory Base Upper Register\r
3505 *\r
3506 * On rev 0 hw, this corresponds to PREFETCH_BASE\r
3507 * On rev 1 hw, this corresponds to UPPER_32BIT_PREF_BASEADDR\r
3508 *\r
3509 * @{\r
3510 */\r
3511 typedef struct pciePrefBaseUpperReg_s {\r
3512 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3513 /**\r
3514 * @brief [rw] Base upper 32bits\r
3515 *\r
3516 * Upper 32 bits of Prefetchable Memory Base Address. Used with 64bit\r
3517 * prefetchable memory addressing only.\r
3518 *\r
3519 * On rev 0 hw, this corresponds to PREFETCH_BASE\r
3520 * On rev 1 hw, this corresponds to ADDRUPP\r
3521 *\r
3522 * Field size: 32 bits\r
3523 */\r
3524 uint32_t base;\r
3525 } pciePrefBaseUpperReg_t;\r
3526 /* @} */\r
3527 \r
3528 /**\r
3529 * @ingroup pcielld_reg_cfg_type1_structures\r
3530 * @brief Specification of the Prefetchable Memory Limit Upper Register\r
3531 *\r
3532 * On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
3533 * On rev 1 hw, this corresponds to UPPER_32BIT_PREF_LIMITADDR\r
3534 *\r
3535 * @{\r
3536 */\r
3537 typedef struct pciePrefLimitUpperReg_s {\r
3538 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3539 /**\r
3540 * @brief [rw] Base upper 32bits\r
3541 *\r
3542 * Upper 32 bits of Prefetchable Memory Limit Address. Used with 64 bit\r
3543 * prefetchable memory addressing only.\r
3544 *\r
3545 * On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
3546 * On rev 1 hw, this corresponds to ADDRUPP_LIMIT\r
3547 *\r
3548 * Field size: 32 bits\r
3549 */\r
3550 uint32_t limit;\r
3551 } pciePrefLimitUpperReg_t;\r
3552 /* @} */\r
3553 \r
3554 /**\r
3555 * @ingroup pcielld_reg_cfg_type1_structures\r
3556 * @brief Specification of the IO Base and Limit Upper 16 bits Register\r
3557 *\r
3558 * On rev 0 hw, this corresponds to IOSPACE\r
3559 * On rev 1 hw, this corresponds to IO_BASE_LIMIT\r
3560 *\r
3561 * @{\r
3562 */\r
3563 typedef struct pcieType1IOSpaceReg_s {\r
3564 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3565 /**\r
3566 * @brief [rw] Upper 16 bits of IO Base Address.\r
3567 *\r
3568 * Used with 32 bit IO space addressing only.\r
3569 *\r
3570 * On rev 0 hw, this corresponds to IOBASE\r
3571 * On rev 1 hw, this corresponds to UPP16_IOBASE\r
3572 *\r
3573 * Field size: 16 bits\r
3574 */\r
3575 uint16_t IOBase;\r
3576 /**\r
3577 * @brief [rw] Upper 16 bits of IO Limit Address.\r
3578 *\r
3579 * Used with 32 bit IO space addressing only.\r
3580 *\r
3581 * On rev 0 hw, this corresponds to IOLIMIT\r
3582 * On rev 1 hw, this corresponds to UPP16_IOLIMIT\r
3583 *\r
3584 * Field size: 16 bits\r
3585 */\r
3586 uint16_t IOLimit;\r
3587 } pcieType1IOSpaceReg_t;\r
3588 /* @} */\r
3589 \r
3590 /**\r
3591 * @ingroup pcielld_reg_cfg_type1_structures\r
3592 * @brief Specification of the Capabilities Pointer Register\r
3593 *\r
3594 * On rev 0 hw, this corresponds to CAP_PTR\r
3595 * On rev 1 hw, this corresponds to CAPPTR\r
3596 *\r
3597 * @{\r
3598 */\r
3599 typedef struct pcieType1CapPtrReg_s {\r
3600 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3601 /**\r
3602 * @brief [rw] First Capability Pointer.\r
3603 *\r
3604 * By default, it points to Power Management Capability structure.\r
3605 * Writable from internal bus interface.\r
3606 *\r
3607 * On rev 0 hw, this corresponds to CAP_PTR\r
3608 * On rev 1 hw, this corresponds to CAPPTR\r
3609 *\r
3610 * Field size: 8 bits\r
3611 */\r
3612 uint8_t capPtr;\r
3613 } pcieType1CapPtrReg_t;\r
3614 /* @} */\r
3615 \r
3616 /**\r
3617 * @ingroup pcielld_reg_cfg_type1_structures\r
3618 * @brief Specification of the Expansion ROM Base Address Register\r
3619 *\r
3620 * On rev 0 hw, this corresponds to EXPNSN_ROM\r
3621 * On rev 1 hw, this corresponds to EXPANSION_ROM_BAR\r
3622 *\r
3623 * @{\r
3624 */\r
3625 typedef struct pcieType1ExpnsnRomReg_s {\r
3626 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3627 /**\r
3628 * @brief [rw] Address of Expansion ROM\r
3629 *\r
3630 * Rev 0 hw: 21 bits are modifiable\r
3631 * Rev 1 hw: only upper 16 bits are modifyable (eg 16-20). Rest are read-only. If users tries\r
3632 * to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
3633 *\r
3634 * On rev 0 hw, this corresponds to EXP_ROM_BASE_ADDR\r
3635 * On rev 1 hw, this corresponds to EXROM_ADDRESS\r
3636 *\r
3637 * Field size: 21CAPPTR bits [0-0x1FFFFF]\r
3638 */\r
3639 uint32_t expRomBaseAddr;\r
3640 /**\r
3641 * @brief [rw] Expansion ROM enable\r
3642 *\r
3643 * On rev 0 hw, this corresponds to EXP_ROM_EN\r
3644 * On rev 1 hw, this corresponds to EXP_ROM_EN\r
3645 *\r
3646 * Field size: 1 bit\r
3647 */\r
3648 uint8_t expRomEn;\r
3649 } pcieType1ExpnsnRomReg_t;\r
3650 /* @} */\r
3651 \r
3652 /**\r
3653 * @ingroup pcielld_reg_cfg_type1_structures\r
3654 * @brief Specification of the Bridge Control and Interrupt Register\r
3655 *\r
3656 * On rev 0 hw, this corresponds to BRIDGE_INT\r
3657 * On rev 1 hw, this corresponds to BRIDGE_INT\r
3658 *\r
3659 * @{\r
3660 */\r
3661 typedef struct pcieType1BridgeIntReg_s {\r
3662 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3663 /**\r
3664 * @brief [ro] Discard Timer SERR Enable Status.\r
3665 *\r
3666 * Not Applicable to PCI Express. Hardwired to 0.\r
3667 *\r
3668 * On rev 0 hw, this corresponds to SERREN_STATUS\r
3669 * On rev 1 hw, this corresponds to DT_SERR_EN\r
3670 *\r
3671 * Field size: 1 bit\r
3672 */\r
3673 uint8_t serrEnStatus;\r
3674 /**\r
3675 * @brief [ro] Discard Timer Status.\r
3676 *\r
3677 * Not applicable to PCI Express. Hardwired to 0.\r
3678 *\r
3679 * On rev 0 hw, this corresponds to TIMER_STATUS\r
3680 * On rev 1 hw, this corresponds to DT_STS\r
3681 *\r
3682 * Field size: 1 bit\r
3683 */\r
3684 uint8_t timerStatus;\r
3685 /**\r
3686 * @brief [ro] Secondary Discard Timer.\r
3687 *\r
3688 * Not applicable to PCI Express. Hardwired to 0.\r
3689 *\r
3690 * On rev 0 hw, this corresponds to SEC_TIMER\r
3691 * On rev 1 hw, this corresponds to SEC_DT\r
3692 *\r
3693 * Field size: 1 bit\r
3694 */\r
3695 uint8_t secTimer;\r
3696 /**\r
3697 * @brief [ro] Primary Discard Timer.\r
3698 *\r
3699 * Not applicable to PCI Express. Hardwired to 0.\r
3700 *\r
3701 * On rev 0 hw, this corresponds to PRI_TIMER\r
3702 * On rev 1 hw, this corresponds to PRI_DT\r
3703 *\r
3704 * Field size: 1 bit\r
3705 */\r
3706 uint8_t priTimer;\r
3707 /**\r
3708 * @brief [ro] Fast Back to Back Transactions Enable.\r
3709 *\r
3710 * Not applicable to PCI Express. Hardwired to 0.\r
3711 *\r
3712 * On rev 0 hw, this corresponds to B2B_EN\r
3713 * On rev 1 hw, this corresponds to FAST_B2B_EN\r
3714 *\r
3715 * Field size: 1 bit\r
3716 */\r
3717 uint8_t b2bEn;\r
3718 /**\r
3719 * @brief [rw] Secondary Bus Reset.\r
3720 *\r
3721 * On rev 0 hw, this corresponds to SEC_BUS_RST\r
3722 * On rev 1 hw, this corresponds to SEC_BUS_RST\r
3723 *\r
3724 * Field size: 1 bit\r
3725 */\r
3726 uint8_t secBusRst;\r
3727 /**\r
3728 * @brief [ro] Master Abort Mode.\r
3729 *\r
3730 * Not applicable to PCI Express. Hardwired to 0.\r
3731 *\r
3732 * On rev 0 hw, this corresponds to MST_ABORT_MODE\r
3733 * On rev 1 hw, this corresponds to MST_ABT_MODE\r
3734 *\r
3735 * Field size: 1 bit\r
3736 */\r
3737 uint8_t mstAbortMode;\r
3738 /**\r
3739 * @brief [rw] VGA 16 bit Decode\r
3740 *\r
3741 * On rev 0 hw, this corresponds to VGA_DECODE\r
3742 * On rev 1 hw, this corresponds to VGA_16B_DEC\r
3743 *\r
3744 * Field size: 1 bit\r
3745 */\r
3746 uint8_t vgaDecode;\r
3747 /**\r
3748 * @brief [rw] VGA Enable\r
3749 *\r
3750 * On rev 0 hw, this corresponds to VGA_EN\r
3751 * On rev 1 hw, this corresponds to VGA_EN\r
3752 *\r
3753 * Field size: 1 bit\r
3754 */\r
3755 uint8_t vgaEn;\r
3756 /**\r
3757 * @brief [rw] ISA Enable\r
3758 *\r
3759 * On rev 0 hw, this corresponds to ISA_EN\r
3760 * On rev 1 hw, this corresponds to ISA_EN\r
3761 *\r
3762 * Field size: 1 bit\r
3763 */\r
3764 uint8_t isaEn;\r
3765 /**\r
3766 * @brief [rw] SERR Enable.\r
3767 *\r
3768 * Set to enable forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL messages.\r
3769 *\r
3770 * On rev 0 hw, this corresponds to SERR_EN\r
3771 * On rev 1 hw, this corresponds to SERR_EN\r
3772 *\r
3773 * Field size: 1 bit\r
3774 */\r
3775 uint8_t serrEn;\r
3776 /**\r
3777 * @brief [rw] Parity Error Response Enable.\r
3778 *\r
3779 * This bit controls the logging of poisoned TLPs in\r
3780 * @ref pcieType1SecStatReg_s::mstDPErr\r
3781 *\r
3782 * On rev 0 hw, this corresponds to PERR_RESP_EN\r
3783 * On rev 1 hw, this corresponds to PERR_RESP_EN\r
3784 *\r
3785 * Field size: 1 bit\r
3786 */\r
3787 uint8_t pErrRespEn;\r
3788 /**\r
3789 * @brief [rw] Interrupt Pin.\r
3790 *\r
3791 * It identifies the legacy interrupt message that the device uses.\r
3792 * For single function configuration, the core only uses INTA. This register\r
3793 * is writable through internal bus interface.\r
3794 *\r
3795 * 0 = Legacy interrupt is not being used\r
3796 * 1h = INTA\r
3797 * 2h = INTB\r
3798 * 3h = INTC\r
3799 * 4h = INTD\r
3800 * Others = Reserved.\r
3801 *\r
3802 * On rev 0 hw, this corresponds to INT_PIN\r
3803 * On rev 1 hw, this corresponds to INT_PIN\r
3804 *\r
3805 * Field size: 8 bits\r
3806 */\r
3807 uint8_t intPin;\r
3808 /**\r
3809 * @brief [rw] Interrupt Line. Value is system software specified.\r
3810 *\r
3811 * On rev 0 hw, this corresponds to INT_LINE\r
3812 * On rev 1 hw, this corresponds to INT_LIN\r
3813 *\r
3814 * Field size: 8 bits\r
3815 */\r
3816 uint8_t intLine;\r
3817 } pcieType1BridgeIntReg_t;\r
3818 /* @} */\r
3819 \r
3820 /*****************************************************************************\r
3821 ********** Power Management Capabilities REGISTERS ************************\r
3822 ****************************************************************************/\r
3823 \r
3824 /**\r
3825 * @ingroup pcielld_reg_cfg_pwr_structures\r
3826 * @brief Specification of the Power Management Capability Register\r
3827 *\r
3828 * This register may be used for both endpoint and root complex modes.\r
3829 *\r
3830 * This register is only available for rev 0 hw.\r
3831 *\r
3832 * @{\r
3833 */\r
3834 typedef struct pciePMCapReg_s {\r
3835 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3836 /**\r
3837 * @brief [rw] PME Support.\r
3838 *\r
3839 * Identifies the power states from which generates PME Messages. A value of\r
3840 * 0 for any bit indicates that the device (or function) is not capable\r
3841 * of generating PME Messages while in that power state.\r
3842 *\r
3843 * bit 0x10: If set, PME Messages can be generated from D3cold.\n\r
3844 * bit 0x08: If set, PME Messages can be generated from D3hot.\n\r
3845 * bit 0x04: If set, PME Messages can be generated from D2.\n\r
3846 * bit 0x02: If set, PME Messages can be generated from D1.\n\r
3847 * bit 0x01: If set, PME Messages can be generated from D0.\r
3848 *\r
3849 * Field size: 5 bits\r
3850 *\r
3851 */\r
3852 uint8_t pmeSuppN;\r
3853 /**\r
3854 * @brief [rw] D2 Support.\r
3855 *\r
3856 * Field size: 1 bit\r
3857 *\r
3858 */\r
3859 uint8_t d2SuppN;\r
3860 /**\r
3861 * @brief [rw] D1 Support.\r
3862 *\r
3863 * Field size: 1 bit\r
3864 *\r
3865 */\r
3866 uint8_t d1SuppN;\r
3867 /**\r
3868 * @brief [rw] Auxiliary Current\r
3869 *\r
3870 * Field size: 3 bits\r
3871 *\r
3872 */\r
3873 uint8_t auxCurrN;\r
3874 /**\r
3875 * @brief [rw] Device Specific Initialization\r
3876 *\r
3877 * Field size: 1 bit\r
3878 *\r
3879 */\r
3880 uint8_t dsiN;\r
3881 /**\r
3882 * @brief [ro] PME clock. Hardwired to zero.\r
3883 *\r
3884 * Field size: 1 bit\r
3885 *\r
3886 */\r
3887 uint8_t pmeClk;\r
3888 /**\r
3889 * @brief [rw] Power Management Specification Version\r
3890 *\r
3891 * Field size: 3 bits\r
3892 *\r
3893 */\r
3894 uint8_t pmeSpecVer;\r
3895 /**\r
3896 * @brief [rw] Next capability pointer.\r
3897 *\r
3898 * By default, it points to Message Signaled Interrupt structure.\r
3899 *\r
3900 * Field size: 8 bits\r
3901 *\r
3902 */\r
3903 uint8_t pmNextPtr;\r
3904 /**\r
3905 * @brief [rw] Power Management Capability ID.\r
3906 *\r
3907 * Field size: 8 bits\r
3908 *\r
3909 */\r
3910 uint8_t pmCapID;\r
3911 } pciePMCapReg_t;\r
3912 /* @} */\r
3913 \r
3914 /**\r
3915 * @ingroup pcielld_reg_cfg_pwr_structures\r
3916 * @brief Specification of the Power Management Capabilities Control and Status Register\r
3917 *\r
3918 * This register may be used for both endpoint and root complex modes.\r
3919 *\r
3920 * This register is only available for rev 0 hw.\r
3921 *\r
3922 * @{\r
3923 */\r
3924 typedef struct pciePMCapCtlStatReg_s {\r
3925 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
3926 /**\r
3927 * @brief [ro] Data register for additional information. Not supported.\r
3928 *\r
3929 * Field size: 8 bits\r
3930 *\r
3931 */\r
3932 uint8_t dataReg;\r
3933 /**\r
3934 * @brief [ro] Bus Power/Clock Control Enable. Hardwired to zero.\r
3935 *\r
3936 * Field size: 1 bit\r
3937 *\r
3938 */\r
3939 uint8_t clkCtrlEn;\r
3940 /**\r
3941 * @brief [ro] B2 and B3 support. Hardwired to zero.\r
3942 *\r
3943 * Field size: 1 bit\r
3944 *\r
3945 */\r
3946 uint8_t b2b3Support;\r
3947 /**\r
3948 * @brief [rw] PME Status. Indicates if a previously enabled PME event occurred or not.\r
3949 *\r
3950 * Write 1 to clear.\r
3951 *\r
3952 * Field size: 1 bit\r
3953 *\r
3954 */\r
3955 uint8_t pmeStatus;\r
3956 /**\r
3957 * @brief [ro] Data Scale. Not supported.\r
3958 *\r
3959 * Field size: 2 bits\r
3960 *\r
3961 */\r
3962 uint8_t dataScale;\r
3963 /**\r
3964 * @brief [ro] Data Select. Not supported.\r
3965 *\r
3966 * Field size: 4 bits\r
3967 *\r
3968 */\r
3969 uint8_t dataSelect;\r
3970 /**\r
3971 * @brief [rw] PME Enable. Value of 1 indicates device is enabled to generate PME.\r
3972 *\r
3973 * Field size: 1 bit\r
3974 *\r
3975 */\r
3976 uint8_t pmeEn;\r
3977 /**\r
3978 * @brief [rw] No Soft Reset.\r
3979 *\r
3980 * It is set to disable reset during a transition from D3 to D0.\r
3981 *\r
3982 * Field size: 1 bit\r
3983 *\r
3984 */\r
3985 uint8_t noSoftRst;\r
3986 /**\r
3987 * @brief [rw] Power State.\r
3988 *\r
3989 * Controls the device power state. Writes are ignored if the state is not\r
3990 * supported.\r
3991 * 0 = D0 power state\r
3992 * 1h = D1 power state\r
3993 * 2h = D2 power state\r
3994 * 3h = D3 power states\r
3995 *\r
3996 * Field size: 2 bits\r
3997 *\r
3998 */\r
3999 uint8_t pwrState;\r
4000 } pciePMCapCtlStatReg_t;\r
4001 /* @} */\r
4002 \r
4003 /*****************************************************************************\r
4004 ********** Message Signaling Interrupt REGISTERS *************************\r
4005 ****************************************************************************/\r
4006 \r
4007 /**\r
4008 * @ingroup pcielld_reg_cfg_msi_structures\r
4009 * @brief Specification of the MSI capabilities Register\r
4010 *\r
4011 * This register may be used for both endpoint and root complex modes.\r
4012 *\r
4013 * This register is only available for rev 0 hw.\r
4014 *\r
4015 * @{\r
4016 */\r
4017 typedef struct pcieMsiCapReg_s {\r
4018 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
4019 /**\r
4020 * @brief [rw] 64bit addressing enabled\r
4021 *\r
4022 * Field size: 1 bit\r
4023 *\r
4024 */\r
4025 uint8_t en64bit;\r
4026 /**\r
4027 * @brief [rw] Multiple Msg enabled\r
4028 *\r
4029 * Indicates that multiple message mode is enabled by software. Number\r
4030 * of messages enabled must not be greater than @ref multMsgCap\r
4031 *\r
4032 * <TABLE>\r
4033 * <TR><TH>@ref multMsgEn</TH><TH>Number of messages</TH></TR>\r
4034 * <TR><TD>0</TD> <TD>1</TD></TR>\r
4035 * <TR><TD>1</TD> <TD>2</TD></TR>\r
4036 * <TR><TD>2</TD> <TD>4</TD></TR>\r
4037 * <TR><TD>3</TD> <TD>8</TD></TR>\r
4038 * <TR><TD>4</TD> <TD>16</TD></TR>\r
4039 * <TR><TD>5</TD> <TD>32</TD></TR>\r
4040 * <TR><TD>others</TD> <TD>reserved</TD></TR>\r
4041 * </TABLE>\r
4042 *\r
4043 * Field size: 3 bits\r
4044 */\r
4045 uint8_t multMsgEn;\r
4046 /**\r
4047 * @brief [rw] Multipe Msg capable\r
4048 *\r
4049 * Multiple message capable.\r
4050 *\r
4051 * <TABLE>\r
4052 * <TR><TH>@ref multMsgCap</TH><TH>Number of messages</TH></TR>\r
4053 * <TR><TD>0</TD> <TD>1</TD></TR>\r
4054 * <TR><TD>1</TD> <TD>2</TD></TR>\r
4055 * <TR><TD>2</TD> <TD>4</TD></TR>\r
4056 * <TR><TD>3</TD> <TD>8</TD></TR>\r
4057 * <TR><TD>4</TD> <TD>16</TD></TR>\r
4058 * <TR><TD>5</TD> <TD>32</TD></TR>\r
4059 * <TR><TD>others</TD> <TD>reserved</TD></TR>\r
4060 * </TABLE>\r
4061 *\r
4062 * Field size: 3 bits\r
4063 */\r
4064 uint8_t multMsgCap;\r
4065 /**\r
4066 * @brief [rw] MSI enabled\r
4067 *\r
4068 * MSI Enabled. When set, INTx must be disabled.\r
4069 *\r
4070 * Field size: 1 bit\r
4071 */\r
4072 uint8_t msiEn;\r
4073 /**\r
4074 * @brief [rw] Next capability pointer\r
4075 *\r
4076 * By default, it points to PCI Express Capabilities structure.\r
4077 *\r
4078 * Field size: 8 bits\r
4079 */\r
4080 uint8_t nextCap;\r
4081 /**\r
4082 * @brief [ro] MSI capability ID\r
4083 *\r
4084 * Field size: 8 bits\r
4085 */\r
4086 uint8_t capId;\r
4087 } pcieMsiCapReg_t;\r
4088 /* @} */\r
4089 \r
4090 /**\r
4091 * @ingroup pcielld_reg_cfg_msi_structures\r
4092 * @brief Specification of the MSI lower 32 bits Register\r
4093 *\r
4094 * This register may be used for both endpoint and root complex modes.\r
4095 *\r
4096 * This register is only available for rev 0 hw.\r
4097 *\r
4098 * @{\r
4099 */\r
4100 typedef struct pcieMsiLo32Reg_s {\r
4101 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
4102 /**\r
4103 * @brief [rw] Lower 32bits address\r
4104 *\r
4105 * Field size: 30 bits\r
4106 *\r
4107 */\r
4108 uint32_t addr;\r
4109 } pcieMsiLo32Reg_t;\r
4110 /* @} */\r
4111 \r
4112 /**\r
4113 * @ingroup pcielld_reg_cfg_msi_structures\r
4114 * @brief Specification of the MSI upper 32 bits Register\r
4115 *\r
4116 * This register may be used for both endpoint and root complex modes.\r
4117 *\r
4118 * This register is only available for rev 0 hw.\r
4119 *\r
4120 * @{\r
4121 */\r
4122 typedef struct pcieMsiUp32Reg_s {\r
4123 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
4124 /**\r
4125 * @brief [rw] Upper 32bits address\r
4126 *\r
4127 * Field size: 32 bits\r
4128 *\r
4129 */\r
4130 uint32_t addr;\r
4131 } pcieMsiUp32Reg_t;\r
4132 /* @} */\r
4133 \r
4134 /**\r
4135 * @ingroup pcielld_reg_cfg_msi_structures\r
4136 * @brief Specification of the MSI Data Register\r
4137 *\r
4138 * This register may be used for both endpoint and root complex modes.\r
4139 *\r
4140 * This register is only available for rev 0 hw.\r
4141 *\r
4142 * @{\r
4143 */\r
4144 typedef struct pcieMsiDataReg_s {\r
4145 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
4146 /**\r
4147 * @brief [rw] MSI data\r
4148 *\r
4149 * Field size: 16 bits\r
4150 *\r
4151 */\r
4152 uint16_t data;\r
4153 } pcieMsiDataReg_t;\r
4154 /* @} */\r
4155 \r
4156 /*****************************************************************************\r
4157 ********** PCIe CAPABILITIES REGISTERS ************************************\r
4158 ****************************************************************************/\r
4159 /**\r
4160 * @ingroup pcielld_reg_cfg_cap_structures\r
4161 * @brief Specification of the PCI Express Capabilities Register\r
4162 *\r
4163 * This register may be used for both endpoint and root complex modes.\r
4164 *\r
4165 * On rev 0 hw, this corresponds to PCIE_CAP\r
4166 * On rev 1 hw, this corresponds to PCIE_CAP\r
4167 *\r
4168 * @{\r
4169 */\r
4170 typedef struct pciePciesCapReg_s {\r
4171 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
4172 /**\r
4173 * @brief [rw] Interrupt Message Number. Updated by hardware and writable through internal bus Interface.\r
4174 *\r
4175 * On rev 0 hw, this corresponds to INT_MSG\r
4176 * On rev 1 hw, this corresponds to IM_NUM\r
4177 *\r
4178 * Field size: 5 bits\r
4179 */\r
4180 uint8_t intMsg;\r
4181 /**\r
4182 * @brief [rw] Slot Implemented. Writable from internal bus interface.\r
4183 *\r
4184 * On rev 0 hw, this corresponds to SLT_IMPL_N\r
4185 * On rev 1 hw, this corresponds to SLOT\r
4186 *\r
4187 * Field size: 1 bit\r
4188 */\r
4189 uint8_t sltImplN;\r
4190 /**\r
4191 * @brief [rw] Device Port Type.\r
4192 *\r
4193 * 0 = EP type\n\r
4194 * 4h = RC type\n\r
4195 * Others = Reserved\r
4196 *\r
4197 * On rev 0 hw, this corresponds to DPORT_TYPE\r
4198 * On rev 1 hw, this corresponds to DEV_TYPE\r
4199 *\r
4200 * Field size: 4 bits\r
4201 */\r
4202 uint8_t dportType;\r
4203 /**\r
4204 * @brief [rw] PCI Express Capability Version\r
4205 *\r
4206 * On rev 0 hw, this corresponds to PCIE_CAP\r
4207 * On rev 1 hw, this corresponds to PCIE_VER\r
4208 *\r
4209 * Field size: 4 bits\r
4210 */\r
4211 uint8_t pcieCap;\r
4212 /**\r
4213 * @brief [rw] Next capability pointer. Writable from internal bus interface.\r
4214 *\r
4215 * On rev 0 hw, this corresponds to NEXT_CAP\r
4216 * On rev 1 hw, this corresponds to PCIE_NX_PTR\r
4217 *\r
4218 * Field size: 8 bits\r
4219 */\r
4220 uint8_t nextCap;\r
4221 /**\r
4222 * @brief [rw] PCIe Capability ID.\r
4223 *\r
4224 * On rev 0 hw, this corresponds to CAP_ID\r
4225 * On rev 1 hw, this corresponds to CAP_ID\r
4226 *\r
4227 * Field size: 8 bits\r
4228 */\r
4229 uint8_t capId;\r
4230 } pciePciesCapReg_t;\r
4231 /* @} */\r
4232 \r
4233 /**\r
4234 * @ingroup pcielld_reg_cfg_cap_structures\r
4235 * @brief Specification of the Device Capabilities Register\r
4236 *\r
4237 * This register may be used for both endpoint and root complex modes.\r
4238 *\r
4239 * On rev 0 hw, this corresponds to DEVICE_CAP\r
4240 * On rev 1 hw, this corresponds to DEV_CAP\r
4241 *\r
4242 * @{\r
4243 */\r
4244 typedef struct pcieDeviceCapReg_s {\r
4245 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
4246 /**\r
4247 * @brief [rw] Function Level Reset Capability\r
4248 *\r
4249 * used on EP only where it is rw. On RC reserved and should be 0\r
4250 *\r
4251 * On rev 0 hw, unsupported\r
4252 * On rev 1 hw, this corresponds to FLR_EN\r
4253 *\r
4254 * Field size: 1 bit\r
4255 */\r
4256 uint8_t flrEn;\r
4257 /**\r
4258 * @brief [rw] Captured Slot Power Limit Scale. For upstream ports (EP ports) only.\r
4259 *\r
4260 * On rev 0 hw, this corresponds to PWR_LIMIT_SCALE\r
4261 * On rev 1 hw, this corresponds to CAPT_SLOW_PWRLIMIT_SCALE\r
4262 *\r
4263 * Field size: 2 bits\r
4264 */\r
4265 uint8_t pwrLimitScale;\r
4266 /**\r
4267 * @brief [rw] Captured Slow Power Limit Value. For upstream ports (EP ports) only.\r
4268 *\r
4269 * On rev 0 hw, this corresponds to PWR_LIMIT_VALUE\r
4270 * On rev 1 hw, this corresponds to CAPT_SLOW_PWRLIMIT_VALUE\r
4271 *\r
4272 * Field size: 8 bits\r
4273 */\r
4274 uint8_t pwrLimitValue;\r
4275 /**\r
4276 * @brief [rw] Role-based Error Reporting. Writable from internal bus interface.\r
4277 *\r
4278 * On rev 0 hw, this corresponds to ERR_RPT\r
4279 * On rev 1 hw, this corresponds to ROLEBASED_ERRRPT\r
4280 *\r
4281 * Field size: 1 bit\r
4282 */\r
4283 uint8_t errRpt;\r
4284 /**\r
4285 * @brief [rw] Endpoint L1 Acceptable Latency. Must be 0 in RC mode. It is 3h for EP mode.\r
4286 *\r
4287 * On rev 0 hw, this corresponds to L1_LATENCY\r
4288 * On rev 1 hw, this corresponds to DEFAULT_EP_L1_LATENCY\r
4289 *\r
4290 * Field size: 3 bits\r
4291 */\r
4292 uint8_t l1Latency;\r
4293 /**\r
4294 * @brief [rw] Endpoint L0s Acceptable Latency. Must be 0 in RC mode. It is 4h for EP mode.\r
4295 *\r
4296 * On rev 0 hw, this corresponds to L0_LATENCY\r
4297 * On rev 1 hw, this corresponds to DEFAULT_EP_L0S_LATENCY\r
4298 *\r
4299 * Field size: 3 bits\r
4300 */\r
4301 uint8_t l0Latency;\r
4302 /**\r
4303 * @brief [rw] Extended Tag Field Supported. Writable from internal interface\r
4304 *\r
4305 * On rev 0 hw, this corresponds to EXT_TAG_FLD\r
4306 * On rev 1 hw, this corresponds to EXTTAGFIELD_SUPPORT\r
4307 *\r
4308 * Field size: 1 bit\r
4309 */\r
4310 uint8_t extTagFld;\r
4311 /**\r
4312 * @brief [rw] Phantom Field Supported. Writable from internal bus interface.\r
4313 *\r
4314 * On rev 0 hw, this corresponds to PHANTOM_FLD\r
4315 * On rev 1 hw, this corresponds to PHANTOMFUNC\r
4316 *\r
4317 * Field size: 2 bits\r
4318 */\r
4319 uint8_t phantomFld;\r
4320 /**\r
4321 * @brief [rw] Maximum Payload size supported. Writable from internal bus interface.\r
4322 *\r
4323 * On rev 0 hw, this corresponds to MAX_PAYLD_SZ\r
4324 * On rev 1 hw, this corresponds to MAX_PAYLOAD_SIZE\r
4325 *\r
4326 * Field size: 3 bits\r
4327 */\r
4328 uint8_t maxPayldSz;\r
4329 } pcieDeviceCapReg_t;\r
4330 /* @} */\r
4331 \r
4332 /**\r
4333 * @ingroup pcielld_reg_cfg_cap_structures\r
4334 * @brief Specification of the Device Status and Control Register\r
4335 *\r
4336 * This register may be used for both endpoint and root complex modes.\r
4337 *\r
4338 * On rev 0 hw, this corresponds to DEV_STAT_CTRL\r
4339 * On rev 1 hw, this corresponds to DEV_CAS\r
4340 *\r
4341 * @{\r
4342 */\r
4343 typedef struct pcieDevStatCtrlReg_s {\r
4344 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
4345 /**\r
4346 * @brief [ro] Transaction Pending\r
4347 *\r
4348 * On rev 0 hw, this corresponds to TPEND\r
4349 * On rev 1 hw, this corresponds to TRANS_PEND\r
4350 *\r
4351 * Field size: 1 bit\r
4352 */\r
4353 uint8_t tpend;\r
4354 /**\r
4355 * @brief [ro] Auxiliary Power Detected\r
4356 *\r
4357 * On rev 0 hw, this corresponds to AUX_PWR\r
4358 * On rev 1 hw, this corresponds to AUXP_DET\r
4359 *\r
4360 * Field size: 1 bit\r
4361 */\r
4362 uint8_t auxPwr;\r
4363 /**\r
4364 * @brief [rw] Unsupported Request Detected\r
4365 *\r
4366 * On rev 0 hw, this corresponds to UNSUP_RQ_DET\r
4367 * On rev 1 hw, this corresponds to UR_DET\r
4368 *\r
4369 * Field size: 1 bit\r
4370 */\r
4371 uint8_t rqDet;\r
4372 /**\r
4373 * @brief [rw] Fatal Error Detected\r
4374 *\r
4375 * On rev 0 hw, this corresponds to FATAL_ERR\r
4376 * On rev 1 hw, this corresponds to FT_DET\r
4377 *\r
4378 * Field size: 1 bit\r
4379 */\r
4380 uint8_t fatalEr;\r
4381 /**\r
4382 * @brief [rw] Non-fatal Error Detected\r
4383 *\r
4384 * On rev 0 hw, this corresponds to NFATAL_ERR\r
4385 * On rev 1 hw, this corresponds to NFT_DET\r
4386 *\r
4387 * Field size: 1 bit\r
4388 */\r
4389 uint8_t nFatalEr;\r
4390 /**\r
4391 * @brief [rw] Correctable Error Detected\r
4392 *\r
4393 * On rev 0 hw, this corresponds to CORR_ERR\r
4394 * On rev 1 hw, this corresponds to COR_DET\r
4395 *\r
4396 * Field size: 1 bit\r
4397 */\r
4398 uint8_t corrEr;\r
4399 /**\r
4400 * @brief [rw] Maximum Read Request Size\r
4401 *\r
4402 * On rev 0 hw, this corresponds to MAX_REQ_SZ\r
4403 * On rev 1 hw, this corresponds to MRRS\r
4404 *\r
4405 * Field size: 3 bits\r
4406 */\r
4407 uint8_t maxSz;\r
4408 /**\r
4409 * @brief [rw] Enable no snoop\r
4410 *\r
4411 * On rev 0 hw, this corresponds to NO_SNOOP\r
4412 * On rev 1 hw, this corresponds to NOSNP_EN\r
4413 *\r
4414 * Field size: 1 bit\r
4415 */\r
4416 uint8_t noSnoop;\r
4417 /**\r
4418 * @brief [rw] AUX Power PM Enable\r
4419 *\r
4420 * On rev 0 hw, this corresponds to AUX_PWR_PM_EN\r
4421 * On rev 1 hw, this corresponds to AUXPM_EN\r
4422 *\r
4423 * Field size: 1 bit\r
4424 */\r
4425 uint8_t auxPwrEn;\r
4426 /**\r
4427 * @brief [rw] Phantom Function Enable\r
4428 *\r
4429 * On rev 0 hw, this corresponds to PHANTOM_EN\r
4430 * On rev 1 hw, this corresponds to PHFUN_EN\r
4431 *\r
4432 * Field size: 1 bit\r
4433 */\r
4434 uint8_t phantomEn;\r
4435 /**\r
4436 * @brief [rw] Extended Tag Field Enable\r
4437 *\r
4438 * On rev 0 hw, this corresponds to XTAG_FIELD_EN\r
4439 * On rev 1 hw, this corresponds to EXTAG_EN\r
4440 *\r
4441 * Field size: 1 bit\r
4442 */\r
4443 uint8_t xtagEn;\r
4444 /**\r
4445 * @brief [rw] Maximum Payload Size\r
4446 *\r
4447 * On rev 0 hw, this corresponds to MAX_PAYLD\r
4448 * On rev 1 hw, this corresponds to MPS\r
4449 *\r
4450 * Field size: 3 bits\r
4451 */\r
4452 uint8_t maxPayld;\r
4453 /**\r
4454 * @brief [rw] Enable Relaxed Ordering\r
4455 *\r
4456 * On rev 0 hw, this corresponds to RELAXED\r
4457 * On rev 1 hw, this corresponds to EN_RO\r
4458 *\r
4459 * Field size: 1 bit\r
4460 */\r
4461 uint8_t relaxed;\r
4462 /**\r
4463 * @brief [rw] Enable Unsupported Request Reporting\r
4464 *\r
4465 * On rev 0 hw, this corresponds to UNSUP_REQ_RP\r
4466 * On rev 1 hw, this corresponds to UR_RE\r
4467 *\r
4468 * Field size: 1 bit\r
4469 */\r
4470 uint8_t reqRp;\r
4471 /**\r
4472 * @brief [rw] Fatal Error Reporting Enable\r
4473 *\r
4474 * On rev 0 hw, this corresponds to FATAL_ERR_RP\r
4475 * On rev 1 hw, this corresponds to FT_RE\r
4476 *\r
4477 * Field size: 1 bit\r
4478 */\r
4479 uint8_t fatalErRp;\r
4480 /**\r
4481 * @brief [rw] Non-fatal Error Reporting Enable\r
4482 *\r
4483 * On rev 0 hw, this corresponds to NFATAL_ERR_RP\r
4484 * On rev 1 hw, this corresponds to NFT_RE\r
4485 *\r
4486 * Field size: 1 bit\r
4487 */\r
4488 uint8_t nFatalErRp;\r
4489 /**\r
4490 * @brief [rw] Correctable Error Reporting Enable\r
4491 *\r
4492 * On rev 0 hw, this corresponds to CORR_ERR_RP\r
4493 * On rev 1 hw, this corresponds to COR_RE\r
4494 *\r
4495 * Field size: 1 bit\r
4496 */\r
4497 uint8_t corErRp;\r
4498 } pcieDevStatCtrlReg_t;\r
4499 /* @} */\r
4500 \r
4501 /**\r
4502 * @ingroup pcielld_reg_cfg_cap_structures\r
4503 * @brief Specification of the Link Capabilities Register\r
4504 *\r
4505 * This register may be used for both endpoint and root complex modes.\r
4506 *\r
4507 * On rev 0 hw, this corresponds to LINK_CAP\r
4508 * On rev 1 hw, this corresponds to LNK_CAP\r
4509 *\r
4510 * @{\r
4511 */\r
4512 typedef struct pcieLinkCapReg_s {\r
4513 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
4514 /**\r
4515 * @brief [rw] Port Number. Writable from internal bus interface.\r
4516 *\r
4517 * On rev 0 hw, this corresponds to PORT_NUM\r
4518 * On rev 1 hw, this corresponds to PORT_NUM\r
4519 *\r
4520 * Field size: 8 bits\r
4521 */\r
4522 uint8_t portNum;\r
4523 /**\r
4524 * @brief [rw] ASPM Optionality Compliance\r
4525 *\r
4526 * On rev 0 hw, unsuppported\r
4527 * On rev 1 hw, this corresponds to ASPM_OPT_COMP\r
4528 *\r
4529 * Field size: 1 bit\r
4530 */\r
4531 uint8_t aspmOptComp;\r
4532 /**\r
4533 * @brief [rw] Bandwidth Notification Capable.\r
4534 *\r
4535 * 0 = For upstream ports (EP ports)\n\r
4536 * 1 = For downstream ports (RC ports)\r
4537 *\r
4538 * On rev 0 hw, this corresponds to BW_NOTIFY_CAP\r
4539 * On rev 1 hw, this corresponds to LNK_BW_NOT_CAP\r
4540 *\r
4541 * Field size: 1 bit\r
4542 */\r
4543 uint8_t bwNotifyCap;\r
4544 /**\r
4545 * @brief [rw] Link Layer Active Reporting Capable.\r
4546 *\r
4547 * 0 = For upstream ports (EP ports)\n\r
4548 * 1 = For downstream ports (RC ports)\r
4549 *\r
4550 * On rev 0 hw, this corresponds to DLL_REP_CAP\r
4551 * On rev 1 hw, this corresponds to DLL_ACTRPT_CAP\r
4552 *\r
4553 * Field size: 1 bit\r
4554 */\r
4555 uint8_t dllRepCap;\r
4556 /**\r
4557 * @brief [rw] Surprise Down Error Reporting Capable. Not supported. Always zero.\r
4558 *\r
4559 * On rev 0 hw, this corresponds to DOWN_ERR_REP_CAP\r
4560 * On rev 1 hw, this corresponds to UNSUP\r
4561 *\r
4562 * Field size: 1 bit\r
4563 */\r
4564 uint8_t downErrRepCap;\r
4565 /**\r
4566 * @brief [rw] Clock Power Management. Writable from internal bus interface.\r
4567 *\r
4568 * For upstream ports (EP Ports), a value of 1h in this bit indicates that\r
4569 * the component tolerates the removal of any reference clock(s) in the L1\r
4570 * and L2/L3 Ready Link states. A value of 0 indicates the reference\r
4571 * clock(s) must not be removed in these Link states.\r
4572 *\r
4573 * For downstream ports (RC Ports), this bit is always 0.\r
4574 *\r
4575 * On rev 0 hw, this corresponds to CLK_PWR_MGMT\r
4576 * On rev 1 hw, this corresponds to CLK_PWR_MGMT\r
4577 *\r
4578 * Field size: 1 bit\r
4579 */\r
4580 uint8_t clkPwrMgmt;\r
4581 /**\r
4582 * @brief [rw] L1 Exit Latency when common clock is used. Writable from internal bus interface.\r
4583 *\r
4584 * <TABLE>\r
4585 * <TR><TH>@ref l1ExitLat</TH><TH>low range</TH><TH>high range</TH></TR>\r
4586 * <TR><TD>0</TD> <TD>0</TD> <TD>64 ns</TD></TR>\r
4587 * <TR><TD>1</TD> <TD>64ns</TD> <TD>128ns</TD></TR>\r
4588 * <TR><TD>2</TD> <TD>128ns</TD> <TD>256ns</TD></TR>\r
4589 * <TR><TD>3</TD> <TD>256ns</TD> <TD>512ns</TD></TR>\r
4590 * <TR><TD>4</TD> <TD>512ns</TD> <TD>1µs</TD></TR>\r
4591 * <TR><TD>5</TD> <TD>1µs</TD> <TD>2µs</TD></TR>\r
4592 * <TR><TD>6</TD> <TD>2µs</TD> <TD>4µs</TD></TR>\r
4593 * <TR><TD>7</TD> <TD>4µs</TD> <TD>and up</TD></TR>\r
4594 * </TABLE>\r
4595 *\r
4596 * On rev 0 hw, this corresponds to L1_EXIT_LAT\r
4597 * On rev 1 hw, this corresponds to L1_EXIT_LAT\r
4598 *\r
4599 * Field size: 3 bits\r
4600 */\r
4601 uint8_t l1ExitLat;\r
4602 /**\r
4603 * @brief [rw] L0s Exit Latency. Writable from internal bus interface.\r
4604 *\r
4605 * <TABLE>\r
4606 * <TR><TH>@ref l1ExitLat</TH><TH>low range</TH><TH>high range</TH></TR>\r
4607 * <TR><TD>0</TD> <TD>0</TD> <TD>64 ns</TD></TR>\r
4608 * <TR><TD>1</TD> <TD>64ns</TD> <TD>128ns</TD></TR>\r
4609 * <TR><TD>2</TD> <TD>128ns</TD> <TD>256ns</TD></TR>\r
4610 * <TR><TD>3</TD> <TD>256ns</TD> <TD>512ns</TD></TR>\r
4611 * <TR><TD>4</TD> <TD>512ns</TD> <TD>1µs</TD></TR>\r
4612 * <TR><TD>5</TD> <TD>1µs</TD> <TD>2µs</TD></TR>\r
4613 * <TR><TD>6</TD> <TD>2µs</TD> <TD>4µs</TD></TR>\r
4614 * <TR><TD>7</TD> <TD>4µs</TD> <TD>and up</TD></TR>\r
4615 * </TABLE>\r
4616 *\r
4617 * On rev 0 hw, this corresponds to L0S_EXIT_LAT\r
4618 * On rev 1 hw, this corresponds to L0S_EXIT_LAT\r
4619 *\r
4620 * Field size: 3 bits\r
4621 */\r
4622 uint8_t losExitLat;\r
4623 /**\r
4624 * @brief [rw] Active State Link Power Management Support. Writable from internal bus interface.\r
4625 *\r
4626 * 1h = L0s entry supported.\n\r
4627 * 3h = L0s and L1 supported.\n\r
4628 * Others = Reserved.\r
4629 *\r
4630 * On rev 0 hw, this corresponds to AS_LINK_PM\r
4631 * On rev 1 hw, this corresponds to AS_LINK_PM_SUPPORT\r
4632 *\r
4633 * Field size: 2 bits\r
4634 */\r
4635 uint8_t asLinkPm;\r
4636 /**\r
4637 * @brief [rw] Maximum Link Width. Writable from internal bus interface.\r
4638 *\r
4639 * 1h = ×1\n\r
4640 * 2h = ×2\n\r
4641 * Others = Reserved.\r
4642 *\r
4643 * On rev 0 hw, this corresponds to MAX_LINK_WIDTH\r
4644 * On rev 1 hw, this corresponds to MAX_LINK_WIDTH\r
4645 *\r
4646 * Field size: 6 bits\r
4647 */\r
4648 uint8_t maxLinkWidth;\r
4649 /**\r
4650 * @brief [rw] Maximum Link Speed. Writable from internal bus interface.\r
4651 *\r
4652 * 1h = 2.5GT/s Link speed supported.\n\r
4653 * 2h = 5.0 GT/s and 2.5 GT/s Link speeds supported.\n\r
4654 * Others = Reserved.\r
4655 *\r
4656 * On rev 0 hw, this corresponds to MAX_LINK_SPEED\r
4657 * On rev 1 hw, this corresponds to MAX_LINK_SPEEDS\r
4658 *\r
4659 * Field size: 4 bits\r
4660 */\r
4661 uint8_t maxLinkSpeed;\r
4662 } pcieLinkCapReg_t;\r
4663 /* @} */\r
4664 \r
4665 /**\r
4666 * @ingroup pcielld_reg_cfg_cap_structures\r
4667 * @brief Specification of the Link Status and Control Register\r
4668 *\r
4669 * This register may be used for both endpoint and root complex modes.\r
4670 *\r
4671 * On rev 0 hw, this corresponds to LINK_STAT_CTRL\r
4672 * On rev 1 hw, this corresponds to LNK_CAS\r
4673 *\r
4674 * @{\r
4675 */\r
4676 typedef struct pcieLinkStatCtrlReg_s {\r
4677 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
4678 /**\r
4679 * @brief [rw] Link Autonomous Bandwidth Status.\r
4680 *\r
4681 * This bit is Set by hardware to indicate that hardware has autonomously\r
4682 * changed Link speed or width, without the Port transitioning through\r
4683 * DL_Down status, for reasons other than to attempt to correct unreliable\r
4684 * Link operation. This bit must be set if the Physical Layer reports a\r
4685 * speed or width change was initiated by the downstream component that\r
4686 * was indicated as an autonomous change.\r
4687 *\r
4688 * Not applicable and reserved for EP.\r
4689 *\r
4690 * On rev 0 hw, this corresponds to LINK_BW_STATUS\r
4691 * On rev 1 hw, this corresponds to LAB_STATUS\r
4692 *\r
4693 * Field size: 1 bit\r
4694 */\r
4695 uint8_t linkBwStatus;\r
4696 /**\r
4697 * @brief [rw] Link Bandwidth Management Status.\r
4698 *\r
4699 * This bit is Set by hardware to indicate that either of the following\r
4700 * has occurred without the Port transitioning through DL_Down status:\r
4701 *\r
4702 * - A Link retraining has completed following a write of 1b to the\r
4703 * Retrain Link bit\r
4704 * - Hardware has changed Link speed or width to attempt to correct\r
4705 * unreliable Link operation, either through an LTSSM timeout or\r
4706 * a higher level process.\r
4707 *\r
4708 * This bit must be set if the Physical Layer reports a speed or width\r
4709 * change was initiated by the downstream component that was not\r
4710 * indicated as an autonomous change.\r
4711 *\r
4712 * Not applicable and reserved for EP.\r
4713 *\r
4714 * On rev 0 hw, this corresponds to LINK_BW_MGMT_STATUS\r
4715 * On rev 1 hw, this corresponds to LBW_STATUS\r
4716 *\r
4717 * Field size: 1 bit\r
4718 */\r
4719 uint8_t linkBwMgmtStatus;\r
4720 /**\r
4721 * @brief [rw] Data Link Layer Active\r
4722 *\r
4723 * This bit indicates the status of the Data Link Control and\r
4724 * Management State Machine. It returns a 1 to indicate the DL_Active state,\r
4725 * 0 otherwise.\r
4726 *\r
4727 * On rev 0 hw, this corresponds to DLL_ACTIVE\r
4728 * On rev 1 hw, this corresponds to DLL_ACT\r
4729 *\r
4730 * Field size: 1 bit\r
4731 */\r
4732 uint8_t dllActive;\r
4733 /**\r
4734 * @brief [rw] Slot Clock Configuration. Writable from internal bus interface.\r
4735 *\r
4736 * This bit indicates that the component uses the same\r
4737 * physical reference clock that the platform provides on the connector.\r
4738 *\r
4739 * On rev 0 hw, this corresponds to SLOT_CLK_CFG\r
4740 * On rev 1 hw, this corresponds to SLOT_CLK_CONFIG\r
4741 *\r
4742 * Field size: 1 bit\r
4743 */\r
4744 uint8_t slotClkCfg;\r
4745 /**\r
4746 * @brief [rw] Link Training. Not applicable to EP.\r
4747 *\r
4748 * On rev 0 hw, this corresponds to LINK_TRAINING\r
4749 * On rev 1 hw, this corresponds to LINK_TRAIN\r
4750 *\r
4751 * Field size: 1 bit\r
4752 */\r
4753 uint8_t linkTraining;\r
4754 /**\r
4755 * @brief [rw] Undefined for PCI Express.\r
4756 *\r
4757 * Field size: 1 bit\r
4758 */\r
4759 uint8_t undef;\r
4760 /**\r
4761 * @brief [rw] Negotiated Link Width. Set automatically by hardware after link initialization.\r
4762 *\r
4763 * On rev 0 hw, this corresponds to NEGOTIATED_LINK_WD\r
4764 * On rev 1 hw, this corresponds to NEG_LW\r
4765 *\r
4766 * Field size: 6 bits\r
4767 */\r
4768 uint8_t negotiatedLinkWd;\r
4769 /**\r
4770 * @brief [rw] Link Speed. Set automatically by hardware after link initialization.\r
4771 *\r
4772 * On rev 0 hw, this corresponds to LINK_SPEED\r
4773 * On rev 1 hw, this corresponds to LINK_SPEED\r
4774 *\r
4775 * Field size: 4 bits\r
4776 */\r
4777 uint8_t linkSpeed;\r
4778 /**\r
4779 * @brief [rw] Link Autonomous Bandwidth Interrupt Enable. Not applicable and is reserved for EP\r
4780 *\r
4781 * On rev 0 hw, this corresponds to LINK_BW_INT_EN\r
4782 * On rev 1 hw, this corresponds to LABIE\r
4783 *\r
4784 * Field size: 1 bit\r
4785 */\r
4786 uint8_t linkBwIntEn;\r
4787 /**\r
4788 * @brief [rw] Link Bandwidth Management Interrupt Enable. Not applicable and is reserved for EP.\r
4789 *\r
4790 * On rev 0 hw, this corresponds to LINK_BW_MGMT_INT_EN\r
4791 * On rev 1 hw, this corresponds to LBMIE\r
4792 *\r
4793 * Field size: 1 bit\r
4794 */\r
4795 uint8_t linkBwMgmtIntEn;\r
4796 /**\r
4797 * @brief [rw] Hardware Autonomous Width Disable. Not supported and hardwired to zero.\r
4798 *\r
4799 * On rev 0 hw, this corresponds to HW_AUTO_WIDTH_DIS\r
4800 * On rev 1 hw, this corresponds to HAWD\r
4801 *\r
4802 * Field size: 1 bit\r
4803 */\r
4804 uint8_t hwAutoWidthDis;\r
4805 /**\r
4806 * @brief [rw] Enable Clock Power Management.\r
4807 *\r
4808 * On rev 0 hw, this corresponds to CLK_PWR_MGMT_EN\r
4809 * On rev 1 hw, this corresponds to EN_CPM\r
4810 *\r
4811 * Field size: 1 bit\r
4812 */\r
4813 uint8_t clkPwrMgmtEn;\r
4814 /**\r
4815 * @brief [rw] Extended Synchronization.\r
4816 *\r
4817 * On rev 0 hw, this corresponds to EXT_SYNC\r
4818 * On rev 1 hw, this corresponds to EXT_SYN\r
4819 *\r
4820 * Field size: 1 bit\r
4821 */\r
4822 uint8_t extSync;\r
4823 /**\r
4824 * @brief [rw] Common Clock Configuration.\r
4825 *\r
4826 * 0 = Indicates that this device and the device at the opposite end of the\r
4827 * link are operating with separate reference clock sources.\n\r
4828 * 1 = Indicates that this device and the device at the opposite end of the\r
4829 * link are operating with a common clock source.\r
4830 *\r
4831 * On rev 0 hw, this corresponds to COMMON_CLK_CFG\r
4832 * On rev 1 hw, this corresponds to COM_CLK_CFG\r
4833 *\r
4834 * Field size: 1 bit\r
4835 */\r
4836 uint8_t commonClkCfg;\r
4837 /**\r
4838 * @brief [rw] Retrain Link. Not applicable and reserved for EP.\r
4839 *\r
4840 * On rev 0 hw, this corresponds to RETRAIN_LINK\r
4841 * On rev 1 hw, this corresponds to RETRAIN_LINK\r
4842 *\r
4843 * Field size: 1 bit\r
4844 */\r
4845 uint8_t retrainLink;\r
4846 /**\r
4847 * @brief [rw] Disables the link by directing the LTSSM to the Disabled state when set.\r
4848 *\r
4849 * On rev 0 hw, this corresponds to LINK_DISABLE\r
4850 * On rev 1 hw, this corresponds to LINK_DIS\r
4851 *\r
4852 * Field size: 1 bit\r
4853 */\r
4854 uint8_t linkDisable;\r
4855 /**\r
4856 * @brief [rw] Read Completion Boundary.\r
4857 *\r
4858 * 0 = 64 bytes\n\r
4859 * 1 = 128 bytes\r
4860 *\r
4861 * On rev 0 hw, this corresponds to RCB\r
4862 * On rev 1 hw, this corresponds to RCB\r
4863 *\r
4864 * Field size: 1 bit\r
4865 */\r
4866 uint8_t rcb;\r
4867 /**\r
4868 * @brief [rw] Active State Link Power Management Control\r
4869 *\r
4870 * 0 = Disabled.\n\r
4871 * 1h = L0s entry enabled.\n\r
4872 * 2h = L1 entry enabled.\n\r
4873 * 3h = L0s and L1 entry enabled.\n\r
4874 *\r
4875 * On rev 0 hw, this corresponds to ACTIVE_LINK_PM\r
4876 * On rev 1 hw, this corresponds to ASPM_CTRL\r
4877 *\r
4878 * Field size: 2 bits\r
4879 */\r
4880 uint8_t activeLinkPm;\r
4881 } pcieLinkStatCtrlReg_t;\r
4882 /* @} */\r
4883 \r
4884 /**\r
4885 * @ingroup pcielld_reg_cfg_cap_structures\r
4886 * @brief Specification of the Slot Capabilities register\r
4887 *\r
4888 * This register may only be used for root complex mode.\r
4889 *\r
4890 * On rev 0 hw, this corresponds to SLOT_CAP\r
4891 * On rev 1 hw, this corresponds to SLOT_CAP\r
4892 *\r
4893 * @{\r
4894 */\r
4895 typedef struct pcieSlotCapReg_s {\r
4896 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
4897 /**\r
4898 * @brief [rw] Physical Slot Number.\r
4899 *\r
4900 * On rev 0 hw, this corresponds to SLOT_NUM\r
4901 * On rev 1 hw, this corresponds to PSN\r
4902 *\r
4903 * Field size: 13 bits [0-0x1FFF]\r
4904 */\r
4905 uint16_t slotNum;\r
4906 /**\r
4907 * @brief [rw] No Command Complete Support\r
4908 *\r
4909 * When Set, this bit indicates that this slot does not generate software\r
4910 * notification when an issued command is completed by the Hot-Plug Controller\r
4911 *\r
4912 * On rev 0 hw, this corresponds to CMD_COMP_SUPP\r
4913 * On rev 1 hw, this corresponds to NCCS\r
4914 *\r
4915 * Field size: 1 bit\r
4916 */\r
4917 uint8_t cmdCompSupp;\r
4918 /**\r
4919 * @brief [rw] Electromechanical Interlock Present.\r
4920 *\r
4921 * When Set, this bit indicates that an Electromechanical Interlock\r
4922 * is implemented on the chassis for this slot.\r
4923 *\r
4924 * On rev 0 hw, this corresponds to EML_PRESENT\r
4925 * On rev 1 hw, this corresponds to EIP\r
4926 *\r
4927 * Field size: 1 bit\r
4928 */\r
4929 uint8_t emlPresent;\r
4930 /**\r
4931 * @brief [rw] Slot Power Limit Scale.\r
4932 *\r
4933 * On rev 0 hw, this corresponds to PWR_LMT_SCALE\r
4934 * On rev 1 hw, this corresponds to SPLS\r
4935 *\r
4936 * Field size: 2 bits\r
4937 */\r
4938 uint8_t pwrLmtScale;\r
4939 /**\r
4940 * @brief [rw] Slot Power Limit Value.\r
4941 *\r
4942 * On rev 0 hw, this corresponds to PWR_LMT_VALUE\r
4943 * On rev 1 hw, this corresponds to SPLV\r
4944 *\r
4945 * Field size: 8 bits\r
4946 */\r
4947 uint8_t pwrLmtValue;\r
4948 /**\r
4949 * @brief [rw] Hot Plug Capable.\r
4950 *\r
4951 * On rev 0 hw, this corresponds to HP_CAP\r
4952 * On rev 1 hw, this corresponds to HPC\r
4953 *\r
4954 * Field size: 1 bit\r
4955 */\r
4956 uint8_t hpCap;\r
4957 /**\r
4958 * @brief [rw] Hot Plug Surprise.\r
4959 *\r
4960 * On rev 0 hw, this corresponds to HP_SURPRISE\r
4961 * On rev 1 hw, this corresponds to HPS\r
4962 *\r
4963 * Field size: 1 bit\r
4964 */\r
4965 uint8_t hpSurprise;\r
4966 /**\r
4967 * @brief [rw] Power Indicator Present.\r
4968 *\r
4969 * On rev 0 hw, this corresponds to PWR_IND\r
4970 * On rev 1 hw, this corresponds to PIP\r
4971 *\r
4972 * Field size: 1 bit\r
4973 */\r
4974 uint8_t pwrInd;\r
4975 /**\r
4976 * @brief [rw] Attention Indicator Present.\r
4977 *\r
4978 * On rev 0 hw, this corresponds to ATTN_IND\r
4979 * On rev 1 hw, this corresponds to AIP\r
4980 *\r
4981 * Field size: 1 bit\r
4982 */\r
4983 uint8_t attnInd;\r
4984 /**\r
4985 * @brief [rw] MRL Sensor Present.\r
4986 *\r
4987 * On rev 0 hw, this corresponds to MRL_SENSOR\r
4988 * On rev 1 hw, this corresponds to MRLSP\r
4989 *\r
4990 * Field size: 1 bit\r
4991 */\r
4992 uint8_t mrlSensor;\r
4993 /**\r
4994 * @brief [rw] Power Controller Present.\r
4995 *\r
4996 * If there is no power controller, software must ensure that system power\r
4997 * is up before reading Presence Detect state\r
4998 *\r
4999 * On rev 0 hw, this corresponds to PWR_CTL\r
5000 * On rev 1 hw, this corresponds to PCP\r
5001 *\r
5002 * Field size: 1 bit\r
5003 */\r
5004 uint8_t pwrCtl;\r
5005 /**\r
5006 * @brief [rw] Attention Indicator Present.\r
5007 *\r
5008 * On rev 0 hw, this corresponds to ATTN_BUTTON\r
5009 * On rev 1 hw, this corresponds to ABP\r
5010 *\r
5011 * Field size: 1 bit\r
5012 */\r
5013 uint8_t attnButton;\r
5014 } pcieSlotCapReg_t;\r
5015 /* @} */\r
5016 \r
5017 /**\r
5018 * @ingroup pcielld_reg_cfg_cap_structures\r
5019 * @brief Specification of the Slot Status and Control register\r
5020 *\r
5021 * This register may only be used for root complex mode.\r
5022 *\r
5023 * On rev 0 hw, this corresponds to SLOT_STAT_CTRL\r
5024 * On rev 1 hw, this corresponds to SLOT_CAS\r
5025 *\r
5026 * @{\r
5027 */\r
5028 typedef struct pcieSlotStatCtrlReg_s {\r
5029 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5030 /**\r
5031 * @brief [rw] Data Link Layer State Changed\r
5032 *\r
5033 * Write 1 to clear.\r
5034 *\r
5035 * On rev 0 hw, this corresponds to DLL_STATE\r
5036 * On rev 1 hw, this corresponds to DSC\r
5037 *\r
5038 * Field size: 1 bit\r
5039 */\r
5040 uint8_t dllState;\r
5041 /**\r
5042 * @brief [ro] Electromechanical Lock Status\r
5043 *\r
5044 * On rev 0 hw, this corresponds to EM_LOCK\r
5045 * On rev 1 hw, this corresponds to EIS\r
5046 *\r
5047 * Field size: 1 bit\r
5048 */\r
5049 uint8_t emLock;\r
5050 /**\r
5051 * @brief [ro] Presence Detect State\r
5052 *\r
5053 * On rev 0 hw, this corresponds to PRESENCE_DET\r
5054 * On rev 1 hw, this corresponds to PDS\r
5055 *\r
5056 * Field size: 1 bit\r
5057 */\r
5058 uint8_t presenceDet;\r
5059 /**\r
5060 * @brief [ro] MRL Sensor State\r
5061 *\r
5062 * On rev 0 hw, this corresponds to MRL_STATE\r
5063 * On rev 1 hw, this corresponds to MRLSS\r
5064 *\r
5065 * Field size: 1 bit\r
5066 */\r
5067 uint8_t mrlState;\r
5068 /**\r
5069 * @brief [rw] Command Completed\r
5070 *\r
5071 * Write 1 to clear.\r
5072 *\r
5073 * On rev 0 hw, this corresponds to CMD_COMPLETE\r
5074 * On rev 1 hw, this corresponds to CC\r
5075 *\r
5076 * Field size: 1 bit\r
5077 */\r
5078 uint8_t cmdComplete;\r
5079 /**\r
5080 * @brief [rw] Presence Detect Changed\r
5081 *\r
5082 * Write 1 to clear.\r
5083 *\r
5084 * On rev 0 hw, this corresponds to PRESENCE_CHG\r
5085 * On rev 1 hw, this corresponds to PDC\r
5086 *\r
5087 * Field size: 1 bit\r
5088 */\r
5089 uint8_t presenceChg;\r
5090 /**\r
5091 * @brief [rw] MRL Sensor Changed\r
5092 *\r
5093 * Write 1 to clear.\r
5094 *\r
5095 * On rev 0 hw, this corresponds to MRL_CHANGE\r
5096 * On rev 1 hw, this corresponds to MRCSC\r
5097 *\r
5098 * Field size: 1 bit\r
5099 */\r
5100 uint8_t mrlChange;\r
5101 /**\r
5102 * @brief [rw] Power Fault Detected\r
5103 *\r
5104 * Write 1 to clear.\r
5105 *\r
5106 * On rev 0 hw, this corresponds to PWR_FAULT\r
5107 * On rev 1 hw, this corresponds to PFD\r
5108 *\r
5109 * Field size: 1 bit\r
5110 */\r
5111 uint8_t pwrFault;\r
5112 /**\r
5113 * @brief [rw] Attention Button Pressed.\r
5114 *\r
5115 * Write 1 to clear.\r
5116 *\r
5117 * On rev 0 hw, this corresponds to ATTN_PRESSED\r
5118 * On rev 1 hw, this corresponds to ABP\r
5119 *\r
5120 * Field size: 1 bit\r
5121 */\r
5122 uint8_t attnPressed;\r
5123 /**\r
5124 * @brief [rw] Data Link Layer State Changed Enable.\r
5125 *\r
5126 * On rev 0 hw, this corresponds to DLL_CHG_EN\r
5127 * On rev 1 hw, this corresponds to DSC_EN\r
5128 *\r
5129 * Field size: 1 bit\r
5130 */\r
5131 uint8_t dllChgEn;\r
5132 /**\r
5133 * @brief [rw] Electromechanical Interlock Control.\r
5134 *\r
5135 * On rev 0 hw, this corresponds to EM_LOCK_CTL\r
5136 * On rev 1 hw, this corresponds to EIC\r
5137 *\r
5138 * Field size: 1 bit\r
5139 */\r
5140 uint8_t emLockCtl;\r
5141 /**\r
5142 * @brief [rw] Power Controller Control\r
5143 *\r
5144 * On rev 0 hw, this corresponds to PM_CTL\r
5145 * On rev 1 hw, this corresponds to PCC\r
5146 *\r
5147 * Field size: 1 bit\r
5148 */\r
5149 uint8_t pmCtl;\r
5150 /**\r
5151 * @brief [rw] Power Indicator Control\r
5152 *\r
5153 * On rev 0 hw, this corresponds to PM_IND_CTL\r
5154 * On rev 1 hw, this corresponds to PIC\r
5155 *\r
5156 * Field size: 2 bits\r
5157 */\r
5158 uint8_t pmIndCtl;\r
5159 /**\r
5160 * @brief [rw] Attention Indicator Control.\r
5161 *\r
5162 * On rev 0 hw, this corresponds to ATTN_IND_CTL\r
5163 * On rev 1 hw, this corresponds to AIC\r
5164 *\r
5165 * Field size: 2 bits\r
5166 */\r
5167 uint8_t attnIndCtl;\r
5168 /**\r
5169 * @brief [rw] Hot Plug Interrupt Enable.\r
5170 *\r
5171 * On rev 0 hw, this corresponds to HP_INT_EN\r
5172 * On rev 1 hw, this corresponds to HPI_EN\r
5173 *\r
5174 * Field size: 1 bit\r
5175 */\r
5176 uint8_t hpIntEn;\r
5177 /**\r
5178 * @brief [rw] Command Completed Interrupt Enable.\r
5179 *\r
5180 * On rev 0 hw, this corresponds to CMD_CMP_INT_EN\r
5181 * On rev 1 hw, this corresponds to CCI_EN\r
5182 *\r
5183 * Field size: 1 bit\r
5184 */\r
5185 uint8_t cmdCmpIntEn;\r
5186 /**\r
5187 * @brief [rw] Presence Detect Changed Enable.\r
5188 *\r
5189 * On rev 0 hw, this corresponds to PRS_DET_CHG_EN\r
5190 * On rev 1 hw, this corresponds to PDC_EN\r
5191 *\r
5192 * Field size: 1 bit\r
5193 */\r
5194 uint8_t prsDetChgEn;\r
5195 /**\r
5196 * @brief [rw] MRL Sensor Changed Enable.\r
5197 *\r
5198 * On rev 0 hw, this corresponds to MRL_CHG_EN\r
5199 * On rev 1 hw, this corresponds to MRLSC_EN\r
5200 *\r
5201 * Field size: 1 bit\r
5202 */\r
5203 uint8_t mrlChgEn;\r
5204 /**\r
5205 * @brief [rw] Power Fault Detected Enable.\r
5206 *\r
5207 * On rev 0 hw, this corresponds to PWR_FLT_DET_EN\r
5208 * On rev 1 hw, this corresponds to PFD_EN\r
5209 *\r
5210 * Field size: 1 bit\r
5211 */\r
5212 uint8_t pwrFltDetEn;\r
5213 /**\r
5214 * @brief [rw] Attention Button Pressed Enable.\r
5215 *\r
5216 * On rev 0 hw, this corresponds to ATTN_BUTT_EN\r
5217 * On rev 1 hw, this corresponds to ABP_EN\r
5218 *\r
5219 * Field size: 1 bit\r
5220 */\r
5221 uint8_t attnButtEn;\r
5222 } pcieSlotStatCtrlReg_t;\r
5223 /* @} */\r
5224 \r
5225 /**\r
5226 * @ingroup pcielld_reg_cfg_cap_structures\r
5227 * @brief Specification of the Root Control and Capabilities Register\r
5228 *\r
5229 * This register may only be used for root complex mode.\r
5230 *\r
5231 * On rev 0 hw, this corresponds to ROOT_CTRL_CAP\r
5232 * On rev 1 hw, this corresponds to ROOT_CAC\r
5233 *\r
5234 * @{\r
5235 */\r
5236 typedef struct pcieRootCtrlCapReg_s {\r
5237 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5238 /**\r
5239 * @brief [ro] CRS Software Visibility. Not supported and set to 0.\r
5240 *\r
5241 * On rev 0 hw, this corresponds to CRS_SW\r
5242 * On rev 1 hw, this corresponds to CRSSV\r
5243 *\r
5244 * Field size: 1 bit\r
5245 */\r
5246 uint8_t crsSw;\r
5247 /**\r
5248 * @brief [ro] CRS Software Visibility Enable. Not supported and set to 0x0.\r
5249 *\r
5250 * On rev 0 hw, this corresponds to CRS_SW_EN\r
5251 * On rev 1 hw, this corresponds to CRSSV_EN\r
5252 *\r
5253 * Field size: 1 bit\r
5254 */\r
5255 uint8_t crsSwEn;\r
5256 /**\r
5257 * @brief [rw] PME Interrupt Enable\r
5258 *\r
5259 * On rev 0 hw, this corresponds to PME_INT_EN\r
5260 * On rev 1 hw, this corresponds to PMEI_EN\r
5261 *\r
5262 * Field size: 1 bit\r
5263 */\r
5264 uint8_t pmeIntEn;\r
5265 /**\r
5266 * @brief [rw] System Error on Fatal Error Enable\r
5267 *\r
5268 * On rev 0 hw, this corresponds to SERR_FATAL_ERR\r
5269 * On rev 1 hw, this corresponds to SEFE_EN\r
5270 *\r
5271 * Field size: 1 bit\r
5272 */\r
5273 uint8_t serrFatalErr;\r
5274 /**\r
5275 * @brief [rw] System Error on Non-fatal Error Enable\r
5276 *\r
5277 * On rev 0 hw, this corresponds to SERR_NFATAL_ERR\r
5278 * On rev 1 hw, this corresponds to SENE_EN\r
5279 *\r
5280 * Field size: 1 bit\r
5281 */\r
5282 uint8_t serrNFatalErr;\r
5283 /**\r
5284 * @brief [rw] System Error on Correctable Error Enable\r
5285 *\r
5286 * On rev 0 hw, this corresponds to SERR_EN\r
5287 * On rev 1 hw, this corresponds to SECE_EN\r
5288 *\r
5289 * Field size: 1 bit\r
5290 */\r
5291 uint8_t serrEn;\r
5292 } pcieRootCtrlCapReg_t;\r
5293 /* @} */\r
5294 \r
5295 /**\r
5296 * @ingroup pcielld_reg_cfg_cap_structures\r
5297 * @brief Specification of the Root Status and Control register\r
5298 *\r
5299 * This register may only be used for root complex mode.\r
5300 *\r
5301 * On rev 0 hw, this corresponds to ROOT_STATUS\r
5302 * On rev 1 hw, this corresponds to ROOT_STS\r
5303 *\r
5304 * @{\r
5305 */\r
5306 typedef struct pcieRootStatusReg_s {\r
5307 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5308 /**\r
5309 * @brief [ro] Indicates that another PME is pending when the PME Status bit is Set.\r
5310 *\r
5311 * On rev 0 hw, this corresponds to PME_PEND\r
5312 * On rev 1 hw, this corresponds to PME_PND\r
5313 *\r
5314 * Field size: 1 bit\r
5315 */\r
5316 uint8_t pmePend;\r
5317 /**\r
5318 * @brief [rw] Indicates that PME was asserted by the PME Requester.\r
5319 *\r
5320 * Write 1 to clear\r
5321 *\r
5322 * On rev 0 hw, this corresponds to PME_STATUS\r
5323 * On rev 1 hw, this corresponds to PME_STS\r
5324 *\r
5325 * Field size: 1 bit\r
5326 */\r
5327 uint8_t pmeStatus;\r
5328 /**\r
5329 * @brief [ro] ID of the last PME Requester.\r
5330 *\r
5331 * This field is only valid when the PME Status bit is Set.\r
5332 *\r
5333 * On rev 0 hw, this corresponds to PME_REQ_ID\r
5334 * On rev 1 hw, this corresponds to PME_RID\r
5335 *\r
5336 * Field size: 16 bits\r
5337 */\r
5338 uint16_t pmeReqID;\r
5339 } pcieRootStatusReg_t;\r
5340 /* @} */\r
5341 \r
5342 \r
5343 /**\r
5344 * @ingroup pcielld_reg_cfg_cap_structures\r
5345 * @brief Specification of the Device Capabilities 2 Register\r
5346 *\r
5347 * This register may be used for both endpoint and root complex modes.\r
5348 *\r
5349 * On rev 0 hw, this corresponds to DEV_CAP2\r
5350 * On rev 1 hw, this corresponds to DEV_CAP_2\r
5351 *\r
5352 * @{\r
5353 */\r
5354 typedef struct pcieDevCap2Reg_s {\r
5355 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5356 /**\r
5357 * @brief [rw] Completion timeout disable supported\r
5358 *\r
5359 * On rev 0 hw, this corresponds to CMPL_TO_DIS_SUPP\r
5360 * On rev 1 hw, this corresponds to CPL_TIMEOUT_DIS_SUPPORTED\r
5361 *\r
5362 * Field size: 1 bit\r
5363 */\r
5364 uint8_t cmplToDisSupp;\r
5365 /**\r
5366 * @brief [rw] Completion timeout ranges supported. Applicable to RC/EP that issue requests on own behalf.\r
5367 *\r
5368 * On rev 0 hw, this corresponds to CMPL_TO_EN\r
5369 * On rev 1 hw, this corresponds to CPL_TIMEOUT_RNG_SUPPORTED\r
5370 *\r
5371 * Field size: 4 bits\r
5372 */\r
5373 uint8_t cmplToEn;\r
5374 /**\r
5375 * @brief [ro] ARI Forwarding Supported\r
5376 *\r
5377 * On rev 0 hw, unsupported\r
5378 * On rev 1 hw, this corresponds to ARI_FWD_SP\r
5379 *\r
5380 * Field size: 1 bit\r
5381 */\r
5382 uint8_t ariFwdSp;\r
5383 /**\r
5384 * @brief [ro] AtomicOp Routing Supported\r
5385 *\r
5386 * On rev 0 hw, unsupported\r
5387 * On rev 1 hw, this corresponds to AOR_SP\r
5388 *\r
5389 * Field size: 1 bit\r
5390 */\r
5391 uint8_t aorSp;\r
5392 /**\r
5393 * @brief [ro] 32-bit AtomicOp Completer Supported\r
5394 *\r
5395 * On rev 0 hw, unsupported\r
5396 * On rev 1 hw, this corresponds to AOC32_SP\r
5397 *\r
5398 * Field size: 1 bit\r
5399 */\r
5400 uint8_t aoc32Sp;\r
5401 /**\r
5402 * @brief [ro] 64-bit AtomicOp Completer Supported\r
5403 *\r
5404 * On rev 0 hw, unsupported\r
5405 * On rev 1 hw, this corresponds to AOC64_SP\r
5406 *\r
5407 * Field size: 1 bit\r
5408 */\r
5409 uint8_t aoc64Sp;\r
5410 /**\r
5411 * @brief [ro] 128-bit CAS Completer Supported\r
5412 *\r
5413 * On rev 0 hw, unsupported\r
5414 * On rev 1 hw, this corresponds to CASC128_SP\r
5415 *\r
5416 * Field size: 1 bit\r
5417 */\r
5418 uint8_t casc128Sp;\r
5419 /**\r
5420 * @brief [ro] No RO-enabled PR-PR Passing\r
5421 *\r
5422 * On rev 0 hw, unsupported\r
5423 * On rev 1 hw, this corresponds to NOROPR\r
5424 *\r
5425 * Field size: 1 bit\r
5426 */\r
5427 uint8_t noRoPR;\r
5428 /**\r
5429 * @brief [ro] TPH Completer Supported\r
5430 *\r
5431 * On rev 0 hw, unsupported\r
5432 * On rev 1 hw, this corresponds to TPHC_SP\r
5433 *\r
5434 * Field size: 1 bit\r
5435 */\r
5436 uint8_t tphcSp;\r
5437 } pcieDevCap2Reg_t;\r
5438 /* @} */\r
5439 \r
5440 /**\r
5441 * @ingroup pcielld_reg_cfg_cap_structures\r
5442 * @brief Specification of the Device Status and Control Register 2\r
5443 *\r
5444 * This register may be used for both endpoint and root complex modes.\r
5445 *\r
5446 * On rev 0 hw, this corresponds to DEV_STAT_CTRL2\r
5447 * On rev 1 hw, this corresponds to DEV_CAS_2\r
5448 *\r
5449 * @{\r
5450 */\r
5451 typedef struct pcieDevStatCtrl2Reg_s {\r
5452 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5453 /**\r
5454 * @brief [rw] Completion timeout disable\r
5455 *\r
5456 * On rev 0 hw, this corresponds to CMPL_TO_DIS\r
5457 * On rev 1 hw, this corresponds to CPL_TIMEOUT_DIS\r
5458 *\r
5459 * Field size: 1 bit\r
5460 */\r
5461 uint8_t cmplToDis;\r
5462 /**\r
5463 * @brief [rw] Completion timeout value.\r
5464 *\r
5465 * It is strongly recommended that the Completion Timeout mechanism\r
5466 * not expire in less than 10 ms.\r
5467 *\r
5468 * <TABLE>\r
5469 * <TR><TH>@ref cmplTo</TH><TH>low range</TH><TH>high range</TH></TR>\r
5470 * <TR><TD>0x0</TD> <TD>50ms</TD> <TD>50s</TD></TR>\r
5471 * <TR><TD>0x1</TD> <TD>50s</TD> <TD>100s</TD></TR>\r
5472 * <TR><TD>0x2</TD> <TD>1ms</TD> <TD>10ms</TD></TR>\r
5473 * <TR><TD>0x5</TD> <TD>16ms</TD> <TD>55ms</TD></TR>\r
5474 * <TR><TD>0x6</TD> <TD>65ms</TD> <TD>210ms</TD></TR>\r
5475 * <TR><TD>0x9</TD> <TD>260ms</TD> <TD>900ms</TD></TR>\r
5476 * <TR><TD>0xA</TD> <TD>1s</TD> <TD>3.5s</TD></TR>\r
5477 * <TR><TD>0xD</TD> <TD>4s</TD> <TD>13s</TD></TR>\r
5478 * <TR><TD>0xE</TD> <TD>17s</TD> <TD>64s</TD></TR>\r
5479 * <TR><TD>others</TD> <TD>reserved</TD> <TD>reserved</TD></TR>\r
5480 * </TABLE>\r
5481 *\r
5482 * On rev 0 hw, this corresponds to CMPL_TO\r
5483 * On rev 1 hw, this corresponds to CPL_TIMEOUT_VALUE\r
5484 *\r
5485 * Field size: 4 bits\r
5486 */\r
5487 uint8_t cmplTo;\r
5488 /**\r
5489 * @brief [rw] ARI Forwarding Supported\r
5490 *\r
5491 * On rev 0 hw, unsupported\r
5492 * On rev 1 hw, this corresponds to ARI_FWD_SP\r
5493 *\r
5494 * Field size: 1 bit\r
5495 */\r
5496 uint8_t ariFwdSp;\r
5497 /**\r
5498 * @brief [rw] AtomicOp Requester Enabled\r
5499 *\r
5500 * On rev 0 hw, unsupported\r
5501 * On rev 1 hw, this corresponds to AOP_REQ_EN\r
5502 *\r
5503 * Field size: 1 bit\r
5504 */\r
5505 uint8_t aopReqEn;\r
5506 /**\r
5507 * @brief [rw] AtomicOp Egress Blocking\r
5508 *\r
5509 * On rev 0 hw, unsupported\r
5510 * On rev 1 hw, this corresponds to AOP_EG_BLK\r
5511 *\r
5512 * Field size: 1 bit\r
5513 */\r
5514 uint8_t aopEgBlk;\r
5515 /**\r
5516 * @brief [rw] IDO Request Enable\r
5517 *\r
5518 * On rev 0 hw, unsupported\r
5519 * On rev 1 hw, this corresponds to IDO_REQ_EN\r
5520 *\r
5521 * Field size: 1 bit\r
5522 */\r
5523 uint8_t idoReqEn;\r
5524 /**\r
5525 * @brief [rw] IDO Completion Enable\r
5526 *\r
5527 * On rev 0 hw, unsupported\r
5528 * On rev 1 hw, this corresponds to IDO_CPL_EN\r
5529 *\r
5530 * Field size: 1 bit\r
5531 */\r
5532 uint8_t idoCplEn;\r
5533 /**\r
5534 * @brief [rw] LTR Mechanism Enable\r
5535 *\r
5536 * On rev 0 hw, unsupported\r
5537 * On rev 1 hw, this corresponds to LTR_EN\r
5538 *\r
5539 * Field size: 1 bit\r
5540 */\r
5541 uint8_t ltrEn;\r
5542 /**\r
5543 * @brief [rw] OBFF Enable\r
5544 *\r
5545 * On rev 0 hw, unsupported\r
5546 * On rev 1 hw, this corresponds to OBFF_EN\r
5547 *\r
5548 * Field size: 1 bit\r
5549 */\r
5550 uint8_t obffEn;\r
5551 } pcieDevStatCtrl2Reg_t;\r
5552 /* @} */\r
5553 \r
5554 /**\r
5555 * @ingroup pcielld_reg_cfg_cap_structures\r
5556 * @brief Specification of the Link Capabilities 2 Register\r
5557 *\r
5558 * This register may be used for both endpoint and root complex modes.\r
5559 *\r
5560 * On rev 0 hw, unsupported\r
5561 * On rev 1 hw, this corresponds to LNK_CAP_2\r
5562 *\r
5563 * @{\r
5564 */\r
5565 /* @} */\r
5566 typedef struct pcieLnkCap2Reg_s {\r
5567 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5568 /**\r
5569 * @brief [ro] Supported Link Speeds Vector\r
5570 *\r
5571 * On rev 0 hw, unsupported\r
5572 * On rev 1 hw, this corresponds to SP_LS_VEC\r
5573 *\r
5574 * Field size: 7 bits\r
5575 */\r
5576 uint8_t spLsVec;\r
5577 /**\r
5578 * @brief [ro] Crosslink Supported\r
5579 *\r
5580 * On rev 0 hw, unsupported\r
5581 * On rev 1 hw, this corresponds to CROSSLINK_SP\r
5582 *\r
5583 * Field size: 1 bit\r
5584 */\r
5585 uint8_t crosslinkSp;\r
5586 } pcieLnkCap2Reg_t;\r
5587 \r
5588 /**\r
5589 * @ingroup pcielld_reg_cfg_cap_structures\r
5590 * @brief Specification of the Link Control 2 Register\r
5591 *\r
5592 * This register may be used for both endpoint and root complex modes.\r
5593 *\r
5594 * On rev 0 hw, this corresponds to LINK_CTRL2\r
5595 * On rev 1 hw, this corresponds to LNK_CAS_2\r
5596 *\r
5597 * @{\r
5598 */\r
5599 typedef struct pcieLinkCtrl2Reg_s {\r
5600 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5601 /**\r
5602 * @brief [rw] Current De-emphasis level\r
5603 *\r
5604 * 0 = -6 dB\n\r
5605 * 1 = -3.5 dB\r
5606 *\r
5607 * On rev 0 hw, this corresponds to DE_EMPH\r
5608 * On rev 1 hw, this corresponds to DEEMPH_LEVEL\r
5609 *\r
5610 * Field size: 1 bit\r
5611 */\r
5612 uint8_t deEmph;\r
5613 /**\r
5614 * @brief [rw] De-emphasis level in polling-compliance state\r
5615 *\r
5616 * This bit sets the de-emphasis level in Polling Compliance state if the\r
5617 * entry occurred due to the Enter Compliance bit being 1.\r
5618 *\r
5619 * 0 = -6 dB\n\r
5620 * 1 = -3.5 dB\r
5621 *\r
5622 * On rev 0 hw, this corresponds to POLL_DEEMPH\r
5623 * On rev 1 hw, this corresponds to COMPL_PRST_DEEMPH\r
5624 *\r
5625 * Field size: 1 bit\r
5626 */\r
5627 uint8_t pollDeemph;\r
5628 /**\r
5629 * @brief [rw] Compliance SOS.\r
5630 *\r
5631 * When this bit is set to 1, the LTSSM is required to send SKP\r
5632 * Ordered Sets periodically in between the modified compliance patterns.\r
5633 *\r
5634 * On rev 0 hw, this corresponds to CMPL_SOS\r
5635 * On rev 1 hw, this corresponds to COMPL_SOS\r
5636 *\r
5637 * Field size: 1 bit\r
5638 */\r
5639 uint8_t cmplSos;\r
5640 /**\r
5641 * @brief [rw] Enter modified compliance.\r
5642 *\r
5643 * When this bit is set to 1, the device transmits Modified Compliance\r
5644 * Pattern if the LTSSM enters Polling Compliance substate.\r
5645 *\r
5646 * On rev 0 hw, this corresponds to ENTR_MOD_COMPL\r
5647 * On rev 1 hw, this corresponds to ENT_MOD_COMPL\r
5648 *\r
5649 * Field size: 1 bit\r
5650 */\r
5651 uint8_t entrModCompl;\r
5652 /**\r
5653 * @brief [rw] Value of non-de-emphasized voltage level at transmitter pins.\r
5654 *\r
5655 * On rev 0 hw, this corresponds to TX_MARGIN\r
5656 * On rev 1 hw, this corresponds to TX_MARGIN\r
5657 *\r
5658 * Field size: 3 bits\r
5659 */\r
5660 uint8_t txMargin;\r
5661 /**\r
5662 * @brief [rw] Selectable De-emphasis.\r
5663 *\r
5664 * When the Link is operating at 5.0 GT/s speed, this bit selects the level\r
5665 * of de-emphasis for an upstream component. When the Link is operating at\r
5666 * 2.5 GT/s speed, the setting of this bit has no effect.\r
5667 *\r
5668 * 0 = -6 dB\n\r
5669 * 1 = -3.5 dB\r
5670 *\r
5671 * On rev 0 hw, this corresponds to SEL_DEEMPH\r
5672 * On rev 1 hw, this corresponds to SEL_DEEMP\r
5673 *\r
5674 * Field size: 1 bit\r
5675 */\r
5676 uint8_t selDeemph;\r
5677 /**\r
5678 * @brief [rw] Hardware Autonomous Speed Disable.\r
5679 *\r
5680 * 0 = Enable hardware to change the link speed.\n\r
5681 * 1 = Disables hardware from changing the Link speed for device specific\r
5682 * reasons other than attempting to correct unreliable Link operation by\r
5683 * reducing Link speed.\r
5684 *\r
5685 * On rev 0 hw, this corresponds to HW_AUTO_SPEED_DIS\r
5686 * On rev 1 hw, this corresponds to HW_AUTO_SP_DIS\r
5687 *\r
5688 * Field size: 1 bit\r
5689 */\r
5690 uint8_t hwAutoSpeedDis;\r
5691 /**\r
5692 * @brief [rw] Enter Compliance.\r
5693 *\r
5694 * Software is permitted to force a Link to enter Compliance mode at the\r
5695 * speed indicated in the Target Link Speed field by setting this bit to\r
5696 * 1 in both components on a Link and then initiating a hot reset on the Link.\r
5697 *\r
5698 * On rev 0 hw, this corresponds to ENTR_COMPL\r
5699 * On rev 1 hw, this corresponds to ENTR_COMPL\r
5700 *\r
5701 * Field size: 1 bit\r
5702 */\r
5703 uint8_t entrCompl;\r
5704 /**\r
5705 * @brief [rw] Target Link Speed.\r
5706 *\r
5707 * 1h = 2.5 GT/s Target Link Speed.\n\r
5708 * 2h = 5.0 GT/s Target Link Speed.\n\r
5709 * Others = Reserved.\r
5710 *\r
5711 * On rev 0 hw, this corresponds to TGT_SPEED\r
5712 * On rev 1 hw, this corresponds to TRGT_LINK_SPEED\r
5713 *\r
5714 * Field size: 4 bits\r
5715 */\r
5716 uint8_t tgtSpeed;\r
5717 /**\r
5718 * @brief [rw] Compliance Pre-set/De-emphasis\r
5719 *\r
5720 * On rev 0 hw, unsupported\r
5721 * On rev 1 hw, this corresponds to COMPL_PRST_DEEMPH\r
5722 *\r
5723 * Field size: 4 bits\r
5724 */\r
5725 uint8_t complPrstDeemph;\r
5726 /**\r
5727 * @brief [ro] Equalization Complete, Gen3 Only\r
5728 *\r
5729 * On rev 0 hw, unsupported\r
5730 * On rev 1 hw, this corresponds to EQ_COMPLETE\r
5731 *\r
5732 * Field size: 1 bit\r
5733 */\r
5734 uint8_t eqComplete;\r
5735 /**\r
5736 * @brief [ro] Equalization Ph1 Success, Gen3 Only\r
5737 *\r
5738 * On rev 0 hw, unsupported\r
5739 * On rev 1 hw, this corresponds to EQ_PH1\r
5740 *\r
5741 * Field size: 1 bit\r
5742 */\r
5743 uint8_t eqPh1;\r
5744 /**\r
5745 * @brief [ro] Equalization Ph2 Success, Gen3 Only\r
5746 *\r
5747 * On rev 0 hw, unsupported\r
5748 * On rev 1 hw, this corresponds to EQ_PH2\r
5749 *\r
5750 * Field size: 1 bit\r
5751 */\r
5752 uint8_t eqPh2;\r
5753 /**\r
5754 * @brief [ro] Equalization Ph3 Success, Gen3 Only\r
5755 *\r
5756 * On rev 0 hw, unsupported\r
5757 * On rev 1 hw, this corresponds to EQ_PH3\r
5758 *\r
5759 * Field size: 1 bit\r
5760 */\r
5761 uint8_t eqPh3;\r
5762 /**\r
5763 * @brief [rw] Link Equilization Request\r
5764 *\r
5765 * On rev 0 hw, unsupported\r
5766 * On rev 1 hw, this corresponds to LINK_EQ_REQ\r
5767 *\r
5768 * Field size: 1 bit\r
5769 */\r
5770 uint8_t linkEqReq;\r
5771 } pcieLinkCtrl2Reg_t;\r
5772 /* @} */\r
5773 \r
5774 \r
5775 /*****************************************************************************\r
5776 ********** PCIe EXTENDED CAPABILITIES REGISTERS ***************************\r
5777 ****************************************************************************/\r
5778 /**\r
5779 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
5780 * @brief Specification of the Extended Capabilities Header register\r
5781 *\r
5782 * This register may be used for both endpoint and root complex modes.\r
5783 *\r
5784 * On rev 0 hw, this corresponds to PCIE_EXTCAP\r
5785 * On rev 1 hw, unsupported\r
5786 *\r
5787 * @{\r
5788 */\r
5789 typedef struct pcieExtCapReg_s {\r
5790 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5791 /**\r
5792 * @brief [ro] Next Capability Pointer\r
5793 *\r
5794 * On rev 0 hw, this corresponds to NEXT_CAP\r
5795 * On rev 1 hw, unsupported\r
5796 *\r
5797 * Field size: 12 bits\r
5798 */\r
5799 uint16_t nextCap;\r
5800 /**\r
5801 * @brief [ro] Extended Capability Version\r
5802 *\r
5803 * On rev 0 hw, this corresponds to EXT_CAP_VER\r
5804 * On rev 1 hw, unsupported\r
5805 *\r
5806 * Field size: 4 bits\r
5807 */\r
5808 uint8_t extCapVer;\r
5809 /**\r
5810 * @brief [ro] PCIe Extended Capability ID\r
5811 *\r
5812 * On rev 0 hw, this corresponds to EXT_CAP_ID\r
5813 * On rev 1 hw, unsupported\r
5814 *\r
5815 * Field size: 16 bits\r
5816 */\r
5817 uint16_t extCapID;\r
5818 } pcieExtCapReg_t;\r
5819 /* @} */\r
5820 \r
5821 /**\r
5822 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
5823 * @brief Specification of the Uncorrectable Error Status register\r
5824 *\r
5825 * This register may be used for both endpoint and root complex modes.\r
5826 *\r
5827 * On rev 0 hw, this corresponds to PCIE_UNCERR\r
5828 * On rev 1 hw, unsupported\r
5829 *\r
5830 * @{\r
5831 */\r
5832 typedef struct pcieUncErrReg_s {\r
5833 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5834 /**\r
5835 * @brief [rw] Unsupported Request Error Status\r
5836 *\r
5837 * Write 1 to clear\r
5838 *\r
5839 * On rev 0 hw, this corresponds to UR_ERR_ST\r
5840 * On rev 1 hw, unsupported\r
5841 *\r
5842 * Field size: 1 bit\r
5843 */\r
5844 uint8_t urErrSt;\r
5845 /**\r
5846 * @brief [rw] ECRC Error Status\r
5847 *\r
5848 * Write 1 to clear\r
5849 *\r
5850 * On rev 0 hw, this corresponds to ECRC_ERR_ST\r
5851 * On rev 1 hw, unsupported\r
5852 *\r
5853 * Field size: 1 bit\r
5854 */\r
5855 uint8_t ecrcErrSt;\r
5856 /**\r
5857 * @brief [rw] Malformed TLP Status\r
5858 *\r
5859 * Write 1 to clear\r
5860 *\r
5861 * On rev 0 hw, this corresponds to MTLP_ERR_ST\r
5862 * On rev 1 hw, unsupported\r
5863 *\r
5864 * Field size: 1 bit\r
5865 */\r
5866 uint8_t mtlpErrSt;\r
5867 /**\r
5868 * @brief [rw] Receiver Overflow Status\r
5869 *\r
5870 * Write 1 to clear\r
5871 *\r
5872 * On rev 0 hw, this corresponds to RCVR_OF_ST\r
5873 * On rev 1 hw, unsupported\r
5874 *\r
5875 * Field size: 1 bit\r
5876 */\r
5877 uint8_t rcvrOfSt;\r
5878 /**\r
5879 * @brief [rw] Unexpected Completion Status\r
5880 *\r
5881 * Write 1 to clear\r
5882 *\r
5883 * On rev 0 hw, this corresponds to UCMP_ST\r
5884 * On rev 1 hw, unsupported\r
5885 *\r
5886 * Field size: 1 bit\r
5887 */\r
5888 uint8_t ucmpSt;\r
5889 /**\r
5890 * @brief [rw] Completer Abort Status\r
5891 *\r
5892 * Write 1 to clear\r
5893 *\r
5894 * On rev 0 hw, this corresponds to CMPL_ABRT_ST\r
5895 * On rev 1 hw, unsupported\r
5896 *\r
5897 * Field size: 1 bit\r
5898 */\r
5899 uint8_t cmplAbrtSt;\r
5900 /**\r
5901 * @brief [rw] Completion Timeout Status\r
5902 *\r
5903 * Write 1 to clear\r
5904 *\r
5905 * On rev 0 hw, this corresponds to CMPL_TMOT_ST\r
5906 * On rev 1 hw, unsupported\r
5907 *\r
5908 * Field size: 1 bit\r
5909 */\r
5910 uint8_t cmplTmotSt;\r
5911 /**\r
5912 * @brief [rw] Flow Control Protocol Error Status\r
5913 *\r
5914 * Write 1 to clear\r
5915 *\r
5916 * On rev 0 hw, this corresponds to FCP_ERR_ST\r
5917 * On rev 1 hw, unsupported\r
5918 *\r
5919 * Field size: 1 bit\r
5920 */\r
5921 uint8_t fcpErrSt;\r
5922 /**\r
5923 * @brief [rw] Poisoned TLP Status\r
5924 *\r
5925 * Write 1 to clear\r
5926 *\r
5927 * On rev 0 hw, this corresponds to PSND_TLP_ST\r
5928 * On rev 1 hw, unsupported\r
5929 *\r
5930 * Field size: 1 bit\r
5931 */\r
5932 uint8_t psndTlpSt;\r
5933 /**\r
5934 * @brief [ro] Surprise Down Error Status. Not supported (always 0)\r
5935 *\r
5936 * On rev 0 hw, this corresponds to SRPS_DN_ST\r
5937 * On rev 1 hw, unsupported\r
5938 *\r
5939 * Field size: 1 bit\r
5940 */\r
5941 uint8_t srpsDnSt;\r
5942 /**\r
5943 * @brief [rw] Data Link Protocol Error Status\r
5944 *\r
5945 * Write 1 to clear\r
5946 *\r
5947 * On rev 0 hw, this corresponds to DLP_ERR_ST\r
5948 * On rev 1 hw, unsupported\r
5949 *\r
5950 * Field size: 1 bit\r
5951 */\r
5952 uint8_t dlpErrSt;\r
5953 } pcieUncErrReg_t;\r
5954 /* @} */\r
5955 \r
5956 /**\r
5957 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
5958 * @brief Specification of the Uncorrectable Error Mask register\r
5959 *\r
5960 * This register may be used for both endpoint and root complex modes.\r
5961 *\r
5962 * On rev 0 hw, this corresponds to PCIE_UNCERR_MASK\r
5963 * On rev 1 hw, unsupported\r
5964 *\r
5965 * @{\r
5966 */\r
5967 typedef struct pcieUncErrMaskReg_s {\r
5968 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
5969 /**\r
5970 * @brief [rw] Unsupported Request Error Mask\r
5971 *\r
5972 * On rev 0 hw, this corresponds to UR_ERR_MSK\r
5973 * On rev 1 hw, unsupported\r
5974 *\r
5975 * Field size: 1 bit\r
5976 */\r
5977 uint8_t urErrMsk;\r
5978 /**\r
5979 * @brief [rw] ECRC Error Mask\r
5980 *\r
5981 * On rev 0 hw, this corresponds to ECRC_ERR_MSK\r
5982 * On rev 1 hw, unsupported\r
5983 *\r
5984 * Field size: 1 bit\r
5985 */\r
5986 uint8_t ecrcErrMsk;\r
5987 /**\r
5988 * @brief [rw] Malformed TLP Mask\r
5989 *\r
5990 * On rev 0 hw, this corresponds to MTLP_ERR_MSK\r
5991 * On rev 1 hw, unsupported\r
5992 *\r
5993 * Field size: 1 bit\r
5994 */\r
5995 uint8_t mtlpErrMsk;\r
5996 /**\r
5997 * @brief [rw] Receiver Overflow Mask\r
5998 *\r
5999 * On rev 0 hw, this corresponds to RCVR_OF_MASK\r
6000 * On rev 1 hw, unsupported\r
6001 *\r
6002 * Field size: 1 bit\r
6003 */\r
6004 uint8_t rcvrOfMsk;\r
6005 /**\r
6006 * @brief [rw] Unexpected Completion Mask\r
6007 *\r
6008 * On rev 0 hw, this corresponds to UCMP_MSK\r
6009 * On rev 1 hw, unsupported\r
6010 *\r
6011 * Field size: 1 bit\r
6012 */\r
6013 uint8_t ucmpMsk;\r
6014 /**\r
6015 * @brief [rw] Completer Abort Mask\r
6016 *\r
6017 * On rev 0 hw, this corresponds to CMPL_ABRT_MSK\r
6018 * On rev 1 hw, unsupported\r
6019 *\r
6020 * Field size: 1 bit\r
6021 */\r
6022 uint8_t cmplAbrtMsk;\r
6023 /**\r
6024 * @brief [rw] Completion Timeout Mask\r
6025 *\r
6026 * On rev 0 hw, this corresponds to CMPL_TMOT_MSK\r
6027 * On rev 1 hw, unsupported\r
6028 *\r
6029 * Field size: 1 bit\r
6030 */\r
6031 uint8_t cmplTmotMsk;\r
6032 /**\r
6033 * @brief [rw] Flow Control Protocol Error Mask\r
6034 *\r
6035 * On rev 0 hw, this corresponds to FCP_ERR_MSK\r
6036 * On rev 1 hw, unsupported\r
6037 *\r
6038 * Field size: 1 bit\r
6039 */\r
6040 uint8_t fcpErrMsk;\r
6041 /**\r
6042 * @brief [rw] Poisoned TLP Mask\r
6043 *\r
6044 * On rev 0 hw, this corresponds to PSND_TLP_MSK\r
6045 * On rev 1 hw, unsupported\r
6046 *\r
6047 * Field size: 1 bit\r
6048 */\r
6049 uint8_t psndTlpMsk;\r
6050 /**\r
6051 * @brief [ro] Surprise Down Error Mask. Not supported (always 0)\r
6052 *\r
6053 * On rev 0 hw, this corresponds to SRPS_DN_MSK\r
6054 * On rev 1 hw, unsupported\r
6055 *\r
6056 * Field size: 1 bit\r
6057 */\r
6058 uint8_t srpsDnMsk;\r
6059 /**\r
6060 * @brief [rw] Data Link Protocol Error Mask\r
6061 *\r
6062 * On rev 0 hw, this corresponds to DLP_ERR_MSK\r
6063 * On rev 1 hw, unsupported\r
6064 *\r
6065 * Field size: 1 bit\r
6066 */\r
6067 uint8_t dlpErrMsk;\r
6068 } pcieUncErrMaskReg_t;\r
6069 /* @} */\r
6070 \r
6071 /**\r
6072 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6073 * @brief Specification of the Uncorrectable Error Severity register\r
6074 *\r
6075 * This register may be used for both endpoint and root complex modes.\r
6076 *\r
6077 * Set each bit to 0 to indicate the error is non-fatal\r
6078 * Set each bit to 1 to indicate the error is fatal.\r
6079 *\r
6080 * On rev 0 hw, this corresponds to PCIE_UNCERR_SVRTY\r
6081 * On rev 1 hw, unsupported\r
6082 *\r
6083 * @{\r
6084 */\r
6085 typedef struct pcieUncErrSvrtyReg_s {\r
6086 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6087 /**\r
6088 * @brief [rw] Unsupported Request Error Severity\r
6089 *\r
6090 * 0=Non-Fatal; 1=Fatal\r
6091 *\r
6092 * On rev 0 hw, this corresponds to UR_ERR_SVRTY\r
6093 * On rev 1 hw, unsupported\r
6094 *\r
6095 * Field size: 1 bit\r
6096 */\r
6097 uint8_t urErrSvrty;\r
6098 /**\r
6099 * @brief [rw] ECRC Error Severity\r
6100 *\r
6101 * 0=Non-Fatal; 1=Fatal\r
6102 *\r
6103 * On rev 0 hw, this corresponds to ECRC_ERR_SVRTY\r
6104 * On rev 1 hw, unsupported\r
6105 *\r
6106 * Field size: 1 bit\r
6107 */\r
6108 uint8_t ecrcErrSvrty;\r
6109 /**\r
6110 * @brief [rw] Malformed TLP Severity\r
6111 *\r
6112 * 0=Non-Fatal; 1=Fatal\r
6113 *\r
6114 * On rev 0 hw, this corresponds to MTLP_ERR_SVRTY\r
6115 * On rev 1 hw, unsupported\r
6116 *\r
6117 * Field size: 1 bit\r
6118 */\r
6119 uint8_t mtlpErrSvrty;\r
6120 /**\r
6121 * @brief [rw] Receiver Overflow Severity\r
6122 *\r
6123 * 0=Non-Fatal; 1=Fatal\r
6124 *\r
6125 * On rev 0 hw, this corresponds to RCVR_OF_SVRTY\r
6126 * On rev 1 hw, unsupported\r
6127 *\r
6128 * Field size: 1 bit\r
6129 */\r
6130 uint8_t rcvrOfSvrty;\r
6131 /**\r
6132 * @brief [rw] Unexpected Completion Severity\r
6133 *\r
6134 * 0=Non-Fatal; 1=Fatal\r
6135 *\r
6136 * On rev 0 hw, this corresponds to UCMP_SVRTY\r
6137 * On rev 1 hw, unsupported\r
6138 *\r
6139 * Field size: 1 bit\r
6140 */\r
6141 uint8_t ucmpSvrty;\r
6142 /**\r
6143 * @brief [rw] Completer Abort Severity\r
6144 *\r
6145 * 0=Non-Fatal; 1=Fatal\r
6146 *\r
6147 * On rev 0 hw, this corresponds to CMPL_ABRT_SVRTY\r
6148 * On rev 1 hw, unsupported\r
6149 *\r
6150 * Field size: 1 bit\r
6151 */\r
6152 uint8_t cmplAbrtSvrty;\r
6153 /**\r
6154 * @brief [rw] Completion Timeout Severity\r
6155 *\r
6156 * 0=Non-Fatal; 1=Fatal\r
6157 *\r
6158 * On rev 0 hw, this corresponds to CMPL_TMOT_SVRTY\r
6159 * On rev 1 hw, unsupported\r
6160 *\r
6161 * Field size: 1 bit\r
6162 */\r
6163 uint8_t cmplTmotSvrty;\r
6164 /**\r
6165 * @brief [rw] Flow Control Protocol Error Severity\r
6166 *\r
6167 * 0=Non-Fatal; 1=Fatal\r
6168 *\r
6169 * On rev 0 hw, this corresponds to FCP_ERR_SVRTY\r
6170 * On rev 1 hw, unsupported\r
6171 *\r
6172 * Field size: 1 bit\r
6173 */\r
6174 uint8_t fcpErrSvrty;\r
6175 /**\r
6176 * @brief [rw] Poisoned TLP Severity\r
6177 *\r
6178 * 0=Non-Fatal; 1=Fatal\r
6179 *\r
6180 * On rev 0 hw, this corresponds to PSND_TLP_SVRTY\r
6181 * On rev 1 hw, unsupported\r
6182 *\r
6183 * Field size: 1 bit\r
6184 */\r
6185 uint8_t psndTlpSvrty;\r
6186 /**\r
6187 * @brief [ro] Surprise Down Error Severity. Not supported (always 0)\r
6188 *\r
6189 * 0=Non-Fatal; 1=Fatal\r
6190 *\r
6191 * On rev 0 hw, this corresponds to SRPS_DN_SVRTY\r
6192 * On rev 1 hw, unsupported\r
6193 *\r
6194 * Field size: 1 bit\r
6195 */\r
6196 uint8_t srpsDnSvrty;\r
6197 /**\r
6198 * @brief [rw] Data Link Protocol Error Severity\r
6199 *\r
6200 * 0 = Non-fatal; 1 = Fatal\r
6201 *\r
6202 * On rev 0 hw, this corresponds to DLP_ERR_SVRTY\r
6203 * On rev 1 hw, unsupported\r
6204 *\r
6205 * Field size: 1 bit\r
6206 */\r
6207 uint8_t dlpErrSvrty;\r
6208 } pcieUncErrSvrtyReg_t;\r
6209 /* @} */\r
6210 \r
6211 /**\r
6212 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6213 * @brief Specification of the Correctable Error Status register\r
6214 *\r
6215 * This register may be used for both endpoint and root complex modes.\r
6216 *\r
6217 * On rev 0 hw, this corresponds to PCIE_CERR\r
6218 * On rev 1 hw, unsupported\r
6219 *\r
6220 * @{\r
6221 */\r
6222 typedef struct pcieCorErrReg_s {\r
6223 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6224 /**\r
6225 * @brief [rw] Advisory Non-Fatal Error Status\r
6226 *\r
6227 * This bit is Set by default to enable compatibility with software\r
6228 * that does not comprehend Role-Based Error Reporting.\r
6229 *\r
6230 * Write 1 to clear\r
6231 *\r
6232 * On rev 0 hw, this corresponds to ADV_NFERR_ST\r
6233 * On rev 1 hw, unsupported\r
6234 *\r
6235 * Field size: 1 bit\r
6236 */\r
6237 uint8_t advNFErrSt;\r
6238 /**\r
6239 * @brief [rw] Replay Timer Timeout Status\r
6240 *\r
6241 * Write 1 to clear\r
6242 *\r
6243 * On rev 0 hw, this corresponds to RPLY_TMR_ST\r
6244 * On rev 1 hw, unsupported\r
6245 *\r
6246 * Field size: 1 bit\r
6247 */\r
6248 uint8_t rplyTmrSt;\r
6249 /**\r
6250 * @brief [rw] REPLAY_NUM Rollover Status\r
6251 *\r
6252 * Write 1 to clear\r
6253 *\r
6254 * On rev 0 hw, this corresponds to RPLT_RO_ST\r
6255 * On rev 1 hw, unsupported\r
6256 *\r
6257 * Field size: 1 bit\r
6258 */\r
6259 uint8_t rpltRoSt;\r
6260 /**\r
6261 * @brief [rw] Bad DLLP Status\r
6262 *\r
6263 * Write 1 to clear\r
6264 *\r
6265 * On rev 0 hw, this corresponds to BAD_DLLP_ST\r
6266 * On rev 1 hw, unsupported\r
6267 *\r
6268 * Field size: 1 bit\r
6269 */\r
6270 uint8_t badDllpSt;\r
6271 /**\r
6272 * @brief [rw] Bad TLP Status\r
6273 *\r
6274 * Write 1 to clear\r
6275 *\r
6276 * On rev 0 hw, this corresponds to BAD_TLP_ST\r
6277 * On rev 1 hw, unsupported\r
6278 *\r
6279 * Field size: 1 bit\r
6280 */\r
6281 uint8_t badTlpSt;\r
6282 /**\r
6283 * @brief [rw] Receiver Error Status\r
6284 *\r
6285 * Write 1 to clear\r
6286 *\r
6287 * On rev 0 hw, this corresponds to RCV_ERR_ST\r
6288 * On rev 1 hw, unsupported\r
6289 *\r
6290 * Field size: 1 bit\r
6291 */\r
6292 uint8_t rcvrErrSt;\r
6293 } pcieCorErrReg_t;\r
6294 /* @} */\r
6295 \r
6296 /**\r
6297 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6298 * @brief Specification of the Correctable Error Mask register\r
6299 *\r
6300 * This register may be used for both endpoint and root complex modes.\r
6301 *\r
6302 * On rev 0 hw, this corresponds to PCIE_CERR_MASK\r
6303 * On rev 1 hw, unsupported\r
6304 *\r
6305 * @{\r
6306 */\r
6307 typedef struct pcieCorErrMaskReg_s {\r
6308 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6309 /**\r
6310 * @brief [rw] Advisory Non-Fatal Error Mask\r
6311 *\r
6312 * On rev 0 hw, this corresponds to ADV_NFERR_MSK\r
6313 * On rev 1 hw, unsupported\r
6314 *\r
6315 * Field size: 1 bit\r
6316 */\r
6317 uint8_t advNFErrMsk;\r
6318 /**\r
6319 * @brief [rw] Replay Timer Timeout Mask\r
6320 *\r
6321 * On rev 0 hw, this corresponds to RPLY_TMR_MSK\r
6322 * On rev 1 hw, unsupported\r
6323 *\r
6324 * Field size: 1 bit\r
6325 */\r
6326 uint8_t rplyTmrMsk;\r
6327 /**\r
6328 * @brief [rw] REPLAY_NUM Rollover Mask\r
6329 *\r
6330 * On rev 0 hw, this corresponds to RPLT_RO_MSK\r
6331 * On rev 1 hw, unsupported\r
6332 *\r
6333 * Field size: 1 bit\r
6334 */\r
6335 uint8_t rpltRoMsk;\r
6336 /**\r
6337 * @brief [rw] Bad DLLP Mask\r
6338 *\r
6339 * On rev 0 hw, this corresponds to BAD_DLLP_MSK\r
6340 * On rev 1 hw, unsupported\r
6341 *\r
6342 * Field size: 1 bit\r
6343 */\r
6344 uint8_t badDllpMsk;\r
6345 /**\r
6346 * @brief [rw] Bad TLP Mask\r
6347 *\r
6348 * On rev 0 hw, this corresponds to BAD_TLP_MSK\r
6349 * On rev 1 hw, unsupported\r
6350 *\r
6351 * Field size: 1 bit\r
6352 */\r
6353 uint8_t badTlpMsk;\r
6354 /**\r
6355 * @brief [rw] Receiver Error Mask\r
6356 *\r
6357 * On rev 0 hw, this corresponds to RCVR_ERR_MSK\r
6358 * On rev 1 hw, unsupported\r
6359 *\r
6360 * Field size: 1 bit\r
6361 */\r
6362 uint8_t rcvrErrMsk;\r
6363 } pcieCorErrMaskReg_t;\r
6364 /* @} */\r
6365 \r
6366 /**\r
6367 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6368 * @brief Specification of the Advanced capabilities and control Register\r
6369 *\r
6370 * This register may be used for both endpoint and root complex modes.\r
6371 *\r
6372 * This register is only available on rev 0 hw.\r
6373 * It is not available on rev 1 hw.\r
6374 *\r
6375 * On rev 0 hw, this corresponds to PCIE_ACCR\r
6376 * On rev 1 hw, unsupported\r
6377 *\r
6378 * @{\r
6379 */\r
6380 typedef struct pcieAccrReg_s {\r
6381 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
6382 /**\r
6383 * @brief [rw] ECRC Check Enable\r
6384 *\r
6385 * On rev 0 hw, this corresponds to ECRC_CHK_EN\r
6386 * On rev 1 hw, unsupported\r
6387 *\r
6388 * Field size: 1bit\r
6389 */\r
6390 uint8_t chkEn;\r
6391 /**\r
6392 * @brief [rw] ECRC Check Capable\r
6393 *\r
6394 * On rev 0 hw, this corresponds to ECRC_CHK_CAP\r
6395 * On rev 1 hw, unsupported\r
6396 *\r
6397 * Field size: 1 bit\r
6398 */\r
6399 uint8_t chkCap;\r
6400 /**\r
6401 * @brief [rw] ECRC Generation Enable\r
6402 *\r
6403 * On rev 0 hw, this corresponds to ECRC_GEN_EN\r
6404 * On rev 1 hw, unsupported\r
6405 *\r
6406 * Field size: 1 bit\r
6407 */\r
6408 uint8_t genEn;\r
6409 /**\r
6410 * @brief [rw] ECRC Generation Capability\r
6411 *\r
6412 * On rev 0 hw, this corresponds to ECRC_GEN_CAP\r
6413 * On rev 1 hw, unsupported\r
6414 *\r
6415 * Field size: 1 bit\r
6416 */\r
6417 uint8_t genCap;\r
6418 /**\r
6419 * @brief [rw] First Error Pointer\r
6420 *\r
6421 * The First Error Pointer is a field that identifies the bit position\r
6422 * of the first error reported in the @ref pcieUncErrReg_s\r
6423 *\r
6424 * On rev 0 hw, this corresponds to FRST_ERR_PTR\r
6425 * On rev 1 hw, unsupported\r
6426 *\r
6427 * Field size: 5 bits\r
6428 */\r
6429 uint8_t erPtr;\r
6430 } pcieAccrReg_t;\r
6431 /* @} */\r
6432 \r
6433 /**\r
6434 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6435 * @brief Specification of the Header Log registers\r
6436 *\r
6437 * These registers may be used for both endpoint and root complex modes.\r
6438 *\r
6439 * There are 4 Header Log registers\r
6440 *\r
6441 * On rev 0 hw, this corresponds to HDR_LOGn (n = 0..3)\r
6442 * On rev 1 hw, unsupported\r
6443 *\r
6444 * @{\r
6445 */\r
6446 typedef struct pcieHdrLogReg_s {\r
6447 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6448 /**\r
6449 * @brief [ro] DWORD of header for a detected error\r
6450 *\r
6451 * On rev 0 hw, this corresponds to HDR_DWn (n = 0..3)\r
6452 * On rev 1 hw, unsupported\r
6453 *\r
6454 * Field size: 32 bits\r
6455 */\r
6456 uint32_t hdrDW;\r
6457 } pcieHdrLogReg_t;\r
6458 /* @} */\r
6459 \r
6460 /**\r
6461 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6462 * @brief Specification of the Root Error Command register\r
6463 *\r
6464 * This register may be used for both endpoint and root complex modes.\r
6465 *\r
6466 * On rev 0 hw, this corresponds to ROOT_ERR_CMD\r
6467 * On rev 1 hw, unsupported\r
6468 *\r
6469 * @{\r
6470 */\r
6471 typedef struct pcieRootErrCmdReg_s {\r
6472 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6473 /**\r
6474 * @brief [rw] Fatal Error Reporting Enable.\r
6475 *\r
6476 * On rev 0 hw, this corresponds to FERR_RPT_EN\r
6477 * On rev 1 hw, unsupported\r
6478 *\r
6479 * Field size: 1 bit\r
6480 */\r
6481 uint8_t ferrRptEn;\r
6482 /**\r
6483 * @brief [rw] Nonfatal Error Reporting Enable.\r
6484 *\r
6485 * On rev 0 hw, this corresponds to NFERR_RPT_EN\r
6486 * On rev 1 hw, unsupported\r
6487 *\r
6488 * Field size: 1 bit\r
6489 */\r
6490 uint8_t nferrRptEn;\r
6491 /**\r
6492 * @brief [rw] Correctable Error Reporting Enable.\r
6493 *\r
6494 * On rev 0 hw, this corresponds to CERR_RPT_EN\r
6495 * On rev 1 hw, unsupported\r
6496 *\r
6497 * Field size: 1 bit\r
6498 */\r
6499 uint8_t cerrRptEn;\r
6500 } pcieRootErrCmdReg_t;\r
6501 /* @} */\r
6502 \r
6503 /**\r
6504 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6505 * @brief Specification of the Root Error Status register\r
6506 *\r
6507 * This register may be used for both endpoint and root complex modes.\r
6508 *\r
6509 * On rev 0 hw, this corresponds to ROOT_ERR_ST\r
6510 * On rev 1 hw, unsupported\r
6511 *\r
6512 * @{\r
6513 */\r
6514 typedef struct pcieRootErrStReg_s {\r
6515 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6516 /**\r
6517 * @brief [rw] AER Interrupt Message Number.\r
6518 *\r
6519 * On rev 0 hw, this corresponds to AER_INT_MSG\r
6520 * On rev 1 hw, unsupported\r
6521 *\r
6522 * Field size: 5 bits\r
6523 */\r
6524 uint8_t aerIntMsg;\r
6525 /**\r
6526 * @brief [rw] Fatal Error Messages Received.\r
6527 *\r
6528 * Write 1 to clear\r
6529 *\r
6530 * On rev 0 hw, this corresponds to FERR_RCV\r
6531 * On rev 1 hw, unsupported\r
6532 *\r
6533 * Field size: 1 bit\r
6534 */\r
6535 uint8_t ferrRcv;\r
6536 /**\r
6537 * @brief [rw] Non-Fatal Error Messages Received.\r
6538 *\r
6539 * Write 1 to clear\r
6540 *\r
6541 * On rev 0 hw, this corresponds to NFERR\r
6542 * On rev 1 hw, unsupported\r
6543 *\r
6544 * Field size: 1 bit\r
6545 */\r
6546 uint8_t nfErr;\r
6547 /**\r
6548 * @brief [rw] First Uncorrectable Fatal Received.\r
6549 *\r
6550 * Write 1 to clear\r
6551 *\r
6552 * On rev 0 hw, this corresponds to UNCOR_FATAL\r
6553 * On rev 1 hw, unsupported\r
6554 *\r
6555 * Field size: 1 bit\r
6556 */\r
6557 uint8_t uncorFatal;\r
6558 /**\r
6559 * @brief [rw] Multiple Uncorrectable Error (ERR_FATAL/NONFATAL) Received.\r
6560 *\r
6561 * Write 1 to clear\r
6562 *\r
6563 * On rev 0 hw, this corresponds to MULT_FNF\r
6564 * On rev 1 hw, unsupported\r
6565 *\r
6566 * Field size: 1 bit\r
6567 */\r
6568 uint8_t multFnf;\r
6569 /**\r
6570 * @brief [rw] Uncorrectable Error (ERR_FATAL/NONFATAL) Received.\r
6571 *\r
6572 * Write 1 to clear\r
6573 *\r
6574 * On rev 0 hw, this corresponds to ERR_FNF\r
6575 * On rev 1 hw, unsupported\r
6576 *\r
6577 * Field size: 1 bit\r
6578 */\r
6579 uint8_t errFnf;\r
6580 /**\r
6581 * @brief [rw] Multiple Correctable Error (ERR_COR) Received.\r
6582 *\r
6583 * Write 1 to clear\r
6584 *\r
6585 * On rev 0 hw, this corresponds to MULT_COR\r
6586 * On rev 1 hw, unsupported\r
6587 *\r
6588 * Field size: 1 bit\r
6589 */\r
6590 uint8_t multCor;\r
6591 /**\r
6592 * @brief [rw] Correctable Error (ERR_COR) Received.\r
6593 *\r
6594 * Write 1 to clear\r
6595 *\r
6596 * On rev 0 hw, this corresponds to CORR_ERR\r
6597 * On rev 1 hw, unsupported\r
6598 *\r
6599 * Field size: 1 bit\r
6600 */\r
6601 uint8_t corrErr;\r
6602 } pcieRootErrStReg_t;\r
6603 /* @} */\r
6604 \r
6605 /**\r
6606 * @ingroup pcielld_reg_cfg_cap_ext_structures\r
6607 * @brief Specification of the Error Source Identification register\r
6608 *\r
6609 * This register may be used for both endpoint and root complex modes.\r
6610 *\r
6611 * This register is only available on rev 0 hw.\r
6612 * It is not available on rev 1 hw.\r
6613 *\r
6614 * On rev 0 hw, this corresponds to ERR_SRC_ID\r
6615 * On rev 1 hw, unsupported\r
6616 *\r
6617 * @{\r
6618 */\r
6619 typedef struct pcieErrSrcIDReg_s {\r
6620 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6621 /**\r
6622 * @brief [ro] Fatal or Non-Fatal error source identification\r
6623 *\r
6624 * On rev 0 hw, this corresponds to FNF_SRC_ID\r
6625 * On rev 1 hw, unsupported\r
6626 *\r
6627 * Field size: 16 bits\r
6628 */\r
6629 uint16_t fnfSrcID;\r
6630 /**\r
6631 * @brief [ro] Correctable error source identification\r
6632 *\r
6633 * On rev 0 hw, this corresponds to CORR_SRC_ID\r
6634 * On rev 1 hw, unsupported\r
6635 *\r
6636 * Field size: 16 bits\r
6637 */\r
6638 uint16_t corrSrcID;\r
6639 } pcieErrSrcIDReg_t;\r
6640 /* @} */\r
6641 \r
6642 /*****************************************************************************\r
6643 ********** PCIe LOCAL/REMOTE PORT LOGIC REGISTERS **************************\r
6644 ****************************************************************************/\r
6645 /**\r
6646 * @ingroup pcielld_reg_cfg_pl_structures\r
6647 * @brief Specification of the Ack Latency Time and Replay Timer register\r
6648 *\r
6649 * On rev 0 hw, this corresponds to PL_ACKTIMER\r
6650 * On rev 1 hw, this corresponds to PCIECTRL_PL_LAT_REL_TIM\r
6651 *\r
6652 * This register may be used for both endpoint and root complex modes.\r
6653 *\r
6654 * @{\r
6655 */\r
6656 typedef struct pciePlAckTimerReg_s {\r
6657 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6658 /**\r
6659 * @brief [rw] Replay Time Limit.\r
6660 *\r
6661 * For rev 0 hw:\r
6662 *\r
6663 * The replay timer expires when it reaches this limit.\r
6664 * Write sticky, a reset will not clear this field\r
6665 *\r
6666 * For rev 1 hw:\r
6667 *\r
6668 * The replay timer expires when it reaches this limit; RW 0xc0\r
6669 * The core initiates a replay upon reception of a Nak or\r
6670 * when the replay timer expires;\r
6671 * The default value depends on number of bytes (NB) per\r
6672 * cycle, which is defined by the maximum core base\r
6673 * frequency of the device PCIe core, corresponding to 250\r
6674 * MHz for PCIe-Gen2 (5 Gbps) operation.\r
6675 * The default is then updated based on the Negotiated Link\r
6676 * Width and Max_Payload_Size;\r
6677 * Note: If operating at 5 Gb/s, then the rounded-up value of\r
6678 * an additional (153 / CX_NB) cycles is added, where\r
6679 * CX_NB correspond to the number of PCIEPCS 8-bit input\r
6680 * symbols per single 16-bit lane, i.e. CX_NB=2. This\r
6681 * means at 5Gbps, 77 extra cycles should be considered\r
6682 * for the replay time limit.\r
6683 * This is for additional internal processing for received\r
6684 * TLPs and transmitted DLLPs.\r
6685 *\r
6686 * Field size: 16 bits\r
6687 */\r
6688 uint16_t rplyLmt;\r
6689 /**\r
6690 * @brief [rw] Round Trip Latency Time Limit.\r
6691 *\r
6692 * For rev 0 hw:\r
6693 *\r
6694 * The Ack/Nak latency timer expires when it reaches this limit.\r
6695 * Write sticky, a reset will not clear this field\r
6696 *\r
6697 * For rev 1 hw:\r
6698 *\r
6699 * The Ack/Nak latency timer expires when it reaches this limit;\r
6700 * The default value depends on number of bytes (NB) per\r
6701 * cycle, which is defined by the maximum core base\r
6702 * frequency of the device PCIe core, corresponding to 250\r
6703 * MHz for PCIe-Gen2 (5 Gbps) operation.\r
6704 * The default is then updated based on the Negotiated Link\r
6705 * Width and Max_Payload_Size.\r
6706 * Note: If operating at 5 Gb/s, then the rounded-up value of\r
6707 * an additional (51 / CX_NB) cycles is added, where\r
6708 * CX_NB correspond to the number of PCIEPCS 8-bit input\r
6709 * symbols per single 16-bit lane, i.e. CX_NB=2. This\r
6710 * means at 5Gbps, 26 extra cycles should be considered\r
6711 * for the acknowledge latency time limit.\r
6712 * This is for additional internal processing for received\r
6713 * TLPs and transmitted DLLPs.\r
6714 *\r
6715 * Field size: 16 bits\r
6716 */\r
6717 uint16_t rndTrpLmt;\r
6718 } pciePlAckTimerReg_t;\r
6719 /* @} */\r
6720 \r
6721 /**\r
6722 * @ingroup pcielld_reg_cfg_pl_structures\r
6723 * @brief Specification of the Other Message register\r
6724 *\r
6725 * On rev 0 hw, this corresponds to PL_OMSG\r
6726 * On rev 1 hw, this corresponds to PCIECTRL_PL_VENDOR_SPECIFIC_DLLP\r
6727 *\r
6728 * This register may be used for both endpoint and root complex modes.\r
6729 *\r
6730 * @{\r
6731 */\r
6732 typedef struct pciePlOMsgReg_s {\r
6733 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6734 /**\r
6735 * @brief [rw] Other Message Register\r
6736 *\r
6737 * It can be used to send a specific PCI Express message in which\r
6738 * case this register is programmed with the payload and bit\r
6739 * @ref pcieLnkCtrlReg_s::msgReq set to transmit the message.\r
6740 *\r
6741 * On rev 0 hw, this corresponds to OMSG\r
6742 * On rev 1 hw, this corresponds to PCIECTRL_PL_VENDOR_SPECIFIC_DLLP.\r
6743 *\r
6744 * Field size: 32 bits\r
6745 */\r
6746 uint32_t oMsg;\r
6747 } pciePlOMsgReg_t;\r
6748 /* @} */\r
6749 \r
6750 /**\r
6751 * @ingroup pcielld_reg_cfg_pl_structures\r
6752 * @brief Specification of the Port Force Link register\r
6753 *\r
6754 * On rev 0 hw, this corresponds to PL_FORCE_LINK\r
6755 * On rev 1 hw, this corresponds to PCIECTRL_PL_PT_LNK_R\r
6756 *\r
6757 * This register may be used for both endpoint and root complex modes.\r
6758 *\r
6759 * @{\r
6760 */\r
6761 typedef struct pciePlForceLinkReg_s {\r
6762 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6763 /**\r
6764 * @brief [rw] Low Power Entrance Count\r
6765 *\r
6766 * On rev 0 hw, this corresponds to LPE_CNT\r
6767 * On rev 1 hw, this corresponds to LOW_POWER_ENTR_CNT.\r
6768 *\r
6769 * Field size: 8 bits\r
6770 */\r
6771 uint8_t lpeCnt;\r
6772 /**\r
6773 * @brief [rw] Link State.\r
6774 *\r
6775 * The link state that the PCIe will be forced to when\r
6776 * @ref forceLink field is set. See @ref pcieLtssmState_e\r
6777 * for LTSSM states encoded values.\r
6778 *\r
6779 * On rev 0 hw, this corresponds to LNK_STATE\r
6780 * On rev 1 hw, this corresponds to FORCED_LINK_COMMAND\r
6781 *\r
6782 * Field size: 6 bits\r
6783 */\r
6784 uint8_t lnkState;\r
6785 /**\r
6786 * @brief [rw] Force Link.\r
6787 *\r
6788 * Forces the link to the state specified by the @ref lnkState field.\r
6789 * The Force Link pulse will trigger link re-negotiation. Self clears.\r
6790 *\r
6791 * on rev 0 hw, this corresponds to FORCE_LINK\r
6792 * on rev 1 hw, this corresponds to FORCE_LINK\r
6793 *\r
6794 * Field size: 1 bit\r
6795 */\r
6796 uint8_t forceLink;\r
6797 /**\r
6798 * @brief [rw] LTSSM state forced by setting @ref forceLink\r
6799 *\r
6800 * on rev 0 hw: unsupported\r
6801 * on rev 1 hw, this corresponds to FORCED_LTSSM_STATE\r
6802 *\r
6803 * Field size: 4 bits\r
6804 */\r
6805 uint8_t forcedLtssmState;\r
6806 /**\r
6807 * @brief [rw] Link Number. Not used for EP.\r
6808 *\r
6809 * on rev 0 hw, this corresponds to LINK_NUM\r
6810 * on rev 1 hw, this corresponds to LINK_NUM\r
6811 *\r
6812 * Field size: 8 bits\r
6813 */\r
6814 uint8_t linkNum;\r
6815 } pciePlForceLinkReg_t;\r
6816 /* @} */\r
6817 \r
6818 /**\r
6819 * @ingroup pcielld_reg_cfg_pl_structures\r
6820 * @brief Specification of the Ack Frequency register\r
6821 *\r
6822 * On rev 0 hw, this corresponds to ACK_FREQ\r
6823 * On rev 1 hw, this corresponds to PCIECTRL_PL_ACK_FREQ_ASPM\r
6824 *\r
6825 * This register may be used for both endpoint and root complex modes.\r
6826 *\r
6827 * @{\r
6828 */\r
6829 typedef struct pcieAckFreqReg_s {\r
6830 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
6831 /**\r
6832 * @brief [rw] Allow ASPM L1 without partner going to L0s.\r
6833 *\r
6834 * Set to allow entering ASPM L1 even when link partner did not\r
6835 * go to L0s. When cleared, the ASPM L1 state is entered only after idle\r
6836 * period during which both RX and TX are in L0s.\r
6837 *\r
6838 * on rev 0 hw, this corresponds to ASPM_L1\r
6839 * on rev 1 hw, this corresponds to L1_ENTR_WO_L0S\r
6840 *\r
6841 * Field size: 1 bit\r
6842 */\r
6843 uint8_t aspmL1;\r
6844 /**\r
6845 * @brief [rw] L1 entrance latency.\r
6846 *\r
6847 * The latency is set to 2^@ref l1EntryLatency microseconds with\r
6848 * the max being 64 microseconds.\r
6849 * <TABLE>\r
6850 * <TR><TH>@ref l1EntryLatency</TH><TH>latency in µs</TH></TR>\r
6851 * <TR><TD>0</TD> <TD>1µs</TD></TR>\r
6852 * <TR><TD>1</TD> <TD>2µs</TD></TR>\r
6853 * <TR><TD>2</TD> <TD>4µs</TD></TR>\r
6854 * <TR><TD>3</TD> <TD>8µs</TD></TR>\r
6855 * <TR><TD>4</TD> <TD>16µs</TD></TR>\r
6856 * <TR><TD>5</TD> <TD>32µs</TD></TR>\r
6857 * <TR><TD>6</TD> <TD>64µs</TD></TR>\r
6858 * <TR><TD>7</TD> <TD>64µs</TD></TR>\r
6859 * </TABLE>\r
6860 *\r
6861 * on rev 0 hw, this corresponds to L1_ENTRY_LATENCY\r
6862 * on rev 1 hw, this corresponds to L1_ENTR_LAT\r
6863 *\r
6864 * Field size: 3 bits\r
6865 */\r
6866 uint8_t l1EntryLatency;\r
6867 /**\r
6868 * @brief [rw] L0s entrance latency.\r
6869 *\r
6870 * The latency is set to @ref l0sEntryLatency + 1 microseconds.\r
6871 * Maximum is 7 microseconds.\r
6872 *\r
6873 * <TABLE>\r
6874 * <TR><TH>@ref l0sEntryLatency</TH><TH>latency in µs</TH></TR>\r
6875 * <TR><TD>0</TD> <TD>1µs</TD></TR>\r
6876 * <TR><TD>1</TD> <TD>2µs</TD></TR>\r
6877 * <TR><TD>2</TD> <TD>3µs</TD></TR>\r
6878 * <TR><TD>3</TD> <TD>4µs</TD></TR>\r
6879 * <TR><TD>4</TD> <TD>5µs</TD></TR>\r
6880 * <TR><TD>5</TD> <TD>6µs</TD></TR>\r
6881 * <TR><TD>6</TD> <TD>7µs</TD></TR>\r
6882 * <TR><TD>7</TD> <TD>7µs</TD></TR>\r
6883 * </TABLE>\r
6884 *\r
6885 * on rev 0 hw, this corresponds to L0S_ENTRY_LATENCY\r
6886 * on rev 1 hw, this corresponds to L0S_ENTR_LAT\r
6887 *\r
6888 * Field size: 3 bits\r
6889 */\r
6890 uint8_t l0sEntryLatency;\r
6891 /**\r
6892 * @brief [rw] Number of fast training sequences for common clock\r
6893 *\r
6894 * Number of fast training sequences when common clock is used\r
6895 * and when transitioning from L0s to L0.\r
6896 *\r
6897 * On rev 0 hw, this corresponds to COMM_NFTS\r
6898 * On rev 1 hw, this corresponds to COMMON_CLK_N_FTS\r
6899 *\r
6900 * Field size: 8 bits\r
6901 */\r
6902 uint8_t commNFts;\r
6903 /**\r
6904 * @brief [rw] Number of fast training sequences to be transmitted\r
6905 *\r
6906 * Number of fast training sequences to be transmitted\r
6907 * when transitioning from L0s to L0. Value of 0 is not supported.\r
6908 *\r
6909 * On rev 0 hw, this corresponds to NFTS\r
6910 * On rev 1 hw, this corresponds to N_FTS\r
6911 *\r
6912 * Field size: 8 bits\r
6913 */\r
6914 uint8_t nFts;\r
6915 /**\r
6916 * @brief [rw] Ack Frequency.\r
6917 *\r
6918 * Default is to wait until 255 Ack DLLPs are pending before it is sent.\r
6919 *\r
6920 * On rev 0 hw, this corresponds to ACK_FREQ\r
6921 * On rev 1 hw, this corresponds to ACK_FREQ\r
6922 *\r
6923 * Field size: 8 bits\r
6924 */\r
6925 uint8_t ackFreq;\r
6926 } pcieAckFreqReg_t;\r
6927 /* @} */\r
6928 \r
6929 /**\r
6930 * @ingroup pcielld_reg_cfg_pl_structures\r
6931 * @brief Specification of the Port Link Control Register\r
6932 *\r
6933 * On rev 0 hw, this corresponds to PL_LINK_CTRL\r
6934 * On rev 1 hw, this corresponds to PCIECTRL_PL_PT_LNK_CTRL_R\r
6935 *\r
6936 * This register may be used for both endpoint and root complex modes.\r
6937 *\r
6938 * @{\r
6939 */\r
6940 typedef struct pcieLnkCtrlReg_s {\r
6941 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
6942 /**\r
6943 * @brief [ro] Crosslink Active\r
6944 *\r
6945 * On rev 0 hw: unsupported\r
6946 * On rev 1 hw, this corresponds to CROSSLINK_ACT\r
6947 *\r
6948 * Field size: 1 bit\r
6949 */\r
6950 uint8_t crosslinkAct;\r
6951 /**\r
6952 * @brief [rw] Crosslink Enable\r
6953 *\r
6954 * On rev 0 hw: unsupported\r
6955 * On rev 1 hw, this corresponds to CROSSLINK_EN\r
6956 *\r
6957 * Field size: 1 bit\r
6958 */\r
6959 uint8_t crosslinkEn;\r
6960 /**\r
6961 * @brief [rw] Link Mode\r
6962 *\r
6963 * <TABLE>\r
6964 * <TR><TH>@ref lnkMode</TH><TH># of lanes</TH></TR>\r
6965 * <TR><TD>0x1</TD> <TD>1</TD></TR>\r
6966 * <TR><TD>0x3</TD> <TD>2</TD></TR>\r
6967 * <TR><TD>0x7</TD> <TD>4</TD></TR>\r
6968 * <TR><TD>0xf</TD> <TD>8</TD></TR>\r
6969 * <TR><TD>0x1f</TD> <TD>16</TD></TR>\r
6970 * <TR><TD>0x3f</TD> <TD>32</TD></TR>\r
6971 * <TR><TD>others</TD> <TD>reserved</TD></TR>\r
6972 * </TABLE>\r
6973 *\r
6974 * On rev 0 hw, this corresponds to LNK_MODE\r
6975 * On rev 1 hw, this corresponds to LINK_MODE\r
6976 *\r
6977 * Field size: 6 bits\r
6978 */\r
6979 uint8_t lnkMode;\r
6980 /**\r
6981 * @brief [rw] Link Rate\r
6982 *\r
6983 * For 2.5 GT/s it is 0x1. This register does not affect any functionality.\r
6984 *\r
6985 * On rev 0 hw, this corresponds to LINK_RATE\r
6986 * On rev 1 hw: unsupported.\r
6987 *\r
6988 * Field size: 4 bits\r
6989 */\r
6990 uint8_t lnkRate;\r
6991 /**\r
6992 * @brief [rw] Fast link mode\r
6993 *\r
6994 * Set all internal timers to fast mode for simulation purposes.\r
6995 *\r
6996 * On rev 0 hw, this corresponds to FLNK_MODE\r
6997 * On rev 1 hw, this corresponds to FAST_LINK\r
6998 *\r
6999 * Field size: 1 bit\r
7000 */\r
7001 uint8_t fLnkMode;\r
7002 /**\r
7003 * @brief [rw] DLL link enable\r
7004 *\r
7005 * DLL Link Enable. Enable link initialization.\r
7006 *\r
7007 * On rev 0 hw, this corresponds to DLL_EN\r
7008 * On rev 1 hw, this corresponds to DL_EN\r
7009 *\r
7010 * Field size: 1 bit\r
7011 */\r
7012 uint8_t dllEn;\r
7013 /**\r
7014 * @brief [rw] Reset Assert\r
7015 *\r
7016 * Triggers a recovery and forces the LTSSM to the Hot Reset state.\r
7017 * Downstream ports (RC ports) only.\r
7018 *\r
7019 * On rev 0 hw, this corresponds to RST_ASRT\r
7020 * On rev 1 hw, this corresponds to RESET_ASSERT\r
7021 *\r
7022 * Field size: 1 bit\r
7023 */\r
7024 uint8_t rstAsrt;\r
7025 /**\r
7026 * @brief [rw] Loopback Enable\r
7027 *\r
7028 * On rev 0 hw, this corresponds to LPBK_EN\r
7029 * On rev 1 hw, this corresponds to LB_EN\r
7030 *\r
7031 * Field size: 1 bit\r
7032 */\r
7033 uint8_t lpbkEn;\r
7034 /**\r
7035 * @brief [rw] Scramble Disable\r
7036 *\r
7037 * On rev 0 hw, this corresponds to SCRM_DIS\r
7038 * On rev 1 hw, this corresponds to SCRAMBLE_DIS\r
7039 *\r
7040 * Field size: 1 bit\r
7041 */\r
7042 uint8_t scrmDis;\r
7043 /**\r
7044 * @brief [rw] Other Message Request\r
7045 *\r
7046 * Set to transmit the message contained in @ref pciePlOMsgReg_s\r
7047 *\r
7048 * On rev 0 hw, this corresponds to OMSG_REQ\r
7049 * On rev 1 hw, this corresponds to VEN_DLLP_REQ\r
7050 *\r
7051 * Field size: 1 bit\r
7052 */\r
7053 uint8_t msgReq;\r
7054 } pcieLnkCtrlReg_t;\r
7055 /* @} */\r
7056 \r
7057 /**\r
7058 * @ingroup pcielld_reg_cfg_pl_structures\r
7059 * @brief Specification of the Lane Skew register\r
7060 *\r
7061 * On rev 0 hw, this corresponds to LANE_SKEW\r
7062 * On rev 1 hw, this corresponds to PCIECTRL_PL_LN_SKW_R\r
7063 *\r
7064 * This register may be used for both endpoint and root complex modes.\r
7065 *\r
7066 * @{\r
7067 */\r
7068 typedef struct pcieLaneSkewReg_s {\r
7069 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
7070 /**\r
7071 * @brief [rw] Set to Disable Lane to Lane Deskew.\r
7072 *\r
7073 * On rev 0 hw, this corresponds to L2L_DESKEW\r
7074 * On rev 1 hw, this corresponds to DIS_L2L_SKEW\r
7075 *\r
7076 * Field size: 1 bit\r
7077 */\r
7078 uint8_t l2Deskew;\r
7079 /**\r
7080 * @brief [rw] Set to disable Ack and Nak DLLP transmission.\r
7081 *\r
7082 * On rev 0 hw, this corresponds to ACK_DISABLE\r
7083 * On rev 1 hw, this corresponds to ACKNAK_DIS\r
7084 *\r
7085 * Field size: 1 bit\r
7086 */\r
7087 uint8_t ackDisable;\r
7088 /**\r
7089 * @brief [rw] Set to disable transmission of Flow Control DLLPs.\r
7090 *\r
7091 * On rev 0 hw, this corresponds to FC_DISABLE\r
7092 * On rev 1 hw, this corresponds to FC_DIS\r
7093 *\r
7094 * Field size: 1 bit\r
7095 */\r
7096 uint8_t fcDisable;\r
7097 /**\r
7098 * @brief [rw] Insert Lane Skew for Transmit.\r
7099 *\r
7100 * The value is in units of one symbol time. Thus a value 0x02 will\r
7101 * force a skew of two symbol times for that lane. Max allowed is\r
7102 * 5 symbol times. This 24 bit field is used for programming skew\r
7103 * for eight lanes with three bits per lane.\r
7104 *\r
7105 * On rev 0 hw, this corresponds to LANE_SKEW\r
7106 * On rev 1 hw, this corresponds to LANE_SKEW\r
7107 *\r
7108 * Field size: 24 bits\r
7109 */\r
7110 uint32_t laneSkew;\r
7111 } pcieLaneSkewReg_t;\r
7112 /* @} */\r
7113 \r
7114 /**\r
7115 * @ingroup pcielld_reg_cfg_pl_structures\r
7116 * @brief Specification of the Symbol Number register\r
7117 *\r
7118 * On rev 0 hw, this corresponds to SYM_NUM\r
7119 * On rev 1 hw, this corresponds to PCIECTRL_PL_SYMB_N_R\r
7120 *\r
7121 * This register may be used for both endpoint and root complex modes.\r
7122 *\r
7123 * @{\r
7124 */\r
7125 typedef struct pcieSymNumReg_s {\r
7126 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
7127 /**\r
7128 * @brief [rw] Configuration requests targeted at function numbers above this\r
7129 * value will result in UR response.\r
7130 *\r
7131 * On rev 0 hw, this corresponds to MAX_FUNC (3 bits)\r
7132 * On rev 1 hw, this corresponds to MAX_FUNC (8 bits)\r
7133 *\r
7134 * Field size: 8 bits\r
7135 */\r
7136 uint8_t maxFunc;\r
7137 /**\r
7138 * @brief [rw] Timer Modifier for Flow Control Watchdog Timer.\r
7139 *\r
7140 * Increases the timer value for Flow Control watchdog timer in\r
7141 * increments of 16 clock cycles.\r
7142 *\r
7143 * On rev 0 hw, this corresponds to FCWATCH_TIMER\r
7144 * On rev 1 hw: unsupported\r
7145 *\r
7146 * Field size: 5 bits\r
7147 */\r
7148 uint8_t fcWatchTimer;\r
7149 /**\r
7150 * @brief [rw] Timer Modifier for Ack/Nak Latency Timer.\r
7151 *\r
7152 * Increases the timer value for the Ack/Nak latency timer in\r
7153 * increments of 64 clock periods.\r
7154 *\r
7155 * On rev 0 hw, this corresponds to ACK_LATENCY_TIMER\r
7156 * On rev 1 hw, this corresponds to ACK_LATENCY_INC\r
7157 *\r
7158 * Field size: 5 bits\r
7159 */\r
7160 uint8_t ackLatencyTimer;\r
7161 /**\r
7162 * @brief [rw] Timer for replaying TLPs in increments of 64 clock cycles.\r
7163 *\r
7164 * Increases the timer value for Ack/Nak latency timer in increments of\r
7165 * 64 clock cycles.\r
7166 *\r
7167 * On rev 0 hw, this corresponds to REPLAY_TIMER\r
7168 * On rev 1 hw, this corresponds to REPLAY_ADJ\r
7169 *\r
7170 * Field size: 5 bits\r
7171 */\r
7172 uint8_t replayTimer;\r
7173 /**\r
7174 * @brief [rw] Number of SKP Symbols.\r
7175 *\r
7176 * On rev 0 hw, this corresponds to SKP_COUNT\r
7177 * On rev 1 hw: unsupported\r
7178 *\r
7179 * Field size: 3 bits\r
7180 */\r
7181 uint8_t skpCount;\r
7182 /**\r
7183 * @brief [rw] Number of TS2 Symbols.\r
7184 *\r
7185 * This field does not affect any functionality.\r
7186 *\r
7187 * On rev 0 hw, this corresponds to NUM_TS2_SYMBOLS\r
7188 * On rev 1 hw: unsupported\r
7189 *\r
7190 * Field size: 4 bits\r
7191 */\r
7192 uint8_t numTs2Symbols;\r
7193 /**\r
7194 * @brief [rw] Number of TS Symbols.\r
7195 *\r
7196 * Set the number of TS identifier symbols that are sent in TS1 and TS2\r
7197 * ordered sets.\r
7198 *\r
7199 * On rev 0 hw, this corresponds to TS_COUNT\r
7200 * On rev 1 hw: unsupported\r
7201 *\r
7202 * Field size: 4 bits\r
7203 */\r
7204 uint8_t tsCount;\r
7205 } pcieSymNumReg_t;\r
7206 /* @} */\r
7207 \r
7208 /**\r
7209 * @ingroup pcielld_reg_cfg_pl_structures\r
7210 * @brief Specification of the Symbol Timer and Filter Mask register\r
7211 *\r
7212 * On rev 0 hw, this corresponds to SYMTIMER_FLTMASK\r
7213 * On rev 1 hw, this corresponds to PCIECTRL_PL_SYMB_T_R\r
7214 *\r
7215 * This register may be used for both endpoint and root complex modes.\r
7216 *\r
7217 * @{\r
7218 */\r
7219 typedef struct pcieSymTimerFltMaskReg_s {\r
7220 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
7221 /**\r
7222 * @brief [rw] 1 = Allow CFG transaction being received on RC.\r
7223 *\r
7224 * On rev 0 hw, this corresponds to F1_CFG_DROP\r
7225 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7226 *\r
7227 * Field size: 1 bit\r
7228 */\r
7229 uint8_t f1CfgDrop;\r
7230 /**\r
7231 * @brief [rw] 1 = Allow IO transaction being received on RC.\r
7232 *\r
7233 * On rev 0 hw, this corresponds to F1_IO_DROP\r
7234 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7235 *\r
7236 * Field size: 1 bit\r
7237 */\r
7238 uint8_t f1IoDrop;\r
7239 /**\r
7240 * @brief [rw] 1 = Allow MSG transaction being received on RC.\r
7241 *\r
7242 * On rev 0 hw, this corresponds to F1_MSG_DROP\r
7243 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7244 *\r
7245 * Field size: 1 bit\r
7246 */\r
7247 uint8_t f1MsgDrop;\r
7248 /**\r
7249 * @brief [rw] 1 = Allow completion TLPs with ECRC errors to be passed up.\r
7250 *\r
7251 * On rev 0 hw, this corresponds to F1_CPL_ECRC_DROP\r
7252 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7253 *\r
7254 * Field size: 1 bit\r
7255 */\r
7256 uint8_t f1CplEcrcDrop;\r
7257 /**\r
7258 * @brief [rw] 1 = Allow TLPs with ECRC errors to be passed up.\r
7259 *\r
7260 * On rev 0 hw, this corresponds to F1_ECRC_DROP\r
7261 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7262 *\r
7263 * Field size: 1 bit\r
7264 */\r
7265 uint8_t f1EcrcDrop;\r
7266 /**\r
7267 * @brief [rw] 1 = Mask length match for received completion TLPs.\r
7268 *\r
7269 * On rev 0 hw, this corresponds to F1_CPL_LEN_TEST\r
7270 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7271 *\r
7272 * Field size: 1 bit\r
7273 */\r
7274 uint8_t f1CplLenTest;\r
7275 /**\r
7276 * @brief [rw] 1 = Mask attribute match on received completion TLPs.\r
7277 *\r
7278 * On rev 0 hw, this corresponds to F1_CPL_ATTR_TEST\r
7279 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7280 *\r
7281 * Field size: 1 bit\r
7282 */\r
7283 uint8_t f1CplAttrTest;\r
7284 /**\r
7285 * @brief [rw] 1 = Mask traffic class match on received completion TLPs.\r
7286 *\r
7287 * On rev 0 hw, this corresponds to F1_CPL_TC_TEST\r
7288 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7289 *\r
7290 * Field size: 1 bit\r
7291 */\r
7292 uint8_t f1CplTcTest;\r
7293 /**\r
7294 * @brief [rw] 1 = Mask function match for received completion TLPs.\r
7295 *\r
7296 * On rev 0 hw, this corresponds to F1_CPL_FUNC_TEST\r
7297 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7298 *\r
7299 * Field size: 1 bit\r
7300 */\r
7301 uint8_t f1CplFuncTest;\r
7302 /**\r
7303 * @brief [rw] 1 = Mask request ID match for received completion TLPs.\r
7304 *\r
7305 * On rev 0 hw, this corresponds to F1_CPL_REQID_TEST\r
7306 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7307 *\r
7308 * Field size: 1 bit\r
7309 */\r
7310 uint8_t f1CplReqIDTest;\r
7311 /**\r
7312 * @brief [rw] 1 = Mask tag error rules for received completion TLPs.\r
7313 *\r
7314 * On rev 0 hw, this corresponds to F1_CPL_TAGERR_TEST\r
7315 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7316 *\r
7317 * Field size: 1 bit\r
7318 */\r
7319 uint8_t f1CplTagErrTest;\r
7320 /**\r
7321 * @brief [rw] 1 = Treat locked read TLPs as supported for EP, UR for RC.\r
7322 *\r
7323 * On rev 0 hw, this corresponds to F1_LOCKED_RD_AS_UR\r
7324 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7325 *\r
7326 * Field size: 1 bit\r
7327 */\r
7328 uint8_t f1LockedRdAsUr;\r
7329 /**\r
7330 * @brief [rw] 1 = Treat type 1 CFG TLPs as supported for EP and UR for RC.\r
7331 *\r
7332 * On rev 0 hw, this corresponds to F1_RE_AS_US\r
7333 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7334 *\r
7335 * Field size: 1 bit\r
7336 */\r
7337 uint8_t f1Cfg1ReAsUs;\r
7338 /**\r
7339 * @brief [rw] 1 = Treat out-of-BAR TLPs as supported requests.\r
7340 *\r
7341 * On rev 0 hw, this corresponds to F1_UR_OUT_OF_BAR\r
7342 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7343 *\r
7344 * Field size: 1 bit\r
7345 */\r
7346 uint8_t f1UrOutOfBar;\r
7347 /**\r
7348 * @brief [rw] 1 = Treat poisoned TLPs as supported requests.\r
7349 *\r
7350 * On rev 0 hw, this corresponds to F1_UR_POISON\r
7351 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7352 *\r
7353 * Field size: 1 bit\r
7354 */\r
7355 uint8_t f1UrPoison;\r
7356 /**\r
7357 * @brief [rw] 1 = Treat function mismatched TLPs as supported requests.\r
7358 *\r
7359 * On rev 0 hw, this corresponds to F1_UR_FUN_MISMATCH\r
7360 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
7361 *\r
7362 * Field size: 1 bit\r
7363 */\r
7364 uint8_t f1UrFunMismatch;\r
7365 /**\r
7366 * @brief [rw] 1 = Disable Flow Control watchdog timer.\r
7367 *\r
7368 * On rev 0 hw, this corresponds to FC_WDOG_DISABLE\r
7369 * On rev 1 hw, this corresponds to DIS_FC_TIM\r
7370 *\r
7371 * Field size: 1 bit\r
7372 */\r
7373 uint8_t fcWdogDisable;\r
7374 /**\r
7375 * @brief [rw] Wait time between SKP ordered sets\r
7376 *\r
7377 * Number of symbol times to wait between transmitting SKP\r
7378 * ordered sets. For example, for a setting of 1536 decimal,\r
7379 * the wait will be for 1537 symbol times.\r
7380 *\r
7381 * On rev 0 hw, this corresponds to SKP_VALUE\r
7382 * On rev 1 hw, this corresponds to SKP_INT\r
7383 *\r
7384 * Field size: 11 bits\r
7385 */\r
7386 uint16_t skpValue;\r
7387 } pcieSymTimerFltMaskReg_t;\r
7388 /* @} */\r
7389 \r
7390 /**\r
7391 * @ingroup pcielld_reg_cfg_pl_structures\r
7392 * @brief Specification of the Filter Mask 2 register\r
7393 *\r
7394 * On rev 0 hw, this corresponds to FLT_MASK2\r
7395 * On rev 1 hw, this corresponds to FLT_MSK_2\r
7396 *\r
7397 * This register may be used for both endpoint and root complex modes.\r
7398 *\r
7399 * @{\r
7400 */\r
7401 typedef struct pcieFltMask2Reg_s {\r
7402 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
7403 /**\r
7404 * @brief [rw] 1 = Enable the filter to handle flush request.\r
7405 *\r
7406 * On rev 0 hw, this corresponds to FLUSH_REQ\r
7407 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
7408 *\r
7409 * Field size: 1 bit\r
7410 */\r
7411 uint8_t flushReq;\r
7412 /**\r
7413 * @brief [rw] 1 = Disable DLLP abort for unexpected CPL.\r
7414 *\r
7415 * On rev 0 hw, this corresponds to DLLP_ABORT\r
7416 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
7417 *\r
7418 * Field size: 1 bit\r
7419 */\r
7420 uint8_t dllpAbort;\r
7421 /**\r
7422 * @brief [rw] 1 = Disable dropping of Vendor MSG Type 1.\r
7423 *\r
7424 * On rev 0 hw, this corresponds to VMSG1_DROP\r
7425 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
7426 *\r
7427 * Field size: 1 bit\r
7428 */\r
7429 uint8_t vmsg1Drop;\r
7430 /**\r
7431 * @brief [rw] 1 = Disable dropping of Vendor MSG Type 0 with UR error reporting.\r
7432 *\r
7433 * On rev 0 hw, this corresponds to VMSG0_DROP\r
7434 * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
7435 *\r
7436 * Field size: 1 bit\r
7437 */\r
7438 uint8_t vmsg0Drop;\r
7439 } pcieFltMask2Reg_t;\r
7440 /* @} */\r
7441 \r
7442 /**\r
7443 * @ingroup pcielld_reg_cfg_pl_structures\r
7444 * @brief Specification of the Debug0 Register\r
7445 *\r
7446 * On rev 0 hw, this corresponds to DEBUG0\r
7447 * On rev 1 hw, this corresponds to reserved\r
7448 *\r
7449 * This register may be used for both endpoint and root complex modes.\r
7450 *\r
7451 * @{\r
7452 */\r
7453 typedef struct pcieDebug0Reg_s {\r
7454 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7455 /**\r
7456 * @brief [ro] Link control bits advertised by link partner.\r
7457 *\r
7458 * On rev 0 hw, this corresponds to TS_LNK_CTRL\r
7459 * On rev 1 hw, unsupported\r
7460 *\r
7461 * Field size: 4 bits\r
7462 */\r
7463 uint8_t tsLnkCtrl;\r
7464 /**\r
7465 * @brief [ro] Currently receiving k237 (PAD) in place of lane number.\r
7466 *\r
7467 * On rev 0 hw, this corresponds to TS_LANE_K237\r
7468 * On rev 1 hw, unsupported\r
7469 *\r
7470 * Field size: 1 bit\r
7471 */\r
7472 uint8_t tsLaneK237;\r
7473 /**\r
7474 * @brief [ro] Currently receiving k237 (PAD) in place of link number.\r
7475 *\r
7476 * On rev 0 hw, this corresponds to TS_LINK_K237\r
7477 * On rev 1 hw, unsupported\r
7478 *\r
7479 * Field size: 1 bit\r
7480 */\r
7481 uint8_t tsLinkK237;\r
7482 /**\r
7483 * @brief [ro] Receiver is receiving logical idle\r
7484 *\r
7485 * On rev 0 hw, this corresponds to RCVD_IDLE0\r
7486 * On rev 1 hw, unsupported\r
7487 *\r
7488 * Field size: 1 bit\r
7489 */\r
7490 uint8_t rcvdIdle0;\r
7491 /**\r
7492 * @brief [ro] 2nd symbol is also idle\r
7493 *\r
7494 * On rev 0 hw, this corresponds to RCVD_IDLE1\r
7495 * On rev 1 hw, unsupported\r
7496 *\r
7497 * Field size: 1 bit\r
7498 */\r
7499 uint8_t rcvdIdle1;\r
7500 /**\r
7501 * @brief [ro] Pipe TX data\r
7502 *\r
7503 * On rev 0 hw, this corresponds to PIPE_TXDATA\r
7504 * On rev 1 hw, unsupported\r
7505 *\r
7506 * Field size: 16 bits\r
7507 */\r
7508 uint16_t pipeTxData;\r
7509 /**\r
7510 * @brief [ro] Pipe transmit K indication\r
7511 *\r
7512 * On rev 0 hw, this corresponds to PIPE_TXDATAK\r
7513 * On rev 1 hw, unsupported\r
7514 *\r
7515 * Field size: 2 bits\r
7516 */\r
7517 uint8_t pipeTxDataK;\r
7518 /**\r
7519 * @brief [ro] A skip ordered set has been transmitted.\r
7520 *\r
7521 * On rev 0 hw, this corresponds to TXB_SKIP_TX\r
7522 * On rev 1 hw, unsupported\r
7523 *\r
7524 * Field size: 1 bit\r
7525 */\r
7526 uint8_t skipTx;\r
7527 /**\r
7528 * @brief [ro] LTSSM current state @ref pcieLtssmState_e\r
7529 *\r
7530 * On rev 0 hw, this corresponds to LTSSM_STATE\r
7531 * On rev 1 hw, unsupported\r
7532 *\r
7533 * Field size: 5 bits\r
7534 */\r
7535 uint8_t ltssmState;\r
7536 } pcieDebug0Reg_t;\r
7537 /* @} */\r
7538 \r
7539 /**\r
7540 * @ingroup pcielld_reg_cfg_pl_structures\r
7541 * @brief Specification of the Debug 1 Register\r
7542 *\r
7543 * On rev 0 hw, this corresponds to DEBUG1\r
7544 * On rev 1 hw, this corresponds to reserved\r
7545 *\r
7546 * This register may be used for both endpoint and root complex modes.\r
7547 *\r
7548 * @{\r
7549 */\r
7550 typedef struct pcieDebug1Reg_s {\r
7551 uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
7552 /**\r
7553 * @brief [rw] Scrambling disabled for the link.\r
7554 *\r
7555 * On rev 0 hw, this corresponds to SCRAMBLER_DISABLE\r
7556 * On rev 1 hw, unsupported\r
7557 *\r
7558 * Field size: 1 bit\r
7559 */\r
7560 uint8_t scramblerDisable;\r
7561 /**\r
7562 * @brief [rw] LTSSM in DISABLE state. Link inoperable.\r
7563 *\r
7564 * On rev 0 hw, this corresponds to LINK_DISABLE\r
7565 * On rev 1 hw, unsupported\r
7566 *\r
7567 * Field size: 1 bit\r
7568 */\r
7569 uint8_t linkDisable;\r
7570 /**\r
7571 * @brief [rw] LTSSM performing link training.\r
7572 *\r
7573 * On rev 0 hw, this corresponds to LINK_IN_TRAINING\r
7574 * On rev 1 hw, unsupported\r
7575 *\r
7576 * Field size: 1 bit\r
7577 */\r
7578 uint8_t linkInTraining;\r
7579 /**\r
7580 * @brief [rw] LTSSM testing for polarity reversal.\r
7581 *\r
7582 * On rev 0 hw, this corresponds to RCVR_REVRS_POL_EN\r
7583 * On rev 1 hw, unsupported\r
7584 *\r
7585 * Field size: 1 bit\r
7586 */\r
7587 uint8_t rcvrRevrsPolEn;\r
7588 /**\r
7589 * @brief [rw] LTSSM-negotiated link reset.\r
7590 *\r
7591 * On rev 0 hw, this corresponds to TRAINING_RST_N\r
7592 * On rev 1 hw, unsupported\r
7593 *\r
7594 * Field size: 1 bit\r
7595 */\r
7596 uint8_t trainingRstN;\r
7597 /**\r
7598 * @brief [rw] PIPE receiver detect/loopback request.\r
7599 *\r
7600 * On rev 0 hw, this corresponds to PIPE_TXDETECTRX_LB\r
7601 * On rev 1 hw, unsupported\r
7602 *\r
7603 * Field size: 1 bit\r
7604 */\r
7605 uint8_t pipeTxdetectrxLb;\r
7606 /**\r
7607 * @brief [rw] PIPE transmit electrical idle request.\r
7608 *\r
7609 * On rev 0 hw, this corresponds to PIPE_TXELECIDLE\r
7610 * On rev 1 hw, unsupported\r
7611 *\r
7612 * Field size: 1 bit\r
7613 */\r
7614 uint8_t pipeTxelecidle;\r
7615 /**\r
7616 * @brief [rw] PIPE transmit compliance request.\r
7617 *\r
7618 * On rev 0 hw, this corresponds to PIPE_TXCOMPLIANCE\r
7619 * On rev 1 hw, unsupported\r
7620 *\r
7621 * Field size: 1 bit\r
7622 */\r
7623 uint8_t pipeTxcompliance;\r
7624 /**\r
7625 * @brief [rw] Application request to initiate training reset.\r
7626 *\r
7627 * On rev 0 hw, this corresponds to APP_INIT_RST\r
7628 * On rev 1 hw, unsupported\r
7629 *\r
7630 * Field size: 1 bit\r
7631 */\r
7632 uint8_t appInitRst;\r
7633 /**\r
7634 * @brief [rw] Link number advertised/confirmed by link partner.\r
7635 *\r
7636 * On rev 0 hw, this corresponds to RMLH_TS_LINK_NUM\r
7637 * On rev 1 hw, unsupported\r
7638 *\r
7639 * Field size: 8 bits\r
7640 */\r
7641 uint8_t rmlhTsLinkNum;\r
7642 /**\r
7643 * @brief [rw] LTSSM reports PHY link up.\r
7644 *\r
7645 * On rev 0 hw, this corresponds to XMLH_LINK_UP\r
7646 * On rev 1 hw, unsupported\r
7647 *\r
7648 * Field size: 1 bit\r
7649 */\r
7650 uint8_t xmlhLinkUp;\r
7651 /**\r
7652 * @brief [rw] Receiver reports skip reception.\r
7653 *\r
7654 * On rev 0 hw, this corresponds to RMLH_INSKIP_RCV\r
7655 * On rev 1 hw, unsupported\r
7656 *\r
7657 * Field size: 1 bit\r
7658 */\r
7659 uint8_t rmlhInskipRcv;\r
7660 /**\r
7661 * @brief [rw] TS1 training sequence received (pulse).\r
7662 *\r
7663 * On rev 0 hw, this corresponds to RMLH_TS1_RCVD\r
7664 * On rev 1 hw, unsupported\r
7665 *\r
7666 * Field size: 1 bit\r
7667 */\r
7668 uint8_t rmlhTs1Rcvd;\r
7669 /**\r
7670 * @brief [rw] TS2 training sequence received (pulse).\r
7671 *\r
7672 * On rev 0 hw, this corresponds to RMLH_TS2_RCVD\r
7673 * On rev 1 hw, unsupported\r
7674 *\r
7675 * Field size: 1 bit\r
7676 */\r
7677 uint8_t rmlhTs2Rcvd;\r
7678 /**\r
7679 * @brief [rw] Receiver detected lane reversal.\r
7680 *\r
7681 * On rev 0 hw, this corresponds to RMLH_RCVD_LANE_REV\r
7682 * On rev 1 hw, unsupported\r
7683 *\r
7684 * Field size: 1 bit\r
7685 */\r
7686 uint8_t rmlhRcvdLaneRev;\r
7687 } pcieDebug1Reg_t;\r
7688 /* @} */\r
7689 \r
7690 \r
7691 /**\r
7692 * @ingroup pcielld_reg_cfg_pl_structures\r
7693 * @brief Specification of the Gen2 Register\r
7694 *\r
7695 * On rev 0 hw, this corresponds to PL_GEN2\r
7696 * On rev 1 hw, this corresponds to PCIECTRL_PL_WIDTH_SPEED_CTL\r
7697 *\r
7698 * This register may be used for both endpoint and root complex modes.\r
7699 *\r
7700 * @{\r
7701 */\r
7702 typedef struct pcieGen2Reg_s {\r
7703 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7704 /**\r
7705 * @brief [rw] Set de-emphasis level for upstream (EP) ports\r
7706 *\r
7707 * On rev 0 hw, this corresponds to DEEMPH\r
7708 * On rev 1 hw, this corresponds to CFG_UP_SEL_DEEMPH\r
7709 *\r
7710 * Field size: 1 bit\r
7711 */\r
7712 uint8_t deemph;\r
7713 /**\r
7714 * @brief [rw] Configure TX compliance receive bit.\r
7715 *\r
7716 * On rev 0 hw, this corresponds to CFG_TX_CMPL\r
7717 * On rev 1 hw, this corresponds to CFG_TX_COMPLIANCE_RCV\r
7718 *\r
7719 * Field size: 1 bit\r
7720 */\r
7721 uint8_t txCmpl;\r
7722 /**\r
7723 * @brief [rw] Configure PHY TX Swing\r
7724 *\r
7725 * 0 = Low Swing\n\r
7726 * 1 = Full Swing\r
7727 *\r
7728 * On rev 0 hw, this corresponds to CFG_TX_SWING\r
7729 * On rev 1 hw, this corresponds to CFG_PHY_TXSWING\r
7730 *\r
7731 * Field size: 1 bit\r
7732 */\r
7733 uint8_t txSwing;\r
7734 /**\r
7735 * @brief [rw] direct speed change\r
7736 *\r
7737 * 0 = Indicates to the LTSSM not to initiate a speed change to Gen2\r
7738 * after the link is initialized at Gen1 speed.\n\r
7739 * 1 = Indicates to the LTSSM to initiate a speed change to Gen2\r
7740 * after the link is initialized at Gen1 speed.\r
7741 *\r
7742 * On rev 0 hw, this corresponds to DIR_SPD\r
7743 * On rev 1 hw, this corresponds to CFG_DIRECTED_SPEED_CHANGE\r
7744 *\r
7745 * Field size: 1 bit\r
7746 */\r
7747 uint8_t dirSpd;\r
7748 /**\r
7749 * @brief [rw] Lane enable. 1h=x1, 2h=x2. Other values reserved.\r
7750 *\r
7751 * On rev 0 hw, this corresponds to LN_EN\r
7752 * On rev 1 hw, this corresponds to CFG_LANE_EN\r
7753 *\r
7754 * Field size: 9 bits\r
7755 */\r
7756 uint16_t lnEn;\r
7757 /**\r
7758 * @brief [rw] number of fast training sequences\r
7759 *\r
7760 * On rev 0 hw, this corresponds to NUM_FTS\r
7761 * On rev 1 hw, this corresponds to CFG_GEN2_N_FTS\r
7762 *\r
7763 * Field size: 8 bit\r
7764 */\r
7765 uint8_t numFts;\r
7766 } pcieGen2Reg_t;\r
7767 /* @} */\r
7768 \r
7769 /**\r
7770 * @ingroup pcielld_reg_cfg_pl_structures\r
7771 * @brief Specification of the AXI Multiple Outbound Decomposed NP SubRequests\r
7772 * Control Register (Sticky)\r
7773 *\r
7774 * On rev 0 hw: unavailable\r
7775 * On rev 1 hw, this corresponds to PCIECTRL_PL_OBNP_SUBREQ_CTRL\r
7776 *\r
7777 * This register may be used for both endpoint and root complex modes.\r
7778 *\r
7779 * @{\r
7780 */\r
7781 typedef struct pciePlconfObnpSubreqCtrlReg_s {\r
7782 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7783 /**\r
7784 * @brief [rw] Enable AXI Multiple Outbound Decomposed NP Sub-Requests\r
7785 *\r
7786 * On rev 1 hw, this corresponds to EN_OBNP_SUBREQ\r
7787 *\r
7788 * Field size: 1 bit\r
7789 */\r
7790 uint8_t enObnpSubreq;\r
7791 } pciePlconfObnpSubreqCtrlReg_t;\r
7792 /* @} */\r
7793 \r
7794 /**\r
7795 * @ingroup pcielld_reg_cfg_pl_structures\r
7796 * @brief Specification of the Transmit Posted FC Credit Status Register (Sticky)\r
7797 *\r
7798 * On rev 0 hw: unavailable\r
7799 * On rev 1 hw, this corresponds to PCIECTRL_PL_TR_P_STS_R\r
7800 *\r
7801 * This register may be used for both endpoint and root complex modes.\r
7802 *\r
7803 * This is an entirely [ro] register\r
7804 *\r
7805 * @{\r
7806 */\r
7807 typedef struct pciePlconfTrPStsRReg_s {\r
7808 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7809 /**\r
7810 * @brief [ro] Transmit Posted Data FC Credits\r
7811 *\r
7812 * On rev 1 hw, this corresponds to PD_CRDT\r
7813 *\r
7814 * Field size: 12 bits\r
7815 */\r
7816 uint16_t pdCrdt;\r
7817 /**\r
7818 * @brief [ro] Transmit Posted Header FC Credits\r
7819 *\r
7820 * On rev 1 hw, this corresponds to PH_CRDT\r
7821 *\r
7822 * Field size: 8 bits\r
7823 */\r
7824 uint8_t phCrdt;\r
7825 } pciePlconfTrPStsRReg_t;\r
7826 /* @} */\r
7827 \r
7828 /**\r
7829 * @ingroup pcielld_reg_cfg_pl_structures\r
7830 * @brief Specification of the Transmit Non-Posted FC Credit Status Register\r
7831 * (Sticky)\r
7832 *\r
7833 * On rev 0 hw: unavailable\r
7834 * On rev 1 hw, this corresponds to PCIECTRL_PL_TR_NP_STS_R\r
7835 *\r
7836 * This register may be used for both endpoint and root complex modes.\r
7837 *\r
7838 * This is an entirely [ro] register\r
7839 *\r
7840 * @{\r
7841 */\r
7842 typedef struct pciePlconfTrNpStsRReg_s {\r
7843 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7844 /**\r
7845 * @brief [ro] Transmit Non-Posted Data FC Credits\r
7846 *\r
7847 * On rev 1 hw, this corresponds to NPD_CRDT\r
7848 *\r
7849 * Field size: 12 bits\r
7850 */\r
7851 uint16_t npdCrdt;\r
7852 /**\r
7853 * @brief [ro] Transmit Non-Posted Header FC Credits\r
7854 *\r
7855 * On rev 1 hw, this corresponds to NPH_CRDT\r
7856 *\r
7857 * Field size: 8 bits\r
7858 */\r
7859 uint8_t nphCrdt;\r
7860 } pciePlconfTrNpStsRReg_t;\r
7861 /* @} */\r
7862 \r
7863 /**\r
7864 * @ingroup pcielld_reg_cfg_pl_structures\r
7865 * @brief Specification of the Transmit Completion FC Credit Status Register\r
7866 * (Sticky)\r
7867 *\r
7868 * On rev 0 hw: unavailable\r
7869 * On rev 1 hw, this corresponds to PCIECTRL_PL_TR_C_STS_R\r
7870 *\r
7871 * This register may be used for both endpoint and root complex modes.\r
7872 *\r
7873 * This is an entirely [ro] register\r
7874 *\r
7875 * @{\r
7876 */\r
7877 typedef struct pciePlconfTrCStsRReg_s {\r
7878 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7879 /**\r
7880 * @brief [ro] Transmit Completion Data FC Credits\r
7881 *\r
7882 * On rev 1 hw, this corresponds to NPD_CRDT\r
7883 *\r
7884 * Field size: 12 bits\r
7885 */\r
7886 uint16_t cpldCrdt;\r
7887 /**\r
7888 * @brief [ro] Transmit Completion Header FC Credits\r
7889 *\r
7890 * On rev 1 hw, this corresponds to NPH_CRDT\r
7891 *\r
7892 * Field size: 8 bits\r
7893 */\r
7894 uint8_t cplhCrdt;\r
7895 } pciePlconfTrCStsRReg_t;\r
7896 /* @} */\r
7897 \r
7898 /**\r
7899 * @ingroup pcielld_reg_cfg_pl_structures\r
7900 * @brief Specification of the Queue Status Register (Sticky)\r
7901 *\r
7902 * On rev 0 hw: unavailable\r
7903 * On rev 1 hw, this corresponds to PCIECTRL_PL_Q_STS_R\r
7904 *\r
7905 * This register may be used for both endpoint and root complex modes.\r
7906 *\r
7907 * @{\r
7908 */\r
7909 typedef struct pciePlconfQStsRReg_s {\r
7910 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7911 /**\r
7912 * @brief [ro] Received TLP FC Credits Not Returned\r
7913 *\r
7914 * On rev 1 hw, this corresponds to CRDT_NOT_RTRN\r
7915 *\r
7916 * Field size: 1 bit\r
7917 */\r
7918 uint8_t crdtNotRtrn;\r
7919 /**\r
7920 * @brief [ro] Transmit Retry Buffer Not Empty\r
7921 *\r
7922 * On rev 1 hw, this corresponds to RTYB_NOT_EMPTY\r
7923 *\r
7924 * Field size: 1 bit\r
7925 */\r
7926 uint8_t rtybNotEmpty;\r
7927 /**\r
7928 * @brief [ro] Received Queue Not Empty\r
7929 *\r
7930 * On rev 1 hw, this corresponds to RCVQ_NOT_EMPTY\r
7931 *\r
7932 * Field size: 1 bit\r
7933 */\r
7934 uint8_t rcvqNotEmpty;\r
7935 /**\r
7936 * @brief [rw] FC Latency Timer Override Value\r
7937 *\r
7938 * On rev 1 hw, this corresponds to FC_LATENCY_OVR\r
7939 *\r
7940 * Field size: 13 bits\r
7941 */\r
7942 uint16_t fcLatencyOvr;\r
7943 /**\r
7944 * @brief [rw] FC Latency Timer Override Enable\r
7945 *\r
7946 * On rev 1 hw, this corresponds to FC_LATENCY_OVR_EN\r
7947 *\r
7948 * Field size: 1 bit\r
7949 */\r
7950 uint8_t fcLatencyOvrEn;\r
7951 } pciePlconfQStsRReg_t;\r
7952 /* @} */\r
7953 \r
7954 /**\r
7955 * @ingroup pcielld_reg_cfg_pl_structures\r
7956 * @brief Specification of the VC Transmit Arbitration Register 1 (Sticky)\r
7957 *\r
7958 * On rev 0 hw: unavailable\r
7959 * On rev 1 hw, this corresponds to PCIECTRL_PL_VC_TR_A_R1\r
7960 *\r
7961 * This register may be used for both endpoint and root complex modes.\r
7962 *\r
7963 * This is an entirely [ro] register\r
7964 *\r
7965 * @{\r
7966 */\r
7967 typedef struct pciePlconfVcTrAR1Reg_s {\r
7968 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
7969 /**\r
7970 * @brief [ro] WRR Weight for VC0\r
7971 *\r
7972 * On rev 1 hw, this corresponds to WRR_VC0\r
7973 *\r
7974 * Field size: 8 bits\r
7975 */\r
7976 uint8_t wrrVc0;\r
7977 /**\r
7978 * @brief [ro] WRR Weight for VC1\r
7979 *\r
7980 * On rev 1 hw, this corresponds to WRR_VC1\r
7981 *\r
7982 * Field size: 8 bits\r
7983 */\r
7984 uint8_t wrrVc1;\r
7985 /**\r
7986 * @brief [ro] WRR Weight for VC2\r
7987 *\r
7988 * On rev 1 hw, this corresponds to WRR_VC2\r
7989 *\r
7990 * Field size: 8 bits\r
7991 */\r
7992 uint8_t wrrVc2;\r
7993 /**\r
7994 * @brief [ro] WRR Weight for VC3\r
7995 *\r
7996 * On rev 1 hw, this corresponds to WRR_VC3\r
7997 *\r
7998 * Field size: 8 bits\r
7999 */\r
8000 uint8_t wrrVc3;\r
8001 } pciePlconfVcTrAR1Reg_t;\r
8002 /* @} */\r
8003 \r
8004 /**\r
8005 * @ingroup pcielld_reg_cfg_pl_structures\r
8006 * @brief Specification of the VC Transmit Arbitration Register 2 (Sticky)\r
8007 *\r
8008 * On rev 0 hw: unavailable\r
8009 * On rev 1 hw, this corresponds to PCIECTRL_PL_VC_TR_A_R2\r
8010 *\r
8011 * This register may be used for both endpoint and root complex modes.\r
8012 *\r
8013 * This is an entirely [ro] register\r
8014 *\r
8015 * @{\r
8016 */\r
8017 typedef struct pciePlconfVcTrAR2Reg_s {\r
8018 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8019 /**\r
8020 * @brief [ro] WRR Weight for VC4\r
8021 *\r
8022 * On rev 1 hw, this corresponds to WRR_VC4\r
8023 *\r
8024 * Field size: 8 bits\r
8025 */\r
8026 uint8_t wrrVc4;\r
8027 /**\r
8028 * @brief [ro] WRR Weight for VC5\r
8029 *\r
8030 * On rev 1 hw, this corresponds to WRR_VC5\r
8031 *\r
8032 * Field size: 8 bits\r
8033 */\r
8034 uint8_t wrrVc5;\r
8035 /**\r
8036 * @brief [ro] WRR Weight for VC6\r
8037 *\r
8038 * On rev 1 hw, this corresponds to WRR_VC6\r
8039 *\r
8040 * Field size: 8 bits\r
8041 */\r
8042 uint8_t wrrVc6;\r
8043 /**\r
8044 * @brief [ro] WRR Weight for VC7\r
8045 *\r
8046 * On rev 1 hw, this corresponds to WRR_VC7\r
8047 *\r
8048 * Field size: 8 bits\r
8049 */\r
8050 uint8_t wrrVc7;\r
8051 } pciePlconfVcTrAR2Reg_t;\r
8052 /* @} */\r
8053 \r
8054 /**\r
8055 * @ingroup pcielld_reg_cfg_pl_structures\r
8056 * @brief Specification of the VC0 Posted Receive Queue Control (Sticky)\r
8057 *\r
8058 * On rev 0 hw: unavailable\r
8059 * On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_PR_Q_C\r
8060 *\r
8061 * This register may be used for both endpoint and root complex modes.\r
8062 *\r
8063 * @{\r
8064 */\r
8065 typedef struct pciePlconfVc0PrQCReg_s {\r
8066 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8067 /**\r
8068 * @brief [ro] VC0 Posted Data Credits\r
8069 *\r
8070 * On rev 1 hw, this corresponds to P_DCRD\r
8071 *\r
8072 * Field size: 12 bits\r
8073 */\r
8074 uint16_t pDcrd;\r
8075 /**\r
8076 * @brief [ro] VC0 Posted Header Credits\r
8077 *\r
8078 * On rev 1 hw, this corresponds to P_HCRD\r
8079 *\r
8080 * Field size: 8 bits\r
8081 */\r
8082 uint8_t pHcrd;\r
8083 /**\r
8084 * @brief [rw] VC0 TLP Type Ordering Rules\r
8085 *\r
8086 * On rev 1 hw, this corresponds to ORDERING_RULES\r
8087 *\r
8088 * <table>\r
8089 * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
8090 * <tr><td>0x0</td><td>STRICT</td><td>Posted, then Completion, then\r
8091 * Non-Posted</td></tr>\r
8092 * <tr><td>0x1</td><td>STANDARD</td><td>As per PCIe standard</td></tr>\r
8093 * </table>\r
8094 *\r
8095 * Field size: 1 bit\r
8096 */\r
8097 uint8_t orderingRules;\r
8098 /**\r
8099 * @brief [rw] VC0 TLP Type Ordering Rules\r
8100 *\r
8101 * On rev 1 hw, this corresponds to ORDERING_RULES\r
8102 *\r
8103 * <table>\r
8104 * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
8105 * <tr><td>0x0</td><td>ROUND_ROBIN</td></tr>\r
8106 * <tr><td>0x1</td><td>STRICT</td><td>Ordering by VC</td></tr>\r
8107 * </table>\r
8108 *\r
8109 * Field size: 1 bit\r
8110 */\r
8111 uint8_t strictVcPriority;\r
8112 /**\r
8113 * @brief [rw] VC0 Poster TLP Queue Mode\r
8114 *\r
8115 * On rev 1 hw, this corresponds to P_QMODE\r
8116 *\r
8117 * <table>\r
8118 * <tr><th>Action/Value</th><th>Mode</th></tr>\r
8119 * <tr><td>Read 0x1</td><td>STORE_AND_FORWARD</td>/tr>\r
8120 * <tr><td>Read 0x2</td><td>CUT_THROUGH</td>/tr>\r
8121 * <tr><td>Read 0x4</td><td>BYPASS</td>/tr>\r
8122 * <tr><td>Others</td><td>Reserved</td>/tr>\r
8123 * </table>\r
8124 *\r
8125 * Field size: 3 bits\r
8126 */\r
8127 uint8_t pQmode;\r
8128 } pciePlconfVc0PrQCReg_t;\r
8129 /* @} */\r
8130 \r
8131 /**\r
8132 * @ingroup pcielld_reg_cfg_pl_structures\r
8133 * @brief Specification of the VC0 Non-Posted Receive Queue Control (Sticky)\r
8134 *\r
8135 * On rev 0 hw: unavailable\r
8136 * On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_NPR_Q_C\r
8137 *\r
8138 * This register may be used for both endpoint and root complex modes.\r
8139 *\r
8140 * @{\r
8141 */\r
8142 typedef struct pciePlconfVc0NprQCReg_s {\r
8143 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8144 /**\r
8145 * @brief [ro] VC0 Non-Posted Data Credits\r
8146 *\r
8147 * On rev 1 hw, this corresponds to NP_DCRD\r
8148 *\r
8149 * Field size: 12 bits\r
8150 */\r
8151 uint16_t npDcrd;\r
8152 /**\r
8153 * @brief [ro] VC0 Non-Posted Header Credits\r
8154 *\r
8155 * On rev 1 hw, this corresponds to NP_HCRD\r
8156 *\r
8157 * Field size: 8 bits\r
8158 */\r
8159 uint8_t npHcrd;\r
8160 /**\r
8161 * @brief [rw] VC0 Non-Poster TLP Queue Mode\r
8162 *\r
8163 * On rev 1 hw, this corresponds to NP_QMODE\r
8164 *\r
8165 * <table>\r
8166 * <tr><th>Action/Value</th><th>Mode</th></tr>\r
8167 * <tr><td>Read 0x1</td><td>STORE_AND_FORWARD</td>/tr>\r
8168 * <tr><td>Read 0x2</td><td>CUT_THROUGH</td>/tr>\r
8169 * <tr><td>Read 0x4</td><td>BYPASS</td>/tr>\r
8170 * <tr><td>Others</td><td>Reserved</td>/tr>\r
8171 * </table>\r
8172 *\r
8173 * Field size: 3 bits\r
8174 */\r
8175 uint8_t npQmode;\r
8176 } pciePlconfVc0NprQCReg_t;\r
8177 /* @} */\r
8178 \r
8179 /**\r
8180 * @ingroup pcielld_reg_cfg_pl_structures\r
8181 * @brief Specification of the VC0 Completion Receive Queue Control (Sticky)\r
8182 *\r
8183 * On rev 0 hw: unavailable\r
8184 * On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_CR_Q_C\r
8185 *\r
8186 * This register may be used for both endpoint and root complex modes.\r
8187 *\r
8188 * @{\r
8189 */\r
8190 typedef struct pciePlconfVc0CrQCReg_s {\r
8191 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8192 /**\r
8193 * @brief [ro] VC0 Completion Data Credits\r
8194 *\r
8195 * On rev 1 hw, this corresponds to CPL_DCRD\r
8196 *\r
8197 * Field size: 12 bits\r
8198 */\r
8199 uint16_t cplDcrd;\r
8200 /**\r
8201 * @brief [ro] VC0 Completion Header Credits\r
8202 *\r
8203 * On rev 1 hw, this corresponds to CPL_HCRD\r
8204 *\r
8205 * Field size: 8 bits\r
8206 */\r
8207 uint8_t cplHcrd;\r
8208 /**\r
8209 * @brief [rw] VC0 Completion TLP Queue Mode\r
8210 *\r
8211 * On rev 1 hw, this corresponds to CPL_QMODE\r
8212 *\r
8213 * <table>\r
8214 * <tr><th>Action/Value</th><th>Mode</th></tr>\r
8215 * <tr><td>Read 0x1</td><td>STORE_AND_FORWARD</td>/tr>\r
8216 * <tr><td>Read 0x2</td><td>CUT_THROUGH</td>/tr>\r
8217 * <tr><td>Read 0x4</td><td>BYPASS</td>/tr>\r
8218 * <tr><td>Others</td><td>Reserved</td>/tr>\r
8219 * </table>\r
8220 *\r
8221 * Field size: 3 bits\r
8222 */\r
8223 uint8_t cplQmode;\r
8224 } pciePlconfVc0CrQCReg_t;\r
8225 /* @} */\r
8226 \r
8227 /**\r
8228 * @ingroup pcielld_reg_cfg_pl_structures\r
8229 * @brief Specification of the PHY Status Register (Sticky)\r
8230 *\r
8231 * On rev 0 hw: unavailable\r
8232 * On rev 1 hw, this corresponds to PCIECTRL_PL_PHY_STS_R\r
8233 *\r
8234 * This register may be used for both endpoint and root complex modes.\r
8235 *\r
8236 * This is an entirely [ro] register\r
8237 *\r
8238 * @{\r
8239 */\r
8240 typedef struct pciePlconfPhyStsRReg_s {\r
8241 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8242 /**\r
8243 * @brief [ro] PHY Status\r
8244 *\r
8245 * On rev 1 hw, this corresponds to PHY_STS\r
8246 *\r
8247 * Field size: 32 bits\r
8248 */\r
8249 uint32_t phySts;\r
8250 } pciePlconfPhyStsRReg_t;\r
8251 /* @} */\r
8252 \r
8253 /**\r
8254 * @ingroup pcielld_reg_cfg_pl_structures\r
8255 * @brief Specification of the PHY Control Register (Sticky)\r
8256 *\r
8257 * On rev 0 hw: unavailable\r
8258 * On rev 1 hw, this corresponds to PCIECTRL_PL_PHY_CTRL_R\r
8259 *\r
8260 * This register may be used for both endpoint and root complex modes.\r
8261 *\r
8262 * @{\r
8263 */\r
8264 typedef struct pciePlconfPhyCtrlRReg_s {\r
8265 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8266 /**\r
8267 * @brief [rw] PHY Control\r
8268 *\r
8269 * On rev 1 hw, this corresponds to PHY_CTRL\r
8270 *\r
8271 * Field size: 32 bits\r
8272 */\r
8273 uint32_t phyCtrl;\r
8274 } pciePlconfPhyCtrlRReg_t;\r
8275 /* @} */\r
8276 \r
8277 /**\r
8278 * @ingroup pcielld_reg_cfg_pl_structures\r
8279 * @brief Specification of the MSI Controller Address Register\r
8280 * (RC-mode MSI receiver)\r
8281 *\r
8282 * On rev 0 hw: unavailable\r
8283 * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_ADDRESS\r
8284 *\r
8285 * This register may be used only for root complex modes.\r
8286 *\r
8287 * @{\r
8288 */\r
8289 typedef struct pciePlconfMsiCtrlAddressReg_s {\r
8290 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8291 /**\r
8292 * @brief [rw] MSI CTRL ADDRESS\r
8293 *\r
8294 * On rev 1 hw, this corresponds to MSI_CTRL_ADDRESS\r
8295 *\r
8296 * Field size: 32 bits\r
8297 */\r
8298 uint32_t msiCtrlAddress;\r
8299 } pciePlconfMsiCtrlAddressReg_t;\r
8300 /* @} */\r
8301 \r
8302 /**\r
8303 * @ingroup pcielld_reg_cfg_pl_structures\r
8304 * @brief Specification of the MSI Controller Upper Address Register\r
8305 * (RC-mode MSI receiver)\r
8306 *\r
8307 * On rev 0 hw: unavailable\r
8308 * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS\r
8309 *\r
8310 * This register may be used only for root complex modes.\r
8311 *\r
8312 * @{\r
8313 */\r
8314 typedef struct pciePlconfMsiCtrlUpperAddressReg_s {\r
8315 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8316 /**\r
8317 * @brief [rw] MSI CTRL UPPER ADDRESS\r
8318 *\r
8319 * On rev 1 hw, this corresponds to MSI_CTRL_UPPER_ADDRESS\r
8320 *\r
8321 * Field size: 32 bits\r
8322 */\r
8323 uint32_t msiCtrlUpperAddress;\r
8324 } pciePlconfMsiCtrlUpperAddressReg_t;\r
8325 /* @} */\r
8326 \r
8327 /**\r
8328 * @ingroup pcielld_reg_cfg_pl_structures\r
8329 * @brief Specification of the MSI Controller Interrupt # N(1) Enable Register\r
8330 *\r
8331 * (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector # i,\r
8332 * with i = MSI data [4:0]\r
8333 *\r
8334 * On rev 0 hw: unavailable\r
8335 * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N\r
8336 *\r
8337 * This register may be used only for root complex modes.\r
8338 *\r
8339 * @{\r
8340 */\r
8341 typedef struct pciePlconfMsiCtrlIntEnableReg_s {\r
8342 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8343 /**\r
8344 * @brief [rw] Status of an enabled bit (vectors) is set upon incoming MSI\r
8345 *\r
8346 * On rev 1 hw, this corresponds to MSI_CTRL_INT_ENABLE\r
8347 *\r
8348 * Field size: 32 bits\r
8349 */\r
8350 uint32_t msiCtrlIntEnable;\r
8351 } pciePlconfMsiCtrlIntEnableReg_t;\r
8352 /* @} */\r
8353 \r
8354 /**\r
8355 * @ingroup pcielld_reg_cfg_pl_structures\r
8356 * @brief Specification of the MSI Controller Interrupt # N(1) Mask Register\r
8357 *\r
8358 * (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI\r
8359 * vector # i, with i = MSI data [4:0]\r
8360 *\r
8361 * On rev 0 hw: unavailable\r
8362 * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_MASK_N\r
8363 *\r
8364 * This register may be used only for root complex modes.\r
8365 *\r
8366 * @{\r
8367 */\r
8368 typedef struct pciePlconfMsiCtrlIntMaskReg_s {\r
8369 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8370 /**\r
8371 * @brief [rw] Status of a masked bit (vector) triggers no IRQ to MPU when set\r
8372 *\r
8373 * On rev 1 hw, this corresponds to MSI_CTRL_INT_MASK\r
8374 *\r
8375 * Field size: 32 bits\r
8376 */\r
8377 uint32_t msiCtrlIntMask;\r
8378 } pciePlconfMsiCtrlIntMaskReg_t;\r
8379 /* @} */\r
8380 \r
8381 /**\r
8382 * @ingroup pcielld_reg_cfg_pl_structures\r
8383 * @brief Specification of the MSI Controller Interrupt # N(1) Status Register\r
8384 *\r
8385 * (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status\r
8386 * of MSI vector # i, with i = MSI data [4:0]\r
8387 *\r
8388 * On rev 0 hw: unavailable\r
8389 * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_STATUS_N\r
8390 *\r
8391 * This register may be used only for root complex modes.\r
8392 *\r
8393 * @{\r
8394 */\r
8395 typedef struct pciePlconfMsiCtrlIntStatusReg_s {\r
8396 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8397 /**\r
8398 * @brief [rw] Status of an enabled bit (vectors) is set upon incoming MSI\r
8399 *\r
8400 * On rev 1 hw, this corresponds to MSI_CTRL_INT_STATUS\r
8401 *\r
8402 * Field size: 32 bits\r
8403 */\r
8404 uint32_t msiCtrlIntStatus;\r
8405 } pciePlconfMsiCtrlIntStatusReg_t;\r
8406 /* @} */\r
8407 \r
8408 /**\r
8409 * @ingroup pcielld_reg_cfg_pl_structures\r
8410 * @brief Specification of the MSI Controller General Purpose IO Register\r
8411 * (RC-mode MSI receiver)\r
8412 *\r
8413 * On rev 0 hw: unavailable\r
8414 * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_GPIO\r
8415 *\r
8416 * This register may be used only for root complex modes.\r
8417 *\r
8418 * @{\r
8419 */\r
8420 typedef struct pciePlconfMsiCtrlGpioReg_s {\r
8421 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8422 /**\r
8423 * @brief [rw] MSI CTRL GPIO\r
8424 *\r
8425 * On rev 1 hw, this corresponds to MSI_CTRL_GPIO\r
8426 *\r
8427 * Field size: 32 bits\r
8428 */\r
8429 uint32_t msiCtrlGpio;\r
8430 } pciePlconfMsiCtrlGpioReg_t;\r
8431 /* @} */\r
8432 \r
8433 /**\r
8434 * @ingroup pcielld_reg_cfg_pl_structures\r
8435 * @brief Specification of the PIPE loopback control register (Sticky)\r
8436 *\r
8437 * On rev 0 hw: unavailable\r
8438 * On rev 1 hw, this corresponds to PCIECTRL_PL_PIPE_LOOPBACK\r
8439 *\r
8440 * This register may be used for both endpoint and root complex modes.\r
8441 *\r
8442 * @{\r
8443 */\r
8444 typedef struct pciePlconfPipeLoopbackReg_s {\r
8445 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8446 /**\r
8447 * @brief [rw] PIPE Loopback Enable\r
8448 *\r
8449 * On rev 1 hw, this corresponds to LOOPBACK_EN\r
8450 *\r
8451 * Field size: 1 bit\r
8452 */\r
8453 uint8_t loopbackEn;\r
8454 } pciePlconfPipeLoopbackReg_t;\r
8455 /* @} */\r
8456 \r
8457 /**\r
8458 * @ingroup pcielld_reg_cfg_pl_structures\r
8459 * @brief Specification of the DIF Read-Only register Write Enable (Sticky)\r
8460 *\r
8461 * On rev 0 hw: unavailable\r
8462 * On rev 1 hw, this corresponds to PCIECTRL_PL_DBI_RO_WR_EN\r
8463 *\r
8464 * This register may be used for both endpoint and root complex modes.\r
8465 *\r
8466 * @{\r
8467 */\r
8468 typedef struct pciePlconfDbiRoWrEnReg_s {\r
8469 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8470 /**\r
8471 * @brief [rw] Control the writability over DIF of certain configuration\r
8472 *\r
8473 * Control the writability over DIF of certain configuration fields that\r
8474 * are RO over the PCIe wire\r
8475 *\r
8476 * <table>\r
8477 * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
8478 * <tr><td>0x0</td><td>WRDIS</td><td>\r
8479 * RO fields are also RO over DIF; Use for RC mode (Type-1) config\r
8480 * to mimic PCIe wire access when using DIF</td></tr>\r
8481 * <tr><td>0x1</td><td>WREN</td><td>\r
8482 * Some RO fields are writable over DIF</td></tr>\r
8483 * </table>\r
8484 *\r
8485 * On rev 1 hw, this corresponds to CX_DBI_RO_WR_EN\r
8486 *\r
8487 * Field size: 1 bit\r
8488 */\r
8489 uint8_t cxDbiRoWrEn;\r
8490 } pciePlconfDbiRoWrEnReg_t;\r
8491 /* @} */\r
8492 \r
8493 /**\r
8494 * @ingroup pcielld_reg_cfg_pl_structures\r
8495 * @brief Specification of the AXI Slave Error Response Register (Sticky)\r
8496 *\r
8497 * On rev 0 hw: unavailable\r
8498 * On rev 1 hw, this corresponds to PCIECTRL_PL_AXI_SLV_ERR_RESP\r
8499 *\r
8500 * This register may be used for both endpoint and root complex modes.\r
8501 *\r
8502 * @{\r
8503 */\r
8504 typedef struct pciePlconfAxiSlvErrRespReg_s {\r
8505 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8506 /**\r
8507 * @brief [rw] Global Slave Error Response Mapping\r
8508 *\r
8509 * On rev 1 hw, this corresponds to SLAVE_ERR_MAP\r
8510 *\r
8511 * Field size: 1 bit\r
8512 */\r
8513 uint8_t slaveErrMap;\r
8514 /**\r
8515 * @brief [rw] DIF Slave Error Response Mapping\r
8516 *\r
8517 * On rev 1 hw, this corresponds to DBI_ERR_MAP\r
8518 *\r
8519 * Field size: 1 bit\r
8520 */\r
8521 uint8_t dbiErrMap;\r
8522 /**\r
8523 * @brief [rw] Vendor ID Non-existent Slave Error Response Mapping\r
8524 *\r
8525 * On rev 1 hw, this corresponds to NO_VID_ERR_MAP\r
8526 *\r
8527 * Field size: 1 bit\r
8528 */\r
8529 uint8_t noVidErrMap;\r
8530 /**\r
8531 * @brief [rw] Graceful Reset and Link Timeout Slave Error Response Mapping\r
8532 *\r
8533 * On rev 1 hw, this corresponds to RESET_TIMEOUT_ERR_MAP\r
8534 *\r
8535 * Field size: 1 bit\r
8536 */\r
8537 uint8_t resetTimeoutErrMap;\r
8538 } pciePlconfAxiSlvErrRespReg_t;\r
8539 /* @} */\r
8540 \r
8541 /**\r
8542 * @ingroup pcielld_reg_cfg_pl_structures\r
8543 * @brief Specification of the Link Down AXI Slave Timeout Register (Sticky)\r
8544 *\r
8545 * On rev 0 hw: unavailable\r
8546 * On rev 1 hw, this corresponds to PCIECTRL_PL_AXI_SLV_TIMEOUT\r
8547 *\r
8548 * This register may be used for both endpoint and root complex modes.\r
8549 *\r
8550 * @{\r
8551 */\r
8552 typedef struct pciePlconfAxiSlvTimeoutReg_s {\r
8553 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8554 /**\r
8555 * @brief [rw] Timeout Value (ms)\r
8556 *\r
8557 * On rev 1 hw, this corresponds to TIMEOUT_VALUE\r
8558 *\r
8559 * Field size: 8 bits\r
8560 */\r
8561 uint8_t timeoutValue;\r
8562 /**\r
8563 * @brief [rw] Enable flush\r
8564 *\r
8565 * On rev 1 hw, this corresponds to FLUSH_EN\r
8566 *\r
8567 * Field size: 1 bit\r
8568 */\r
8569 uint8_t flushEn;\r
8570 } pciePlconfAxiSlvTimeoutReg_t;\r
8571 /* @} */\r
8572 \r
8573 /**\r
8574 * @ingroup pcielld_reg_cfg_pl_structures\r
8575 * @brief Specification of the iATU Viewport Register\r
8576 *\r
8577 * makes the registers of the corresponding iATU region accessible\r
8578 *\r
8579 * On rev 0 hw: unavailable\r
8580 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_INDEX\r
8581 *\r
8582 * This register may be used for both endpoint and root complex modes.\r
8583 *\r
8584 * @{\r
8585 */\r
8586 typedef struct pciePlconfIatuIndexReg_s {\r
8587 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8588 /**\r
8589 * @brief [rw] Region Direction\r
8590 *\r
8591 * <table>\r
8592 * <tr><th>Value</th><th>Mode</th></tr>\r
8593 * <tr><td>0x0</td><td>OUTBOUND</td></tr>\r
8594 * <tr><td>0x1</td><td>INBOUND</td></tr>\r
8595 * </table>\r
8596 *\r
8597 * On rev 1 hw, this corresponds to REGION_DIRECTION\r
8598 *\r
8599 * Field size: 1 bit\r
8600 */\r
8601 uint8_t regionDirection;\r
8602 /**\r
8603 * @brief [rw] Region Index\r
8604 *\r
8605 * On rev 1 hw, this corresponds to REGION_INDEX\r
8606 *\r
8607 * Outbound region, from 0 to 15.\r
8608 * Inbound region, from 0 to 3.\r
8609 *\r
8610 * Field size: 4 bits\r
8611 */\r
8612 uint8_t regionIndex;\r
8613 } pciePlconfIatuIndexReg_t;\r
8614 /* @} */\r
8615 \r
8616 /**\r
8617 * @ingroup pcielld_reg_cfg_pl_structures\r
8618 * @brief Specification of the iATU Region Control 1 Register\r
8619 *\r
8620 * On rev 0 hw: unavailable\r
8621 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_1\r
8622 *\r
8623 * This register may be used for both endpoint and root complex modes.\r
8624 *\r
8625 * @{\r
8626 */\r
8627 typedef struct pciePlconfIatuRegCtrl1Reg_s {\r
8628 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8629 /**\r
8630 * @brief [rw] type\r
8631 *\r
8632 * On rev 1 hw, this corresponds to TYPE\r
8633 *\r
8634 * Outbound: TYPE applied to outgoing TLP with matching addess\r
8635 * Inbound: TYPE-match criteria\r
8636 *\r
8637 * Field size: 4 bits\r
8638 */\r
8639 uint8_t type;\r
8640 /**\r
8641 * @brief [rw] TC\r
8642 *\r
8643 * On rev 1 hw, this corresponds to TC\r
8644 *\r
8645 * Outbound: TC applied to outgoing TLP with matching addess\r
8646 * Inbound: TC-match criteria (if TC_match_enable=1)\r
8647 *\r
8648 * Field size: 4 bits\r
8649 */\r
8650 uint8_t tc;\r
8651 /**\r
8652 * @brief [rw] TD\r
8653 *\r
8654 * On rev 1 hw, this corresponds to TD\r
8655 *\r
8656 * Outbound: TD applied to outgoing TLP with matching addess\r
8657 * Inbound: TD-match criteria (if TD_match_enable=1)\r
8658 *\r
8659 * Field size: 1 bit\r
8660 */\r
8661 uint8_t td;\r
8662 /**\r
8663 * @brief [rw] ATTR\r
8664 *\r
8665 * On rev 1 hw, this corresponds to ATTR\r
8666 *\r
8667 * Outbound: ATTR applied to outgoing TLP with matching addess\r
8668 * Inbound: ATTR-match criteria (if ATTR_match_enable=1)\r
8669 *\r
8670 * Field size: 2 bits\r
8671 */\r
8672 uint8_t attr;\r
8673 /**\r
8674 * @brief [rw] AT\r
8675 *\r
8676 * On rev 1 hw, this corresponds to AT\r
8677 *\r
8678 * Outbound: AT applied to outgoing TLP with matching addess\r
8679 * Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)\r
8680 *\r
8681 * Field size: 2 bits\r
8682 */\r
8683 uint8_t at;\r
8684 /**\r
8685 * @brief [rw] function number\r
8686 *\r
8687 * On rev 1 hw, this corresponds to FUNCTION_NUMBER\r
8688 *\r
8689 * Outbound: F.N; applied to outgoing TLP (RID) with RW 0x0 matching addess\r
8690 * Inbound: F.N.-match criteria for incoming TLP\r
8691 * (if Function_Number_match_enable=1)\r
8692 *\r
8693 * Field size: 5 bits\r
8694 */\r
8695 uint8_t functionNumber;\r
8696 } pciePlconfIatuRegCtrl1Reg_t;\r
8697 /* @} */\r
8698 \r
8699 /**\r
8700 * @ingroup pcielld_reg_cfg_pl_structures\r
8701 * @brief Specification of the iATU Region Control 2 Register\r
8702 *\r
8703 * On rev 0 hw: unavailable\r
8704 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_2\r
8705 *\r
8706 * This register may be used for both endpoint and root complex modes.\r
8707 *\r
8708 * @{\r
8709 */\r
8710 typedef struct pciePlconfIatuRegCtrl2Reg_s {\r
8711 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8712 /**\r
8713 * @brief [rw] MESSAGECODE\r
8714 *\r
8715 * On rev 1 hw, this corresponds to MESSAGECODE\r
8716 *\r
8717 * Outbound: MessageCode applied to outgoing message RW 0x0 TLP with\r
8718 * matching addess\r
8719 * Inbound: MessageCode-match criteria for infoming message TLP\r
8720 * (if Message_Code_match_enable=1)\r
8721 *\r
8722 * Field size: 8 bits\r
8723 */\r
8724 uint8_t messagecode;\r
8725 /**\r
8726 * @brief [rw] BAR_NUMBER\r
8727 *\r
8728 * On rev 1 hw, this corresponds to BAR_NUMBER\r
8729 *\r
8730 * BAR number for mayching with incoming MEM, I/O TLP RW 0x0\r
8731 * (if Match_Mode = 1)\r
8732 *\r
8733 * <table>\r
8734 * <tr><th>Value</th><th>Mode</th></tr>\r
8735 * <tr><td>0x0</td><td>BAR0</td></tr>\r
8736 * <tr><td>0x1</td><td>BAR1</td></tr>\r
8737 * <tr><td>0x2</td><td>BAR2</td></tr>\r
8738 * <tr><td>0x3</td><td>BAR3</td></tr>\r
8739 * <tr><td>0x4</td><td>BAR4</td></tr>\r
8740 * <tr><td>0x5</td><td>BAR5</td></tr>\r
8741 * <tr><td>0x6</td><td>ROM</td></tr>\r
8742 * </table>\r
8743 *\r
8744 * Field size: 3 bits\r
8745 */\r
8746 uint8_t barNumber;\r
8747 /**\r
8748 * @brief [rw] Enable TC match criteria on inbound TLP\r
8749 *\r
8750 * On rev 1 hw, this corresponds to TC_MATCH_ENABLE\r
8751 *\r
8752 * Field size: 1 bit\r
8753 */\r
8754 uint8_t tcMatchEnable;\r
8755 /**\r
8756 * @brief [rw] Enable TD match criteria on inbound TLP\r
8757 *\r
8758 * On rev 1 hw, this corresponds to TD_MATCH_ENABLE\r
8759 *\r
8760 * Field size: 1 bit\r
8761 */\r
8762 uint8_t tdMatchEnable;\r
8763 /**\r
8764 * @brief [rw] Enable ATTR match criteria on inbound TLP\r
8765 *\r
8766 * On rev 1 hw, this corresponds to ATTR_MATCH_ENABLE\r
8767 *\r
8768 * Field size: 1 bit\r
8769 */\r
8770 uint8_t attrMatchEnable;\r
8771 /**\r
8772 * @brief [rw] Enable AT match criteria on inbound TLP\r
8773 *\r
8774 * On rev 1 hw, this corresponds to AT_MATCH_ENABLE\r
8775 *\r
8776 * ATS NOT SUPPORTED: DO NOT USE\r
8777 *\r
8778 * Field size: 1 bit\r
8779 */\r
8780 uint8_t atMatchEnable;\r
8781 /**\r
8782 * @brief [rw] function number match enable\r
8783 *\r
8784 * On rev 1 hw, this corresponds to FUNCTION_NUMBER_MATCH_ENABLE\r
8785 *\r
8786 * Outbound: Function Number Translation Bypass\r
8787 * Inbound: Enable Function Number match criteria\r
8788 *\r
8789 * Field size: 1 bit\r
8790 */\r
8791 uint8_t functionNumberMatchEnable;\r
8792 /**\r
8793 * @brief [rw] VIRTUAL FUNCTIONS NOT IMPLEMENTED\r
8794 *\r
8795 * On rev 1 hw, this corresponds to VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE\r
8796 *\r
8797 * Field size: 1 bit\r
8798 */\r
8799 uint8_t virtualFunctionNumberMatchEnable;\r
8800 /**\r
8801 * @brief [rw] Enable MessageCode match criteria on inbound TLP\r
8802 *\r
8803 * On rev 1 hw, this corresponds to MESSAGE_CODE_MATCH_ENABLE\r
8804 *\r
8805 * Field size: 1 bit\r
8806 */\r
8807 uint8_t messageCodeMatchEnable;\r
8808 /**\r
8809 * @brief [rw] Override HW-generated completion status when responding inbound TLP\r
8810 *\r
8811 * On rev 1 hw, this corresponds to RESPONSE_CODE\r
8812 *\r
8813 * <table>\r
8814 * <tr><th>Value</th><th>description</th></tr>\r
8815 * <tr><td>0x0</td><td>No override, use HW-generated CS</td></tr>\r
8816 * <tr><td>0x1</td><td>Unsupported Request: CS= 3'b001</td></tr>\r
8817 * <tr><td>0x2</td><td>Completer Abort: CS= 3'b100</td></tr>\r
8818 * </table>\r
8819 *\r
8820 * Field size: 2 bits\r
8821 */\r
8822 uint8_t responseCode;\r
8823 /**\r
8824 * @brief [rw] fuzzy type match mode\r
8825 *\r
8826 * On rev 1 hw, this corresponds to FUZZY_TYPE_MATCH_MODE\r
8827 *\r
8828 * Outbound: DMA Bypass Mode RW 0x0\r
8829 * Inbound: Relax matching on inbound TLP TYPE:\r
8830 * CfgRd0 == CfgRd1\r
8831 * CfgWr0 == CfgWr1\r
8832 * MRd == MRdLk\r
8833 * routing field of Msg/MsgD ignored\r
8834 *\r
8835 * Field size: 1 bit\r
8836 */\r
8837 uint8_t fuzzyTypeMatchMode;\r
8838 /**\r
8839 * @brief [rw] Enable the shifting of CFG CID (BDF),\r
8840 *\r
8841 * On rev 1 hw, this corresponds to CFG_SHIFT_MODE\r
8842 *\r
8843 * Incoming and outgoing TLP;\r
8844 * CFG get mapped to a contiguous 2**28 = * 256 MByte address space\r
8845 * Untranslated CID = CFG_DW#3[31:16]\r
8846 * Shifted CID = CFG_DW#3[27:12]\r
8847 *\r
8848 * Field size: 1 bit\r
8849 */\r
8850 uint8_t cfgShiftMode;\r
8851 /**\r
8852 * @brief [rw] Redefine match criteria as outside the defined range\r
8853 *\r
8854 * On rev 1 hw, this corresponds to INVERT_MODE\r
8855 *\r
8856 * (instead of inside)\r
8857 *\r
8858 * Field size: 1 bit\r
8859 */\r
8860 uint8_t invertMode;\r
8861 /**\r
8862 * @brief [rw] Sets inbound TLP match mode\r
8863 *\r
8864 * On rev 1 hw, this corresponds to MATCH_MODE\r
8865 *\r
8866 * Depending on TYPE\r
8867 * 0x0: MEM,I/O: Address Match: as per region base & limit registers;\r
8868 * CFG0: Routing ID Match: Completer ID (BDF) + reg\r
8869 * address matches base & limit-defined region;\r
8870 * MSG[D]: Address Match: as per region base & limit registers\r
8871 * 0x1: MEM,I/O: BAR match: as defined in BAR_number field;\r
8872 * CFG0: Accept mode: Completer ID (BDF) is ignored;\r
8873 * MSG[D]: VendorID match: VendorID = upper_base[15:0] +\r
8874 * VendorDefined = lower_base/limit\r
8875 *\r
8876 * Field size: 1 bit\r
8877 */\r
8878 uint8_t matchMode;\r
8879 /**\r
8880 * @brief [rw] Enable AT for this region\r
8881 *\r
8882 * On rev 1 hw, this corresponds to REGION_ENABLE\r
8883 *\r
8884 * Field size: 1 bit\r
8885 */\r
8886 uint8_t regionEnable;\r
8887 } pciePlconfIatuRegCtrl2Reg_t;\r
8888 /* @} */\r
8889 \r
8890 /**\r
8891 * @ingroup pcielld_reg_cfg_pl_structures\r
8892 * @brief Specification of the iATU Region Lower Base Address Register\r
8893 * (2**12 = 4kbyte - aligned)\r
8894 *\r
8895 * On rev 0 hw: unavailable\r
8896 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LOWER_BASE\r
8897 *\r
8898 * This register may be used for both endpoint and root complex modes.\r
8899 *\r
8900 * @{\r
8901 */\r
8902 \r
8903 typedef struct pciePlconfIatuRegLowerBaseReg_s {\r
8904 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8905 /**\r
8906 * @brief [rw] Lower Base Address (read-write part)\r
8907 *\r
8908 * On rev 1 hw, this corresponds to IATU_REG_LOWER_BASE\r
8909 *\r
8910 * Note: @ref iatuRegLowerBase is >> 12 version of address, with 0 LSBs cut off.\r
8911 *\r
8912 * Field size: 20 bits\r
8913 */\r
8914 uint32_t iatuRegLowerBase;\r
8915 /**\r
8916 * @brief [ro] Lower Base Address (read-only part)\r
8917 *\r
8918 * On rev 1 hw, this corresponds to ZERO\r
8919 *\r
8920 * This portion is always 0 to enforce 4K alignment.\r
8921 *\r
8922 * Field size: 12 bits\r
8923 */\r
8924 uint16_t zero;\r
8925 } pciePlconfIatuRegLowerBaseReg_t;\r
8926 /* @} */\r
8927 \r
8928 /**\r
8929 * @ingroup pcielld_reg_cfg_pl_structures\r
8930 * @brief Specification of the iATU Region Upper Base Address Register\r
8931 *\r
8932 * On rev 0 hw: unavailable\r
8933 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_UPPER_BASE\r
8934 *\r
8935 * This register may be used for both endpoint and root complex modes.\r
8936 *\r
8937 * @{\r
8938 */\r
8939 typedef struct pciePlconfIatuRegUpperBaseReg_s {\r
8940 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8941 /**\r
8942 * @brief [rw] Upper Base Address\r
8943 *\r
8944 * On rev 1 hw, this corresponds to IATU_REG_UPPER_BASE\r
8945 *\r
8946 * Field size: 32 bits\r
8947 */\r
8948 uint32_t iatuRegUpperBase;\r
8949 } pciePlconfIatuRegUpperBaseReg_t;\r
8950 /* @} */\r
8951 \r
8952 /**\r
8953 * @ingroup pcielld_reg_cfg_pl_structures\r
8954 * @brief Specification of the iATU Region Limit Address Register\r
8955 *\r
8956 * On rev 0 hw: unavailable\r
8957 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LIMIT\r
8958 *\r
8959 * This register may be used for both endpoint and root complex modes.\r
8960 *\r
8961 * @{\r
8962 */\r
8963 typedef struct pciePlconfIatuRegLimitReg_s {\r
8964 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
8965 /**\r
8966 * @brief [ro] Region limit address\r
8967 *\r
8968 * On rev 1 hw, this corresponds to IATU_REG_LIMIT\r
8969 *\r
8970 * Field size: 20 bits\r
8971 */\r
8972 uint32_t iatuRegLimit;\r
8973 /**\r
8974 * @brief [ro] Region limit address (mask)\r
8975 *\r
8976 * On rev 1 hw, this corresponds to ONES\r
8977 *\r
8978 * This portion is always 0xfff to enforce 4K portion of mask.\r
8979 *\r
8980 * Field size: 12 bits\r
8981 */\r
8982 uint16_t ones;\r
8983 } pciePlconfIatuRegLimitReg_t;\r
8984 /* @} */\r
8985 \r
8986 /**\r
8987 * @ingroup pcielld_reg_cfg_pl_structures\r
8988 * @brief Specification of the iATU Region Lower Target Address Register\r
8989 * (2**12 = 4kbyte - aligned)\r
8990 *\r
8991 * On rev 0 hw: unavailable\r
8992 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LOWER_TARGET\r
8993 *\r
8994 * This register may be used for both endpoint and root complex modes.\r
8995 *\r
8996 * @{\r
8997 */\r
8998 \r
8999 typedef struct pciePlconfIatuRegLowerTargetReg_s {\r
9000 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9001 /**\r
9002 * @brief [rw] Lower Target Address (read-write part)\r
9003 *\r
9004 * On rev 1 hw, this corresponds to IATU_REG_LOWER_TARGET\r
9005 *\r
9006 * Note: @ref iatuRegLowerTarget is >> 12 version of address, with 0 LSBs cut off.\r
9007 *\r
9008 * Field size: 20 bits\r
9009 */\r
9010 uint32_t iatuRegLowerTarget;\r
9011 /**\r
9012 * @brief [ro] Lower Target Address (read-only part)\r
9013 *\r
9014 * On rev 1 hw, this corresponds to ZERO\r
9015 *\r
9016 * This portion is always 0 to enforce 4K alignment.\r
9017 *\r
9018 * Field size: 12 bits\r
9019 */\r
9020 uint16_t zero;\r
9021 } pciePlconfIatuRegLowerTargetReg_t;\r
9022 /* @} */\r
9023 \r
9024 /**\r
9025 * @ingroup pcielld_reg_cfg_pl_structures\r
9026 * @brief Specification of the iATU Region Upper Target Address Register\r
9027 *\r
9028 * On rev 0 hw: unavailable\r
9029 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_UPPER_TARGET\r
9030 *\r
9031 * This register may be used for both endpoint and root complex modes.\r
9032 *\r
9033 * @{\r
9034 */\r
9035 typedef struct pciePlconfIatuRegUpperTargetReg_s {\r
9036 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9037 /**\r
9038 * @brief [rw] Upper Target Address\r
9039 *\r
9040 * On rev 1 hw, this corresponds to ATU_REG_UPPER_TARGET\r
9041 *\r
9042 * Field size: 32 bits\r
9043 */\r
9044 uint8_t iatuRegUpperTarget;\r
9045 } pciePlconfIatuRegUpperTargetReg_t;\r
9046 /* @} */\r
9047 \r
9048 /**\r
9049 * @ingroup pcielld_reg_cfg_pl_structures\r
9050 * @brief Specification of the iATU Region Control 3 Register\r
9051 *\r
9052 * On rev 0 hw: unavailable\r
9053 * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_3\r
9054 *\r
9055 * VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED\r
9056 *\r
9057 * This register may be used for both endpoint and root complex modes.\r
9058 *\r
9059 * This is an entirely [ro] register\r
9060 *\r
9061 * @{\r
9062 */\r
9063 typedef struct pciePlconfIatuRegCtrl3Reg_s {\r
9064 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9065 /**\r
9066 * @brief [ro] IATU CTRL 3\r
9067 *\r
9068 * On rev 1 hw, this corresponds to IATU_REG_CTRL_3\r
9069 *\r
9070 * This register is not used as virtual functions are not supported. It is\r
9071 * always 0.\r
9072 *\r
9073 * Field size: 32 bits\r
9074 */\r
9075 uint32_t iatuRegCtrl3;\r
9076 } pciePlconfIatuRegCtrl3Reg_t;\r
9077 /* @} */\r
9078 \r
9079 /**\r
9080 * @ingroup pcielld_reg_ti_conf\r
9081 * @brief Specification of the TI CONF Revision register\r
9082 *\r
9083 * This register may be used for both endpoint and root complex modes.\r
9084 *\r
9085 * This register is only available on rev 1 hw (TI_CONF_REVISION)\r
9086 * This register is completely RO.\r
9087 *\r
9088 * This register is very similar to hw rev 0's @ref pciePidReg_t\r
9089 *\r
9090 * @{\r
9091 */\r
9092 typedef struct pcieTiConfRevisionReg_s {\r
9093 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9094 uint8_t yMinor; /**< @brief [ro] minor rev - 6 bits*/\r
9095 uint8_t custom; /**< @brief [ro] customer special rev - 2 bits */\r
9096 uint8_t xMajor; /**< @brief [ro] major rev - 3 bits*/\r
9097 uint8_t rRtl; /**< @brief [ro] RTL rev - 5 bits */\r
9098 uint8_t func; /**< @brief [ro] function code - 12 bits */\r
9099 uint8_t scheme; /**< @brief [ro] scheme - 2 bits */\r
9100 uint8_t bu; /**< @brief [ro] business unit - 2 bits */\r
9101 } pcieTiConfRevisionReg_t;\r
9102 /* @} */\r
9103 \r
9104 /**\r
9105 * @ingroup pcielld_reg_ti_conf\r
9106 * @brief Specification of the TI CONF Sys Config Register\r
9107 *\r
9108 * This register may be used for both endpoint and root complex modes.\r
9109 *\r
9110 * This register is only available on rev 1 hw (TI_CONF_SYSCONFIG)\r
9111 *\r
9112 * @{\r
9113 */\r
9114 typedef struct pcieTiConfSysConfigReg_s {\r
9115 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9116 /**\r
9117 * @brief [rw] PM mode of local target (slave)\r
9118 *\r
9119 * PM mode of local target (slave); Target shall be capable\r
9120 * RW 0x2 of handling read/write transaction as long as it is\r
9121 * out of IDLE state.\r
9122 *\r
9123 * <table>\r
9124 * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
9125 * <tr><td>0x0</td><td>Force-idle</td><td>\r
9126 * local target's idle state follows (acknowledges) the system's idle\r
9127 * requests unconditionally, regardless of the IP module's internal\r
9128 * requirements.\r
9129 * </tr><tr><td>0x1</td><td>No-idle</td><td>\r
9130 * local target never enters idle state.\r
9131 * </tr><tr><td>0x2</td><td>Smart-idl</td><td>\r
9132 * local target's idle state eventually follows (acknowledges) the\r
9133 * system's idle requests, depending on the IP module's internal\r
9134 * requirements. Module shall not generate (IRQ- or DMA-request-related)\r
9135 * wakeup events.\r
9136 * </tr><tr><td>0x3</td><td>Smart-idle wakeup-capable</td><td>\r
9137 * local target's idle state eventually follows (acknowledges) the\r
9138 * system's idle requests, depending on the IP module's internal\r
9139 * requirements. IP module may generate (IRQ- or DMArequest-\r
9140 * related) wakeup events when in idle state.\r
9141 * </td></tr></table>\r
9142 *\r
9143 * On rev 1 hw, this corresponds to IDLEMODE\r
9144 *\r
9145 * Field size: 2 bits\r
9146 */\r
9147 uint8_t idlemode;\r
9148 /**\r
9149 * @brief [rw] number of fast training sequences\r
9150 *\r
9151 * PM mode of local initiator (master); Initiator may generate read/write\r
9152 * transaction as long as it is out of STANDBY state.\r
9153 *\r
9154 * <table>\r
9155 * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
9156 * <tr><td>0x0</td><td>Force-standby</td><td>\r
9157 * Initiator is unconditionally placed in standby state.\r
9158 * </tr><tr><td>0x1</td><td>No-standby</td><td>\r
9159 * initiator is unconditionally placed out of standby state.\r
9160 * </tr><tr><td>0x2</td><td>Smart-standby</td><td>\r
9161 * initiator's standby state depends on internal conditions, i.e. the\r
9162 * module's functional requirements. Asynchronous wakeup events\r
9163 * cannot be generated.\r
9164 * </tr><tr><td>0x3</td><td>Smart-standby, wakeup-capable</td><td>\r
9165 * initiator's standby state depends on internal conditions, ie the\r
9166 * module's functional requirements. Asynchronous wakeup events can\r
9167 * be generated.\r
9168 * </td></tr></table>\r
9169 *\r
9170 * On rev 1 hw, this corresponds to STANDBYMODE\r
9171 *\r
9172 * Field size: 2 bits\r
9173 */\r
9174 uint8_t standbymode;\r
9175 /**\r
9176 * @brief [rw] no-snoop to coherent mapping\r
9177 *\r
9178 * Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed\r
9179 * to SoC system bus (AXI) master as a 'coherent' inband flag.\r
9180 *\r
9181 * <table>\r
9182 * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
9183 * <tr><td>0x0</td><td>DIS</td><td>AXI not coherent</td></tr>\r
9184 * <tr><td>0x1</td><td>EN</td><td>\r
9185 * AXI coherent = not(PCIE "NS") i.e. cache-coherence is preserved\r
9186 * </td></tr></table>\r
9187 *\r
9188 * On rev 1 hw, this corresponds to MCOHERENT_EN\r
9189 *\r
9190 * Field size: 1 bit\r
9191 */\r
9192 uint8_t mcoherentEn;\r
9193 } pcieTiConfSysConfigReg_t;\r
9194 /* @} */\r
9195 \r
9196 /**\r
9197 * @ingroup pcielld_reg_ti_conf\r
9198 * @brief Specification of the TI CONF IRQ EOI Register\r
9199 *\r
9200 * This register may be used for both endpoint and root complex modes.\r
9201 *\r
9202 * This register is only available on rev 1 hw (TI_CONF_IRQ_EOI)\r
9203 * @{\r
9204 */\r
9205 typedef struct pcieTiConfIrqEoiReg_s {\r
9206 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9207 /**\r
9208 * @brief [rw] IRQ Line Number to EOI\r
9209 *\r
9210 * Write the IRQ line number to apply SW EOI to it.\r
9211 * Write 0x0: SW EOI on main interrupt line\r
9212 * Write 0x1: SW EOI on message-signalled (MSI) interrupt line\r
9213 *\r
9214 * Read always returns zeros\r
9215 *\r
9216 * On rev 1 hw, this corresponds to LINE_NUMBER\r
9217 *\r
9218 * Field size: 4 bits\r
9219 */\r
9220 uint8_t lineNumber;\r
9221 } pcieTiConfIrqEoiReg_t;\r
9222 /* @} */\r
9223 \r
9224 /**\r
9225 * @ingroup pcielld_reg_ti_conf\r
9226 * @brief Specification of the TI CONF IRQ Main common spec\r
9227 *\r
9228 * This structure is used for reading/writing 4 different registers:\r
9229 * @ref pcieTiConfIrqStatusRawMainReg_t\r
9230 * @ref pcieTiConfIrqStatusMainReg_t\r
9231 * @ref pcieTiConfIrqEnableSetMainReg_t\r
9232 * @ref pcieTiConfIrqEnableClrMainReg_t.\r
9233 *\r
9234 * This register may be used for both endpoint and root complex modes.\r
9235 *\r
9236 * This register is only available on rev 1 hw.\r
9237 *\r
9238 * @{\r
9239 */\r
9240 typedef struct pcieTiConfIrqMain_s {\r
9241 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9242 uint8_t errSys; /**< @brief System Error IRQ */\r
9243 uint8_t errFatal; /**< @brief Fatal Error message received IRQ */\r
9244 uint8_t errNonfatal; /**< @brief Non-Fatal Error message received IRQ */\r
9245 uint8_t errCor; /**< @brief Correctable Error message received IRQ */\r
9246 uint8_t errAxi; /**< @brief AXI tag lookup fatal Error IRQ */\r
9247 uint8_t errEcrc; /**< @brief ECRC Error IRQ */\r
9248 uint8_t pmeTurnOff; /**< @brief Power Management Event Turn-Off message received IRQ */\r
9249 uint8_t pmeToAck; /**< @brief Power Management Event Turn-Off Ack message IRQ */\r
9250 uint8_t pmPme; /**< @brief PM Power Management Event message received IRQ */\r
9251 uint8_t linkReqRst; /**< @brief Link Request Reset IRQ */\r
9252 uint8_t linkUpEvt; /**< @brief Link-up state change IRQ */\r
9253 uint8_t cfgBmeEvt; /**< @brief CFG "Bus Master Enable" change IRQ */\r
9254 uint8_t cfgMseEvt; /**< @brief CFG "Memory Space Enable" change IRQ */\r
9255 } pcieTiConfIrqMain_t;\r
9256 /* @} */\r
9257 \r
9258 /**\r
9259 * @ingroup pcielld_reg_ti_conf\r
9260 * @brief Specification of the TI CONF IRQ Status Raw main Register\r
9261 *\r
9262 * Raw status of 'main' interrupt requests; Set even if event is not enabled.\r
9263 * Write 1 to set the (raw) status, mostly for debug (regular status also gets set).\r
9264 *\r
9265 * For each IRQ in @ref pcieTiConfIrqMain_t\r
9266 * <table>\r
9267 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9268 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9269 * <tr><td>Write</td><td>1</td><td>Triggers IRQ Event by software</td></tr>\r
9270 * <tr><td>Read</td><td>0</td><td>IRQ event not pending</td></tr>\r
9271 * <tr><td>Read</td><td>1</td><td>IRQ event is pending</td></tr>\r
9272 * </table>\r
9273 *\r
9274 * This register may be used for both endpoint and root complex modes.\r
9275 *\r
9276 * This register is only available on rev 1 hw (TI_CONF_IRQSTATUS_RAW_MAIN)\r
9277 *\r
9278 */\r
9279 typedef pcieTiConfIrqMain_t pcieTiConfIrqStatusRawMainReg_t;\r
9280 /* @} */\r
9281 \r
9282 /**\r
9283 * @ingroup pcielld_reg_ti_conf\r
9284 * @brief Specification of the TI CONF IRQ Status Main register\r
9285 *\r
9286 * Regular status of 'main' interrupt requests; Set only when enabled.\r
9287 * Write 1 to clear after interrupt has been serviced\r
9288 * (raw status also gets cleared).\r
9289 *\r
9290 * For each IRQ in @ref pcieTiConfIrqMain_t\r
9291 * <table>\r
9292 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9293 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9294 * <tr><td>Write</td><td>1</td><td>Clear pending IRQ Event, if any</td></tr>\r
9295 * <tr><td>Read</td><td>0</td><td>IRQ event not pending</td></tr>\r
9296 * <tr><td>Read</td><td>1</td><td>IRQ event is pending</td></tr>\r
9297 * </table>\r
9298 *\r
9299 * This register may be used for both endpoint and root complex modes.\r
9300 *\r
9301 * This register is only available on rev 1 hw (TI_CONF_IRQSTATUS_MAIN)\r
9302 *\r
9303 * @{\r
9304 */\r
9305 typedef pcieTiConfIrqMain_t pcieTiConfIrqStatusMainReg_t;\r
9306 /* @} */\r
9307 \r
9308 /**\r
9309 * @ingroup pcielld_reg_ti_conf\r
9310 * @brief Specification of the TI CONF IRQ Enable Set register\r
9311 *\r
9312 * Enable of 'main' interrupt requests; Write 1 to set (ie to enable\r
9313 * interrupt). Readout is the same as corresponding _CLR register.\r
9314 *\r
9315 * For each IRQ in @ref pcieTiConfIrqMain_t\r
9316 * <table>\r
9317 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9318 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9319 * <tr><td>Write</td><td>1</td><td>Enable event</td></tr>\r
9320 * <tr><td>Read</td><td>0</td><td>IRQ event is disabled</td></tr>\r
9321 * <tr><td>Read</td><td>1</td><td>IRQ event is enabled</td></tr>\r
9322 * </table>\r
9323 *\r
9324 * This register may be used for both endpoint and root complex modes.\r
9325 *\r
9326 * This register is only available on rev 1 hw (TI_CONF_IRQSTATUS_MAIN)\r
9327 *\r
9328 * @{\r
9329 */\r
9330 typedef pcieTiConfIrqMain_t pcieTiConfIrqEnableSetMainReg_t;\r
9331 /* @} */\r
9332 \r
9333 /**\r
9334 * @ingroup pcielld_reg_ti_conf\r
9335 * @brief Specification of the TI CONF IRQ Enable Clear register\r
9336 *\r
9337 * Enable of 'main' interrupt requests; Write 1 to clear\r
9338 * (ie to disable interrupt). Readout is the same\r
9339 * as corresponding _SET register.\r
9340 *\r
9341 * For each IRQ in @ref pcieTiConfIrqMain_t\r
9342 * <table>\r
9343 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9344 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9345 * <tr><td>Write</td><td>1</td><td>Disable event</td></tr>\r
9346 * <tr><td>Read</td><td>0</td><td>IRQ event is disabled</td></tr>\r
9347 * <tr><td>Read</td><td>1</td><td>IRQ event is enabled</td></tr>\r
9348 * </table>\r
9349 *\r
9350 * This register may be used for both endpoint and root complex modes.\r
9351 *\r
9352 * This register is only available on rev 1 hw (TI_CONF_IRQENABLE_CLR_MAIN)\r
9353 *\r
9354 * @{\r
9355 */\r
9356 typedef pcieTiConfIrqMain_t pcieTiConfIrqEnableClrMainReg_t;\r
9357 /* @} */\r
9358 \r
9359 /**\r
9360 * @ingroup pcielld_reg_ti_conf\r
9361 * @brief Specification of the TI CONF IRQ MSI common spec\r
9362 *\r
9363 * This structure is used for reading/writing 4 different registers:\r
9364 * @ref pcieTiConfIrqStatusRawMsiReg_t\r
9365 * @ref pcieTiConfIrqStatusMsiReg_t\r
9366 * @ref pcieTiConfIrqEnableSetMsiReg_t\r
9367 * @ref pcieTiConfIrqEnableClrMsiReg_t.\r
9368 *\r
9369 * This register may be used for both endpoint and root complex modes.\r
9370 *\r
9371 * This register is only available on rev 1 hw.\r
9372 *\r
9373 * @{\r
9374 */\r
9375 typedef struct pcieTiConfIrqMsi_s {\r
9376 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9377 uint8_t inta; /**< @brief INTA IRQ */\r
9378 uint8_t intb; /**< @brief INTB IRQ */\r
9379 uint8_t intc; /**< @brief INTC IRQ */\r
9380 uint8_t intd; /**< @brief INTD IRQ */\r
9381 uint8_t msi; /**< @brief Message Signaled Interrupt (MSI) IRQ */\r
9382 } pcieTiConfIrqMsi_t;\r
9383 /* @} */\r
9384 \r
9385 /**\r
9386 * @ingroup pcielld_reg_ti_conf\r
9387 * @brief Specification of the TI CONF IRQ Status Raw MSI Register\r
9388 *\r
9389 * Raw status of legacy and MSI interrupt requests; Set even if\r
9390 * event is not enabled. Write 1 to set the (raw) status, mostly\r
9391 * for debug (regular status also gets set).\r
9392 *\r
9393 * For each IRQ in @ref pcieTiConfIrqMsi_t\r
9394 * <table>\r
9395 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9396 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9397 * <tr><td>Write</td><td>1</td><td>Triggers IRQ Event by software</td></tr>\r
9398 * <tr><td>Read</td><td>0</td><td>IRQ event not pending</td></tr>\r
9399 * <tr><td>Read</td><td>1</td><td>IRQ event is pending</td></tr>\r
9400 * </table>\r
9401 *\r
9402 * This register may be used for both endpoint and root complex modes.\r
9403 *\r
9404 * This register is only available on rev 1 hw (TI_CONF_IRQSTATUS_RAW_MSI)\r
9405 *\r
9406 * @{\r
9407 */\r
9408 typedef pcieTiConfIrqMsi_t pcieTiConfIrqStatusRawMsiReg_t;\r
9409 /* @} */\r
9410 \r
9411 /**\r
9412 * @ingroup pcielld_reg_ti_conf\r
9413 * @brief Specification of the TI CONF IRQ Status MSI register\r
9414 *\r
9415 * Regular status of legacy and MSI interrupt requests; Set only\r
9416 * when enabled. Write 1 to clear after interrupt has been serviced\r
9417 * (raw status also gets cleared). HW-generated events are self-clearing.\r
9418 *\r
9419 * For each IRQ in @ref pcieTiConfIrqMsi_t\r
9420 * <table>\r
9421 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9422 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9423 * <tr><td>Write</td><td>1</td><td>Clear pending IRQ Event, if any</td></tr>\r
9424 * <tr><td>Read</td><td>0</td><td>IRQ event not pending</td></tr>\r
9425 * <tr><td>Read</td><td>1</td><td>IRQ event is pending</td></tr>\r
9426 * </table>\r
9427 *\r
9428 * This register may be used for both endpoint and root complex modes.\r
9429 *\r
9430 * This register is only available on rev 1 hw (TI_CONF_IRQSTATUS_MSI)\r
9431 *\r
9432 * @{\r
9433 */\r
9434 typedef pcieTiConfIrqMsi_t pcieTiConfIrqStatusMsiReg_t;\r
9435 /* @} */\r
9436 \r
9437 /**\r
9438 * @ingroup pcielld_reg_ti_conf\r
9439 * @brief Specification of the TI CONF IRQ MSI Enable Set register\r
9440 *\r
9441 * Enable of legacy and MSI interrupt requests; Write 1 to set (ie to\r
9442 * enable interrupt). Readout is the same as corresponding _CLR register.\r
9443 *\r
9444 * For each IRQ in @ref pcieTiConfIrqMsi_t\r
9445 * <table>\r
9446 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9447 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9448 * <tr><td>Write</td><td>1</td><td>Enable event</td></tr>\r
9449 * <tr><td>Read</td><td>0</td><td>IRQ event is disabled</td></tr>\r
9450 * <tr><td>Read</td><td>1</td><td>IRQ event is enabled</td></tr>\r
9451 * </table>\r
9452 *\r
9453 * This register may be used for both endpoint and root complex modes.\r
9454 *\r
9455 * This register is only available on rev 1 hw (TI_CONF_IRQENABLE_SET_MSI)\r
9456 *\r
9457 * @{\r
9458 */\r
9459 typedef pcieTiConfIrqMsi_t pcieTiConfIrqEnableSetMsiReg_t;\r
9460 /* @} */\r
9461 \r
9462 /**\r
9463 * @ingroup pcielld_reg_ti_conf\r
9464 * @brief Specification of the TI CONF IRQ MSI Enable Clear register\r
9465 *\r
9466 * Enable of legacy and MSI interrupt requests; Write 1 to clear\r
9467 * (ie to disable interrupt). Readout is the same as corresponding\r
9468 * _SET register.\r
9469 *\r
9470 * For each IRQ in @ref pcieTiConfIrqMsi_t\r
9471 * <table>\r
9472 * <tr><th>action</th><th>value</th><th>description</th></tr>\r
9473 * <tr><td>Write</td><td>0</td><td>No effect</td></tr>\r
9474 * <tr><td>Write</td><td>1</td><td>Disable event</td></tr>\r
9475 * <tr><td>Read</td><td>0</td><td>IRQ event is disabled</td></tr>\r
9476 * <tr><td>Read</td><td>1</td><td>IRQ event is enabled</td></tr>\r
9477 * </table>\r
9478 *\r
9479 * This register may be used for both endpoint and root complex modes.\r
9480 *\r
9481 * This register is only available on rev 1 hw (TI_CONF_IRQENABLE_CLR_MSI)\r
9482 *\r
9483 * @{\r
9484 */\r
9485 typedef pcieTiConfIrqMsi_t pcieTiConfIrqEnableClrMsiReg_t;\r
9486 /* @} */\r
9487 \r
9488 /**\r
9489 * @ingroup pcielld_reg_ti_conf\r
9490 * @brief Specification of the TI CONF Device Type register\r
9491 *\r
9492 * Sets the Dual-Mode device's type\r
9493 *\r
9494 * This register may be used for both endpoint and root complex modes.\r
9495 *\r
9496 * This register is only available on rev 1 hw (TI_CONF_DEVICE_TYPE)\r
9497 *\r
9498 * @{\r
9499 */\r
9500 typedef struct pcieTiConfDeviceTypeReg_s {\r
9501 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9502 /**\r
9503 * @brief [rw] Device Type\r
9504 *\r
9505 * PCIe device type including the contents of the PCI config\r
9506 * space (Type-0 for EP, Type-1 for RC); Apply fundamental\r
9507 * reset after change; Do not change during core operation.\r
9508 *\r
9509 * <table>\r
9510 * <tr><th>value</th><th>description</th></tr>\r
9511 * <tr><td>0x0</td><td>PCIe endpoint (EP)</td></tr>\r
9512 * <tr><td>0x1</td><td>Legacy PCIe endpoint (LEG_EP)</td></tr>\r
9513 * <tr><td>0x4</td><td>Root Complex (RC)</td></tr>\r
9514 * <tr><td>Other values</td><td>Reserved</td></tr>\r
9515 * </table>\r
9516 *\r
9517 * On rev 1 hw, this corresponds to LINE_NUMBER\r
9518 *\r
9519 * Field size: 4 bits\r
9520 */\r
9521 uint8_t type;\r
9522 } pcieTiConfDeviceTypeReg_t;\r
9523 /* @} */\r
9524 \r
9525 /**\r
9526 * @ingroup pcielld_reg_ti_conf\r
9527 * @brief Specification of the TI CONF Device Command register\r
9528 *\r
9529 * Device command (startup control and status);\r
9530 * WARNING: cleared by all reset conditions, including fundamental reset\r
9531 *\r
9532 * This register may be used for both endpoint and root complex modes.\r
9533 *\r
9534 * This register is only available on rev 1 hw (TI_CONF_DEVICE_CMD)\r
9535 *\r
9536 * @{\r
9537 */\r
9538 typedef struct pcieTiConfDeviceCmdReg_s {\r
9539 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9540 /**\r
9541 * @brief [ro] LTSSM state/substate implementation-specific, for\r
9542 * debug (@ref pcieLtssmState_e)\r
9543 *\r
9544 * <table>\r
9545 * <tr><th>read value</th><th>description</th></tr>\r
9546 * <tr><td>0x00</td><td>DETECT_QUIET</td></tr>\r
9547 * <tr><td>0x01</td><td>DETECT_ACT</td></tr>\r
9548 * <tr><td>0x02</td><td>POLL_ACTIVE</td></tr>\r
9549 * <tr><td>0x03</td><td>POLL_COMPLIANCE</td></tr>\r
9550 * <tr><td>0x04</td><td>POLL_CONFIG</td></tr>\r
9551 * <tr><td>0x05</td><td>PRE_DETECT_QUIET</td></tr>\r
9552 * <tr><td>0x06</td><td>DETECT_WAIT</td></tr>\r
9553 * <tr><td>0x07</td><td>CFG_LINKWD_START</td></tr>\r
9554 * <tr><td>0x08</td><td>CFG_LINKWD_ACEPT</td></tr>\r
9555 * <tr><td>0x09</td><td>CFG_LANENUM_WAIT</td></tr>\r
9556 * <tr><td>0x0A</td><td>CFG_LANENUM_ACEPT</td></tr>\r
9557 * <tr><td>0x0B</td><td>CFG_COMPLETE</td></tr>\r
9558 * <tr><td>0x0C</td><td>CFG_IDLE</td></tr>\r
9559 * <tr><td>0x0D</td><td>RCVRY_LOCK</td></tr>\r
9560 * <tr><td>0x0E</td><td>RCVRY_SPEED</td></tr>\r
9561 * <tr><td>0x0F</td><td>RCVRY_RCVRCFG</td></tr>\r
9562 * <tr><td>0x10</td><td>RCVRY_IDLE</td></tr>\r
9563 * <tr><td>0x11</td><td>L0</td></tr>\r
9564 * <tr><td>0x12</td><td>L0S</td></tr>\r
9565 * <tr><td>0x13</td><td>L123_SEND_EIDLE</td></tr>\r
9566 * <tr><td>0x14</td><td>L1_IDLE</td></tr>\r
9567 * <tr><td>0x15</td><td>L2_IDLE</td></tr>\r
9568 * <tr><td>0x16</td><td>L2_WAKE</td></tr>\r
9569 * <tr><td>0x17</td><td>DISABLED_ENTRY</td></tr>\r
9570 * <tr><td>0x18</td><td>DISABLED_IDLE</td></tr>\r
9571 * <tr><td>0x19</td><td>DISABLED</td></tr>\r
9572 * <tr><td>0x1A</td><td>LPBK_ENTRY</td></tr>\r
9573 * <tr><td>0x1B</td><td>LPBK_ACTIVE</td></tr>\r
9574 * <tr><td>0x1C</td><td>LPBK_EXIT</td></tr>\r
9575 * <tr><td>0x1D</td><td>LPBK_EXIT_TIMEOUT</td></tr>\r
9576 * <tr><td>0x1E</td><td>HOT_RESET_ENTRY</td></tr>\r
9577 * <tr><td>0x1F</td><td>HOT_RESET</td></tr>\r
9578 * <tr><td>0x20</td><td>RCVRY_EQ0</td></tr>\r
9579 * <tr><td>0x21</td><td>RCVRY_EQ1</td></tr>\r
9580 * <tr><td>0x22</td><td>RCVRY_EQ2</td></tr>\r
9581 * <tr><td>0x23</td><td>RCVRY_EQ3</td></tr>\r
9582 * </table>\r
9583 *\r
9584 * On rev 1 hw, this corresponds to LTSSM_STATE\r
9585 *\r
9586 * Field size: 6 bits\r
9587 */\r
9588 uint8_t ltssmState;\r
9589 /**\r
9590 * @brief [rw] LTSSM enable: start the PCI link\r
9591 *\r
9592 * Set bit to start PCIE link training. Note: this bit is\r
9593 * CLEARED BY FUNDAMENTAL RESET)\r
9594 *\r
9595 * <table>\r
9596 * <tr><th>value</th><th>description</th></tr>\r
9597 * <tr><td>0x0</td><td>DISABLED</td></tr>\r
9598 * <tr><td>0x1</td><td>ENABLED</td></tr>\r
9599 * </table>\r
9600 *\r
9601 * On rev 1 hw, this corresponds to LTSSM_EN\r
9602 *\r
9603 * Field size: 1 bit\r
9604 */\r
9605 uint8_t ltssmEn;\r
9606 /**\r
9607 * @brief [rw] Application Request Retry Enable\r
9608 *\r
9609 * Application Request Retry Enable. Note: this bit is CLEARED\r
9610 * BY FUNDAMENTAL RESET)\r
9611 *\r
9612 * <table>\r
9613 * <tr><th>value</th><th>description</th></tr>\r
9614 * <tr><td>0x0</td><td>DISABLED:\r
9615 * Incoming PCI transactions are processed normally</td></tr>\r
9616 * <tr><td>0x1</td><td>ENABLED:\r
9617 * Incoming PCI transactions are responded with "retry"</td></tr>\r
9618 * </table>\r
9619 *\r
9620 * On rev 1 hw, this corresponds to APP_REQ_RETRY_EN\r
9621 *\r
9622 * Field size: 1 bit\r
9623 */\r
9624 uint8_t appReqRetryEn;\r
9625 uint8_t devNum; /**< @brief [ro] PCIe device number (5 bits) */\r
9626 uint8_t busNum; /**< @brief [ro] PCIe bus number (8 bits) */\r
9627 } pcieTiConfDeviceCmdReg_t;\r
9628 /* @} */\r
9629 \r
9630 /**\r
9631 * @ingroup pcielld_reg_ti_conf\r
9632 * @brief Specification of the TI CONF PM Control Register\r
9633 *\r
9634 * Power Management Control\r
9635 *\r
9636 * This register may be used for both endpoint and root complex modes.\r
9637 *\r
9638 * This register is only available on rev 1 hw (TI_CONF_PM_CTRL)\r
9639 *\r
9640 * @{\r
9641 */\r
9642 typedef struct pcieTiConfPmCtrlReg_s {\r
9643 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9644 /**\r
9645 * @brief [wo] Transmits PME_Turn_Off message downstream (RC mode only)\r
9646 *\r
9647 * Eventually sends all links of hierarchy domain to L2L/3_ready\r
9648 *\r
9649 * <table>\r
9650 * <tr><th>write value</th><th>description</th></tr>\r
9651 * <tr><td>0x0</td><td>NOACTION</td></tr>\r
9652 * <tr><td>0x1</td><td>TRANSMIT</td></tr>\r
9653 * </table>\r
9654 *\r
9655 * Reads always return 0.\r
9656 *\r
9657 * On rev 1 hw, this corresponds to PME_TURN_OFF\r
9658 *\r
9659 * Field size: 1 bit\r
9660 */\r
9661 uint8_t pmeTurnOff;\r
9662 /**\r
9663 * @brief [wo] Transmits PM_PME wakeup message (EP mode only)\r
9664 *\r
9665 * <table>\r
9666 * <tr><th>write value</th><th>description</th></tr>\r
9667 * <tr><td>0x0</td><td>NOACTION</td></tr>\r
9668 * <tr><td>0x1</td><td>TRANSMIT</td></tr>\r
9669 * </table>\r
9670 *\r
9671 * Reads always return 0.\r
9672 *\r
9673 * On rev 1 hw, this corresponds to PM_PME\r
9674 *\r
9675 * Field size: 1 bit\r
9676 */\r
9677 uint8_t pmPme;\r
9678 /**\r
9679 * @brief [rw] Indicates system readiness for the link to enter L2/L3\r
9680 *\r
9681 * Allows the transmission of PM_Enter_L23 following\r
9682 * PM_Turn_OFF / PME_TO_Ack handshake. Self-cleared upon transition to L2/L3.\r
9683 *\r
9684 * <table>\r
9685 * <tr><th>value</th><th>description</th></tr>\r
9686 * <tr><td>0x0</td><td>NOT_READY</td></tr>\r
9687 * <tr><td>0x1</td><td>READY</td></tr>\r
9688 * </table>\r
9689 *\r
9690 * On rev 1 hw, this corresponds to L23_READY\r
9691 *\r
9692 * Field size: 1 bit\r
9693 */\r
9694 uint8_t l23Ready;\r
9695 /**\r
9696 * @brief [rw] Request to transition to L1 state\r
9697 *\r
9698 * <table>\r
9699 * <tr><th>value</th><th>description</th></tr>\r
9700 * <tr><td>0x0</td><td>INACTIVE (No request)</td></tr>\r
9701 * <tr><td>0x1</td><td>ACTIVE (L1 entry request)</td></tr>\r
9702 * </table>\r
9703 *\r
9704 * On rev 1 hw, this corresponds to REQ_ENTR_L1\r
9705 *\r
9706 * Field size: 1 bit\r
9707 */\r
9708 uint8_t reqEntrL1;\r
9709 /**\r
9710 * @brief [rw] Request to exit L1 state (to L0)\r
9711 *\r
9712 * <table>\r
9713 * <tr><th>value</th><th>description</th></tr>\r
9714 * <tr><td>0x0</td><td>INACTIVE (No request)</td></tr>\r
9715 * <tr><td>0x1</td><td>ACTIVE (L1 exit request)</td></tr>\r
9716 * </table>\r
9717 *\r
9718 * On rev 1 hw, this corresponds to REQ_EXIT_L1\r
9719 *\r
9720 * Field size: 1 bit\r
9721 */\r
9722 uint8_t reqExitL1;\r
9723 /**\r
9724 * @brief [rw] Auxilliary Power Detection\r
9725 *\r
9726 * Status of Vaux detection for the PCIe controller.\r
9727 * Determines transition to L2 vs L3 upon Vmain turn-off.\r
9728 *\r
9729 * <table>\r
9730 * <tr><th>value</th><th>description</th></tr>\r
9731 * <tr><td>0x0</td><td>UNPOWERED:\r
9732 * Vaux not present: D3cold maps to L3 link state</td></tr>\r
9733 * <tr><td>0x1</td><td>POWERED:\r
9734 * Vaux present: D3cold maps to L2 link state</td></tr>\r
9735 * </table>\r
9736 *\r
9737 * On rev 1 hw, this corresponds to AUX_PWR_DET\r
9738 *\r
9739 * Field size: 1 bit\r
9740 */\r
9741 uint8_t auxPwrDet;\r
9742 } pcieTiConfPmCtrlReg_t;\r
9743 /* @} */\r
9744 \r
9745 /**\r
9746 * @ingroup pcielld_reg_ti_conf\r
9747 * @brief Specification of the TI CONF PHY CS\r
9748 *\r
9749 * Physical Layer Control and Status\r
9750 *\r
9751 * This register may be used for both endpoint and root complex modes.\r
9752 *\r
9753 * This register is only available on rev 1 hw (TI_CONF_PHY_CS)\r
9754 *\r
9755 * @{\r
9756 */\r
9757 typedef struct pcieTiConfPhyCsReg_s {\r
9758 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9759 /**\r
9760 * @brief [ro] Link status, from LTSSM\r
9761 *\r
9762 * <table>\r
9763 * <tr><th>value</th><th>description</th></tr>\r
9764 * <tr><td>0x0</td><td>DOWN</td></tr>\r
9765 * <tr><td>0x1</td><td>UP</td></tr>\r
9766 * </table>\r
9767 *\r
9768 * On rev 1 hw, this corresponds to LINK_UP\r
9769 *\r
9770 * Field size: 1 bit\r
9771 */\r
9772 uint8_t linkUp;\r
9773 /**\r
9774 * @brief [rw] Manual lane reversal control\r
9775 *\r
9776 * Manual lane reversal control, allowing lane 0 and lane 1\r
9777 * to be swapped by default; Both Tx and Rx are reversed;\r
9778 * Polarity of the individual lane is unchanged\r
9779 *\r
9780 * <table>\r
9781 * <tr><th>value</th><th>description</th></tr>\r
9782 * <tr><td>0x0</td><td>STRAIGHT</td></tr>\r
9783 * <tr><td>0x1</td><td>REVERSED</td></tr>\r
9784 * </table>\r
9785 *\r
9786 * On rev 1 hw, this corresponds to REVERSE_LANES\r
9787 *\r
9788 * Field size: 1 bit\r
9789 */\r
9790 uint8_t reverseLanes;\r
9791 } pcieTiConfPhyCsReg_t;\r
9792 /* @} */\r
9793 \r
9794 /**\r
9795 * @ingroup pcielld_reg_ti_conf\r
9796 * @brief Specification of the TI CONF INTX ASSERT\r
9797 *\r
9798 * Legacy INTx ASSERT message control, with 'x' in (A,B,C,D) set by\r
9799 * the 'Interrupt Pin' field.\r
9800 *\r
9801 * Write 1 to send message, read to get the status; EP mode only\r
9802 *\r
9803 * This register may be used for endpoint mode only.\r
9804 *\r
9805 * This register is only available on rev 1 hw (TI_CONF_INTX_ASSERT)\r
9806 *\r
9807 * @{\r
9808 */\r
9809 typedef struct pcieTiConfIntxAssertReg_s {\r
9810 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9811 /**\r
9812 * @brief [rw] INTx ASSERT for function 0\r
9813 *\r
9814 * <table>\r
9815 * <tr><th>action/value</th><th>description</th></tr>\r
9816 * <tr><td>Write 0x0</td><td>No action</td></tr>\r
9817 * <tr><td>Write 0x1</td><td>Transmit INTx ASSERT to RC</td></tr>\r
9818 * <tr><td>Read 0x0</td><td>INTx is inactive (deasserted)</td></tr>\r
9819 * <tr><td>Read 0x1</td><td>INTx is active (asserted)</td></tr>\r
9820 * </table>\r
9821 *\r
9822 * On rev 1 hw, this corresponds to ASSERT_F0\r
9823 *\r
9824 * Field size: 1 bit\r
9825 */\r
9826 uint8_t assertF0;\r
9827 } pcieTiConfIntxAssertReg_t;\r
9828 /* @} */\r
9829 \r
9830 /**\r
9831 * @ingroup pcielld_reg_ti_conf\r
9832 * @brief Specification of the TI CONF INTX DEASSERT\r
9833 *\r
9834 * Legacy INTx DEASSERT message control, with 'x' in (A,B,C,D) set by\r
9835 * the 'Interrupt Pin' field.\r
9836 *\r
9837 * Write 1 to send message, read to get the status; EP mode only\r
9838 *\r
9839 * This register may be used for endpoint mode only.\r
9840 *\r
9841 * This register is only available on rev 1 hw (TI_CONF_INTX_DEASSERT)\r
9842 *\r
9843 * @{\r
9844 */\r
9845 typedef struct pcieTiConfIntxDeassertReg_s {\r
9846 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9847 /**\r
9848 * @brief [rw] INTx ASSERT for function 0\r
9849 *\r
9850 * <table>\r
9851 * <tr><th>action/value</th><th>description</th></tr>\r
9852 * <tr><td>Write 0x0</td><td>No action</td></tr>\r
9853 * <tr><td>Write 0x1</td><td>Transmit INTx DEASSERT to RC</td></tr>\r
9854 * <tr><td>Read 0x0</td><td>INTx is inactive (deasserted)</td></tr>\r
9855 * <tr><td>Read 0x1</td><td>INTx is active (asserted)</td></tr>\r
9856 * </table>\r
9857 *\r
9858 * On rev 1 hw, this corresponds to DEASSERT_F0\r
9859 *\r
9860 * Field size: 1 bit\r
9861 */\r
9862 uint8_t deassertF0;\r
9863 } pcieTiConfIntxDeassertReg_t;\r
9864 /* @} */\r
9865 \r
9866 /**\r
9867 * @ingroup pcielld_reg_ti_conf\r
9868 * @brief Specification of the TI CONF MSI XMT Register\r
9869 *\r
9870 * MSI transmitter (EP mode); Specifies parameters of MSI, together\r
9871 * with MSI capability descriptor already configured by remote RC.\r
9872 *\r
9873 * This register may be used for endpoint mode only.\r
9874 *\r
9875 * This register is only available on rev 1 hw (TI_CONF_MSI_XMT)\r
9876 *\r
9877 * @{\r
9878 */\r
9879 typedef struct pcieTiConfMsiXmtReg_s {\r
9880 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9881 /**\r
9882 * @brief [rw] MSI transmit request (and grant status)\r
9883 *\r
9884 * <table>\r
9885 * <tr><th>action/value</th><th>description</th></tr>\r
9886 * <tr><td>Write 0x0</td><td>No action</td></tr>\r
9887 * <tr><td>Write 0x1</td><td>Request MSI transmission</td></tr>\r
9888 * <tr><td>Read 0x0</td><td>MSI transmission request pending</td></tr>\r
9889 * <tr><td>Read 0x1</td><td>No MSI request pending (last request granted)</td></tr>\r
9890 * </table>\r
9891 *\r
9892 * On rev 1 hw, this corresponds to MSI_REQ_GRANT\r
9893 *\r
9894 * Field size: 1 bit\r
9895 */\r
9896 uint8_t msiReqGrant;\r
9897 /**\r
9898 * @brief [rw] Function number for transmitted MSI\r
9899 *\r
9900 * Always 0 for single-function EP\r
9901 *\r
9902 * On rev 1 hw, this corresponds to MSI_FUNC_NUM\r
9903 *\r
9904 * Field size: 3 bits\r
9905 */\r
9906 uint8_t msiFuncNum;\r
9907 /**\r
9908 * @brief [rw] Vector number for transmitted MSI\r
9909 *\r
9910 * (as allowed by RC at RW 0x0 enumeration)\r
9911 *\r
9912 * On rev 1 hw, this corresponds to MSI_VECTOR\r
9913 *\r
9914 * Field size: 5 bits\r
9915 */\r
9916 uint8_t msiVector;\r
9917 /**\r
9918 * @brief [rw] Traffic class (TC) for transmitted MSI\r
9919 *\r
9920 * On rev 1 hw, this corresponds to MSI_TC\r
9921 *\r
9922 * Field size: 3 bits\r
9923 */\r
9924 uint8_t msiTc;\r
9925 } pcieTiConfMsiXmtReg_t;\r
9926 /* @} */\r
9927 \r
9928 /**\r
9929 * @ingroup pcielld_reg_ti_conf\r
9930 * @brief Specification of the TI CONF Debug Config\r
9931 *\r
9932 * Configuration of debug_data output and register (observability)\r
9933 *\r
9934 * This register may be used for both endpoint and root complex modes.\r
9935 *\r
9936 * This register is only available on rev 1 hw (TI_CONF_DEBUG_CFG)\r
9937 *\r
9938 * @{\r
9939 */\r
9940 typedef struct pcieTiConfDebugCfgReg_s {\r
9941 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9942 /**\r
9943 * @brief [rw] Debug_data mode\r
9944 *\r
9945 * On rev 1 hw, this corresponds to SEL\r
9946 *\r
9947 * Field size: 6 bits\r
9948 */\r
9949 uint8_t sel;\r
9950 } pcieTiConfDebugCfgReg_t;\r
9951 /* @} */\r
9952 \r
9953 /**\r
9954 * @ingroup pcielld_reg_ti_conf\r
9955 * @brief Specification of the TI CONF Debug Data\r
9956 *\r
9957 * Debug data vector, depending on DEBUG_CFG.sel value\r
9958 *\r
9959 * This register may be used for both endpoint and root complex modes.\r
9960 *\r
9961 * This register is only available on rev 1 hw (TI_CONF_DEBUG_DATA\r
9962 *\r
9963 * Entire register is [RO]\r
9964 *\r
9965 * @{\r
9966 */\r
9967 typedef struct pcieTiConfDebugDataReg_s {\r
9968 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9969 /**\r
9970 * @brief [ro] Debug\r
9971 *\r
9972 * On rev 1 hw, this corresponds to DEBUG\r
9973 *\r
9974 * Field size: 32 bits\r
9975 */\r
9976 uint32_t debug;\r
9977 } pcieTiConfDebugDataReg_t;\r
9978 /* @} */\r
9979 \r
9980 /**\r
9981 * @ingroup pcielld_reg_ti_conf\r
9982 * @brief Specification of the TI CONF Diag Control\r
9983 *\r
9984 * Diagnostic control\r
9985 *\r
9986 * This register may be used for both endpoint and root complex modes.\r
9987 *\r
9988 * This register is only available on rev 1 hw (TI_CONF_DIAG_CTRL)\r
9989 *\r
9990 * @{\r
9991 */\r
9992 typedef struct pcieTiConfDiagCtrlReg_s {\r
9993 uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
9994 /**\r
9995 * @brief [rw] Corrupts LSB of LCRC in the next packet, then self-clears.\r
9996 *\r
9997 * <table>\r
9998 * <tr><th>action/value</th><th>description</th></tr>\r
9999 * <tr><td>Write 0x0</td><td>not defined</td></tr>\r
10000 * <tr><td>Write 0x1</td><td>Request CRC corruption</td></tr>\r
10001 * <tr><td>Read 0x0</td><td>No CRC corruption pending</td></tr>\r
10002 * <tr><td>Read 0x1</td><td>CRC corruption pending</td></tr>\r
10003 * </table>\r
10004 *\r
10005 * On rev 1 hw, this corresponds to INV_LCRC\r
10006 *\r
10007 * Field size: 1 bit\r
10008 */\r
10009 uint8_t invLcrc;\r
10010 /**\r
10011 * @brief [rw] Corrupts LSB of ECRC in the next packet, then self-clears.\r
10012 *\r
10013 * <table>\r
10014 * <tr><th>action/value</th><th>description</th></tr>\r
10015 * <tr><td>Write 0x0</td><td>not defined</td></tr>\r
10016 * <tr><td>Write 0x1</td><td>Request CRC corruption</td></tr>\r
10017 * <tr><td>Read 0x0</td><td>No CRC corruption pending</td></tr>\r
10018 * <tr><td>Read 0x1</td><td>CRC corruption pending</td></tr>\r
10019 * </table>\r
10020 *\r
10021 * On rev 1 hw, this corresponds to INV_ECRC\r
10022 *\r
10023 * Field size: 1 bit\r
10024 */\r
10025 uint8_t invEcrc;\r
10026 /**\r
10027 * @brief [rw] SW must write 0\r
10028 *\r
10029 * On rev 1 hw, this corresponds to RESERVED(2)\r
10030 *\r
10031 * Field size: 1 bit\r
10032 */\r
10033 uint8_t fastLinkMode;\r
10034 } pcieTiConfDiagCtrlReg_t;\r
10035 /* @} */\r
10036 \r
10037 \r
10038 /**\r
10039 * @ingroup pcielld_api_structures\r
10040 * @brief Specification all registers\r
10041 *\r
10042 * This structure allows one or more registers to be read or written\r
10043 * through a single call.\r
10044 *\r
10045 * The user populates one or more pointers to structures. All structures\r
10046 * that are non-NULL are read or written.\r
10047 *\r
10048 * Once the pointers are populated, use @ref Pcie_readRegs and/or\r
10049 * @ref Pcie_writeRegs to perform the actual register accesses\r
10050 *\r
10051 */\r
10052 typedef struct pcieRegisters_s {\r
10053 \r
10054 /*****************************************************************************************\r
10055 *Application Registers\r
10056 *****************************************************************************************/\r
10057 pciePidReg_t *pid; /**< @brief PID */\r
10058 pcieCmdStatusReg_t *cmdStatus; /**< @brief Command Status*/\r
10059 pcieCfgTransReg_t *cfgTrans; /**< @brief Config Transaction*/\r
10060 pcieIoBaseReg_t *ioBase; /**< @brief IO TLP base*/\r
10061 pcieTlpCfgReg_t *tlpCfg; /**< @brief TLP Config*/\r
10062 pcieRstCmdReg_t *rstCmd; /**< @brief Reset Command*/\r
10063 pciePmCmdReg_t *pmCmd; /**< @brief Power Management Command*/\r
10064 pciePmCfgReg_t *pmCfg; /**< @brief Power Management Config*/\r
10065 pcieActStatusReg_t *actStatus; /**< @brief Activity Status */\r
10066 pcieObSizeReg_t *obSize; /**< @brief Outbound Translation region size*/\r
10067 pcieDiagCtrlReg_t *diagCtrl; /**< @brief Diagnostic Control */\r
10068 pcieEndianReg_t *endian; /**< @brief Endian Register*/\r
10069 pciePriorityReg_t *priority; /**< @brief Transaction Priority Register */\r
10070 pcieIrqEOIReg_t *irqEOI; /**< @brief End of Interrupt Register */\r
10071 pcieMsiIrqReg_t *msiIrq; /**< @brief MSI Interrupt IRQ Register*/\r
10072 pcieEpIrqSetReg_t *epIrqSet; /**< @brief Endpoint Interrupt Request Set Register*/\r
10073 pcieEpIrqClrReg_t *epIrqClr; /**< @brief Endpoint Interrupt Request clear Register*/\r
10074 pcieEpIrqStatusReg_t *epIrqStatus; /**< @brief Endpoint Interrupt status Register*/\r
10075 pcieGenPurposeReg_t *genPurpose[4]; /**< @brief General Purpose Registers */\r
10076 pcieMsiIrqStatusRawReg_t *msiIrqStatusRaw[8]; /**< @brief MSI Raw Interrupt Status Register*/\r
10077 pcieMsiIrqStatusReg_t *msiIrqStatus[8]; /**< @brief MSI Interrupt Enabled Status Register*/\r
10078 pcieMsiIrqEnableSetReg_t *msiIrqEnableSet[8]; /**< @brief MSI Interrupt Enable Set Register*/\r
10079 pcieMsiIrqEnableClrReg_t *msiIrqEnableClr[8]; /**< @brief MSI Interrupt Enable Clear Register*/\r
10080 pcieLegacyIrqStatusRawReg_t *legacyIrqStatusRaw[4]; /**< @brief Raw Interrupt Status Register*/\r
10081 pcieLegacyIrqStatusReg_t *legacyIrqStatus[4]; /**< @brief Interrupt Enabled Status Register*/\r
10082 pcieLegacyIrqEnableSetReg_t *legacyIrqEnableSet[4]; /**< @brief Interrupt Enable Set Register*/\r
10083 pcieLegacyIrqEnableClrReg_t *legacyIrqEnableClr[4]; /**< @brief Interrupt Enable Clear Register*/\r
10084 pcieErrIrqStatusRawReg_t *errIrqStatusRaw; /**< @brief Raw Interrupt Status Register*/\r
10085 pcieErrIrqStatusReg_t *errIrqStatus; /**< @brief Interrupt Enabled Status Register*/\r
10086 pcieErrIrqEnableSetReg_t *errIrqEnableSet; /**< @brief Interrupt Enable Set Register*/\r
10087 pcieErrIrqEnableClrReg_t *errIrqEnableClr; /**< @brief Interrupt Enable Clear Register*/\r
10088 pciePmRstIrqStatusRawReg_t *pmRstIrqStatusRaw; /**< @brief Power Management and Reset Raw Interrupt Status Register*/\r
10089 pciePmRstIrqStatusReg_t *pmRstIrqStatus; /**< @brief Power Management and Reset Interrupt Enabled Status Register*/\r
10090 pciePmRstIrqEnableSetReg_t *pmRstIrqEnableSet; /**< @brief Power Management and Reset Interrupt Enable Set Register*/\r
10091 pciePmRstIrqEnableClrReg_t *pmRstIrqEnableClr; /**< @brief Power Management and Reset Interrupt Enable Clear Register*/\r
10092 pcieObOffsetLoReg_t *obOffsetLo[8]; /**< @brief Outbound Translation region offset Low*/\r
10093 pcieObOffsetHiReg_t *obOffsetHi[8]; /**< @brief Outbound Translation region offset High*/\r
10094 pcieIbBarReg_t *ibBar[4]; /**< @brief Inbound Translation BAR*/\r
10095 pcieIbStartLoReg_t *ibStartLo[4]; /**< @brief Inbound Translation start Low*/\r
10096 pcieIbStartHiReg_t *ibStartHi[4]; /**< @brief Inbound Translation start High*/\r
10097 pcieIbOffsetReg_t *ibOffset[4]; /**< @brief Inbound Translation offset*/\r
10098 pciePcsCfg0Reg_t *pcsCfg0; /**< @brief PCS Configuration 0 Register */\r
10099 pciePcsCfg1Reg_t *pcsCfg1; /**< @brief PCS Configuration 1 Register */\r
10100 pciePcsStatusReg_t *pcsStatus; /**< @brief PCS Status Register */\r
10101 pcieSerdesCfg0Reg_t *serdesCfg0; /**< @brief SERDES config 0 Register*/\r
10102 pcieSerdesCfg1Reg_t *serdesCfg1; /**< @brief SERDES config 1 Register*/\r
10103 \r
10104 /*****************************************************************************************\r
10105 *Configuration Registers\r
10106 *****************************************************************************************/\r
10107 \r
10108 /*Type 0, Type1 Common Registers*/\r
10109 pcieVndDevIdReg_t *vndDevId; /**< @brief Vendor and device ID*/\r
10110 pcieStatusCmdReg_t *statusCmd; /**< @brief Status Command*/\r
10111 pcieRevIdReg_t *revId; /**< @brief Class code and Revision ID*/\r
10112 \r
10113 /*Type 0 Registers*/\r
10114 pcieBistReg_t *bist; /**< @brief Bist Header*/\r
10115 pcieType0BarIdx_t *type0BarIdx; /**< @brief Type 0 (EP) BAR register*/\r
10116 pcieType0Bar32bitIdx_t *type0Bar32bitIdx; /**< @brief Type 0 BAR 32bits register*/\r
10117 pcieCardbusCisPointerReg_t *cardbusCisPointer; /**< @brief cardbus CIS pointer register*/\r
10118 pcieSubIdReg_t *subId; /**< @brief Subsystem ID*/\r
10119 pcieExpRomReg_t *expRom; /**< @brief Expansion ROM base addr*/\r
10120 pcieCapPtrReg_t *capPtr; /**< @brief Capabilities Pointer*/\r
10121 pcieIntPinReg_t *intPin; /**< @brief Interrupt Pin*/\r
10122 \r
10123 /*Type 1 Registers*/\r
10124 pcieType1BistHeaderReg_t *type1BistHeader; /**< @brief Bist Header, Latency Timer, Cache Line */\r
10125 pcieType1BarIdx_t *type1BarIdx; /**< @brief Type 1 (RC) BAR register*/\r
10126 pcieType1Bar32bitIdx_t *type1Bar32bitIdx; /**< @brief Type 1 BAR 32bits register*/\r
10127 pcieType1BusNumReg_t *type1BusNum; /**< @brief Latency Timer and Bus Number */\r
10128 pcieType1SecStatReg_t *type1SecStat; /**< @brief Secondary Status and IO space */\r
10129 pcieType1MemspaceReg_t *type1Memspace; /**< @brief Memory Limit*/\r
10130 pciePrefMemReg_t *prefMem; /**< @brief Prefetch Memory Limit and Base*/\r
10131 pciePrefBaseUpperReg_t *prefBaseUpper; /**< @brief Prefetch Memory Base Upper*/\r
10132 pciePrefLimitUpperReg_t *prefLimitUpper; /**< @brief Prefetch Memory Limit Upper*/\r
10133 pcieType1IOSpaceReg_t *type1IOSpace; /**< @brief IO Base and Limit Upper 16 bits */\r
10134 pcieType1CapPtrReg_t *type1CapPtr; /**< @brief Capabilities pointer */\r
10135 pcieType1ExpnsnRomReg_t *type1ExpnsnRom; /**< @brief Expansion ROM base addr */\r
10136 pcieType1BridgeIntReg_t *type1BridgeInt; /**< @brief Bridge Control and Interrupt Pointer */\r
10137 \r
10138 /* Power Management Capabilities Registers */\r
10139 pciePMCapReg_t *pmCap; /**< @brief Power Management Capabilities */\r
10140 pciePMCapCtlStatReg_t *pmCapCtlStat; /**< @brief Power Management Control and Status */\r
10141 \r
10142 /*MSI Capabilities Registers*/\r
10143 pcieMsiCapReg_t *msiCap; /**< @brief MSI Capabilities */\r
10144 pcieMsiLo32Reg_t *msiLo32; /**< @brief MSI Lower 32 bits */\r
10145 pcieMsiUp32Reg_t *msiUp32; /**< @brief MSI Upper 32 bits */\r
10146 pcieMsiDataReg_t *msiData; /**< @brief MSI Data */\r
10147 \r
10148 /*Capabilities Registers*/\r
10149 pciePciesCapReg_t *pciesCap; /**< @brief PCI Express Capabilities Register*/\r
10150 pcieDeviceCapReg_t *deviceCap; /**< @brief Device Capabilities Register*/\r
10151 pcieDevStatCtrlReg_t *devStatCtrl; /**< @brief Device Status and Control*/\r
10152 pcieLinkCapReg_t *linkCap; /**< @brief Link Capabilities Register*/\r
10153 pcieLinkStatCtrlReg_t *linkStatCtrl; /**< @brief Link Status and Control Register*/\r
10154 pcieSlotCapReg_t *slotCap; /**< @brief Slot Capabilities Register */\r
10155 pcieSlotStatCtrlReg_t *slotStatCtrl; /**< @brief Slot Status and Control Register */\r
10156 pcieRootCtrlCapReg_t *rootCtrlCap; /**< @brief Root Control and Capabilities Register */\r
10157 pcieRootStatusReg_t *rootStatus; /**< @brief Root Status and Control Register */\r
10158 pcieDevCap2Reg_t *devCap2; /**< @brief Device Capabilities 2 Register*/\r
10159 pcieDevStatCtrl2Reg_t *devStatCtrl2; /**< @brief Device Status and Control 2 Register*/\r
10160 pcieLnkCap2Reg_t *linkCap2; /**< @brief Link Capabilities 2 Register*/\r
10161 pcieLinkCtrl2Reg_t *linkCtrl2; /**< @brief Link Control 2 Register*/\r
10162 \r
10163 /*Capabilities Extended Registers*/\r
10164 pcieExtCapReg_t *extCap; /**< @brief Extended Capabilties Header */\r
10165 pcieUncErrReg_t *uncErr; /**< @brief Uncorrectable Error Status */\r
10166 pcieUncErrMaskReg_t *uncErrMask; /**< @brief Uncorrectable Error Mask */\r
10167 pcieUncErrSvrtyReg_t *uncErrSvrty; /**< @brief Uncorrectable Error Severity */\r
10168 pcieCorErrReg_t *corErr; /**< @brief Correctable Error Status */\r
10169 pcieCorErrMaskReg_t *corErrMask; /**< @brief Correctable Error Mask */\r
10170 pcieAccrReg_t *accr; /**< @brief Advanced Capabilities and Control*/\r
10171 pcieHdrLogReg_t *hdrLog[4]; /**< @brief Header Log Registers */\r
10172 pcieRootErrCmdReg_t *rootErrCmd; /**< @brief Root Error Command */\r
10173 pcieRootErrStReg_t *rootErrSt; /**< @brief Root Error Status */\r
10174 pcieErrSrcIDReg_t *errSrcID; /**< @brief Error Source Identification */\r
10175 \r
10176 /*Port Logic Registers*/\r
10177 pciePlAckTimerReg_t *plAckTimer; /**< @brief Ack Latency Time and Replay Timer */\r
10178 pciePlOMsgReg_t *plOMsg; /**< @brief Other Message */\r
10179 pciePlForceLinkReg_t *plForceLink; /**< @brief Port Force Link */\r
10180 pcieAckFreqReg_t *ackFreq; /**< @brief Ack Frequency */\r
10181 pcieLnkCtrlReg_t *lnkCtrl; /**< @brief Port Link Control*/\r
10182 pcieLaneSkewReg_t *laneSkew; /**< @brief Lane Skew */\r
10183 pcieSymNumReg_t *symNum; /**< @brief Symbol Number */\r
10184 pcieSymTimerFltMaskReg_t *symTimerFltMask; /**< @brief Symbol Timer and Filter Mask */\r
10185 pcieFltMask2Reg_t *fltMask2; /**< @brief Filter Mask 2 */\r
10186 pcieDebug0Reg_t *debug0; /**< @brief Debug 0*/\r
10187 pcieDebug1Reg_t *debug1; /**< @brief Debug 1 Register*/\r
10188 pcieGen2Reg_t *gen2; /**< @brief Gen2 */\r
10189 \r
10190 /* Rev 1 PLCONF */\r
10191 pciePlconfObnpSubreqCtrlReg_t *plconfObnpSubreqCtrl; /**< @brief PCIECTRL_PL_OBNP_SUBREQ_CTRL*/\r
10192 pciePlconfTrPStsRReg_t *plconfTrPStsR; /**< @brief PCIECTRL_PL_TR_P_STS_R*/\r
10193 pciePlconfTrNpStsRReg_t *plconfTrNpStsR; /**< @brief PCIECTRL_PL_TR_NP_STS_R*/\r
10194 pciePlconfTrCStsRReg_t *plconfTrCStsR; /**< @brief PCIECTRL_PL_TR_C_STS_R*/\r
10195 pciePlconfQStsRReg_t *plconfQStsR; /**< @brief PCIECTRL_PL_Q_STS_R*/\r
10196 pciePlconfVcTrAR1Reg_t *plconfVcTrAR1; /**< @brief PCIECTRL_PL_VC_TR_A_R1*/\r
10197 pciePlconfVcTrAR2Reg_t *plconfVcTrAR2; /**< @brief PCIECTRL_PL_VC_TR_A_R2*/\r
10198 pciePlconfVc0PrQCReg_t *plconfVc0PrQC; /**< @brief PCIECTRL_PL_VC0_PR_Q_C*/\r
10199 pciePlconfVc0NprQCReg_t *plconfVc0NprQC; /**< @brief PCIECTRL_PL_VC0_NPR_Q_C*/\r
10200 pciePlconfVc0CrQCReg_t *plconfVc0CrQC; /**< @brief PCIECTRL_PL_VC0_CR_Q_C*/\r
10201 /* note: plconfWidthSpeedCtlReg_t is mapped to gen2 above */\r
10202 pciePlconfPhyStsRReg_t *plconfPhyStsR; /**< @brief PCIECTRL_PL_PHY_STS_R*/\r
10203 pciePlconfPhyCtrlRReg_t *plconfPhyCtrlR; /**< @brief PCIECTRL_PL_PHY_CTRL_R*/\r
10204 pciePlconfMsiCtrlAddressReg_t *plconfMsiCtrlAddress; /**< @brief PCIECTRL_PL_MSI_CTRL_ADDRESS*/\r
10205 pciePlconfMsiCtrlUpperAddressReg_t *plconfMsiCtrlUpperAddress; /**< @brief PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS*/\r
10206 pciePlconfMsiCtrlIntEnableReg_t *plconfMsiCtrlIntEnable[8]; /**< @brief PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N*/\r
10207 pciePlconfMsiCtrlIntMaskReg_t *plconfMsiCtrlIntMask[8]; /**< @brief PCIECTRL_PL_MSI_CTRL_INT_MASK_N*/\r
10208 pciePlconfMsiCtrlIntStatusReg_t *plconfMsiCtrlIntStatus[8]; /**< @brief PCIECTRL_PL_MSI_CTRL_INT_STATUS_N*/\r
10209 pciePlconfMsiCtrlGpioReg_t *plconfMsiCtrlGpio; /**< @brief PCIECTRL_PL_MSI_CTRL_GPIO*/\r
10210 pciePlconfPipeLoopbackReg_t *plconfPipeLoopback; /**< @brief PCIECTRL_PL_PIPE_LOOPBACK*/\r
10211 pciePlconfDbiRoWrEnReg_t *plconfDbiRoWrEn; /**< @brief PCIECTRL_PL_DBI_RO_WR_EN*/\r
10212 pciePlconfAxiSlvErrRespReg_t *plconfAxiSlvErrResp; /**< @brief PCIECTRL_PL_AXI_SLV_ERR_RESP*/\r
10213 pciePlconfAxiSlvTimeoutReg_t *plconfAxiSlvTimeout; /**< @brief PCIECTRL_PL_AXI_SLV_TIMEOUT*/\r
10214 pciePlconfIatuIndexReg_t *plconfIatuIndex; /**< @brief PCIECTRL_PL_IATU_INDEX*/\r
10215 pciePlconfIatuRegCtrl1Reg_t *plconfIatuRegCtrl1; /**< @brief PCIECTRL_PL_IATU_REG_CTRL_1*/\r
10216 pciePlconfIatuRegCtrl2Reg_t *plconfIatuRegCtrl2; /**< @brief PCIECTRL_PL_IATU_REG_CTRL_2*/\r
10217 pciePlconfIatuRegLowerBaseReg_t *plconfIatuRegLowerBase; /**< @brief PCIECTRL_PL_IATU_REG_LOWER_BASE*/\r
10218 pciePlconfIatuRegUpperBaseReg_t *plconfIatuRegUpperBase; /**< @brief PCIECTRL_PL_IATU_REG_UPPER_BASE*/\r
10219 pciePlconfIatuRegLimitReg_t *plconfIatuRegLimit; /**< @brief PCIECTRL_PL_IATU_REG_LIMIT*/\r
10220 pciePlconfIatuRegLowerTargetReg_t *plconfIatuRegLowerTarget; /**< @brief PCIECTRL_PL_IATU_REG_LOWER_TARGET*/\r
10221 pciePlconfIatuRegUpperTargetReg_t *plconfIatuRegUpperTarget; /**< @brief PCIECTRL_PL_IATU_REG_UPPER_TARGET*/\r
10222 pciePlconfIatuRegCtrl3Reg_t *plconfIatuRegCtrl3; /**< @brief PCIECTRL_PL_IATU_REG_CTRL_3*/\r
10223 \r
10224 /*****************************************************************************************\r
10225 * HW Rev 1 configuration registers\r
10226 *****************************************************************************************/\r
10227 /* TI Configuration registers (PCIECTRL_TI_CONF* in TRM) */\r
10228 pcieTiConfRevisionReg_t *tiConfRevision; /**< @brief PCIECTRL_TI_CONF_REVISION*/\r
10229 pcieTiConfSysConfigReg_t *tiConfSysConfig; /**< @brief PCIECTRL_TI_CONF_SYSCONFIG*/\r
10230 pcieTiConfIrqEoiReg_t *tiConfIrqEoi; /**< @brief PCIECTRL_TI_CONF_IRQ_EOI*/\r
10231 pcieTiConfIrqStatusRawMainReg_t *tiConfIrqStatusRawMain; /**< @brief PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN*/\r
10232 pcieTiConfIrqStatusMainReg_t *tiConfIrqStatusMain; /**< @brief PCIECTRL_TI_CONF_IRQSTATUS_MAIN*/\r
10233 pcieTiConfIrqEnableSetMainReg_t *tiConfIrqEnableSetMain; /**< @brief PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN*/\r
10234 pcieTiConfIrqEnableClrMainReg_t *tiConfIrqEnableClrMain; /**< @brief PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN*/\r
10235 pcieTiConfIrqStatusRawMsiReg_t *tiConfIrqStatusRawMsi; /**< @brief PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI*/\r
10236 pcieTiConfIrqStatusMsiReg_t *tiConfIrqStatusMsi; /**< @brief PCIECTRL_TI_CONF_IRQSTATUS_MSI*/\r
10237 pcieTiConfIrqEnableSetMsiReg_t *tiConfIrqEnableSetMsi; /**< @brief PCIECTRL_TI_CONF_IRQENABLE_SET_MSI*/\r
10238 pcieTiConfIrqEnableClrMsiReg_t *tiConfIrqEnableClrMsi; /**< @brief PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI*/\r
10239 pcieTiConfDeviceTypeReg_t *tiConfDeviceType; /**< @brief PCIECTRL_TI_CONF_DEVICE_TYPE*/\r
10240 pcieTiConfDeviceCmdReg_t *tiConfDeviceCmd; /**< @brief PCIECTRL_TI_CONF_DEVICE_CMD*/\r
10241 pcieTiConfPmCtrlReg_t *tiConfPmCtrl; /**< @brief PCIECTRL_TI_CONF_PM_CTRL*/\r
10242 pcieTiConfPhyCsReg_t *tiConfPhyCs; /**< @brief PCIECTRL_TI_CONF_PHY_CS*/\r
10243 pcieTiConfIntxAssertReg_t *tiConfIntxAssert; /**< @brief PCIECTRL_TI_CONF_INTX_ASSERT*/\r
10244 pcieTiConfIntxDeassertReg_t *tiConfIntxDeassert; /**< @brief PCIECTRL_TI_CONF_INTX_DEASSERT*/\r
10245 pcieTiConfMsiXmtReg_t *tiConfMsiXmt; /**< @brief PCIECTRL_TI_CONF_MSI_XMT*/\r
10246 pcieTiConfDebugCfgReg_t *tiConfDebugCfg; /**< @brief PCIECTRL_TI_CONF_DEBUG_CFG*/\r
10247 pcieTiConfDebugDataReg_t *tiConfDebugData; /**< @brief PCIECTRL_TI_CONF_DEBUG_DATA*/\r
10248 pcieTiConfDiagCtrlReg_t *tiConfDiagCtrl; /**< @brief PCIECTRL_TI_CONF_DIAG_CTRL*/\r
10249 } pcieRegisters_t;\r
10250 \r
10251 /*****************************************************************************\r
10252 ********** Configuration Structures **********************\r
10253 ****************************************************************************/\r
10254 \r
10255 /**\r
10256 * @ingroup pcielld_api_structures\r
10257 * @brief Specification of pcieIbTransCfg\r
10258 *\r
10259 * The pcieIbTransCfg is used to configure the Inbound Translation Registers\r
10260 */\r
10261 typedef struct pcieIbTransCfg_s {\r
10262 /**\r
10263 * @brief Inbound Translation BAR match\r
10264 */\r
10265 uint8_t ibBar;\r
10266 /**\r
10267 * @brief Low Inbound Start address (32bits)\r
10268 */\r
10269 uint32_t ibStartAddrLo;\r
10270 /**\r
10271 * @brief High Inbound Start address (32bits)\r
10272 */\r
10273 uint32_t ibStartAddrHi;\r
10274 /**\r
10275 * @brief Inbound Translation Address Offset (32bits)\r
10276 */\r
10277 uint32_t ibOffsetAddr;\r
10278 /**\r
10279 * @brief Identifies the translation region (0-3)\r
10280 */\r
10281 uint8_t region;\r
10282 } pcieIbTransCfg_t;\r
10283 \r
10284 /**\r
10285 * @ingroup pcielld_api_structures\r
10286 * @brief Specification of pcieBarCfg\r
10287 *\r
10288 * The pcieBarCfg is used to configure a 32bits BAR Register\r
10289 * or the lower 32bits of a 64bits BAR register. \n\r
10290 * This should NOT be used to configure BAR masks.\n\r
10291 * This should NOT be used to configure the Upper 32bits of\r
10292 * a 64bits BAR register.\r
10293 */\r
10294 typedef struct pcieBarCfg_s {\r
10295 /**\r
10296 * @brief Local or remote peripheral\r
10297 */\r
10298 pcieLocation_e location;\r
10299 /**\r
10300 * @brief PCIe mode\r
10301 */\r
10302 pcieMode_e mode;\r
10303 /**\r
10304 * @brief Base Address (32bits)\r
10305 */\r
10306 uint32_t base;\r
10307 /**\r
10308 * @brief Prefetch\r
10309 */\r
10310 pcieBarPref_e prefetch;\r
10311 /**\r
10312 * @brief Type\r
10313 */\r
10314 pcieBarType_e type;\r
10315 /**\r
10316 * @brief Memory Space\r
10317 */\r
10318 pcieBarMem_e memSpace;\r
10319 /**\r
10320 * @brief BAR index\r
10321 */\r
10322 uint8_t idx;\r
10323 } pcieBarCfg_t;\r
10324 \r
10325 /**\r
10326 * @ingroup pcielld_api_structures\r
10327 * @brief Specification of Pcie_DeviceCfgBaseAddr\r
10328 *\r
10329 * The Pcie_DeviceCfg is used to specify device level configuration\r
10330 * to the LLD.\r
10331 */\r
10332 typedef struct\r
10333 {\r
10334 void *cfgBase;\r
10335 void *dataBase;\r
10336 volatile uint32_t *pcieSSModeAddr; /**< address of PCIESSMODE register */\r
10337 uint32_t pcieSSModeMask; /**< mask for PCIESSMODE field in @ref pcieSSModeAddr */\r
10338 uint32_t pcieSSModeShift; /**< shift for PCIESSMODE field in @ref pcieSSModeAddr */\r
10339 } Pcie_DeviceCfgBaseAddr;\r
10340 \r
10341 /**\r
10342 * @ingroup pcielld_api_structures\r
10343 * @brief Specification of Pcie_Handle\r
10344 *\r
10345 * The Pcie_Handle is used to identify a PCIE LLD instance\r
10346 */\r
10347 typedef void *Pcie_Handle;\r
10348 \r
10349 /**\r
10350 * @ingroup pcielld_api_structures\r
10351 * @brief Specification of Pcie_FxnTable\r
10352 *\r
10353 * The Pcie_FxnTable is used to abstract multiple implementations of\r
10354 * pcie hardware.\r
10355 */\r
10356 typedef struct\r
10357 {\r
10358 /*! Function to set PCIE to EP or RC for one device */\r
10359 pcieRet_e (*setInterfaceMode) (Pcie_Handle handle, pcieMode_e mode);\r
10360 /*! Function to get the PCIE data area base address & size */\r
10361 pcieRet_e (*getMemSpaceRange) (Pcie_Handle handle, void **base,\r
10362 uint32_t *size);\r
10363 /*! Function to read any PCIE register(s) */\r
10364 pcieRet_e (*readRegs) (Pcie_Handle handle, pcieLocation_e location,\r
10365 pcieRegisters_t *readRegs);\r
10366 /*! Function to write any PCIE register(s) */\r
10367 pcieRet_e (*writeRegs) (Pcie_Handle handle, pcieLocation_e location,\r
10368 pcieRegisters_t *writeRegs);\r
10369 /*! Function to configure outbound translation registers */\r
10370 pcieRet_e (*cfgObOffset) (Pcie_Handle handle, uint32_t obAddrLo,\r
10371 uint32_t obAddrHi, uint8_t region);\r
10372 /*! Function to configure inbound translation registers */\r
10373 pcieRet_e (*cfgIbTrans) (Pcie_Handle handle, pcieIbTransCfg_t *ibCfg);\r
10374 /*! Function to configure a BAR register */\r
10375 pcieRet_e (*cfgBar) (Pcie_Handle handle, pcieBarCfg_t *barCfg);\r
10376 } Pcie_FxnTable;\r
10377 \r
10378 /**\r
10379 * @ingroup pcielld_api_structures\r
10380 * @brief Specification of Pcie_DeviceCfg\r
10381 *\r
10382 * The Pcie_DeviceCfg is used to specify device level configuration\r
10383 * to the LLD.\r
10384 */\r
10385 #define pcie_MAX_PERIPHS 4 /**< Maximum peripherals (base addresses) supported by LLD */\r
10386 typedef struct\r
10387 {\r
10388 Pcie_DeviceCfgBaseAddr *basesPtr[pcie_MAX_PERIPHS]; /**< base addreses */\r
10389 Pcie_FxnTable *fxnTablePtr[pcie_MAX_PERIPHS]; /**< function pointers */\r
10390 } Pcie_DeviceCfg;\r
10391 \r
10392 /**\r
10393 * @ingroup pcielld_api_structures\r
10394 * @brief Specification of Pcie_InitCfg\r
10395 *\r
10396 * The Pcie_InitCfg is used to specify per-core\r
10397 * configuration to the LLD. It is used with @ref Pcie_init ()\r
10398 * once per core.\r
10399 */\r
10400 typedef struct\r
10401 {\r
10402 Pcie_DeviceCfg dev; /**< Device Configuration */\r
10403 } Pcie_InitCfg;\r
10404 \r
10405 /**\r
10406 * @ingroup pcielld_api_functions\r
10407 * @brief Pcie_init sets device configuration\r
10408 *\r
10409 * @details This function binds a device configuration to\r
10410 * the LLD. This must be done before calling\r
10411 * the other APIs.\r
10412 *\r
10413 * Calling init is nondestrictive, ie it can be\r
10414 * done more than once without side effects (assuming\r
10415 * same argument is passed each time).\r
10416 *\r
10417 * @pre No assumptions\r
10418 *\r
10419 * @retval pcieRet_e status\r
10420 *\r
10421 * @post pcieLObj.device gets set to argument\r
10422 */\r
10423 pcieRet_e Pcie_init\r
10424 (\r
10425 const Pcie_InitCfg *cfg /**< [in] configuration */\r
10426 );\r
10427 \r
10428 /**\r
10429 * @ingroup pcielld_api_functions\r
10430 * @brief Pcie_open creates/opens a PCIe instance\r
10431 *\r
10432 * @details This function creates a handle. The peripheral itself\r
10433 * is not modified. More than one handle to the same\r
10434 * PCIe peripheral can exist at the same time.\r
10435 *\r
10436 * @pre pHandle != NULL\r
10437 * @pre *pHandle == NULL\r
10438 *\r
10439 * @retval pcieRet_e status\r
10440 *\r
10441 * @post *pHandle == valid handle\r
10442 */\r
10443 pcieRet_e Pcie_open\r
10444 (\r
10445 int deviceNum, /**< [in] PCIe device number (0,1,...) */\r
10446 Pcie_Handle *pHandle /**< [out] Resulting instance handle */\r
10447 );\r
10448 \r
10449 /**\r
10450 * @ingroup pcielld_api_functions\r
10451 * @brief Pcie_close Closes (frees) the driver handle.\r
10452 *\r
10453 * @details The handle is released. The peripheral itself is not\r
10454 * modified.\r
10455 *\r
10456 * @pre pHandle != NULL\r
10457 * @pre *pHandle == valid handle\r
10458 *\r
10459 * @retval pcieRet_e status\r
10460 *\r
10461 * @post *pHandle == NULL\r
10462 */\r
10463 pcieRet_e Pcie_close\r
10464 (\r
10465 Pcie_Handle *pHandle /**< [in] The PCIE LLD instance indentifier */\r
10466 );\r
10467 \r
10468 /**\r
10469 * @ingroup pcielld_api_functions\r
10470 * @brief Pcie_readRegs Performs a register read\r
10471 *\r
10472 * @details Reads one or more of the device registers\r
10473 *\r
10474 * Each non-NULL register pointer in readRegs will be read and\r
10475 * broken into its fields.\r
10476 *\r
10477 * Some registers have multiple instances (e.g. BAR registers, there is\r
10478 * BAR0, BAR1, etc). In these cases an "index" is used to select which\r
10479 * instance of the register will be accessed (e.g. use index 0 to access BAR0 and so on).\r
10480 *\r
10481 * Registers that need an "index" input\r
10482 * can only be read one index at a time. Also, "index" must be set\r
10483 * by the code before issuing a read request.\r
10484 *\r
10485 * It is the users responsibility to ensure that no other tasks\r
10486 * or cores will modify the registers while they are read,\r
10487 * or betwen the time the registers are read and they are\r
10488 * later written back.\r
10489 *\r
10490 *\r
10491 * Since the peripheral is shared across the device, and even\r
10492 * between peripherals, it is not expected to be dynamically\r
10493 * reprogramed (such as between thread or task switches). It\r
10494 * should only be reprogrammed at startup or when changing\r
10495 * applications. Therefore, there is a single-entry API instead\r
10496 * of a set of inlines since it is not time-critical code.\r
10497 *\r
10498 * @retval pcieRet_e status\r
10499 */\r
10500 pcieRet_e Pcie_readRegs\r
10501 (\r
10502 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
10503 pcieLocation_e location, /**< [in] Local or remote peripheral */\r
10504 pcieRegisters_t *readRegs /**< [in/out] List of registers to read */\r
10505 );\r
10506 \r
10507 /**\r
10508 * @ingroup pcielld_api_functions\r
10509 * @brief Pcie_writeRegs Performs a configuration write\r
10510 *\r
10511 * @details Writes one or more of the device registers.\r
10512 *\r
10513 * Each non-NULL register pointer in writeRegs will be writen.\r
10514 *\r
10515 * Some registers have multiple instances (e.g. BAR registers, there is\r
10516 * BAR0, BAR1, etc). In these cases an "index" is used to select which\r
10517 * instance of the register will be accessed (e.g. use index 0 to access BAR0 and so on).\r
10518 *\r
10519 * Registers that need an "index" input can only be written\r
10520 * one index at a time.\r
10521 *\r
10522 * It is the users responsibility to ensure that no other tasks\r
10523 * or cores will modify the registers while they are read,\r
10524 * or betwen the time the registers are read and they are\r
10525 * later written back.\r
10526 *\r
10527 * The user will typically use @ref Pcie_readRegs to read the current\r
10528 * values in the registers, modify them in the local copies, then\r
10529 * write back using @ref Pcie_writeRegs.\r
10530 *\r
10531 * On exit, the actual written values are returned in each register's\r
10532 * reg->raw.\r
10533 *\r
10534 * Since the peripheral is shared across the device, and even\r
10535 * between peripherals, it is not expected to be dynamically\r
10536 * reprogramed (such as between thread or task switches). It\r
10537 * should only be reprogrammed at startup or when changing\r
10538 * applications. Therefore, there is a single-entry API instead\r
10539 * of a set of inlines since it is not time-critical code.\r
10540 *\r
10541 * @retval pcieRet_e status\r
10542 */\r
10543 pcieRet_e Pcie_writeRegs\r
10544 (\r
10545 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
10546 pcieLocation_e location, /**< [in] Local or remote peripheral */\r
10547 pcieRegisters_t *writeRegs /**< [in] List of registers to write */\r
10548 );\r
10549 \r
10550 /**\r
10551 * @ingroup pcielld_api_functions\r
10552 * @brief Pcie_setInterfaceMode sets the PCI mode for specified interface\r
10553 *\r
10554 * Note: if the PCIESSMODE field is in a register protected by a kicker\r
10555 * mechanism, unlock it before calling this function. It is not\r
10556 * multicore safe to repeatedly unlock/lock the kicker.\r
10557 *\r
10558 * @retval pcieRet_e status\r
10559 */\r
10560 pcieRet_e Pcie_setInterfaceMode\r
10561 (\r
10562 Pcie_Handle handle, /**< [in] specified interface */\r
10563 pcieMode_e mode /**< [in] PCIE Mode */\r
10564 );\r
10565 \r
10566 /**\r
10567 * @ingroup pcielld_api_functions\r
10568 * @brief Pcie_getMemSpaceRange Returns the PCIe Internal Address\r
10569 * Range for the device's internal address range 1, which is\r
10570 * the Memory Space.\r
10571 *\r
10572 * @retval pcieRet_e status\r
10573 */\r
10574 pcieRet_e Pcie_getMemSpaceRange\r
10575 (\r
10576 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
10577 void **base, /**< [out] The memory space base address */\r
10578 uint32_t *size /**< [out] Total size of the memory space [bytes] */\r
10579 );\r
10580 \r
10581 \r
10582 /**\r
10583 * @ingroup pcielld_api_functions\r
10584 * @brief Pcie_cfgObOffset Configures the Outbound Offset registers\r
10585 * for outbound address translation\r
10586 *\r
10587 * @retval pcieRet_e status\r
10588 */\r
10589 pcieRet_e Pcie_cfgObOffset\r
10590 (\r
10591 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
10592 uint32_t obAddrLo, /**< [in] Low Outbound address offset (32bits) */\r
10593 uint32_t obAddrHi, /**< [in] High Outbound address offset (32bits) */\r
10594 uint8_t region /**< [in] Identifies the Outbound region (0-7) */\r
10595 );\r
10596 \r
10597 /**\r
10598 * @ingroup pcielld_api_functions\r
10599 * @brief Pcie_cfgIbTrans Configures the Inbound Address Translation registers.\r
10600 *\r
10601 * @retval pcieRet_e status\r
10602 */\r
10603 pcieRet_e Pcie_cfgIbTrans\r
10604 (\r
10605 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
10606 pcieIbTransCfg_t *ibCfg /**< [in] Inbound Address Translation Configuration parameters */\r
10607 );\r
10608 \r
10609 /**\r
10610 * @ingroup pcielld_api_functions\r
10611 * @brief Pcie_cfgBar is used to configure a 32bits BAR Register\r
10612 *\r
10613 * A BAR register can represent any of the following:\n\r
10614 * (a) a 32bit BAR\n\r
10615 * (b) the lower 32bits of a 64bits BAR\n\r
10616 * (c) the upper 32bits of a 64bits BAR\n\r
10617 * (d) a BAR mask\n\r
10618 *\r
10619 * BAR registers can always be accessed using @ref Pcie_readRegs\r
10620 * and/or @ref Pcie_writeRegs.\r
10621 *\r
10622 * @ref Pcie_cfgBar is used to configure a 32bits BAR Register or the lower\r
10623 * 32bits of a 64bits BAR register. That is, (a) and (b) above.\r
10624 *\r
10625 * @ref Pcie_cfgBar should NOT be used to configure the Upper 32bits of a 64bits BAR register (c).\n\r
10626 * @ref Pcie_cfgBar should NOT be used to configure BAR masks (d). \n\n\r
10627 * In order to access BAR masks or Upper 32bits BAR, use @ref Pcie_readRegs and/or\r
10628 * @ref Pcie_writeRegs to perform the actual 32bits register accesses, using\r
10629 * @ref pcieType0Bar32bitIdx_t (for a End point BAR) or @ref pcieType1Bar32bitIdx_t (for a Root Complex BAR).\r
10630 *\r
10631 *\r
10632 * @retval pcieRet_e status\r
10633 */\r
10634 pcieRet_e Pcie_cfgBar\r
10635 (\r
10636 Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
10637 pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */\r
10638 );\r
10639 \r
10640 \r
10641 /**\r
10642 * @ingroup pcielld_api_functions\r
10643 * @brief Pcie_getVersion returns the PCIE LLD version information\r
10644 *\r
10645 * @details This function is used to get the version information of the PCIE LLD in 0xAABBCCDD format.\r
10646 * where Arch (AA); API Changes (BB); Major (CC); Minor (DD)\r
10647 *\r
10648 * @retval 32-bit version information\r
10649 */\r
10650 uint32_t Pcie_getVersion (void);\r
10651 \r
10652 \r
10653 /**\r
10654 * @ingroup pcielld_api_functions\r
10655 * @brief Pcie_getVersionStr returns the PCIE LLD version string\r
10656 *\r
10657 * @details This function is used to get the version string of the PCIE LLD.\r
10658 *\r
10659 * @retval Version string\r
10660 */\r
10661 const char* Pcie_getVersionStr (void);\r
10662 \r
10663 #ifdef __cplusplus\r
10664 }\r
10665 #endif\r
10666 \r
10667 #endif /* _PCIE_H */\r
10668 \r
10669 /* Nothing past this point */\r
10670 \r