index 4d8888ad5602a66d85a4a1489965c5d980434941..0cb2cd808be6b93a74cf03a65bcd2e7d9f8cbe33 100644 (file)
--- a/pcie.h
+++ b/pcie.h
/*\r
*\r
- * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/\r
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/\r
*\r
*\r
* Redistribution and use in source and binary forms, with or without\r
pcie_RET_INV_DEVICENUM, /**< @ref Pcie_open deviceNum invalid */\r
pcie_RET_INV_INITCFG, /**< Invalid Pcie_InitCfg */\r
pcie_RET_INV_FXNPTR, /**< Top level API doesn't have dev specific fxn */\r
- pcie_RET_NO_INIT /**< Forgot to call Pcie_init() ? */\r
+ pcie_RET_NO_INIT, /**< Forgot to call Pcie_init() ? */\r
+ pcie_RET_UNSUPPORTED, /**< Unsupported API */\r
+ pcie_RET_RANGECHK /**< Rangecheck failed */\r
} pcieRet_e;\r
/* @} */\r
\r
* This Register contains the major and minor revisions\r
* for the PCIe module.\r
*\r
- * This register is only used on rev 0 hw, but is very similar to rev 1's\r
+ * This register is only used on rev 0/2 hw, but is very similar to rev 1's\r
* @ref pcieTiConfRevisionReg_t\r
*\r
* On rev 0 hw, this corresponds to PID\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PID\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to SCHEME\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to FUNC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 12 bits\r
*/\r
uint16_t func;\r
+ /**\r
+ * @brief [ro] Module ID of the Peripheral\r
+ *\r
+ * 0x6810 is PCIe\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MODID\r
+ *\r
+ * Field size: 16 bits\r
+ */\r
+ uint16_t modId;\r
/**\r
* @brief [ro] RTL Version\r
*\r
* On rev 0 hw, this corresponds to RTL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RTL\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MAJOR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MAJOR\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CUSTOM\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CUSTOM\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MINOR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MINOR\r
*\r
* Field size: 6 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMD_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMD_STATUS\r
*\r
* @{\r
*/\r
typedef struct pcieCmdStatusReg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Set to enable manual reversal for RX lanes.\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_LANE_FLIP_EN\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t rxLaneFlipEn;\r
+ /**\r
+ * @brief [rw] Set to enable manual reversal for TX lanes.\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to TX_LANE_FLIP_EN\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t txLaneFlipEn;\r
/**\r
* @brief [rw] Set to enable writing to BAR mask registers that are overlaid on BAR registers.\r
*\r
* On rev 0 hw, this corresponds to DBI_CS2\r
* On rev 1 hw, unsupported (but see @ref pciePlconfDbiRoWrEnReg_t::cxDbiRoWrEn)\r
+ * On rev 2 hw, this corresponds to DBI_CS2\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to APP_RETRY_EN\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfDeviceCmdReg_t::appReqRetryEn)\r
+ * On rev 2 hw, this corresponds to APP_RETRY_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to POSTED_WR_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to IB_XLT_EN\r
* On rev 1 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_XLT_EN\r
* On rev 1 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LTSSM_EN\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfDeviceCmdReg_t::ltssmEn)\r
+ * On rev 2 hw, this corresponds to LTSSM_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_SETUP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_TYPE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_BUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_DEVICE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 5 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_FUNC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to IOBASE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to IOBASE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 20 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to TLPCFG\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to RELAXED\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NO_SNOOP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RSTCMD\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RSTCMD\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to FLUSH_N\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t flush;\r
+ /**\r
+ * @brief [ro] Bridge flush status\r
+ *\r
+ * Used to ensure no pending transactions prior to issuing warm reset.\r
+ * 0 = No transaction is pending.\r
+ * 1 = There are transactions pending.\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FLR_PF_ACTIVE\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t flrPfActive;\r
/**\r
* @brief [w1] Write 1 to initiate a downstream hot reset sequence on downstream.\r
*\r
* On rev 0 hw, this corresponds to INIT_RST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INIT_RST\r
*\r
* Field size: 1 bit\r
*/\r
} pcieRstCmdReg_t;\r
/* @} */\r
\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the PTM Config register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTMCFG\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmCfgReg_s {\r
+ uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Select ptm_local_clk bit input to CPTS.\r
+ *\r
+ * 0 will select ptm_local_clk[0], \r
+ * 1 will select ptm_local_clk[1] ...\r
+ * 63 will select ptm_local_clk[63]\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_CLK_SEL\r
+ *\r
+ * Field size: 6 bit\r
+ */\r
+ uint8_t ptmClkSel;\r
+ /**\r
+ * @brief [ro] '1' indicates PTM context is valid-EP only\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_CONTEXT_VALID\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmContextValid;\r
+ /**\r
+ * @brief [w1] Write '1' to enable PTM transaction.EP only.\r
+ *\r
+ * EP will initiate one PTM transaction when this field is updated.\r
+ * Always reads '0'\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_MANUAL_UPDATE\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmManualUpdate;\r
+ /**\r
+ * @brief [rw] Write '1' to enable PTM auto-update-EP only\r
+ *\r
+ * EP will automatically initiate PTM transaction every 10ms\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_AUTO_UPDATE\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmAutoUpdate;\r
+} pciePtmCfgReg_t;\r
+/* @} */\r
+\r
/**\r
* @ingroup pcielld_reg_app_structures\r
* @brief Specification of the Power Management Command Register\r
*\r
* On rev 0 hw, this corresponds to PMCMD\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMCMD\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_XMT_TURNOFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_XMT_TURNOFF\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_XMT_PME\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_XMT_PME\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PMCFG\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to ENTR_L23\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ACT_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_NOT_EMPTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to IB_NOT_EMPTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_SIZE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_SIZE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to DIAG_CTRL\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t)\r
+ * On rev 2 hw\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INV_ECRC\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t::invEcrc)\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to INV_LCRC\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t::invLcrc)\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ENDIAN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to ENDIAN_MODE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRIORITY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MST_PRIV\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MST_PRIVID\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MST_PRIORITY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to IRQ_EOI\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfIrqEoiReg_t)\r
+ * On rev 2 hw, this corresponds to IRQ_EOI\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to EOI\r
* On rev 1 hw, unsupported (but see @ref pcieTiConfIrqEoiReg_t::lineNumber)\r
+ * On rev 2 hw, this corresponds to EOI\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI_IRQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR_IRQ\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI_IRQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR_IRQ\r
*\r
- * Field size: 32 bits\r
+ * Field size: 32 bits (rev 0) or 31 bits (rev 2)\r
*/\r
uint32_t msiIrq;\r
} pcieMsiIrqReg_t;\r
*\r
* On rev 0 hw, this corresponds to EP_IRQ_SET\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_SET\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to EP_IRQ_SET\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_SET_0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to EP_IRQ_CLR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_CLR\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to EP_IRQ_CLR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_CLR_0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to EP_IRQ_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_STATUS\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to EP_IRQ_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_STATUS_0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to GPR# where # = 0..3\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to GPR# where # = 0..3\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to GENERIC# where # = 0..3\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to GENERIC# where # = 0..3\r
*\r
* Field size: 32 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_STATUS_RAW where # = 0..7\r
* On rev 1 hw, unsupported (but similar to @ref pciePlconfMsiCtrlIntStatusReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS_RAW where # = 0..7\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_STATUS_RAW where # = 0..7\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS_RAW where # = 0..7\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_STATUS where # = 0..7\r
* On rev 1 hw, unsupported (but similar to @ref pciePlconfMsiCtrlIntStatusReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS where # = 0..7\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_STATUS where # = 0..7\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS where # = 0..7\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_SET where # = 0..7\r
* On rev 1 hw, unsupported (but similar to @ref pcieTiConfIrqEnableSetMsiReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_SET where # = 0..7\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_SET where # = 0..7\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_SET where # = 0..7\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_CLR where # = 0..7\r
* On rev 1 hw, unsupported (but similar to @ref pcieTiConfIrqEnableClrMsiReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_CLR where # = 0..7\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_CLR where # = 0..7\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_CLR where # = 0..7\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to LEGACY_#_IRQ_STATUS_RAW where # = A..D (0-3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_STATUS_RAW where # = A..D (0-3)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_# where # = A..D\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INT_# where # = A..D\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LEGACY_#_IRQ_STATUS where # = A..D (0-3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_STATUS where # = A..D (0-3)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_# where # = A..D\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INT_# where # = A..D\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LEGACY_#_IRQ_ENABLE_SET where # = A..D (0-3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_ENABLE_SET where # = A..D (0-3)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_# where # = A..D\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INT_# where # = A..D\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LEGACY_#_IRQ_ENABLE_CLR where # = A..D (0-3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_ENABLE_CLR where # = A..D (0-3)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_# where # = A..D\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INT_# where # = A..D\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_IRQ_STATUS_RAW\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_STATUS_RAW\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AER\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_AER_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AXI\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_CORR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_CORR_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_NONFATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_NONFATAL_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_FATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_FATAL_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_SYS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_SYS_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_IRQ_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_STATUS\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AER\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_AER\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AXI\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_CORR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_CORR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_NONFATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_NONFATAL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_FATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_FATAL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_SYS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_SYS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_IRQ_ENABLE_SET\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_ENABLE_SET\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AER\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_AER\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AXI\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_CORR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_CORR_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_NONFATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_NONFATAL_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_FATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_FATAL_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_SYS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_SYS_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_IRQ_ENABLE_CLR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_ENABLE_CLR\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AER\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_AER_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_AXI\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_CORR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_CORR_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_NONFATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_NONFATAL_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_FATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_FATAL_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_SYS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_SYS_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PMRST_IRQ_STATUS_RAW\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_STATUS_RAW\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to LNK_RST_REQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LNK_RST_REQ_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_PME\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_PME_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TO_ACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TO_ACK_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TURNOFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TURNOFF_RAW\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PMRST_IRQ_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_STATUS\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to LNK_RST_REQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LNK_RST_REQ\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_PME\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_PME\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TO_ACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TO_ACK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TURNOFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TURNOFF\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PMRST_ENABLE_SET\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_ENABLE_SET\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to LNK_RST_REQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LNK_RST_REQ_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_PME\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_PME_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TO_ACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TO_ACK_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TURNOFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TURNOFF_EN_SET\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PMRST_ENABLE_CLR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_ENABLE_CLR\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to LNK_RST_REQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LNK_RST_REQ_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_PME\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_PME_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TO_ACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TO_ACK_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_TURNOFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PM_TURNOFF_EN_CLR\r
*\r
* Field size: 1 bit\r
*/\r
} pciePmRstIrqEnableClrReg_t;\r
/* @} */\r
\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Raw Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS_RAW\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqStatusRawReg_s {\r
+ uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Link Request Reset interrupt raw status\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_CLK_UPDATED_RAW\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmClkUpdated;\r
+} pciePtmIrqStatusRawReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqStatusReg_s {\r
+ uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Link Request Reset interrupt raw status\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_CLK_UPDATED\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmClkUpdated;\r
+} pciePtmIrqStatusReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Raw Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS_ENABLE_SET\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqEnableSetReg_s {\r
+ uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Link Request Reset interrupt raw status\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_CLK_UPDATED_EN_SET\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmClkUpdated;\r
+} pciePtmIrqEnableSetReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Raw Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS_ENABLE_CLR\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqEnableClrReg_s {\r
+ uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Link Request Reset interrupt raw status\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_CLK_UPDATED_EN_CLR\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ptmClkUpdated;\r
+} pciePtmIrqEnableClrReg_t;\r
+/* @} */\r
+\r
/**\r
* @ingroup pcielld_reg_app_structures\r
* @brief Specification of the Outbound Translation Region Offset Low and Index Register\r
* On rev 0 hw, this corresponds to OB_OFFSET_INDEXn where n = 0..7\r
* On rev 1 hw, unsupported (but similar to iATU\r
* starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ * starting at @ref pciePlconfIatuIndexReg_t)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_OFFSETn_LO (n = 0..7)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 12 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_ENABLEn (n = 0..7)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
* On rev 0 hw, this corresponds to OB_OFFSETn_HI where n = 0..7\r
* On rev 1 hw, unsupported (but similar to iATU\r
* starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ * starting at @ref pciePlconfIatuIndexReg_t)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to OB_OFFSETn_HI (n = 0..7)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 32 bits\r
*/\r
* On rev 0 hw, this corresponds to IB_BARn where n = 0..3\r
* On rev 1 hw, unsupported (but similar to iATU\r
* starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ * starting at @ref pciePlconfIatuIndexReg_t)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to IB_BARn (n = 0..3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
* On rev 0 hw, this corresponds to IB_STARTn_LO where n = 0..3\r
* On rev 1 hw, unsupported (but similar to iATU\r
* starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ * starting at @ref pciePlconfIatuIndexReg_t)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to IB_STARTn_LO (n = 0..3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 24 bits\r
*/\r
* On rev 0 hw, this corresponds to IB_STARTn_LO where n = 0..3\r
* On rev 1 hw, unsupported (but similar to iATU\r
* starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ * starting at @ref pciePlconfIatuIndexReg_t)\r
* @{\r
*/\r
typedef struct pcieIbStartHiReg_s {\r
*\r
* On rev 0 hw, this corresponds to IB_STARTn_HI (n = 0..3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 32 bits\r
*/\r
* On rev 0 hw, this corresponds to IB_OFFSETn where n = 0..3\r
* On rev 1 hw, unsupported (but similar to iATU\r
* starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ * starting at @ref pciePlconfIatuIndexReg_t)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to IB_OFFSETn (n = 0..3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 24 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_CFG0\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_SYNC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_HOLDOFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_RC_DELAY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_DET_DELAY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_SHRT_TM\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_STAT186\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_FIX_TERM\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_FIX_STD\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_L2_ENIDL_OFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_L0S_RX_OFF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_RXTX_ON\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_RXTX_RST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_CFG1\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_ERR_BIT\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 10 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_ERR_LN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_ERR_MODE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_STATUS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_REV\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_LN_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_TX_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCS_RX_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERDES_CFG0\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_LOOPBACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_MSYNC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_CM\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_INVPAIR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_LOOPBACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_ENOC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_EQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_CDR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_LOS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_ALIGN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_INVPAIR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERDES_CFG1\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_LOOPBACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_MSYNC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_CM\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_INVPAIR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_LOOPBACK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_ENOC\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_EQ\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_CDR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_LOS\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_ALIGN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_INVPAIR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to VENDOR_DEVICE_ID\r
* On rev 1 hw, this corresponds to DEVICE_VENDORID\r
+ * On rev 2 hw, this corresponds to DEVICE_ID_VENDOR_ID_REG and TYPE1_DEV_ID_VEND_ID_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to DEVICE_ID\r
* On rev 1 hw, this corresponds to DEVICEID\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_DEVICE_ID or DEVICE_ID_VENDOR_ID_REG\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to VENDOR_ID\r
* On rev 1 hw, this corresponds to VENDORID\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_VENDOR_ID and VENDOR_ID\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to STATUS_COMMAND\r
* On rev 1 hw, this corresponds to STATUS_COMMAND_REGISTER\r
+ * On rev 2 hw, this corresponds to STATUS_COMMAND_REG and TYPE1_STATUS_COMMAND_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PARITY_ERROR\r
* On rev 1 hw, this corresponds to DETECT_PARERR\r
+ * On rev 2 hw, this corresponds to DETECTED_PARITY_ERR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SIG_SYS_ERROR\r
* On rev 1 hw, this corresponds to SIGNAL_SYSERR\r
+ * On rev 2 hw, this corresponds to SIGNALED_SYS_ERR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_MST_ABORT\r
* On rev 1 hw, this corresponds to RCVD_MASTERABORT\r
+ * On rev 2 hw, this corresponds to RCVD_MASTER_ABORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_TGT_ABORT\r
* On rev 1 hw, this corresponds to RCVD_TRGTABORT\r
+ * On rev 2 hw, this corresponds to RCVD_TARGET_ABORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SIG_TGT_ABORT\r
* On rev 1 hw, this corresponds to SIGNAL_TRGTABORT\r
+ * On rev 2 hw, this corresponds to SIGNALED_TARGET_ABORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to DEVSEL_TIME\r
+ * On rev 2 hw, this corresponds to DEV_SEL_TIMING\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to DAT_PAR_ERRROR\r
* On rev 1 hw, this corresponds to MASTERDATA_PARERR\r
+ * On rev 2 hw, this corresponds to MASTER_DPE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to FAST_B2B\r
+ * On rev 2 hw, this corresponds to FAST_B2B_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to C66MHZ_CAP\r
+ * On rev 2 hw, this corresponds to FAST_66MHZ_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_LIST\r
* On rev 1 hw, this corresponds to CAP_LIST\r
+ * On rev 2 hw, this corresponds to CAP_LIST\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_STAT\r
* On rev 1 hw, this corresponds to INTX_STATUS\r
+ * On rev 2 hw, this corresponds to INT_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to INTX_DIS\r
* On rev 1 hw, this corresponds to INTX_ASSER_DIS\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_INT_EN and INT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERR_EN\r
* On rev 1 hw, this corresponds to SERR_EN\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_SERREN and SERREN\r
*\r
* Field size: 1 bit\r
*/\r
/**\r
* @brief [ro] Bit hardwired to 0 for PCIExpress\r
*\r
- * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
+ * Hardwired to 0 for PCIExpress. Only defined on rev 1/2 hw version.\r
*\r
* Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to IDSEL_CTRL\r
+ * On rev 2 hw, this corresponds to PCI_TYPE_IDSEL_STEPPING and IDSEL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PAR_ERR_RESP\r
* On rev 1 hw, this corresponds to PARITYERRRESP\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_PARITY_ERR_EN and PERREN\r
*\r
* Field size: 1 bit\r
*/\r
/**\r
* @brief [ro] Bit hardwired to 0 for PCIExpress\r
*\r
- * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
+ * Hardwired to 0 for PCIExpress. Only defined on rev 1/2 hw version.\r
*\r
* Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to VGA_SNOOP\r
+ * On rev 2 hw, this corresponds to PCI_TYPE_VGA_PALETTE_SNOOP and VGAPS\r
*\r
* Field size: 1 bit\r
*/\r
/**\r
* @brief [ro] Bit hardwired to 0 for PCIExpress\r
*\r
- * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
+ * Hardwired to 0 for PCIExpress. Only defined on rev 1/2 hw version.\r
*\r
* Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to MEMWR_INVA\r
+ * On rev 2 hw, this corresponds to PCI_TYPE_MWI_ENABLE / MWI_EN\r
*\r
* Field size: 1 bit\r
*/\r
/**\r
* @brief [ro] Bit hardwired to 0 for PCIExpress\r
*\r
- * Hardwired to 0 for PCIExpress. Only defined on rev 1 hw version.\r
+ * Hardwired to 0 for PCIExpress. Only defined on rev 1/2 hw version.\r
*\r
* Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to SPEC_CYCLE_EN\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_SPECIAL_CYCLE_OPERATION and SCO\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BUS_MS\r
* On rev 1 hw, this corresponds to BUSMASTER_EN\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_BUS_MASTER_EN and BME\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MEM_SP\r
* On rev 1 hw, this corresponds to MEM_SPACE_EN\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_MEM_SPACE_EN and MSE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to IO_SP\r
* On rev 1 hw, this corresponds to IO_SPACE_EN\r
+ * On rev 2 hw, this corresponds to PCI_TYPE0_IO_EN / IO_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CLASSCODE_REVID\r
* On rev 1 hw, this corresponds to CLASSCODE_REVISIONID\r
+ * On rev 2 hw, this corresponds to CLASS_CODE_REVISION_ID\r
*\r
* @{\r
*/\r
* @brief [ro] Class Code\r
*\r
* On rev 0 hw, the register presents this as 24 bits.\r
- * On rev 1 hw, the register presetns as 3 8bit fields, but they will all be\r
+ * On rev 1/2 hw, the register presents as 3 8bit fields, but they will all be\r
* packed/unpacked from classCode for backward/forward compatibility.\r
*\r
* On rev 0 hw, this corresponds to CLASSCODE\r
* On rev 1 hw, this corresponds to BASE_CLS_CD, SUBCLS_CD and PROG_IF_CODE\r
+ * On rev 2 hw, this corresponds to BASE_CLASS_CODE, SUBCLASS_CODE and PROGRAM_INTERFACE\r
*\r
* Field size: 24 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to REVID\r
* On rev 1 hw, this corresponds to REVID\r
+ * On rev 2 hw, this corresponds to REVID\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to BARn\r
* On rev 1 hw, this corresponds to BARn\r
+ * On rev 2 hw, this corresponds to BAR_REGn\r
*\r
* @{\r
*/\r
* Rev 0 hw: 28 bits are modifiable\r
* Rev 1 hw: only upper 12 bits are modifyable (eg 16-27). Rest are read-only. If users tries\r
* to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
+ * Rev 2 hw: 28 bits are modifiable\r
*\r
* Field size: 28 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to BIST_HEADER\r
* On rev 1 hw, this corresponds to BIST_HEAD_LAT_CACH\r
+ * On rev 2 hw, this corresponds to BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to BIST_CAP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to START_BIST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to COMP_CODE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to BIST\r
+ * On rev 2 hw, this corresponds to BIST\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MULFUN_DEV\r
* On rev 1 hw, this corresponds to MFD\r
+ * On rev 2 hw, this corresponds to MULTI_FUNC\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to HDR_TYPE\r
* On rev 1 hw, this corresponds to HEAD_TYP\r
+ * On rev 1 hw, this corresponds to HEADER_TYPE\r
*\r
* Field size: 7 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to LAT_TMR\r
* On rev 1 hw, this corresponds to MSTR_LAT_TIM\r
+ * On rev 2 hw, this corresponds to LATENCY_MASTER_TIMER\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CACHELN_SIZ\r
* On rev 1 hw, this corresponds to CACH_LN_SZE\r
+ * On rev 2 hw, this corresponds to CACHE_LINE_SIZE\r
*\r
* Field size: 8 bits\r
*/\r
\r
/**\r
* @ingroup pcielld_reg_cfg_type0_structures\r
- * @brief Specification of the Subsystem Vendor ID Register\r
+ * @brief Specification of the Cardbus CIS pointer register\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to CARDBUS_CIS_POINTER\r
+ * On rev 2 hw, this corresponds to CARDBUS_CIS_PTR_REG\r
*\r
* @{\r
*/\r
/**\r
* @brief [rw] Cardbus CIS pointer (CS)\r
*\r
- * This register is only used in rev 1 hw. It is physically present but marked reserved\r
+ * This register is only used in rev 1/2 hw. It is physically present but marked reserved\r
* in rev 0 hardware, so this structure/API isn't used.\r
*\r
* Field size: 32 bits\r
*\r
* On rev 0 hw, this corresponds to SUBSYS_VNDR_ID\r
* On rev 1 hw, this corresponds to SUBID_SUBVENDORID\r
+ * On rev 2 hw, this corresponds to SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to SUBSYS_ID\r
* On rev 1 hw, this corresponds to SUBSYS_DEV_ID_N\r
+ * On rev 2 hw, this corresponds to SUBSYS_DEV_ID\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SUBSYS_VEN_ID\r
* On rev 1 hw, this corresponds to SUBSYS_VENDOR_ID_N\r
+ * On rev 2 hw, this corresponds to SUBSYS_VENDOR_ID\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXPNSN_ROM\r
* On rev 1 hw, this corresponds to EXPANSION_ROM_BAR\r
+ * On rev 2 hw, this corresponds to EXP_ROM_BASE_ADDR_REG\r
*\r
* @{\r
*/\r
* Rev 1 hw: only upper 16 bits are modifyable (eg 16-31). Lower 5 bits are\r
* r/o. Attempt to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
*\r
+ * Rev 2 hw: entire 21 bits are r/w\r
+ *\r
* On rev 0 hw, this corresponds to EXP_ROM_BASE_ADDR and EXROM_ADDRESS_RO\r
* On rev 1 hw, this corresponds to EXROM_ADDRESS\r
+ * On rev 2 hw, this corresponds to EXP_ROM_BASE_ADDRES\r
*\r
* Field size: 21 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXP_ROM_EN\r
* On rev 1 hw, this corresponds to EXROM_EN\r
+ * On rev 2 hw, this corresponds to ROM_BAR_ENABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_PTR\r
* On rev 1 hw, this corresponds to CAPPTR\r
+ * On rev 2 hw, this corresponds to PCI_CAP_PTR_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_PTR\r
* On rev 1 hw, this corresponds to CAPPTR\r
+ * On rev 2 hw, this corresponds to CAP_POINTER\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_PIN\r
* On rev 1 hw, this corresponds to INTERRUPT\r
+ * On rev 2 hw, this corresponds to MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_PIN\r
* On rev 1 hw, this corresponds to INT_PIN\r
+ * On rev 2 hw, this corresponds to INT_PIN\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_LINE\r
* On rev 1 hw, this corresponds to INT_LIN\r
+ * On rev 2 hw, this corresponds to INT_LIN\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* This structure is used to access a Root Complex BAR. For more details, please refer to @ref pcieBarReg_t.\r
*\r
+ * On rev 2 hw, not supported (use IATU instead)\r
+ *\r
* @{\r
*/\r
typedef struct pcieType1BarIdx_s {\r
*\r
* This structure is used to access a Root Complex BAR. For more details, please refer to @ref pcieBar32bitReg_t.\r
*\r
+ * On rev 2 hw, not supported (use IATU instead)\r
+ *\r
* @{\r
*/\r
typedef struct pcieType1Bar32bitIdx_s {\r
*\r
* On rev 0 hw, this corresponds to BIST_HEADER\r
* On rev 1 hw, this corresponds to BIST_HEAD_LAT_CACH\r
+ * On rev 2 hw, this corresponds to TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to BIST_CAP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to START_BIST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to COMP_CODE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to BIST\r
+ * On rev 2 hw, this corresponds to BIST\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MULFUN_DEV\r
* On rev 1 hw, this corresponds to MFD\r
+ * On rev 2 hw, this corresponds to MULTI_FUNC\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to HDR_TYPE\r
* On rev 1 hw, this corresponds to HEAD_TYP\r
+ * On rev 2 hw, this corresponds to HEADER_TYPE\r
*\r
* Field size: 7 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to LAT_TMR\r
* On rev 1 hw, this corresponds to MSTR_LAT_TIM\r
+ * On rev 2 hw, this corresponds to LATENCY_MASTER_TIMER\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CACHELN_SIZE\r
* On rev 1 hw, this corresponds to CACH_LN_SIZE\r
+ * On rev 2 hw, this corresponds to CACHE_LINE_SIZE\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to BUSNUM\r
* On rev 1 hw, this corresponds to BUS_NUM_REG\r
+ * On rev 2 hw, this corresponds to SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to SEC_LAT_TMR\r
* On rev 1 hw, this corresponds to SEC_LAT_TIMER\r
+ * On rev 2 hw, this corresponds to SEC_LAT_TIMER\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SUB_BUS_NUM\r
* On rev 1 hw, this corresponds to SUBORD_BUS_NUM\r
+ * On rev 2 hw, this corresponds to SUB_BUS\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SEC_BUS_NUM\r
* On rev 1 hw, this corresponds to SEC_BUS_NUM\r
+ * On rev 2 hw, this corresponds to SEC_BUS\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRI_BUS_NUM\r
* On rev 1 hw, this corresponds to PRIM_BUS_NUM\r
+ * On rev 2 hw, this corresponds to PRIM_BUS\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SECSTAT\r
* On rev 1 hw, this corresponds to IOBASE_LIMIT_SEC_STATUS\r
+ * On rev 2 hw, this corresponds to SEC_STAT_IO_LIMIT_IO_BASE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to DTCT_PERROR\r
* On rev 1 hw, this corresponds to DET_PAR_ERR\r
+ * On rev 2 hw, this corresponds to SEC_STAT_DPE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_SYS_ERROR\r
* On rev 1 hw, this corresponds to RCVD_SYS_ERR\r
+ * On rev 2 hw, this corresponds to SEC_STAT_RCVD_SYS_ERR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_MST_ABORT\r
* On rev 1 hw, this corresponds to RCVD_MSTR_ABORT\r
+ * On rev 2 hw, this corresponds to SEC_STAT_RCVD_MSTR_ABRT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RX_TGT_ABORT\r
* On rev 1 hw, this corresponds to RCVD_TRGT_ABORT\r
+ * On rev 2 hw, this corresponds to SEC_STAT_RCVD_TRGT_ABRT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_TGT_ABORT\r
* On rev 1 hw, this corresponds to SGNLD_TRGT_ABORT\r
+ * On rev 2 hw, this corresponds to SEC_STAT_SIG_TRGT_ABRT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to DEVSEL_TIMING\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MST_DPERR\r
* On rev 1 hw, this corresponds to MSTR_DATA_PRTY_ERR\r
+ * On rev 2 hw, this corresponds to SEC_STAT_MDPE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to FAST_B2B_CAP\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to C66MHZ_CAPA\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to IO_LIMIT\r
* On rev 1 hw, this corresponds to IO_SPACE_LIMIT\r
+ * On rev 2 hw, this corresponds to IO_LIMIT\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to IO_LIMIT_ADDR\r
* On rev 1 hw, this corresponds to IODECODE_32\r
+ * On rev 2 hw, this corresponds to IO_DECODE_BITS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to IO_BASE\r
* On rev 1 hw, this corresponds to IO_SPACE_BASE\r
+ * On rev 2 hw, this corresponds to IO_BASE\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to IO_BASE_ADDR\r
* On rev 1 hw, this corresponds to IODECODE_32_0\r
+ * On rev 2 hw, this corresponds to IO_DECODE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MEMSPACE\r
* On rev 1 hw, this corresponds to MEM_BASE_LIMIT\r
+ * On rev 2 hw, this corresponds to MEM_LIMIT_MEM_BASE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MEM_LIMIT\r
* On rev 1 hw, this corresponds to MEM_LIMIT_ADDR\r
+ * On rev 2 hw, this corresponds to MEM_LIMIT\r
*\r
* Field size: 12 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MEM_BASE\r
* On rev 1 hw, this corresponds to MEM_BASE_ADDR\r
+ * On rev 2 hw, this corresponds to MEM_BASE\r
*\r
* Field size: 12 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_MEM\r
* On rev 1 hw, this corresponds to PREF_MEM_BASE_LIMIT\r
+ * On rev 2 hw, this corresponds to PREF_MEM_LIMIT_PREF_MEM_BASE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
* On rev 1 hw, this corresponds to PREF_MEM_ADDR\r
+ * On rev 2 hw, this corresponds to PREF_MEM_LIMIT\r
*\r
* Field size: 12 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRE_LIMIT_ADDR\r
* On rev 1 hw, this corresponds to MEMDECODE_64\r
+ * On rev 2 hw, this corresponds to MEM_LIMIT_DECODE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_BASE\r
* On rev 1 hw, this corresponds to UPPPREF_MEM_ADDR\r
+ * On rev 2 hw, this corresponds to PREF_MEM_BASE\r
*\r
* Field size: 12 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRE_BASE_ADDR\r
* On rev 1 hw, this corresponds to MEMDECODE_64_0\r
+ * On rev 2 hw, this corresponds to PREF_MEM_DECODE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_BASE\r
* On rev 1 hw, this corresponds to UPPER_32BIT_PREF_BASEADDR\r
+ * On rev 2 hw, this corresponds to PREF_BASE_UPPER_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_BASE\r
* On rev 1 hw, this corresponds to ADDRUPP\r
+ * On rev 2 hw, this corresponds to PREF_MEM_BASE_UPPER\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
* On rev 1 hw, this corresponds to UPPER_32BIT_PREF_LIMITADDR\r
+ * On rev 2 hw, this corresponds to PREF_LIMIT_UPPER_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
* On rev 1 hw, this corresponds to ADDRUPP_LIMIT\r
+ * On rev 2 hw, this corresponds to PREF_MEM_LIMIT_UPPER\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to IOSPACE\r
* On rev 1 hw, this corresponds to IO_BASE_LIMIT\r
+ * On rev 2 hw, this corresponds to IO_LIMIT_UPPER_IO_BASE_UPPER_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to IOBASE\r
* On rev 1 hw, this corresponds to UPP16_IOBASE\r
+ * On rev 2 hw, this corresponds to IO_BASE_UPPER\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to IOLIMIT\r
* On rev 1 hw, this corresponds to UPP16_IOLIMIT\r
+ * On rev 2 hw, this corresponds to IO_LIMIT_UPPER\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_PTR\r
* On rev 1 hw, this corresponds to CAPPTR\r
+ * On rev 2 hw, this corresponds to TYPE1_CAP_PTR_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_PTR\r
* On rev 1 hw, this corresponds to CAPPTR\r
+ * On rev 2 hw, this corresponds to CAP_POINTER\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXPNSN_ROM\r
* On rev 1 hw, this corresponds to EXPANSION_ROM_BAR\r
+ * On rev 2 hw, this corresponds to TYPE1_EXP_ROM_BASE_REG\r
*\r
* @{\r
*/\r
* Rev 0 hw: 21 bits are modifiable\r
* Rev 1 hw: only upper 16 bits are modifyable (eg 16-20). Rest are read-only. If users tries\r
* to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
+ * Rev 2 hw: 21 bits are modifiable\r
*\r
* On rev 0 hw, this corresponds to EXP_ROM_BASE_ADDR\r
* On rev 1 hw, this corresponds to EXROM_ADDRESS\r
+ * On rev 2 hw, this corresponds to EXP_ROM_BASE_ADDRESS\r
*\r
* Field size: 21CAPPTR bits [0-0x1FFFFF]\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXP_ROM_EN\r
* On rev 1 hw, this corresponds to EXP_ROM_EN\r
+ * On rev 2 hw, this corresponds to ROM_BAR_ENABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BRIDGE_INT\r
* On rev 1 hw, this corresponds to BRIDGE_INT\r
+ * On rev 2 hw, this corresponds to BRIDGE_CTRL_INT_PIN_INT_LINE_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERREN_STATUS\r
* On rev 1 hw, this corresponds to DT_SERR_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TIMER_STATUS\r
* On rev 1 hw, this corresponds to DT_STS\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SEC_TIMER\r
* On rev 1 hw, this corresponds to SEC_DT\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRI_TIMER\r
* On rev 1 hw, this corresponds to PRI_DT\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to B2B_EN\r
* On rev 1 hw, this corresponds to FAST_B2B_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SEC_BUS_RST\r
* On rev 1 hw, this corresponds to SEC_BUS_RST\r
+ * On rev 2 hw, this corresponds to SBR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MST_ABORT_MODE\r
* On rev 1 hw, this corresponds to MST_ABT_MODE\r
+ * On rev 2 hw, this corresponds to MSTR_ABORT_MODE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to VGA_DECODE\r
* On rev 1 hw, this corresponds to VGA_16B_DEC\r
+ * On rev 2 hw, this corresponds to VGA_16B_DEC\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to VGA_EN\r
* On rev 1 hw, this corresponds to VGA_EN\r
+ * On rev 2 hw, this corresponds to VGA_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ISA_EN\r
* On rev 1 hw, this corresponds to ISA_EN\r
+ * On rev 2 hw, this corresponds to ISA_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERR_EN\r
* On rev 1 hw, this corresponds to SERR_EN\r
+ * On rev 2 hw, this corresponds to SERR_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PERR_RESP_EN\r
* On rev 1 hw, this corresponds to PERR_RESP_EN\r
+ * On rev 2 hw, this corresponds to PERE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_PIN\r
* On rev 1 hw, this corresponds to INT_PIN\r
+ * On rev 2 hw, this corresponds to INT_PIN\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_LINE\r
* On rev 1 hw, this corresponds to INT_LIN\r
+ * On rev 2 hw, this corresponds to INT_LINE\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PMCAP for EP and RC\r
* On rev 1 hw, this corresponds to PM_CAP for EP only\r
+ * On rev 2 hw, this corresponds to CAP_ID_NXT_PTR_REG for EP and RC\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PME_SUPP_N\r
* On rev 1 hw, this corresponds to PME_SP\r
+ * On rev 2 hw, this corresponds to PME_SUPPORT\r
*\r
* Field size: 5 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to D2_SUPP_N\r
* On rev 1 hw, this corresponds to D2_SP\r
+ * On rev 2 hw, this corresponds to D2_SUPPORT\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to D1_SUPP_N\r
* On rev 1 hw, this corresponds to D1_SP\r
+ * On rev 2 hw, this corresponds to D1_SUPPORT\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to AUX_CURR_N\r
* On rev 1 hw, this corresponds to AUX_CUR\r
+ * On rev 2 hw, this corresponds to AUX_CURR\r
*\r
* Field size: 3 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to DSI_N\r
* On rev 1 hw, this corresponds to DSI\r
+ * On rev 2 hw, this corresponds to DSI\r
*\r
* Field size: 1 bit\r
*\r
/**\r
* @brief [ro] PME clock. Hardwired to zero.\r
*\r
- * On rev 0 hw, this corresponds to D2_SUPP_N\r
- * On rev 1 hw, this corresponds to D2_SP\r
+ * On rev 0 hw, this corresponds to PME_CLK\r
+ * On rev 1 hw, this corresponds to PME_CLK\r
+ * On rev 2 hw, this corresponds to PME_CLK\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to PME_SPEC_VER\r
* On rev 1 hw, this corresponds to PMC_VER\r
+ * On rev 2 hw, this corresponds to PM_SPEC_VER\r
*\r
* Field size: 3 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to PM_NEXT_PTR\r
* On rev 1 hw, this corresponds to PM_NX_PTR\r
+ * On rev 2 hw, this corresponds to PM_NEXT_POINTER\r
*\r
* Field size: 8 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to PM_CAP_ID\r
* On rev 1 hw, this corresponds to CAP_ID\r
+ * On rev 2 hw, this corresponds to PM_CAP_ID\r
*\r
* Field size: 8 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to PM_CTL_STAT for EP and RC\r
* On rev 1 hw, this corresponds to PM_CSR for EP only\r
+ * On rev 2 hw, this corresponds to CON_STATUS_REG for EP and RC only\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to DATA_REG\r
* On rev 1 hw, this corresponds to DATA1\r
+ * On rev 2 hw, this corresponds to DATA_REG_ADD_INFO\r
*\r
* Field size: 8 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to CLK_CTRL_EN\r
* On rev 1 hw, this corresponds to BP_CCE\r
+ * On rev 2 hw, this corresponds to BUS_PWR_CLK_CON_EN\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to B2_B3_SUPPORT\r
* On rev 1 hw, this corresponds to B2B3_SP\r
+ * On rev 2 hw, this corresponds to B2_B3_SUPPORT\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to PME_STATUS\r
* On rev 1 hw, this corresponds to PME_STATUS\r
+ * On rev 2 hw, this corresponds to PME_STATUS\r
*\r
* Write 1 to clear.\r
*\r
*\r
* On rev 0 hw, this corresponds to DATA_SCALE\r
* On rev 1 hw, this corresponds to DATA_SCALE\r
+ * On rev 2 hw, this corresponds to DATA_SCALE\r
*\r
* Field size: 2 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to DATA_SELECT\r
* On rev 1 hw, this corresponds to DATA_SEL\r
+ * On rev 2 hw, this corresponds to DATA_SELECT\r
*\r
* Field size: 4 bits\r
*\r
/**\r
* @brief [rw] PME Enable. Value of 1 indicates device is enabled to generate PME.\r
*\r
- * On rev 0 hw, this corresponds to PM_CAP_ID\r
- * On rev 1 hw, this corresponds to CAP_ID\r
+ * On rev 0 hw, this corresponds to PME_EN\r
+ * On rev 1 hw, this corresponds to PME_EN\r
+ * On rev 2 hw, this corresponds to PME_ENABLE\r
*\r
* Field size: 1 bit\r
*\r
*\r
* It is set to disable reset during a transition from D3 to D0.\r
*\r
- * On rev 0 hw, this corresponds to PME_EN\r
- * On rev 1 hw, this corresponds to PME_EN\r
+ * On rev 0 hw, this corresponds to NO_SOFT_RST\r
+ * On rev 1 hw, this corresponds to NSR\r
+ * On rev 2 hw, this corresponds to NO_SOFT_RST\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to PWR_STATE\r
* On rev 1 hw, this corresponds to PM_STATE\r
+ * On rev 2 hw, this corresponds to POWER_STATE\r
*\r
* Field size: 2 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to MSI_CAP for EP and RC\r
* On rev 1 hw, this corresponds to MSI_CAP for EP only\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_ID_NEXT_CTRL_REG for EP only\r
*\r
* @{\r
*/\r
typedef struct pcieMsiCapReg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] MSI Per Vector Masking supported\r
+ *\r
+ * on rev 0 hw: unsupported\r
+ * on rev 1 hw: unsupported\r
+ * On rev 2 hw, this corresponds to PCI_MSI_EXT_DATA_EN\r
+ *\r
+ * Field size: 1 bit\r
+ *\r
+ */\r
+ uint8_t extDataEn;\r
+ /**\r
+ * @brief [ro] Extended message data capable\r
+ *\r
+ * on rev 0 hw: unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCI_MSI_EXT_DATA_CAP\r
+ *\r
+ * Field size: 1 bit\r
+ *\r
+ */\r
+ uint8_t extDataCap;\r
/**\r
* @brief [ro] MSI Per Vector Masking supported\r
*\r
* on rev 0 hw: unsupported\r
* On rev 1 hw, this corresponds to PVM_EN\r
+ * On rev 2 hw, this corresponds to PCI_PVM_SUPPORT\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to 64BIT_EN\r
* On rev 1 hw, this corresponds to MSI_64_EN\r
+ * On rev 2 hw, this corresponds to PCI_MSI_64_BIT_ADDR_CAP\r
*\r
* Field size: 1 bit\r
*\r
*\r
* On rev 0 hw, this corresponds to MULT_MSG_EN\r
* On rev 1 hw, this corresponds to MME\r
+ * On rev 2 hw, this corresponds to PCI_MSI_MULTIPLE_MSG_EN\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MULT_MSG_CAP\r
* On rev 1 hw, this corresponds to MMC\r
+ * On rev 2 hw, this corresponds to PCI_MSI_MULTIPLE_MSG_CAP\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI_EN\r
* On rev 1 hw, this corresponds to MSI_EN\r
+ * On rev 2 hw, this corresponds to PCI_MSI_ENABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NEXT_CAP\r
* On rev 1 hw, this corresponds to MSI_NX_PTR\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_NEXT_OFFSET\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_ID\r
* On rev 1 hw, this corresponds to CAP_ID\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_ID\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI_LOW32 for EP and RC\r
* On rev 1 hw, this corresponds to MSI_ADD_L32 for EP only\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_04H_REG for EP only\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to LOW32_ADDR\r
* On rev 1 hw, this corresponds to ADDR\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_04H\r
*\r
* Field size: 30 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to MSI_UP32 for EP and RC\r
* On rev 1 hw, this corresponds to MSI_ADD_L32 for EP only\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_08H_REG for EP only\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to UP32_ADDR\r
* On rev 1 hw, this corresponds to ADDR\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_08H\r
*\r
* Field size: 32 bits\r
*\r
*\r
* On rev 0 hw, this corresponds to MSI_DATA for EP and RC\r
* On rev 1 hw, this corresponds to MSI_DATA for EP only\r
- *\r
- * This register is only available for rev 0 hw.\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_0CH_REG for EP only\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to MSI_DATA\r
* On rev 1 hw, this corresponds to DATA\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_0CH\r
*\r
* Field size: 16 bits\r
*\r
} pcieMsiDataReg_t;\r
/* @} */\r
\r
+/**\r
+ * @ingroup pcielld_reg_cfg_msi_structures\r
+ * @brief Specification of the MSI_CAP_OFF_14H_REG Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_10H_REG for EP only\r
+ *\r
+ * This register is only available for rev 2 hw.\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pcieMsiCapOff10H {\r
+ uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] MSI data\r
+ *\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_10H\r
+ *\r
+ * Field size: 32 bits\r
+ *\r
+ */\r
+ uint32_t data;\r
+} pcieMsiCapOff10HReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_cfg_msi_structures\r
+ * @brief Specification of the MSI Data Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_14H_REG for EP only\r
+ *\r
+ * This register is only available for rev 2 hw.\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pcieMsiCapOff14H {\r
+ uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] MSI data\r
+ *\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_14H\r
+ *\r
+ * Field size: 32 bits\r
+ *\r
+ */\r
+ uint32_t data;\r
+} pcieMsiCapOff14HReg_t;\r
+/* @} */\r
+\r
+\r
/*****************************************************************************\r
********** PCIe CAPABILITIES REGISTERS ************************************\r
****************************************************************************/\r
*\r
* On rev 0 hw, this corresponds to PCIE_CAP\r
* On rev 1 hw, this corresponds to PCIE_CAP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to INT_MSG\r
* On rev 1 hw, this corresponds to IM_NUM\r
+ * On rev 2 hw, this corresponds to PCIE_INT_MSG_NUM\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SLT_IMPL_N\r
* On rev 1 hw, this corresponds to SLOT\r
+ * On rev 2 hw, this corresponds to PCIE_SLOT_IMP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DPORT_TYPE\r
* On rev 1 hw, this corresponds to DEV_TYPE\r
+ * On rev 2 hw, this corresponds to PCIE_DEV_PORT_TYPE\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_CAP\r
* On rev 1 hw, this corresponds to PCIE_VER\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_REG\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to NEXT_CAP\r
* On rev 1 hw, this corresponds to PCIE_NX_PTR\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_NEXT_PTR\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CAP_ID\r
* On rev 1 hw, this corresponds to CAP_ID\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ID\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to DEVICE_CAP\r
* On rev 1 hw, this corresponds to DEV_CAP\r
+ * On rev 2 hw, this corresponds to DEVICE_CAPABILITIES_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to FLR_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_FLR_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_LIMIT_SCALE\r
* On rev 1 hw, this corresponds to CAPT_SLOW_PWRLIMIT_SCALE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_LIMIT_VALUE\r
* On rev 1 hw, this corresponds to CAPT_SLOW_PWRLIMIT_VALUE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_RPT\r
* On rev 1 hw, this corresponds to ROLEBASED_ERRRPT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ROLE_BASED_ERR_REPORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to L1_LATENCY\r
* On rev 1 hw, this corresponds to DEFAULT_EP_L1_LATENCY\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EP_L1_ACCPT_LATENCY\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to L0_LATENCY\r
* On rev 1 hw, this corresponds to DEFAULT_EP_L0S_LATENCY\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EP_L0S_ACCPT_LATENCY\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXT_TAG_FLD\r
* On rev 1 hw, this corresponds to EXTTAGFIELD_SUPPORT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EXT_TAG_SUPP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PHANTOM_FLD\r
* On rev 1 hw, this corresponds to PHANTOMFUNC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PHANTOM_FUNC_SUPPORT\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MAX_PAYLD_SZ\r
* On rev 1 hw, this corresponds to MAX_PAYLOAD_SIZE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MAX_PAYLOAD_SIZE\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to DEV_STAT_CTRL\r
* On rev 1 hw, this corresponds to DEV_CAS\r
+ * On rev 2 hw, this corresponds to DEVICE_CONTROL_DEVICE_STATUS\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to TPEND\r
* On rev 1 hw, this corresponds to TRANS_PEND\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_TRANS_PENDING\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to AUX_PWR\r
* On rev 1 hw, this corresponds to AUXP_DET\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_AUX_POWER_DETECTED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to UNSUP_RQ_DET\r
* On rev 1 hw, this corresponds to UR_DET\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_UNSUPPORTED_REQ_DETECTED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FATAL_ERR\r
* On rev 1 hw, this corresponds to FT_DET\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_FATAL_ERR_DETECTED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NFATAL_ERR\r
* On rev 1 hw, this corresponds to NFT_DET\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_NON_FATAL_ERR_DETECTED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CORR_ERR\r
* On rev 1 hw, this corresponds to COR_DET\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CORR_ERR_DETECTED\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t corrEr;\r
+ /**\r
+ * @brief [rw] Initiate Function Level Reset (for EP)\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 1 hw, this corresponds to PCIE_CAP_INITIATE_FLR\r
+ *\r
+ * Field size: 3 bits\r
+ */\r
+ uint8_t initFLR;\r
/**\r
* @brief [rw] Maximum Read Request Size\r
*\r
* On rev 0 hw, this corresponds to MAX_REQ_SZ\r
* On rev 1 hw, this corresponds to MRRS\r
+ * On rev 1 hw, this corresponds to PCIE_CAP_MAX_READ_REQ_SIZE\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to NO_SNOOP\r
* On rev 1 hw, this corresponds to NOSNP_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EN_NO_SNOOP\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] AUX Power PM Enable\r
*\r
* On rev 0 hw, this corresponds to AUX_PWR_PM_EN\r
- * On rev 1 hw, this corresponds to AUXPM_EN\r
+ * On rev 1 hw, this corresponds to AUXM_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_AUX_POWER_PM_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PHANTOM_EN\r
* On rev 1 hw, this corresponds to PHFUN_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PHANTOM_FUNC_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to XTAG_FIELD_EN\r
* On rev 1 hw, this corresponds to EXTAG_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EXT_TAG_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MAX_PAYLD\r
* On rev 1 hw, this corresponds to MPS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MAX_PAYLOAD_SIZE_CS\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to RELAXED\r
* On rev 1 hw, this corresponds to EN_RO\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EN_REL_ORDER\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to UNSUP_REQ_RP\r
* On rev 1 hw, this corresponds to UR_RE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_UNSUPPORT_REQ_REP_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FATAL_ERR_RP\r
* On rev 1 hw, this corresponds to FT_RE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_FATAL_ERR_REPORT_E\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NFATAL_ERR_RP\r
* On rev 1 hw, this corresponds to NFT_RE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_NON_FATAL_ERR_REPORT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CORR_ERR_RP\r
* On rev 1 hw, this corresponds to COR_RE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CORR_ERR_REPORT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_CAP\r
* On rev 1 hw, this corresponds to LNK_CAP\r
+ * On rev 2 hw, this corresponds to LINK_CAPABILITIES_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PORT_NUM\r
* On rev 1 hw, this corresponds to PORT_NUM\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PORT_NUM\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, unsuppported\r
* On rev 1 hw, this corresponds to ASPM_OPT_COMP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ASPM_OPT_COMPLIANCE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BW_NOTIFY_CAP\r
* On rev 1 hw, this corresponds to LNK_BW_NOT_CAP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_BW_NOT_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLL_REP_CAP\r
* On rev 1 hw, this corresponds to DLL_ACTRPT_CAP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_DLL_ACTIVE_REP_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DOWN_ERR_REP_CAP\r
* On rev 1 hw, this corresponds to UNSUP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CLK_PWR_MGMT\r
* On rev 1 hw, this corresponds to CLK_PWR_MGMT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CLOCK_POWER_MAN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to L1_EXIT_LAT\r
* On rev 1 hw, this corresponds to L1_EXIT_LAT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_L1_EXIT_LATENCY\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to L0S_EXIT_LAT\r
* On rev 1 hw, this corresponds to L0S_EXIT_LAT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_L0S_EXIT_LATENCY\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to AS_LINK_PM\r
* On rev 1 hw, this corresponds to AS_LINK_PM_SUPPORT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MAX_LINK_WIDTH\r
* On rev 1 hw, this corresponds to MAX_LINK_WIDTH\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MAX_LINK_WIDTH\r
*\r
* Field size: 6 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to MAX_LINK_SPEED\r
* On rev 1 hw, this corresponds to MAX_LINK_SPEEDS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MAX_LINK_SPEED\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_STAT_CTRL\r
* On rev 1 hw, this corresponds to LNK_CAS\r
+ * On rev 2 hw, this corresponds to LINK_CONTROL_LINK_STATUS_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_BW_STATUS\r
* On rev 1 hw, this corresponds to LAB_STATUS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_AUTO_BW_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_BW_MGMT_STATUS\r
* On rev 1 hw, this corresponds to LBW_STATUS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_BW_MAN_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLL_ACTIVE\r
* On rev 1 hw, this corresponds to DLL_ACT\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_DLL_ACTIVE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SLOT_CLK_CFG\r
* On rev 1 hw, this corresponds to SLOT_CLK_CONFIG\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SLOT_CLK_CONFIG\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_TRAINING\r
* On rev 1 hw, this corresponds to LINK_TRAIN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_TRAINING\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NEGOTIATED_LINK_WD\r
* On rev 1 hw, this corresponds to NEG_LW\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_NEGO_LINK_WIDTH\r
*\r
* Field size: 6 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_SPEED\r
* On rev 1 hw, this corresponds to LINK_SPEED\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_SPEED\r
*\r
* Field size: 4 bits\r
*/\r
uint8_t linkSpeed;\r
+ /**\r
+ * @brief [rw] DRS Signalling Control\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_DRS_SIGNALING_CONTROL\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t drsSigCtrl;\r
/**\r
* @brief [rw] Link Autonomous Bandwidth Interrupt Enable. Not applicable and is reserved for EP\r
*\r
* On rev 0 hw, this corresponds to LINK_BW_INT_EN\r
* On rev 1 hw, this corresponds to LABIE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_AUTO_BW_INT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_BW_MGMT_INT_EN\r
* On rev 1 hw, this corresponds to LBMIE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_BW_MAN_INT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to HW_AUTO_WIDTH_DIS\r
* On rev 1 hw, this corresponds to HAWD\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_HW_AUTO_WIDTH_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CLK_PWR_MGMT_EN\r
* On rev 1 hw, this corresponds to EN_CPM\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EN_CLK_POWER_MAN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXT_SYNC\r
* On rev 1 hw, this corresponds to EXT_SYN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EXTENDED_SYNCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to COMMON_CLK_CFG\r
* On rev 1 hw, this corresponds to COM_CLK_CFG\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_COMMON_CLK_CONFIG\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RETRAIN_LINK\r
* On rev 1 hw, this corresponds to RETRAIN_LINK\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_RETRAIN_LINK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_DISABLE\r
* On rev 1 hw, this corresponds to LINK_DIS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCB\r
* On rev 1 hw, this corresponds to RCB\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_RCB\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ACTIVE_LINK_PM\r
* On rev 1 hw, this corresponds to ASPM_CTRL\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SLOT_CAP\r
* On rev 1 hw, this corresponds to SLOT_CAP\r
+ * On rev 2 hw, this corresponds to SLOT_CAPABILITIES_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to SLOT_NUM\r
* On rev 1 hw, this corresponds to PSN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PHY_SLOT_NUM\r
*\r
* Field size: 13 bits [0-0x1FFF]\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMD_COMP_SUPP\r
* On rev 1 hw, this corresponds to NCCS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_NO_CMD_CPL_SUPPORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to EML_PRESENT\r
* On rev 1 hw, this corresponds to EIP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ELECTROMECH_INTERLOCK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_LMT_SCALE\r
* On rev 1 hw, this corresponds to SPLS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SLOT_POWER_LIMIT_SCALE\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_LMT_VALUE\r
* On rev 1 hw, this corresponds to SPLV\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SLOT_POWER_LIMIT_VALUE\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to HP_CAP\r
* On rev 1 hw, this corresponds to HPC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_HOT_PLUG_CAPABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to HP_SURPRISE\r
* On rev 1 hw, this corresponds to HPS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_HOT_PLUG_SURPRISE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_IND\r
* On rev 1 hw, this corresponds to PIP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_POWER_INDICATOR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ATTN_IND\r
* On rev 1 hw, this corresponds to AIP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_INDICATOR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MRL_SENSOR\r
* On rev 1 hw, this corresponds to MRLSP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_CTL\r
* On rev 1 hw, this corresponds to PCP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_POWER_CONTROLLER\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ATTN_BUTTON\r
* On rev 1 hw, this corresponds to ABP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_INDICATOR_BUTTON\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SLOT_STAT_CTRL\r
* On rev 1 hw, this corresponds to SLOT_CAS\r
+ * On rev 2 hw, this corresponds to SLOT_CONTROL_SLOT_STATUS\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLL_STATE\r
* On rev 1 hw, this corresponds to DSC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_DLL_STATE_CHANGED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to EM_LOCK\r
* On rev 1 hw, this corresponds to EIS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRESENCE_DET\r
* On rev 1 hw, this corresponds to PDS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PRESENCE_DETECT_STATE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MRL_STATE\r
* On rev 1 hw, this corresponds to MRLSS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR_STATE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMD_COMPLETE\r
* On rev 1 hw, this corresponds to CC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CMD_CPLD\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRESENCE_CHG\r
* On rev 1 hw, this corresponds to PDC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PRESENCE_DETECTED_CHANGED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MRL_CHANGE\r
* On rev 1 hw, this corresponds to MRCSC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR_CHANGED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_FAULT\r
* On rev 1 hw, this corresponds to PFD\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_POWER_FAULT_DETECTED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ATTN_PRESSED\r
* On rev 1 hw, this corresponds to ABP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_BUTTON_PRESSED\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLL_CHG_EN\r
* On rev 1 hw, this corresponds to DSC_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_DLL_STATE_CHANGED_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to EM_LOCK_CTL\r
* On rev 1 hw, this corresponds to EIC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_CTL\r
* On rev 1 hw, this corresponds to PCC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_POWER_INDICATOR_CTRL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PM_IND_CTL\r
* On rev 1 hw, this corresponds to PIC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_POWER_INDICATOR_CTRL\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to ATTN_IND_CTL\r
* On rev 1 hw, this corresponds to AIC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_INDICATOR_CTR\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to HP_INT_EN\r
* On rev 1 hw, this corresponds to HPI_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_HOT_PLUG_INT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMD_CMP_INT_EN\r
* On rev 1 hw, this corresponds to CCI_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CMD_CPL_INT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PRS_DET_CHG_EN\r
* On rev 1 hw, this corresponds to PDC_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PRESENCE_DETECT_CHANGE_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MRL_CHG_EN\r
* On rev 1 hw, this corresponds to MRLSC_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR_CHANGED_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PWR_FLT_DET_EN\r
* On rev 1 hw, this corresponds to PFD_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_POWER_FAULT_DETECTED_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ATTN_BUTT_EN\r
* On rev 1 hw, this corresponds to ABP_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ROOT_CTRL_CAP\r
* On rev 1 hw, this corresponds to ROOT_CAC\r
+ * On rev 2 hw, this corresponds to ROOT_CONTROL_ROOT_CAPABILITIES_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to CRS_SW\r
* On rev 1 hw, this corresponds to CRSSV\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CRS_SW_VISIBILITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CRS_SW_EN\r
* On rev 1 hw, this corresponds to CRSSV_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CRS_SW_VISIBILITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PME_INT_EN\r
* On rev 1 hw, this corresponds to PMEI_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PME_INT_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERR_FATAL_ERR\r
* On rev 1 hw, this corresponds to SEFE_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERR_NFATAL_ERR\r
* On rev 1 hw, this corresponds to SENE_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SERR_EN\r
* On rev 1 hw, this corresponds to SECE_EN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ROOT_STATUS\r
* On rev 1 hw, this corresponds to ROOT_STS\r
+ * On rev 2 hw, this corresponds to ROOT_STATUS_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to PME_PEND\r
* On rev 1 hw, this corresponds to PME_PND\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PME_PENDING\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PME_STATUS\r
* On rev 1 hw, this corresponds to PME_STS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PME_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PME_REQ_ID\r
* On rev 1 hw, this corresponds to PME_RID\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_PME_REQ\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to DEV_CAP2\r
* On rev 1 hw, this corresponds to DEV_CAP_2\r
+ * On rev 2 hw, this corresponds to DEVICE_CAPABILITIES2_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TO_DIS_SUPP\r
* On rev 1 hw, this corresponds to CPL_TIMEOUT_DIS_SUPPORTED\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TO_EN\r
* On rev 1 hw, this corresponds to CPL_TIMEOUT_RNG_SUPPORTED\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_RANGE\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to ARI_FWD_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ARI_FORWARD_SUPPORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to AOR_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ATOMIC_ROUTING_SUPP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to AOC32_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_32_ATOMIC_CPL_SUPP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to AOC64_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_64_ATOMIC_CPL_SUPP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to CASC128_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_128_CAS_CPL_SUPP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to NOROPR\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_NO_RO_EN_PR2PR_PAR\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t noRoPR;\r
+ /**\r
+ * @brief [ro] LTR Mechanism Supported\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LTR_SUPP\r
+ *\r
+ * Field size: 2 bit\r
+ */\r
+ uint8_t ltrSupp;\r
/**\r
* @brief [ro] TPH Completer Supported\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to TPHC_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_TPH_CMPLT_SUPPORT_0 | PCIE_CAP_TPH_CMPLT_SUPPORT_1\r
*\r
- * Field size: 1 bit\r
+ * Field size: 2 bit\r
*/\r
uint8_t tphcSp;\r
-} pcieDevCap2Reg_t;\r
-/* @} */\r
-\r
-/**\r
- * @ingroup pcielld_reg_cfg_cap_structures\r
+ /**\r
+ * @brief [ro] LN System CLS\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCIE_CAP2_LN_SYS_CLS\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t lnSysCls;\r
+ /**\r
+ * @brief [ro] 10-Bit Tag Completer Supported (ep only)\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t tag10bitCompSupp;\r
+ /**\r
+ * @brief [ro] 10-Bit Tag Requester Supported\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t tag10bitReqSupp;\r
+ /**\r
+ * @brief [ro] [OBFF] Optimized Buffer Flush/fill Supported\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_OBFF_SUPPORT\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t obffSupp;\r
+\r
+} pcieDevCap2Reg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_cfg_cap_structures\r
* @brief Specification of the Device Status and Control Register 2\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* On rev 0 hw, this corresponds to DEV_STAT_CTRL2\r
* On rev 1 hw, this corresponds to DEV_CAS_2\r
+ * On rev 2 hw, this corresponds to DEVICE_CONTROL2_DEVICE_STATUS2_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TO_DIS\r
* On rev 1 hw, this corresponds to CPL_TIMEOUT_DIS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TO\r
* On rev 1 hw, this corresponds to CPL_TIMEOUT_VALUE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_VALUE\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to ARI_FWD_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ARI_FORWARD_SUPPORT_CS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to AOP_REQ_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to AOP_EG_BLK\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to IDO_REQ_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to IDO_CPL_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to LTR_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to OBFF_EN\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to LNK_CAP_2\r
+ * On rev 2 hw, this corresponds to LINK_CAPABILITIES2_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to SP_LS_VEC\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR\r
*\r
* Field size: 7 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to CROSSLINK_SP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CROSS_LINK_SUPPORT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_CTRL2\r
* On rev 1 hw, this corresponds to LNK_CAS_2\r
+ * On rev 2 hw, this corresponds to LINK_CONTROL2_LINK_STATUS2_REG\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to DE_EMPH\r
* On rev 1 hw, this corresponds to DEEMPH_LEVEL\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_CURR_DEEMPHASIS\r
*\r
* Field size: 1 bit\r
*/\r
* 1 = -3.5 dB\r
*\r
* On rev 0 hw, this corresponds to POLL_DEEMPH\r
- * On rev 1 hw, this corresponds to COMPL_PRST_DEEMPH\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_SOS\r
* On rev 1 hw, this corresponds to COMPL_SOS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_COMPLIANCE_SOS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ENTR_MOD_COMPL\r
* On rev 1 hw, this corresponds to ENT_MOD_COMPL\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ENTER_MODIFIED_COMPLIANCE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TX_MARGIN\r
* On rev 1 hw, this corresponds to TX_MARGIN\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_TX_MARGIN\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SEL_DEEMPH\r
* On rev 1 hw, this corresponds to SEL_DEEMP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_SEL_DEEMPHASIS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to HW_AUTO_SPEED_DIS\r
* On rev 1 hw, this corresponds to HW_AUTO_SP_DIS\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_HW_AUTO_SPEED_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ENTR_COMPL\r
* On rev 1 hw, this corresponds to ENTR_COMPL\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ENTER_COMPLIANCE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TGT_SPEED\r
* On rev 1 hw, this corresponds to TRGT_LINK_SPEED\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_TARGET_LINK_SPEED\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to COMPL_PRST_DEEMPH\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_COMPLIANCE_PRESET\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to EQ_COMPLETE\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to EQ_PH1\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL_P1\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to EQ_PH2\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL_P2\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to EQ_PH3\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL_P3\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, unsupported\r
* On rev 1 hw, this corresponds to LINK_EQ_REQ\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_LINK_EQ_REQ\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t linkEqReq;\r
+ /**\r
+ * @brief [rw] Downstream Component Presence\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to DOWNSTREAM_COMPO_PRESENCE\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t downCompPres;\r
+ /**\r
+ * @brief [rw] DRS Message Received\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to DRS_MESSAGE_RECEIVED\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t drsMsgRecv;\r
} pcieLinkCtrl2Reg_t;\r
/* @} */\r
\r
*\r
* On rev 0 hw, this corresponds to PCIE_EXTCAP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to AER_EXT_CAP_HDR_OFF\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to NEXT_CAP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to NEXT_OFFSET\r
*\r
* Field size: 12 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXT_CAP_VER\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CAP_VERSION\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to EXT_CAP_ID\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CAP_ID\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_UNCERR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNCORR_ERR_STATUS_OFF\r
*\r
* @{\r
*/\r
typedef struct pcieUncErrReg_s {\r
uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] TLP Prefix Blocked Error Status\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to TLP_PRFX_BLOCKED_ERR_STATUS\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t tlpPrfxBlockedErrSt;\r
+ /**\r
+ * @brief [rw] Uncorrectable Internal Error Status\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INTERNAL_ERR_STATUS\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t intErrSt;\r
/**\r
* @brief [rw] Unsupported Request Error Status\r
*\r
*\r
* On rev 0 hw, this corresponds to UR_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNSUPPORTED_REQ_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ECRC_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MTLP_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MALF_TLP_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVR_OF_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to REC_OVERFLOW_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to UCMP_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNEXP_CMPLT_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_ABRT_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMPLT_ABORT_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TMOT_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMPLT_TIMEOUT_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FCP_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FC_PROTOCOL_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PSND_TLP_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to POIS_TLP_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SRPS_DN_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to SURPRISE_DOWN_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLP_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to DL_PROTOCOL_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_UNCERR_MASK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNCORR_ERR_MASK_OFF\r
*\r
* @{\r
*/\r
typedef struct pcieUncErrMaskReg_s {\r
uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [ro] TLP Prefix Blocked Error Mask\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to TLP_PRFX_BLOCKED_ERR_MASK\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t tlpPrfxBlockedErrMsk;\r
+ /**\r
+ * @brief [ro] AtomicOp Egress Block Mask\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ATOMIC_EGRESS_BLOCKED_ERR_MASK\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t atomicEgressBlockedErrMsk;\r
+ /**\r
+ * @brief [rw] Uncorrectable Internal Error Mask\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INTERNAL_ERR_MASK\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t intErrMsk;\r
/**\r
* @brief [rw] Unsupported Request Error Mask\r
*\r
* On rev 0 hw, this corresponds to UR_ERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNSUPPORTED_REQ_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ECRC_ERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MTLP_ERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MALF_TLP_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVR_OF_MASK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to REC_OVERFLOW_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to UCMP_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to NEXP_CMPLT_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_ABRT_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMPLT_ABORT_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TMOT_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMPLT_TIMEOUT_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FCP_ERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FC_PROTOCOL_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PSND_TLP_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to POIS_TLP_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SRPS_DN_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to SURPRISE_DOWN_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLP_ERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to DL_PROTOCOL_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_UNCERR_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNCORR_ERR_SEV_OFF\r
*\r
* @{\r
*/\r
typedef struct pcieUncErrSvrtyReg_s {\r
uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [ro] TLP Prefix Blocked Error Mask\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to TLP_PRFX_BLOCKED_ERR_SEVERITY\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t tlpPrfxBlockedErrSvrty;\r
+ /**\r
+ * @brief [ro] AtomicOp Egress Block Mask\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t atomicEgressBlockedErrSvrty;\r
+ /**\r
+ * @brief [rw] Uncorrectable Internal Error Mask\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INTERNAL_ERR_SEVERITY\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t intErrSvrty;\r
/**\r
* @brief [rw] Unsupported Request Error Severity\r
*\r
*\r
* On rev 0 hw, this corresponds to UR_ERR_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNSUPPORTED_REQ_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ECRC_ERR_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MTLP_ERR_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MALF_TLP_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVR_OF_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to REC_OVERFLOW_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to UCMP_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNEXP_CMPLT_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_ABRT_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMPLT_ABORT_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CMPL_TMOT_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMPLT_TIMEOUT_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FCP_ERR_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FC_PROTOCOL_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PSND_TLP_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to POIS_TLP_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SRPS_DN_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to SURPRISE_DOWN_ERR_SVRITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLP_ERR_SVRTY\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to DL_PROTOCOL_ERR_SEVERITY\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_CERR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORR_ERR_STATUS_OFF\r
*\r
* @{\r
*/\r
typedef struct pcieCorErrReg_s {\r
uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Header Log Overflow Error Status\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to HEADER_LOG_OVERFLOW_STATUS\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t hdrLogOverflowErrSt;\r
+ /**\r
+ * @brief [rw] Corrected Internal Error Status\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORRECTED_INT_ERR_STATUS\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t corrIntErrSt;\r
/**\r
* @brief [rw] Advisory Non-Fatal Error Status\r
*\r
*\r
* On rev 0 hw, this corresponds to ADV_NFERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ADVISORY_NON_FATAL_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RPLY_TMR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RPL_TIMER_TIMEOUT_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RPLT_RO_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to REPLAY_NO_ROLEOVER_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BAD_DLLP_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to BAD_DLLP_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BAD_TLP_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to BAD_TLP_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCV_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_ERR_STATUS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_CERR_MASK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORR_ERR_MASK_OFF\r
*\r
* @{\r
*/\r
typedef struct pcieCorErrMaskReg_s {\r
uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
- /**\r
+ /**\r
+ * @brief [rw] Header Log Overflow Error Status\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to HEADER_LOG_OVERFLOW_MASK\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t hdrLogOverflowErrMsk;\r
+ /**\r
+ * @brief [rw] Corrected Internal Error Status\r
+ *\r
+ * Write 1 to clear\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORRECTED_INT_ERR_MASK\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t corrIntErrMsk;\r
+ /**\r
* @brief [rw] Advisory Non-Fatal Error Mask\r
*\r
* On rev 0 hw, this corresponds to ADV_NFERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ADVISORY_NON_FATAL_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RPLY_TMR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RPL_TIMER_TIMEOUT_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RPLT_RO_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to REPLAY_NO_ROLEOVER_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BAD_DLLP_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to BAD_DLLP_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to BAD_TLP_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to BAD_TLP_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVR_ERR_MSK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_ERR_MASK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PCIE_ACCR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ADV_ERR_CAP_CTRL_OFF\r
*\r
* @{\r
*/\r
typedef struct pcieAccrReg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [ro] Multiple Header Recording Enable\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MULTIPLE_HEADER_EN\r
+ *\r
+ * Field size: 1bit\r
+ */\r
+ uint8_t multHdrEn;\r
+ /**\r
+ * @brief [ro] Multiple Header Recording Capable\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MULTIPLE_HEADER_CAP\r
+ *\r
+ * Field size: 1bit\r
+ */\r
+ uint8_t multHdrCap;\r
/**\r
* @brief [rw] ECRC Check Enable\r
*\r
* On rev 0 hw, this corresponds to ECRC_CHK_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_CHK_EN\r
*\r
* Field size: 1bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ECRC_CHK_CAP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_CHK_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ECRC_GEN_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_GEN_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ECRC_GEN_CAP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ECRC_GEN_CAP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FRST_ERR_PTR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FIRST_ERR_POINTER\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to HDR_LOGn (n = 0..3)\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to HDR_LOG_n_OFF (n = 0..3)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to HDR_DWn (n = 0..3)\r
* On rev 1 hw, unsupported\r
- *\r
+ * On rev 2 hw, this corresponds to (n=FIRST..FOURTH)\r
+ * (n_DWORD_FOURTH_BYTE << 24) | (n_DWORD_THIRD_BYTE << 16) |\r
+ * (n_DWORD_SECOND_BYTE << 8 ) | (n_DWORD_FIRST_BYTE << 0 )\r
* Field size: 32 bits\r
*/\r
uint32_t hdrDW;\r
*\r
* On rev 0 hw, this corresponds to ROOT_ERR_CMD\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ROOT_ERR_CMD_OFF (root complex only)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to FERR_RPT_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FATAL_ERR_REPORTING_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NFERR_RPT_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to NON_FATAL_ERR_REPORTING_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CERR_RPT_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORR_ERR_REPORTING_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ROOT_ERR_ST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ROOT_ERR_STATUS_OFF (root complex only)\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to AER_INT_MSG\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ADV_ERR_INT_MSG_NUM\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to FERR_RCV\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to _FATAL_ERR_MSG_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to NFERR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to NON_FATAL_ERR_MSG_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to UNCOR_FATAL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to FIRST_UNCORR_FATAL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MULT_FNF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MUL_ERR_FATAL_NON_FATAL_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_FNF\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_FATAL_NON_FATAL_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to MULT_COR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MUL_ERR_COR_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CORR_ERR\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_COR_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to ERR_SRC_ID\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_SRC_ID_OFF\r
*\r
* @{\r
*/\r
*\r
* On rev 0 hw, this corresponds to FNF_SRC_ID\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_FATAL_NON_FATAL_SOURCE_ID\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to CORR_SRC_ID\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_COR_SOURCE_ID\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PL_ACKTIMER\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_LAT_REL_TIM\r
+ * On rev 2 hw, this corresponds to ACK_LATENCY_TIMER_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* This is for additional internal processing for received\r
* TLPs and transmitted DLLPs.\r
*\r
+ * For rev 2 hw: REPLAY_TIME_LIMIT\r
+ *\r
* Field size: 16 bits\r
*/\r
uint16_t rplyLmt;\r
* This is for additional internal processing for received\r
* TLPs and transmitted DLLPs.\r
*\r
+ * For rev 2 hw: ROUND_TRIP_LATENCY_TIME_LIMIT\r
+ *\r
* Field size: 16 bits\r
*/\r
uint16_t rndTrpLmt;\r
*\r
* On rev 0 hw, this corresponds to PL_OMSG\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VENDOR_SPECIFIC_DLLP\r
+ * On rev 2 hw, this corresponds to VENDOR_SPEC_DLLP_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to OMSG\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VENDOR_SPECIFIC_DLLP.\r
+ * On rev 2 hw, this corresponds to VENDOR_SPEC_DLLP.\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PL_FORCE_LINK\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_PT_LNK_R\r
+ * On rev 2 hw, this corresponds to PORT_FORCE_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to LPE_CNT\r
* On rev 1 hw, this corresponds to LOW_POWER_ENTR_CNT.\r
+ * On rev 2 hw, this is reserved.\r
*\r
* Field size: 8 bits\r
*/\r
uint8_t lpeCnt;\r
+ /**\r
+ * @brief [rw] Do Deskew for SRIS\r
+ *\r
+ * Use the transitions from TS2 to Logical Idle Symbol, SKP OS to\r
+ * Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew\r
+ * for SRIS instead of using received SKP OS if\r
+ * doDeskewForSris is set to 1\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 0 & 1 hw, this is reserved\r
+ * On rev 2 hw, this corresponds to DO_DESKEW_FOR_SRIS\r
+ *\r
+ * Field size: 1 bits\r
+ */\r
+ uint8_t doDeskewForSris;\r
/**\r
* @brief [rw] Link State.\r
*\r
*\r
* On rev 0 hw, this corresponds to LNK_STATE\r
* On rev 1 hw, this corresponds to FORCED_LINK_COMMAND\r
+ * On rev 2 hw, this corresponds to LINK_STATE\r
*\r
* Field size: 6 bits\r
*/\r
*\r
* on rev 0 hw, this corresponds to FORCE_LINK\r
* on rev 1 hw, this corresponds to FORCE_LINK\r
+ * on rev 2 hw, this corresponds to FORCE_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* on rev 0 hw: unsupported\r
* on rev 1 hw, this corresponds to FORCED_LTSSM_STATE\r
+ * on rev 2 hw, this corresponds to FORCED_LTSSM\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* on rev 0 hw, this corresponds to LINK_NUM\r
* on rev 1 hw, this corresponds to LINK_NUM\r
+ * on rev 2 hw, this corresponds to LINK_NUM\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to ACK_FREQ\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_ACK_FREQ_ASPM\r
+ * On rev 2 hw, this corresponds to ACK_F_ASPM_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* on rev 0 hw, this corresponds to ASPM_L1\r
* on rev 1 hw, this corresponds to L1_ENTR_WO_L0S\r
+ * on rev 2 hw, this corresponds to ENTER_ASPM\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* on rev 0 hw, this corresponds to L1_ENTRY_LATENCY\r
* on rev 1 hw, this corresponds to L1_ENTR_LAT\r
+ * on rev 2 hw, this corresponds to L1_ENTRANCE_LATENCY\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* on rev 0 hw, this corresponds to L0S_ENTRY_LATENCY\r
* on rev 1 hw, this corresponds to L0S_ENTR_LAT\r
+ * on rev 2 hw, this corresponds to L0S_ENTRANCE_LATENCY\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to COMM_NFTS\r
* On rev 1 hw, this corresponds to COMMON_CLK_N_FTS\r
+ * On rev 2 hw, this corresponds to COMMON_CLK_N_FTS\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to NFTS\r
* On rev 1 hw, this corresponds to N_FTS\r
+ * On rev 2 hw, this corresponds to ACK_N_FTS\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to ACK_FREQ\r
* On rev 1 hw, this corresponds to ACK_FREQ\r
+ * On rev 2 hw, this corresponds to ACK_FREQ\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PL_LINK_CTRL\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_PT_LNK_CTRL_R\r
+ * On rev 2 hw, this corresponds to PORT_LINK_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw: unsupported\r
* On rev 1 hw, this corresponds to CROSSLINK_ACT\r
+ * On rev 2 hw: unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw: unsupported\r
* On rev 1 hw, this corresponds to CROSSLINK_EN\r
+ * On rev 2 hw: unsupported\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LNK_MODE\r
* On rev 1 hw, this corresponds to LINK_MODE\r
+ * On rev 2 hw, this corresponds to LINK_CAPABLE\r
*\r
* Field size: 6 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_RATE\r
* On rev 1 hw: unsupported.\r
+ * On rev 2 hw: unsupported.\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to FLNK_MODE\r
* On rev 1 hw, this corresponds to FAST_LINK\r
+ * On rev 2 hw, this corresponds to FAST_LINK_MODE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLL_EN\r
* On rev 1 hw, this corresponds to DL_EN\r
+ * On rev 2 hw, this corresponds to DLL_LINK_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RST_ASRT\r
* On rev 1 hw, this corresponds to RESET_ASSERT\r
+ * On rev 2 hw, this corresponds to RESET_ASSERT\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LPBK_EN\r
* On rev 1 hw, this corresponds to LB_EN\r
+ * On rev 2 hw, this corresponds to LOOPBACK_ENABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SCRM_DIS\r
* On rev 1 hw, this corresponds to SCRAMBLE_DIS\r
+ * On rev 2 hw, this corresponds to SCRAMBLE_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to OMSG_REQ\r
* On rev 1 hw, this corresponds to VEN_DLLP_REQ\r
+ * On rev 2 hw, this corresponds to VENDOR_SPECIFIC_DLLP_REQ\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LANE_SKEW\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_LN_SKW_R\r
+ * On rev 2 hw, this corresponds to LANE_SKEW_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to L2L_DESKEW\r
* On rev 1 hw, this corresponds to DIS_L2L_SKEW\r
+ * On rev 2 hw, this corresponds to DISABLE_LANE_TO_LANE_DESKEW\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t l2Deskew;\r
+ /**\r
+ * @brief [rw] Set lanes allowed for loopback\r
+ *\r
+ * Implementation-specific Number of Lanes Set the implementation specific\r
+ * number of lanes\r
+ * Allowed values are:\r
+ * 0000b: 1 lane\r
+ * 0001b: 2 lanes\r
+ * 0011b: 4 lanes\r
+ * 0111b: 8 lanes\r
+ * 1111b: 16 lanes\r
+ * The number of lanes to be used when in Loopback\r
+ * Master The number of lanes programmed must be equal to or less\r
+ * than the valid number of lanes set in LINK_CAPABLE field You must\r
+ * configure this field before initiating Loopback by writing in the\r
+ * LOOPBACK_ENABLE field The controller will transition from\r
+ * LoopbackEntry to LoopbackActive after receiving two consecutive\r
+ * TS1 Ordered Sets with the Loopback bit asserted on the\r
+ * implementation specific number of lanes configured in this field Note:\r
+ * This register field is sticky\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to IMPLEMENT_NUM_LANES\r
+ *\r
+ * Field size: 4 bits\r
+ */\r
+ uint8_t implementNumLanes;\r
/**\r
* @brief [rw] Set to disable Ack and Nak DLLP transmission.\r
*\r
* On rev 0 hw, this corresponds to ACK_DISABLE\r
* On rev 1 hw, this corresponds to ACKNAK_DIS\r
+ * On rev 2 hw, this corresponds to ACK_NAK_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FC_DISABLE\r
* On rev 1 hw, this corresponds to FC_DIS\r
+ * On rev 2 hw, this corresponds to FLOW_CTRL_DISABLE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LANE_SKEW\r
* On rev 1 hw, this corresponds to LANE_SKEW\r
+ * On rev 2 hw, this corresponds to INSERT_LANE_SKEW\r
*\r
* Field size: 24 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SYM_NUM\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_SYMB_N_R\r
+ * On rev 2 hw, this corresponds to TIMER_CTRL_MAX_FUNC_NUM_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to MAX_FUNC (3 bits)\r
* On rev 1 hw, this corresponds to MAX_FUNC (8 bits)\r
+ * On rev 2 hw, this corresponds to MAX_FUNC_NUM (8 bits)\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to FCWATCH_TIMER\r
* On rev 1 hw: unsupported\r
+ * On rev 2 hw: unsupported\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to ACK_LATENCY_TIMER\r
* On rev 1 hw, this corresponds to ACK_LATENCY_INC\r
+ * On rev 2 hw, this corresponds to TIMER_MOD_ACK_NAK\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to REPLAY_TIMER\r
* On rev 1 hw, this corresponds to REPLAY_ADJ\r
+ * On rev 2 hw, this corresponds to TIMER_MOD_REPLAY_TIMER\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to SKP_COUNT\r
* On rev 1 hw: unsupported\r
+ * On rev 2 hw: unsupported\r
*\r
* Field size: 3 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to NUM_TS2_SYMBOLS\r
* On rev 1 hw: unsupported\r
+ * On rev 2 hw: unsupported\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to TS_COUNT\r
* On rev 1 hw: unsupported\r
+ * On rev 2 hw: unsupported\r
*\r
* Field size: 4 bits\r
*/\r
uint8_t tsCount;\r
+ /**\r
+ * @brief [rw] Number of TS Symbols.\r
+ *\r
+ * Set the number of TS identifier symbols that are sent in TS1 and TS2\r
+ * ordered sets.\r
+ *\r
+ * On rev 0 hw: unsupported\r
+ * On rev 1 hw: unsupported\r
+ * On rev 2 hw: FAST_LINK_SCALING_FACTOR\r
+ *\r
+ * Fast Link Timer Scaling Factor Sets the scaling factor of LTSSM\r
+ * timer when FAST_LINK_MODE field in PCIE_EP_PORT_LINK_CTRL_OFF is set to '1'\r
+ * 0: Scaling Factor is 1024 [1ms is 1us]\r
+ * 1: Scaling Factor is 256 [1ms is 4us]\r
+ * 2: Scaling Factor is 64 [1ms is 16us]\r
+ * 3: Scaling Factor is 16 [1ms is 64us]\r
+ * Not used for M-PCIe Note: This register field is sticky\r
+ *\r
+ * Field size: 3 bits\r
+ */\r
+ uint8_t fastLinkScalingFactor;\r
} pcieSymNumReg_t;\r
/* @} */\r
\r
*\r
* On rev 0 hw, this corresponds to SYMTIMER_FLTMASK\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_SYMB_T_R\r
+ * On rev 2 hw, this corresponds to SYMBOL_TIMER_FILTER_1_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to F1_CFG_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_RC_CFG_DISCARD\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_IO_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_RC_IO_DISCARD\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_MSG_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_MSG_DROP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_ECRC_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_ECRC_DISCARD\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_ECRC_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_ECRC_DISCARD\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_LEN_TEST\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_LEN_MATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_ATTR_TEST\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_ATTR_MATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_TC_TEST\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_TC_MATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_FUNC_TEST\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_FUNC_MATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_REQID_TEST\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_REQID_MATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_CPL_TAGERR_TEST\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_TAGERR_MATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_LOCKED_RD_AS_UR\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_LOCKED_RD_AS_UR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_RE_AS_US\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CFG_TYPE1_RE_AS_UR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_UR_OUT_OF_BAR\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_UR_OUTSIDE_BAR\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_UR_POISON\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_UR_POIS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to F1_UR_FUN_MISMATCH\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+ * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_UR_FUNC_MISMATCH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to FC_WDOG_DISABLE\r
* On rev 1 hw, this corresponds to DIS_FC_TIM\r
+ * On rev 2 hw, this corresponds to DISABLE_FC_WD_TIMER\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to SKP_VALUE\r
* On rev 1 hw, this corresponds to SKP_INT\r
+ * On rev 2 hw, this corresponds to SKP_INT_VAL\r
*\r
* Field size: 11 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to FLT_MASK2\r
* On rev 1 hw, this corresponds to FLT_MSK_2\r
+ * On rev 2 hw, this corresponds to FILTER_MASK_2_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*/\r
typedef struct pcieFltMask2Reg_s {\r
uint32_t raw; /**< [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] 1 = Drop PRS messages silently\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_PRS_DROP\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t dropPRS;\r
+ /**\r
+ * @brief [rw] 1 = Enable unmask TD bit if CX_STRIP_ECRC_ENABLE\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_UNMASK_TD\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t unmaskTD;\r
+ /**\r
+ * @brief [rw] 1 = Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_UNMASK_UR_POIS_TRGT0\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t unmaskUrPOIS;\r
+ /**\r
+ * @brief [rw] 1 = Drop LN Messages silently\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_LN_VENMSG1_DROP\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t dropLN;\r
/**\r
* @brief [rw] 1 = Enable the filter to handle flush request.\r
*\r
* On rev 0 hw, this corresponds to FLUSH_REQ\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_HANDLE_FLUSH\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DLLP_ABORT\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_DABORT_4UCPL\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to VMSG1_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_VENMSG1_DROP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to VMSG0_DROP\r
* On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+ * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_VENMSG0_DROP\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DEBUG0\r
* On rev 1 hw, this corresponds to reserved\r
+ * On rev 2 hw, this corresponds to PL_DEBUG0_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to TS_LNK_CTRL\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to TS_LANE_K237\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TS_LINK_K237\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVD_IDLE0\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVD_IDLE1\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PIPE_TXDATA\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 16 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to PIPE_TXDATAK\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 2 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to TXB_SKIP_TX\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LTSSM_STATE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 5 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to DEBUG1\r
* On rev 1 hw, this corresponds to reserved\r
+ * On rev 2 hw, this corresponds to PL_DEBUG1_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw, this corresponds to SCRAMBLER_DISABLE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_DISABLE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to LINK_IN_TRAINING\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RCVR_REVRS_POL_EN\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to TRAINING_RST_N\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PIPE_TXDETECTRX_LB\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PIPE_TXELECIDLE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PIPE_TXCOMPLIANCE\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to APP_INIT_RST\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RMLH_TS_LINK_NUM\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw, this corresponds to XMLH_LINK_UP\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RMLH_INSKIP_RCV\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RMLH_TS1_RCVD\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RMLH_TS2_RCVD\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to RMLH_RCVD_LANE_REV\r
* On rev 1 hw, unsupported\r
+ * On rev 2 hw, presumed same as rev 0\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to PL_GEN2\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_WIDTH_SPEED_CTL\r
+ * On rev 2 hw, this corresponds to GEN2_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*/\r
typedef struct pcieGen2Reg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+ * @brief [rw] Electrical Idle Inference Mode at Gen1 Rate\r
+ *\r
+ * 0: Use RxElecIdle signal to infer Electrical Idle -\r
+ * 1: Use RxValid signal to infer Electrical Idle\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to GEN1_EI_INFERENCE\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t gen1EiInference;\r
/**\r
* @brief [rw] Set de-emphasis level for upstream (EP) ports\r
*\r
* On rev 0 hw, this corresponds to DEEMPH\r
* On rev 1 hw, this corresponds to CFG_UP_SEL_DEEMPH\r
+ * On rev 2 hw, this corresponds to SEL_DEEMPHASIS\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_TX_CMPL\r
* On rev 1 hw, this corresponds to CFG_TX_COMPLIANCE_RCV\r
+ * On rev 1 hw, this corresponds to CONFIG_TX_COMP_RX\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to CFG_TX_SWING\r
* On rev 1 hw, this corresponds to CFG_PHY_TXSWING\r
+ * On rev 2 hw, this corresponds to CONFIG_PHY_TX_CHANGE\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw, this corresponds to DIR_SPD\r
* On rev 1 hw, this corresponds to CFG_DIRECTED_SPEED_CHANGE\r
+ * On rev 2 hw, this corresponds to DIRECT_SPEED_CHANGE\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t dirSpd;\r
+ /**\r
+ * @brief [rw] Enable Auto flipping of the lanes\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to AUTO_LANE_FLIP_CTRL_EN\r
+ *\r
+ * Field size: 1 bits\r
+ */\r
+ uint8_t autoFlipEn;\r
+ /**\r
+ * @brief [rw] Predetermined Lane for Auto Flip\r
+ *\r
+ * Flip This field defines which physical\r
+ * lane is connected to logical Lane0 by the flip operation \r
+ * performed in Detect \r
+ * Allowed values are: - 3'b\r
+ * 000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/\r
+ * 2-1 or CX_NL/\r
+ * 4-1 or CX_NL/\r
+ * 8-1, depending on which lane is detected\r
+ * 001: Connect logical Lane0 to physical lane 1\r
+ * 010: Connect logical Lane0 to physical lane 3\r
+ * 011: Connect logical Lane0 to physical lane 7\r
+ * 100: Connect logical Lane0 to physical lane 15 \r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PRE_DET_LANE\r
+ *\r
+ * Field size: 3 bits\r
+ */\r
+ uint8_t preDetLane;\r
/**\r
* @brief [rw] Lane enable. 1h=x1, 2h=x2. Other values reserved.\r
*\r
* On rev 0 hw, this corresponds to LN_EN\r
* On rev 1 hw, this corresponds to CFG_LANE_EN\r
+ * On rev 2 hw, this corresponds to NUM_OF_LANES\r
*\r
- * Field size: 9 bits\r
+ * Field size: 9 bits (5 bits rev 2)\r
*/\r
uint16_t lnEn;\r
/**\r
*\r
* On rev 0 hw, this corresponds to NUM_FTS\r
* On rev 1 hw, this corresponds to CFG_GEN2_N_FTS\r
+ * On rev 2 hw, this corresponds to FAST_TRAINING_SEQ\r
*\r
* Field size: 8 bit\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_OBNP_SUBREQ_CTRL\r
+ * On rev 2 hw, this corresponds to AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
/**\r
* @brief [rw] Enable AXI Multiple Outbound Decomposed NP Sub-Requests\r
*\r
+ * On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to EN_OBNP_SUBREQ\r
+ * On rev 2 hw, this corresponds to OB_RD_SPLIT_BURST_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_TR_P_STS_R\r
+ * On rev 2 hw, this corresponds to TX_P_FC_CREDIT_STATUS_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [ro] Transmit Posted Data FC Credits\r
*\r
* On rev 1 hw, this corresponds to PD_CRDT\r
+ * On rev 2 hw, this corresponds to TX_P_DATA_FC_CREDIT\r
*\r
* Field size: 12 bits\r
*/\r
* @brief [ro] Transmit Posted Header FC Credits\r
*\r
* On rev 1 hw, this corresponds to PH_CRDT\r
+ * On rev 2 hw, this corresponds to TX_P_HEADER_FC_CREDIT\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_TR_NP_STS_R\r
+ * On rev 2 hw, this corresponds to TX_NP_FC_CREDIT_STATUS_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [ro] Transmit Non-Posted Data FC Credits\r
*\r
* On rev 1 hw, this corresponds to NPD_CRDT\r
+ * On rev 2 hw, this corresponds to TX_NP_DATA_FC_CREDIT\r
*\r
* Field size: 12 bits\r
*/\r
* @brief [ro] Transmit Non-Posted Header FC Credits\r
*\r
* On rev 1 hw, this corresponds to NPH_CRDT\r
+ * On rev 2 hw, this corresponds to TX_NP_HEADER_FC_CREDIT\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_TR_C_STS_R\r
+ * On rev 2 hw, this corresponds to TX_CPL_FC_CREDIT_STATUS_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [ro] Transmit Completion Data FC Credits\r
*\r
* On rev 1 hw, this corresponds to NPD_CRDT\r
+ * On rev 2 hw, this corresponds to TX_CPL_DATA_FC_CREDIT\r
*\r
* Field size: 12 bits\r
*/\r
* @brief [ro] Transmit Completion Header FC Credits\r
*\r
* On rev 1 hw, this corresponds to NPH_CRDT\r
+ * On rev 2 hw, this corresponds to TX_CPL_HEADER_FC_CREDIT\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] Received TLP FC Credits Not Returned\r
*\r
* On rev 1 hw, this corresponds to CRDT_NOT_RTRN\r
+ * On rev 2 hw, this corresponds to RX_TLP_FC_CREDIT_NON_RETURN\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [ro] Transmit Retry Buffer Not Empty\r
*\r
* On rev 1 hw, this corresponds to RTYB_NOT_EMPTY\r
+ * On rev 2 hw, this corresponds to TX_RETRY_BUFFER_NE\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [ro] Received Queue Not Empty\r
*\r
* On rev 1 hw, this corresponds to RCVQ_NOT_EMPTY\r
+ * On rev 2 hw, this corresponds to RX_QUEUE_NON_EMPTY\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t rcvqNotEmpty;\r
+ /**\r
+ * @brief [r/w1c] Receive Credit Queue Overflow\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_QUEUE_OVERFLOW\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t rxQueueOverflow;\r
+ /**\r
+ * @brief [r/w1c] Receive Serialization Queue Not Empty\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_SERIALIZATION_Q_NON_EMPTY\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t rxSerQNEmpty;\r
+ /**\r
+ * @brief [r/w1c] Receive Serialization Queue Write Error\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_SERIALIZATION_Q_WRITE_ERR\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t rxSerQWErr;\r
+ /**\r
+ * @brief [r/w1c] Receive Serialization Read Error\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RX_SERIALIZATION_Q_READ_ERR\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t rxSerRErr;\r
/**\r
* @brief [rw] FC Latency Timer Override Value\r
*\r
* On rev 1 hw, this corresponds to FC_LATENCY_OVR\r
+ * On rev 2 hw, this corresponds to TIMER_MOD_FLOW_CONTROL\r
*\r
* Field size: 13 bits\r
*/\r
* @brief [rw] FC Latency Timer Override Enable\r
*\r
* On rev 1 hw, this corresponds to FC_LATENCY_OVR_EN\r
+ * On rev 2 hw, this corresponds to TIMER_MOD_FLOW_CONTROL_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VC_TR_A_R1\r
+ * On rev 2 hw, this corresponds to VC_TX_ARBI_1_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [ro] WRR Weight for VC0\r
*\r
* On rev 1 hw, this corresponds to WRR_VC0\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_0\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] WRR Weight for VC1\r
*\r
* On rev 1 hw, this corresponds to WRR_VC1\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_1\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] WRR Weight for VC2\r
*\r
* On rev 1 hw, this corresponds to WRR_VC2\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_2\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] WRR Weight for VC3\r
*\r
* On rev 1 hw, this corresponds to WRR_VC3\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_3\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VC_TR_A_R2\r
+ * On rev 2 hw, this corresponds to VC_TX_ARBI_2_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [ro] WRR Weight for VC4\r
*\r
* On rev 1 hw, this corresponds to WRR_VC4\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_4\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] WRR Weight for VC5\r
*\r
* On rev 1 hw, this corresponds to WRR_VC5\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_5\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] WRR Weight for VC6\r
*\r
* On rev 1 hw, this corresponds to WRR_VC6\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_6\r
*\r
* Field size: 8 bits\r
*/\r
* @brief [ro] WRR Weight for VC7\r
*\r
* On rev 1 hw, this corresponds to WRR_VC7\r
+ * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_7\r
*\r
* Field size: 8 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_PR_Q_C\r
+ * On rev 2 hw, this corresponds to VC0_P_RX_Q_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @{\r
*/\r
-typedef struct pciePlconfVc0PrQCReg_s {\r
+typedef struct pciePlconfVcPrQCReg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
/**\r
* @brief [ro] VC0 Posted Data Credits\r
*\r
* On rev 1 hw, this corresponds to P_DCRD\r
+ * On rev 2 hw, this corresponds to VC0_P_DATA_CREDIT\r
*\r
* Field size: 12 bits\r
*/\r
* @brief [ro] VC0 Posted Header Credits\r
*\r
* On rev 1 hw, this corresponds to P_HCRD\r
+ * On rev 2 hw, this corresponds to VC0_P_HEADER_CREDIT\r
*\r
* Field size: 8 bits\r
*/\r
uint8_t pHcrd;\r
+ /**\r
+ * @brief [rw] VC0 Scale Posted Data Credits\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to VC0_P_DATA_SCALE\r
+ *\r
+ * Field size: 2 bits\r
+ */\r
+ uint8_t pDataScale;\r
+ /**\r
+ * @brief [rw] VC0 Scale Posted Header Credits\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to VC0_P_HDR_SCALE\r
+ *\r
+ * Field size: 2 bits\r
+ */\r
+ uint8_t pHdrScale;\r
/**\r
* @brief [rw] VC0 TLP Type Ordering Rules\r
*\r
* On rev 1 hw, this corresponds to ORDERING_RULES\r
+ * On rev 2 hw, this corresponds to TLP_TYPE_ORDERING_VC0\r
*\r
* <table>\r
* <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
/**\r
* @brief [rw] VC0 TLP Type Ordering Rules\r
*\r
- * On rev 1 hw, this corresponds to ORDERING_RULES\r
+ * On rev 1 hw, this corresponds to STRICT_VC_PRIORITY\r
+ * On rev 2 hw, this corresponds to VC_ORDERING_RX_Q\r
*\r
* <table>\r
* <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
* @brief [rw] VC0 Poster TLP Queue Mode\r
*\r
* On rev 1 hw, this corresponds to P_QMODE\r
+ * On rev 2 hw, unsupported\r
*\r
* <table>\r
* <tr><th>Action/Value</th><th>Mode</th></tr>\r
* Field size: 3 bits\r
*/\r
uint8_t pQmode;\r
-} pciePlconfVc0PrQCReg_t;\r
+} pciePlconfVcPrQCReg_t;\r
/* @} */\r
\r
+/**\r
+ * @ingroup pcielld_reg_cfg_pl_structures\r
+ * @brief backwards compatibility alias for Vc0 */\r
+typedef pciePlconfVcPrQCReg_t pciePlconfVc0PrQCReg_t;\r
+\r
/**\r
* @ingroup pcielld_reg_cfg_pl_structures\r
* @brief Specification of the VC0 Non-Posted Receive Queue Control (Sticky)\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_NPR_Q_C\r
+ * On rev 2 hw, this corresponds to VC0_NP_RX_Q_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @{\r
*/\r
-typedef struct pciePlconfVc0NprQCReg_s {\r
+typedef struct pciePlconfVcNprQCReg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
/**\r
* @brief [ro] VC0 Non-Posted Data Credits\r
*\r
* On rev 1 hw, this corresponds to NP_DCRD\r
+ * On rev 2 hw, this corresponds to VC0_NP_DATA_CREDIT\r
*\r
* Field size: 12 bits\r
*/\r
* @brief [ro] VC0 Non-Posted Header Credits\r
*\r
* On rev 1 hw, this corresponds to NP_HCRD\r
+ * On rev 2 hw, this corresponds to VC0_NP_HEADER_CREDIT\r
*\r
* Field size: 8 bits\r
*/\r
uint8_t npHcrd;\r
+ /**\r
+ * @brief [rw] VC0 Scale Non-Posted Data Credits\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to VC0_NP_DATA_SCALE\r
+ *\r
+ * Field size: 2 bits\r
+ */\r
+ uint8_t npDataScale;\r
+ /**\r
+ * @brief [rw] VC0 Scale Non-Posted Header Credits\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to VC0_NP_HDR_SCALE\r
+ *\r
+ * Field size: 2 bits\r
+ */\r
+ uint8_t npHdrScale;\r
/**\r
* @brief [rw] VC0 Non-Poster TLP Queue Mode\r
*\r
* On rev 1 hw, this corresponds to NP_QMODE\r
+ * On rev 2 hw, unsupported\r
*\r
* <table>\r
* <tr><th>Action/Value</th><th>Mode</th></tr>\r
* Field size: 3 bits\r
*/\r
uint8_t npQmode;\r
-} pciePlconfVc0NprQCReg_t;\r
+} pciePlconfVcNprQCReg_t;\r
/* @} */\r
\r
+/**\r
+ * @ingroup pcielld_reg_cfg_pl_structures\r
+ * @brief backwards compatibility alias for Vc0 */\r
+typedef pciePlconfVcNprQCReg_t pciePlconfVc0NprQCReg_t;\r
+\r
/**\r
* @ingroup pcielld_reg_cfg_pl_structures\r
* @brief Specification of the VC0 Completion Receive Queue Control (Sticky)\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_CR_Q_C\r
+ * On rev 1 hw, this corresponds to VC0_CPL_RX_Q_CTRL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @{\r
*/\r
-typedef struct pciePlconfVc0CrQCReg_s {\r
+typedef struct pciePlconfVcCrQCReg_s {\r
uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
/**\r
* @brief [ro] VC0 Completion Data Credits\r
*\r
* On rev 1 hw, this corresponds to CPL_DCRD\r
+ * On rev 2 hw, this corresponds to VC0_NP_DATA_CREDIT\r
*\r
* Field size: 12 bits\r
*/\r
* @brief [ro] VC0 Completion Header Credits\r
*\r
* On rev 1 hw, this corresponds to CPL_HCRD\r
+ * On rev 2 hw, this corresponds to VC0_NP_HEADER_CREDIT\r
*\r
* Field size: 8 bits\r
*/\r
uint8_t cplHcrd;\r
+ /**\r
+ * @brief [rw] VC0 Scale CPL Data Credits\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to VC0_CPL_DATA_SCALE\r
+ *\r
+ * Field size: 2 bits\r
+ */\r
+ uint8_t cplDataScale;\r
+ /**\r
+ * @brief [rw] VC0 Scale CPL Header Credits\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to VC0_CPL_HDR_SCALE\r
+ *\r
+ * Field size: 2 bits\r
+ */\r
+ uint8_t cplHdrScale;\r
/**\r
* @brief [rw] VC0 Completion TLP Queue Mode\r
*\r
* On rev 1 hw, this corresponds to CPL_QMODE\r
+ * On rev 2 hw, unsupported\r
*\r
* <table>\r
* <tr><th>Action/Value</th><th>Mode</th></tr>\r
* Field size: 3 bits\r
*/\r
uint8_t cplQmode;\r
-} pciePlconfVc0CrQCReg_t;\r
+} pciePlconfVcCrQCReg_t;\r
/* @} */\r
\r
+/**\r
+ * @ingroup pcielld_reg_cfg_pl_structures\r
+ * @brief backwards compatibility alias for Vc0 */\r
+typedef pciePlconfVcCrQCReg_t pciePlconfVc0CrQCReg_t;\r
+\r
/**\r
* @ingroup pcielld_reg_cfg_pl_structures\r
* @brief Specification of the PHY Status Register (Sticky)\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_PHY_STS_R\r
+ * On rev 2 hw, this corresponds to PHY_STATUS_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [ro] PHY Status\r
*\r
* On rev 1 hw, this corresponds to PHY_STS\r
+ * On rev 2 hw, this corresponds to PHY_STATUS\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_PHY_CTRL_R\r
+ * On rev 2 hw, this corresponds to PHY_CONTROL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] PHY Control\r
*\r
* On rev 1 hw, this corresponds to PHY_CTRL\r
+ * On rev 2 hw, this corresponds to PHY_CONTROL\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_ADDRESS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_ADDR_OFF\r
*\r
* This register may be used only for root complex modes.\r
*\r
* @brief [rw] MSI CTRL ADDRESS\r
*\r
* On rev 1 hw, this corresponds to MSI_CTRL_ADDRESS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_ADDR\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_UPPER_ADDR_OFF\r
*\r
* This register may be used only for root complex modes.\r
*\r
* @brief [rw] MSI CTRL UPPER ADDRESS\r
*\r
* On rev 1 hw, this corresponds to MSI_CTRL_UPPER_ADDRESS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_UPPER_ADDR\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_EN_OFF\r
*\r
* This register may be used only for root complex modes.\r
*\r
* @brief [rw] Status of an enabled bit (vectors) is set upon incoming MSI\r
*\r
* On rev 1 hw, this corresponds to MSI_CTRL_INT_ENABLE\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_EN\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_MASK_N\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_MASK_OFF\r
*\r
* This register may be used only for root complex modes.\r
*\r
* @brief [rw] Status of a masked bit (vector) triggers no IRQ to MPU when set\r
*\r
* On rev 1 hw, this corresponds to MSI_CTRL_INT_MASK\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_MASK\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_STATUS_N\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_STATUS_OFF\r
*\r
* This register may be used only for root complex modes.\r
*\r
* @brief [rw] Status of an enabled bit (vectors) is set upon incoming MSI\r
*\r
* On rev 1 hw, this corresponds to MSI_CTRL_INT_STATUS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_STATUS\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_GPIO\r
+ * On rev 2 hw, this corresponds to MSI_GPIO_IO_OFF\r
*\r
* This register may be used only for root complex modes.\r
*\r
* @brief [rw] MSI CTRL GPIO\r
*\r
* On rev 1 hw, this corresponds to MSI_CTRL_GPIO\r
+ * On rev 2 hw, this corresponds to MSI_GPIO_REG\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_PIPE_LOOPBACK\r
+ * On rev 2 hw, this corresponds to PIPE_LOOPBACK_CONTROL_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] PIPE Loopback Enable\r
*\r
* On rev 1 hw, this corresponds to LOOPBACK_EN\r
+ * On rev 2 hw, this corresponds to PIPE_LOOPBACK\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_DBI_RO_WR_EN\r
+ * On rev 2 hw, this corresponds to MISC_CONTROL_1_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* </table>\r
*\r
* On rev 1 hw, this corresponds to CX_DBI_RO_WR_EN\r
+ * On rev 2 hw, this corresponds to DBI_RO_WR_EN\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t cxDbiRoWrEn;\r
+ /**\r
+ * @brief [rw] Default target a received IO or MEM request with UR/CA/CRS\r
+ *\r
+ * 0: The controller drops all incoming I/O or MEM requests [after\r
+ * corresponding error reporting] A completion with UR status will be\r
+ * generated for non-posted requests -\r
+ * 1: The controller forwards all incoming I/O or MEM requests with\r
+ * UR/CA/CRS status to your application Default value is\r
+ * DEFAULT_TARGET configuration parameter Note: This register field\r
+ * is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to DEFAULT_TARGET\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t defaultTarget;\r
+ /**\r
+ * @brief [rw] UR_CA_MASK_4_TRGT1\r
+ *\r
+ * This field only applies to request TLPs [with UR filtering status] that\r
+ * you have chosen to forward to the application [when you set\r
+ * DEFAULT_TARGET in this register] -\r
+ *\r
+ * '1' the core suppresses error logging, Error Message generation, and\r
+ * CPL generation [for non-posted requests] - You should set this if you\r
+ * have set the Default Target port logic register to '1' Default is\r
+ * CX_MASK_UR_CA_4_TRGT1 configuration parameter\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UR_CA_MASK_4_TRGT1\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t urCaMask4Trgt1;\r
+ /**\r
+ * @brief [rw] Enables Simplified Replay Timer [Gen4]\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to SIMPLIFIED_REPLAY_TIMER\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t simpReplayTimer;\r
+ /**\r
+ * @brief [rw] When ARI is enabled, enables use of the device ID\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ARI_DEVICE_NUMBER\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t ariDevNumber;\r
} pciePlconfDbiRoWrEnReg_t;\r
/* @} */\r
\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_AXI_SLV_ERR_RESP\r
+ * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_DEFAULT_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] Global Slave Error Response Mapping\r
*\r
* On rev 1 hw, this corresponds to SLAVE_ERR_MAP\r
+ * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_GLOBAL\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] DIF Slave Error Response Mapping\r
*\r
* On rev 1 hw, this corresponds to DBI_ERR_MAP\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] Vendor ID Non-existent Slave Error Response Mapping\r
*\r
* On rev 1 hw, this corresponds to NO_VID_ERR_MAP\r
+ * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_VENDORID\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] Graceful Reset and Link Timeout Slave Error Response Mapping\r
*\r
* On rev 1 hw, this corresponds to RESET_TIMEOUT_ERR_MAP\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t resetTimeoutErrMap;\r
+ /**\r
+ * @brief [rw] CRS Slave Error Response Mapping\r
+ *\r
+ * CRS Slave Error Response Mapping Determines the AXI slave\r
+ * response for CRS completions AHB: - always returns OKAY AXI: -\r
+ * 00: OKAY\r
+ * 01: OKAY with all FFFF_FFFF data for all CRS completions\r
+ * 10: OKAY with FFFF_0001 data for CRS completions to vendor ID\r
+ * read requests, OKAY with FFFF_FFFF data for all other CRS\r
+ * completions\r
+ * 11: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field\r
+ * determines the PCIe-to-AXI Slave error response mapping]\r
+ *\r
+ * This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_CRS\r
+ *\r
+ * Field size: 2 bit\r
+ */\r
+ uint8_t errorResponseCrs;\r
+ /**\r
+ * @brief [rw] AXI Slave Response Error Map\r
+ *\r
+ * AXI Slave Response Error Map Allows you to selectively map the\r
+ * errors received from the PCIe completion [for non-posted requests]\r
+ * to the AXI slave responses, slv_rresp or slv_bresp The\r
+ * recommended setting is SLVERR CRS is always mapped to OKAY -\r
+ * [bit 0] 0: UR [unsupported request] -> DECERR\r
+ * 1: UR [unsupported request] -> SLVERR\r
+ * [bit 1] 0: CRS [configuration retry status] -> DECERR\r
+ * 1: CRS [configuration retry status] -> SLVERR\r
+ * [bit 2] 0: CA [completer abort] -> DECERR\r
+ * 1: CA [completer abort] -> SLVERR\r
+ * [bit 3]: Reserved\r
+ * [bit 4]: Reserved\r
+ * [bit 5]: 0: Completion Timeout -> DECERR\r
+ * 1: Completion Timeout -> SLVERR\r
+ * The AXI bridge internally drops\r
+ * [processes internally but not passed to your application] a\r
+ * completion that has been marked by the Rx filter as UC or MLF, and\r
+ * does not pass its status directly down to the slave interface It waits\r
+ * for a timeout and then signals "Completion Timeout" to the slave\r
+ * interface The controller sets the AXI slave read databus to 0xFFFF\r
+ * for all error responses\r
+ *\r
+ * Note: This register field is sticky\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_MAP\r
+ *\r
+ * Field size: 6 bits\r
+ */\r
+ uint8_t errorResponseMap;\r
} pciePlconfAxiSlvErrRespReg_t;\r
/* @} */\r
\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_AXI_SLV_TIMEOUT\r
+ * On rev 2 hw, this corresponds to AMBA_LINK_TIMEOUT_OFF\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_INDEX\r
+ * On rev 2 hw: the index selection emulated in SW (all windows are available in HW all the time)\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* </table>\r
*\r
* On rev 1 hw, this corresponds to REGION_DIRECTION\r
+ * On rev 2 hw, this is virtual sw register to demux 16 inbound/outbound regions\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] Region Index\r
*\r
* On rev 1 hw, this corresponds to REGION_INDEX\r
+ * On rev 2 hw, this is virtual sw register to demux 16 inbound/outbound regions\r
*\r
* Outbound region, from 0 to 15.\r
- * Inbound region, from 0 to 3.\r
+ * Inbound region, from 0 to 3 (rev 1) or 0 to 15 (rev 2)\r
*\r
* Field size: 4 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_1\r
+ * On rev 2 hw, this corresponds to IATU_REGION_CTRL_1_OFF_OUTBOUND and\r
+ * IATU_REGION_CTRL_1_OFF_INBOUND\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] type\r
*\r
* On rev 1 hw, this corresponds to TYPE\r
+ * On rev 2 hw, this corresponds to TYPE\r
*\r
* Outbound: TYPE applied to outgoing TLP with matching addess\r
* Inbound: TYPE-match criteria\r
*\r
- * Field size: 4 bits\r
+ * Field size: 5 bits\r
*/\r
uint8_t type;\r
/**\r
* @brief [rw] TC\r
*\r
* On rev 1 hw, this corresponds to TC\r
+ * On rev 2 hw, this corresponds to TC\r
*\r
* Outbound: TC applied to outgoing TLP with matching addess\r
* Inbound: TC-match criteria (if TC_match_enable=1)\r
*\r
- * Field size: 4 bits\r
+ * Field size: 3 bits\r
*/\r
uint8_t tc;\r
/**\r
* @brief [rw] TD\r
*\r
* On rev 1 hw, this corresponds to TD\r
+ * On rev 2 hw, this corresponds to TD\r
*\r
* Outbound: TD applied to outgoing TLP with matching addess\r
* Inbound: TD-match criteria (if TD_match_enable=1)\r
* @brief [rw] ATTR\r
*\r
* On rev 1 hw, this corresponds to ATTR\r
+ * On rev 2 hw, this corresponds to ATTR\r
*\r
* Outbound: ATTR applied to outgoing TLP with matching addess\r
* Inbound: ATTR-match criteria (if ATTR_match_enable=1)\r
* @brief [rw] AT\r
*\r
* On rev 1 hw, this corresponds to AT\r
+ * On rev 2 hw, unsupported\r
*\r
* Outbound: AT applied to outgoing TLP with matching addess\r
* Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)\r
* Field size: 2 bits\r
*/\r
uint8_t at;\r
+ /**\r
+ * @brief [rw] Increase the maximum ATU Region size\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INCREASE_REGION_SIZE\r
+ *\r
+ * Outbound: F.N; applied to outgoing TLP (RID) with RW 0x0 matching addess\r
+ * Inbound: F.N.-match criteria for incoming TLP\r
+ * (if Function_Number_match_enable=1)\r
+ *\r
+ * Field size: rev 1: 5 bits; rev 2: 3 bits\r
+ */\r
+ uint8_t increaseRegionSize;\r
/**\r
* @brief [rw] function number\r
*\r
* On rev 1 hw, this corresponds to FUNCTION_NUMBER\r
+ * On rev 2 hw, this corresponds to CTRL_1_FUNC_NUM\r
*\r
* Outbound: F.N; applied to outgoing TLP (RID) with RW 0x0 matching addess\r
* Inbound: F.N.-match criteria for incoming TLP\r
* (if Function_Number_match_enable=1)\r
*\r
- * Field size: 5 bits\r
+ * Field size: rev 1: 5 bits; rev 2: 3 bits\r
*/\r
uint8_t functionNumber;\r
} pciePlconfIatuRegCtrl1Reg_t;\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_2\r
+ * On rev 2 hw, this corresponds to IATU_REGION_CTRL_2_OFF_OUTBOUND and\r
+ * IATU_REGION_CTRL_2_OFF_INBOUND\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] MESSAGECODE\r
*\r
* On rev 1 hw, this corresponds to MESSAGECODE\r
+ * On rev 2 hw, this corresponds to MSG_CODE\r
*\r
* Outbound: MessageCode applied to outgoing message RW 0x0 TLP with\r
* matching addess\r
* @brief [rw] BAR_NUMBER\r
*\r
* On rev 1 hw, this corresponds to BAR_NUMBER\r
+ * On rev 2 hw, this corresponds to incoming BAR_NUM (not used for outgoing)\r
*\r
* BAR number for mayching with incoming MEM, I/O TLP RW 0x0\r
* (if Match_Mode = 1)\r
* Field size: 3 bits\r
*/\r
uint8_t barNumber;\r
+ /**\r
+ * @brief [rw] TAG\r
+ *\r
+ * The substituted TAG field [byte 6] in the outgoing TLP header\r
+ * when TAG_SUBSTITUTE_EN is set\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to TAG for outbound only\r
+ *\r
+ * Field size: 8 bits\r
+ */\r
+ uint8_t tag;\r
+ /**\r
+ * @brief [rw] \r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MSG_TYPE_MATCH_MODE (inbound)\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t msgTypeMatchMode;\r
/**\r
* @brief [rw] Enable TC match criteria on inbound TLP\r
*\r
* On rev 1 hw, this corresponds to TC_MATCH_ENABLE\r
+ * On rev 2 hw, this corresponds to TC_MATCH_EN (inbound)\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] Enable TD match criteria on inbound TLP\r
*\r
* On rev 1 hw, this corresponds to TD_MATCH_ENABLE\r
+ * On rev 2 hw, this corresponds to TD_MATCH_EN (inbound)\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] Enable ATTR match criteria on inbound TLP\r
*\r
* On rev 1 hw, this corresponds to ATTR_MATCH_ENABLE\r
+ * On rev 2 hw, this corresponds to ATTR_MATCH_EN (inbound)\r
*\r
* Field size: 1 bit\r
*/\r
* @brief [rw] Enable AT match criteria on inbound TLP\r
*\r
* On rev 1 hw, this corresponds to AT_MATCH_ENABLE\r
+ * On rev 2 hw, unsupported\r
*\r
* ATS NOT SUPPORTED: DO NOT USE\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t atMatchEnable;\r
+ /**\r
+ * @brief [rw] TAG Substitute Enable\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to TAG_SUBSTITUTE_EN\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t tagSubstEn;\r
/**\r
* @brief [rw] function number match enable\r
*\r
* On rev 1 hw, this corresponds to FUNCTION_NUMBER_MATCH_ENABLE\r
+ * On rev 2 hw, this corresponds to FUNC_BYPASS(outbound) or FUNC_NUM_MATCH_EN (inbound)\r
*\r
* Outbound: Function Number Translation Bypass\r
* Inbound: Enable Function Number match criteria\r
* @brief [rw] VIRTUAL FUNCTIONS NOT IMPLEMENTED\r
*\r
* On rev 1 hw, this corresponds to VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE\r
+ * On rev 2 hw, unsupported\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t virtualFunctionNumberMatchEnable;\r
+ /**\r
+ * @brief [rw] Serialize Non-Posted Requests\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to SNP (outbound)\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t SNP;\r
/**\r
* @brief [rw] Enable MessageCode match criteria on inbound TLP\r
*\r
* On rev 1 hw, this corresponds to MESSAGE_CODE_MATCH_ENABLE\r
+ * On rev 2 hw, this corresponds to MSG_CODE_MATCH_EN(inbound)\r
*\r
* Field size: 1 bit\r
*/\r
uint8_t messageCodeMatchEnable;\r
+ /**\r
+ * @brief [rw] Inhibit TLP Payload Data for TLP's in Matched Region\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to INHIBIT_PAYLOAD\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t inhibitPayload;\r
+ /**\r
+ * @brief [rw] Header Substitute Enable (outbound)\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to HEADER_SUBSTITUTE_EN (outbound)\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t headerSubstEn;\r
+ /**\r
+ * @brief [rw] Single Address Location Translate Enable (inbound)\r
+ *\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to SINGLE_ADDR_LOC_TRANS_EN (inbound)\r
+ *\r
+ * Field size: 1 bit\r
+ */\r
+ uint8_t singleAddrLocTransEn;\r
/**\r
* @brief [rw] Override HW-generated completion status when responding inbound TLP\r
*\r
* On rev 1 hw, this corresponds to RESPONSE_CODE\r
+ * On rev 2 hw, this corresponds to RESPONSE_CODE (inbound)\r
*\r
* <table>\r
* <tr><th>Value</th><th>description</th></tr>\r
* @brief [rw] fuzzy type match mode\r
*\r
* On rev 1 hw, this corresponds to FUZZY_TYPE_MATCH_MODE\r
+ * On rev 2 hw, this corresponds to FUZZY_TYPE_MATCH_CODE (inbound)\r
*\r
* Outbound: DMA Bypass Mode RW 0x0\r
* Inbound: Relax matching on inbound TLP TYPE:\r
* @brief [rw] Enable the shifting of CFG CID (BDF),\r
*\r
* On rev 1 hw, this corresponds to CFG_SHIFT_MODE\r
+ * On rev 2 hw, this corresponds to CFG_SHIFT_MODE\r
*\r
* Incoming and outgoing TLP;\r
* CFG get mapped to a contiguous 2**28 = * 256 MByte address space\r
* @brief [rw] Redefine match criteria as outside the defined range\r
*\r
* On rev 1 hw, this corresponds to INVERT_MODE\r
+ * On rev 2 hw, this corresponds to INVERT_MODE\r
*\r
* (instead of inside)\r
*\r
* @brief [rw] Sets inbound TLP match mode\r
*\r
* On rev 1 hw, this corresponds to MATCH_MODE\r
+ * On rev 2 hw, this corresponds to MATCH_MODE (inbound)\r
*\r
* Depending on TYPE\r
* 0x0: MEM,I/O: Address Match: as per region base & limit registers;\r
* @brief [rw] Enable AT for this region\r
*\r
* On rev 1 hw, this corresponds to REGION_ENABLE\r
+ * On rev 2 hw, this corresponds to REGION_EN\r
*\r
* Field size: 1 bit\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LOWER_BASE\r
+ * On rev 2 hw, this corresponds to IATU_LWR_BASE_ADDR_OFF_OUTBOUND and\r
+ * IATU_LWR_BASE_ADDR_OFF_INBOUND\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] Lower Base Address (read-write part)\r
*\r
* On rev 1 hw, this corresponds to IATU_REG_LOWER_BASE\r
+ * On rev 2 hw, this corresponds to LWR_BASE_RW\r
*\r
- * Note: @ref iatuRegLowerBase is >> 12 version of address, with 0 LSBs cut off.\r
+ * Note: On rev 1 @ref iatuRegLowerBase is >> 12 version of address, with 0 LSBs cut off\r
+ * Note: On rev 2 @ref iatuRegLowerBase is >> 16 version of address, with 0 LSBs cut off\r
*\r
- * Field size: 20 bits\r
+ * Field size: 20 bits (rev 1) or 16 bits (rev 2)\r
*/\r
uint32_t iatuRegLowerBase;\r
/**\r
* @brief [ro] Lower Base Address (read-only part)\r
*\r
* On rev 1 hw, this corresponds to ZERO\r
+ * On rev 2 hw, this corresponds to LWR_BASE_HW\r
*\r
- * This portion is always 0 to enforce 4K alignment.\r
+ * This portion is always 0 to enforce 4K alignment (rev 1) or 64K (rev 2)\r
*\r
- * Field size: 12 bits\r
+ * Field size: 12 bits (rev 1) or 16 bits (rev 2)\r
*/\r
uint16_t zero;\r
} pciePlconfIatuRegLowerBaseReg_t;\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_UPPER_BASE\r
+ * On rev 2 hw, this corresponds to IATU_UPPER_BASE_ADDR_OFF_OUTBOUND and\r
+ * IATU_LIMIT_ADDR_OFF_INBOUND\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] Upper Base Address\r
*\r
* On rev 1 hw, this corresponds to IATU_REG_UPPER_BASE\r
+ * On rev 2 hw, this corresponds to UPPER_BASE_RW\r
*\r
* Field size: 32 bits\r
*/\r
* @brief [ro] Region limit address\r
*\r
* On rev 1 hw, this corresponds to IATU_REG_LIMIT\r
+ * On rev 2 hw, this corresponds to LIMIT_ADDR_RW\r
*\r
- * Field size: 20 bits\r
+ * Note: On rev 1 @ref iatuRegLimit is >> 12 version of address, with 0 LSBs cut off\r
+ * Note: On rev 2 @ref iatuRegLimit is >> 16 version of address, with 0 LSBs cut off\r
+ *\r
+ * Field size: 20 bits (rev 1) or 16 bits (rev 2)\r
*/\r
uint32_t iatuRegLimit;\r
/**\r
* @brief [ro] Region limit address (mask)\r
*\r
* On rev 1 hw, this corresponds to ONES\r
+ * On rev 2 hw, this corresponds to LIMIT_ADDR_HW\r
*\r
- * This portion is always 0xfff to enforce 4K portion of mask.\r
+ * This portion is always all 1s to enforce 4K alignment (rev 1) or 64K (rev 2)\r
*\r
- * Field size: 12 bits\r
+ * Field size: 12 bits (rev 1) or 16 bits (rev 2)\r
*/\r
uint16_t ones;\r
} pciePlconfIatuRegLimitReg_t;\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LOWER_TARGET\r
+ * On rev 2 hw, this corresponds to IATU_LWR_TARGET_ADDR_OFF_OUTBOUND and\r
+ * IATU_LWR_TARGET_ADDR_OFF_INBOUND\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] Lower Target Address (read-write part)\r
*\r
* On rev 1 hw, this corresponds to IATU_REG_LOWER_TARGET\r
+ * On rev 2 hw, this corresponds to LWR_TARGET_RW_OUTBOUND and LWR_TARGET_RW\r
*\r
- * Note: @ref iatuRegLowerTarget is >> 12 version of address, with 0 LSBs cut off.\r
+ * Note: On rev 1 @ref iatuRegLowerTarget is >> 12 version of address, with 0 LSBs cut off\r
+ * Note: On rev 2 @ref iatuRegLowerTarget is >> 16 version of address, with 0 LSBs cut off\r
*\r
- * Field size: 20 bits\r
+ * Field size: 20 bits (rev 1) or 16 bits (rev 2)\r
*/\r
uint32_t iatuRegLowerTarget;\r
/**\r
* @brief [ro] Lower Target Address (read-only part)\r
*\r
* On rev 1 hw, this corresponds to ZERO\r
+ * On rev 2 hw, this corresponds to LWR_TARGET_RW_OUTBOUND (low 16 bits) and\r
+ * LWR_TARGET_HW\r
*\r
- * This portion is always 0 to enforce 4K alignment.\r
+ * This portion is always 0 to enforce 4K alignment (rev 1) or 64K (rev 2)\r
*\r
- * Field size: 12 bits\r
+ * Field size: 12 bits (rev 1) or 16 bits (rev 2)\r
*/\r
uint16_t zero;\r
} pciePlconfIatuRegLowerTargetReg_t;\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_UPPER_TARGET\r
+ * On rev 2 hw, this corresponds to IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND and\r
+ * IATU_UPPER_TARGET_ADDR_OFF_INBOUND\r
*\r
* This register may be used for both endpoint and root complex modes.\r
*\r
* @brief [rw] Upper Target Address\r
*\r
* On rev 1 hw, this corresponds to ATU_REG_UPPER_TARGET\r
+ * On rev 2 hw, this corresponds to UPPER_TARGET_RW\r
*\r
* Field size: 32 bits\r
*/\r
*\r
* On rev 0 hw: unavailable\r
* On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_3\r
+ * On rev 2 hw: unavailable\r
*\r
* VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED\r
*\r
pcieIoBaseReg_t *ioBase; /**< @brief IO TLP base*/\r
pcieTlpCfgReg_t *tlpCfg; /**< @brief TLP Config*/\r
pcieRstCmdReg_t *rstCmd; /**< @brief Reset Command*/\r
+ pciePtmCfgReg_t *ptmCfg; /**< @brief PTM Config Command*/\r
pciePmCmdReg_t *pmCmd; /**< @brief Power Management Command*/\r
pciePmCfgReg_t *pmCfg; /**< @brief Power Management Config*/\r
pcieActStatusReg_t *actStatus; /**< @brief Activity Status */\r
pciePmRstIrqStatusReg_t *pmRstIrqStatus; /**< @brief Power Management and Reset Interrupt Enabled Status Register*/\r
pciePmRstIrqEnableSetReg_t *pmRstIrqEnableSet; /**< @brief Power Management and Reset Interrupt Enable Set Register*/\r
pciePmRstIrqEnableClrReg_t *pmRstIrqEnableClr; /**< @brief Power Management and Reset Interrupt Enable Clear Register*/\r
+ pciePtmIrqStatusRawReg_t *ptmIrqStatusRaw; /**< @brief Precision Time Measurement Raw Interrupt Status Register*/\r
+ pciePtmIrqStatusReg_t *ptmIrqStatus; /**< @brief Precision Time Measurement Interrupt Enabled Status Register*/\r
+ pciePtmIrqEnableSetReg_t *ptmIrqEnableSet; /**< @brief Precision Time Measurement Interrupt Enable Set Register*/\r
+ pciePtmIrqEnableClrReg_t *ptmIrqEnableClr; /**< @brief Precision Time Measurement Interrupt Enable Clear Register*/\r
pcieObOffsetLoReg_t *obOffsetLo[8]; /**< @brief Outbound Translation region offset Low*/\r
pcieObOffsetHiReg_t *obOffsetHi[8]; /**< @brief Outbound Translation region offset High*/\r
pcieIbBarReg_t *ibBar[4]; /**< @brief Inbound Translation BAR*/\r
pcieMsiLo32Reg_t *msiLo32; /**< @brief MSI Lower 32 bits */\r
pcieMsiUp32Reg_t *msiUp32; /**< @brief MSI Upper 32 bits */\r
pcieMsiDataReg_t *msiData; /**< @brief MSI Data */\r
+ pcieMsiCapOff10HReg_t *msiCapOff10H; /**< @brief MSI Cap Off 10H */\r
+ pcieMsiCapOff14HReg_t *msiCapOff14H; /**< @brief MSI Cap Off 14H */\r
\r
/*Capabilities Registers*/\r
pciePciesCapReg_t *pciesCap; /**< @brief PCI Express Capabilities Register*/\r
pciePlconfVc0PrQCReg_t *plconfVc0PrQC; /**< @brief PCIECTRL_PL_VC0_PR_Q_C*/\r
pciePlconfVc0NprQCReg_t *plconfVc0NprQC; /**< @brief PCIECTRL_PL_VC0_NPR_Q_C*/\r
pciePlconfVc0CrQCReg_t *plconfVc0CrQC; /**< @brief PCIECTRL_PL_VC0_CR_Q_C*/\r
+ pciePlconfVcPrQCReg_t *plconfVcPrQC[3]; /**< @brief for VC1..VC3 */\r
+ pciePlconfVcNprQCReg_t *plconfVcNprQC[3]; /**< @brief for VC1..VC3 */\r
+ pciePlconfVcCrQCReg_t *plconfVcCrQC[3]; /**< @brief for VC1..VC3 */\r
/* note: plconfWidthSpeedCtlReg_t is mapped to gen2 above */\r
pciePlconfPhyStsRReg_t *plconfPhyStsR; /**< @brief PCIECTRL_PL_PHY_STS_R*/\r
pciePlconfPhyCtrlRReg_t *plconfPhyCtrlR; /**< @brief PCIECTRL_PL_PHY_CTRL_R*/\r
* Base address of the "data" area (remote device memory) \r
*/\r
void *dataBase;\r
+ /**\r
+ * Reserved part of real data area due to memory mapping. For example\r
+ * on some M4s the PCIe address is at 0x20000000 which is illegal for\r
+ * M4. Thus its moved to 0x24000000. In this case dataReserved\r
+ * is 0x04000000.\r
+ */\r
+ uint32_t dataReserved;\r
/** \r
* Revision-dependant device params. Look for Pciev#_DevParams in\r
* src/v#/pcie.h. Not all HW will have these (put NULL).\r
{\r
/*! Function to set PCIE to EP or RC for one device */\r
pcieRet_e (*setInterfaceMode) (Pcie_Handle handle, pcieMode_e mode);\r
+ /*! Function to get the PCIE data area reserved size */\r
+ pcieRet_e (*getMemSpaceReserved) (Pcie_Handle handle, uint32_t *resSize);\r
/*! Function to get the PCIE data area base address & size */\r
pcieRet_e (*getMemSpaceRange) (Pcie_Handle handle, void **base,\r
uint32_t *size);\r
pcieMode_e mode /**< [in] PCIE Mode */\r
);\r
\r
+/**\r
+ * @ingroup pcielld_api_functions\r
+ * @brief Pcie_getMemSpaceReserved returns amount of reserved space \r
+ * between beginning of hardware's data area and the base returned\r
+ * by @ref Pcie_getMemSpaceRange. \r
+ *\r
+ * @retval pcieRet_e status\r
+ */\r
+pcieRet_e Pcie_getMemSpaceReserved\r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ uint32_t *resSize /**< [out] Total size of the memory space [bytes] */\r
+);\r
+\r
+\r
/**\r
* @ingroup pcielld_api_functions\r
* @brief Pcie_getMemSpaceRange Returns the PCIe Internal Address\r