NOTICE OF RELOCATION

[keystone-rtos/pcie-lld.git] / pcie.h

diff --git a/pcie.h b/pcie.h
index 4d8888ad5602a66d85a4a1489965c5d980434941..0cb2cd808be6b93a74cf03a65bcd2e7d9f8cbe33 100644 (file)
--- a/pcie.h
+++ b/pcie.h
@@ -1,6 +1,6 @@
 /*\r
  *\r
- * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/\r
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/\r
  *\r
  *\r
  *  Redistribution and use in source and binary forms, with or without\r
@@ -241,7 +241,9 @@ typedef enum
   pcie_RET_INV_DEVICENUM, /**< @ref Pcie_open deviceNum invalid */\r
   pcie_RET_INV_INITCFG,   /**< Invalid Pcie_InitCfg */\r
   pcie_RET_INV_FXNPTR,    /**< Top level API doesn't have dev specific fxn */\r
-  pcie_RET_NO_INIT        /**< Forgot to call Pcie_init() ? */\r
+  pcie_RET_NO_INIT,       /**< Forgot to call Pcie_init() ? */\r
+  pcie_RET_UNSUPPORTED,   /**< Unsupported API */\r
+  pcie_RET_RANGECHK       /**< Rangecheck failed */\r
 } pcieRet_e;\r
 /* @} */\r
 \r
@@ -407,11 +409,12 @@ typedef enum pcieAtuRegionMatchMode
  * This Register contains the major and minor revisions\r
  * for the PCIe module.\r
  *\r
- * This register is only used on rev 0 hw, but is very similar to rev 1's\r
+ * This register is only used on rev 0/2 hw, but is very similar to rev 1's\r
  * @ref pcieTiConfRevisionReg_t\r
  *\r
  * On rev 0 hw, this corresponds to PID\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PID\r
  *\r
  * @{\r
  */\r
@@ -422,6 +425,7 @@ typedef struct pciePidReg_s {
    *\r
    * On rev 0 hw, this corresponds to SCHEME\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -433,15 +437,29 @@ typedef struct pciePidReg_s {
    *\r
    * On rev 0 hw, this corresponds to FUNC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 12 bits\r
    */\r
   uint16_t func;\r
+  /**\r
+   * @brief [ro] Module ID of the Peripheral\r
+   *\r
+   * 0x6810 is PCIe\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MODID\r
+   *\r
+   * Field size: 16 bits\r
+   */\r
+  uint16_t modId;\r
   /**\r
    * @brief [ro] RTL Version\r
    *\r
    * On rev 0 hw, this corresponds to RTL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RTL\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -451,6 +469,7 @@ typedef struct pciePidReg_s {
    *\r
    * On rev 0 hw, this corresponds to MAJOR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MAJOR\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -460,6 +479,7 @@ typedef struct pciePidReg_s {
    *\r
    * On rev 0 hw, this corresponds to CUSTOM\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CUSTOM\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -469,6 +489,7 @@ typedef struct pciePidReg_s {
    *\r
    * On rev 0 hw, this corresponds to MINOR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MINOR\r
    *\r
    * Field size: 6 bits\r
    */\r
@@ -485,16 +506,38 @@ typedef struct pciePidReg_s {
  *\r
  * On rev 0 hw, this corresponds to CMD_STATUS\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CMD_STATUS\r
  *\r
  * @{\r
  */\r
 typedef struct pcieCmdStatusReg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Set to enable manual reversal for RX lanes.\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_LANE_FLIP_EN\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t rxLaneFlipEn;\r
+  /**\r
+   * @brief [rw] Set to enable manual reversal for TX lanes.\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to TX_LANE_FLIP_EN\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t txLaneFlipEn;\r
   /**\r
    * @brief [rw] Set to enable writing to BAR mask registers that are overlaid on BAR registers.\r
    *\r
    * On rev 0 hw, this corresponds to DBI_CS2\r
    * On rev 1 hw, unsupported (but see @ref pciePlconfDbiRoWrEnReg_t::cxDbiRoWrEn)\r
+   * On rev 2 hw, this corresponds to DBI_CS2\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -509,6 +552,7 @@ typedef struct pcieCmdStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to APP_RETRY_EN\r
    * On rev 1 hw, unsupported (but see @ref pcieTiConfDeviceCmdReg_t::appReqRetryEn)\r
+   * On rev 2 hw, this corresponds to APP_RETRY_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -522,6 +566,7 @@ typedef struct pcieCmdStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to POSTED_WR_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -534,6 +579,7 @@ typedef struct pcieCmdStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to IB_XLT_EN\r
    * On rev 1 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
+   * On rev 2 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -546,6 +592,7 @@ typedef struct pcieCmdStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to OB_XLT_EN\r
    * On rev 1 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
+   * On rev 2 hw, unsupported (but see @ref pciePlconfIatuIndexReg_t)\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -558,6 +605,7 @@ typedef struct pcieCmdStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to LTSSM_EN\r
    * On rev 1 hw, unsupported (but see @ref pcieTiConfDeviceCmdReg_t::ltssmEn)\r
+   * On rev 2 hw, this corresponds to LTSSM_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -572,6 +620,7 @@ typedef struct pcieCmdStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to CFG_SETUP\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -585,6 +634,7 @@ typedef struct pcieCfgTransReg_s {
    *\r
    * On rev 0 hw, this corresponds to CFG_TYPE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -594,6 +644,7 @@ typedef struct pcieCfgTransReg_s {
    *\r
    * On rev 0 hw, this corresponds to CFG_BUS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -603,6 +654,7 @@ typedef struct pcieCfgTransReg_s {
    *\r
    * On rev 0 hw, this corresponds to CFG_DEVICE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 5 bit\r
    */\r
@@ -612,6 +664,7 @@ typedef struct pcieCfgTransReg_s {
    *\r
    * On rev 0 hw, this corresponds to CFG_FUNC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -626,6 +679,7 @@ typedef struct pcieCfgTransReg_s {
  *\r
  * On rev 0 hw, this corresponds to IOBASE\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -636,6 +690,7 @@ typedef struct pcieIoBaseReg_s {
    *\r
    * On rev 0 hw, this corresponds to IOBASE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 20 bits\r
    *\r
@@ -650,6 +705,7 @@ typedef struct pcieIoBaseReg_s {
  *\r
  * On rev 0 hw, this corresponds to TLPCFG\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -660,6 +716,7 @@ typedef struct pcieTlpCfgReg_s {
    *\r
    * On rev 0 hw, this corresponds to RELAXED\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -669,6 +726,7 @@ typedef struct pcieTlpCfgReg_s {
    *\r
    * On rev 0 hw, this corresponds to NO_SNOOP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -683,6 +741,7 @@ typedef struct pcieTlpCfgReg_s {
  *\r
  * On rev 0 hw, this corresponds to RSTCMD\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to RSTCMD\r
  *\r
  * @{\r
  */\r
@@ -697,15 +756,31 @@ typedef struct pcieRstCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to FLUSH_N\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t flush;\r
+  /**\r
+   * @brief [ro] Bridge flush status\r
+   *\r
+   * Used to ensure no pending transactions prior to issuing warm reset.\r
+   * 0 = No transaction is pending.\r
+   * 1 = There are transactions pending.\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FLR_PF_ACTIVE\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t flrPfActive;\r
   /**\r
    * @brief [w1] Write 1 to initiate a downstream hot reset sequence on downstream.\r
    *\r
    * On rev 0 hw, this corresponds to INIT_RST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INIT_RST\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -713,12 +788,77 @@ typedef struct pcieRstCmdReg_s {
 } pcieRstCmdReg_t;\r
 /* @} */\r
 \r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the PTM Config register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTMCFG\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmCfgReg_s {\r
+  uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Select ptm_local_clk bit input to CPTS.\r
+   *\r
+   * 0 will select ptm_local_clk[0], \r
+   * 1 will select ptm_local_clk[1] ...\r
+   * 63 will select ptm_local_clk[63]\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_CLK_SEL\r
+   *\r
+   * Field size: 6 bit\r
+   */\r
+  uint8_t ptmClkSel;\r
+  /**\r
+   * @brief [ro] '1' indicates PTM context is valid-EP only\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_CONTEXT_VALID\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmContextValid;\r
+  /**\r
+   * @brief [w1] Write '1' to enable PTM transaction.EP only.\r
+   *\r
+   * EP will initiate one PTM transaction when this field is updated.\r
+   * Always reads '0'\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_MANUAL_UPDATE\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmManualUpdate;\r
+  /**\r
+   * @brief [rw] Write '1' to enable PTM auto-update-EP only\r
+   *\r
+   * EP will automatically initiate PTM transaction every 10ms\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_AUTO_UPDATE\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmAutoUpdate;\r
+} pciePtmCfgReg_t;\r
+/* @} */\r
+\r
 /**\r
  * @ingroup pcielld_reg_app_structures\r
  * @brief Specification of the Power Management Command Register\r
  *\r
  * On rev 0 hw, this corresponds to PMCMD\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMCMD\r
  *\r
  * @{\r
  */\r
@@ -734,6 +874,7 @@ typedef struct pciePmCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_XMT_TURNOFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_XMT_TURNOFF\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -748,6 +889,7 @@ typedef struct pciePmCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_XMT_PME\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_XMT_PME\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -762,6 +904,7 @@ typedef struct pciePmCmdReg_s {
  *\r
  * On rev 0 hw, this corresponds to PMCFG\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -777,6 +920,7 @@ typedef struct pciePmCfgReg_s {
    *\r
    * On rev 0 hw, this corresponds to ENTR_L23\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -790,6 +934,7 @@ typedef struct pciePmCfgReg_s {
  *\r
  * On rev 0 hw, this corresponds to ACT_STATUS\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -800,6 +945,7 @@ typedef struct pcieActStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to OB_NOT_EMPTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -809,6 +955,7 @@ typedef struct pcieActStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to IB_NOT_EMPTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -822,6 +969,7 @@ typedef struct pcieActStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to OB_SIZE\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -841,6 +989,7 @@ typedef struct pcieObSizeReg_s {
    *\r
    * On rev 0 hw, this corresponds to OB_SIZE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -854,6 +1003,7 @@ typedef struct pcieObSizeReg_s {
  *\r
  * On rev 0 hw, this corresponds to DIAG_CTRL\r
  * On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t)\r
+ * On rev 2 hw\r
  *\r
  * @{\r
  */\r
@@ -867,6 +1017,7 @@ typedef struct pcieDiagCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to INV_ECRC\r
    * On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t::invEcrc)\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -879,6 +1030,7 @@ typedef struct pcieDiagCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to INV_LCRC\r
    * On rev 1 hw, unsupported (but see @ref pcieTiConfDiagCtrlReg_t::invLcrc)\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -892,6 +1044,7 @@ typedef struct pcieDiagCtrlReg_s {
  *\r
  * On rev 0 hw, this corresponds to ENDIAN\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -910,6 +1063,7 @@ typedef struct pcieEndianReg_s {
    *\r
    * On rev 0 hw, this corresponds to ENDIAN_MODE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -923,6 +1077,7 @@ typedef struct pcieEndianReg_s {
  *\r
  * On rev 0 hw, this corresponds to PRIORITY\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -933,6 +1088,7 @@ typedef struct pciePriorityReg_s {
    *\r
    * On rev 0 hw, this corresponds to MST_PRIV\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -942,6 +1098,7 @@ typedef struct pciePriorityReg_s {
    *\r
    * On rev 0 hw, this corresponds to MST_PRIVID\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -952,6 +1109,7 @@ typedef struct pciePriorityReg_s {
    *\r
    * On rev 0 hw, this corresponds to MST_PRIORITY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -965,6 +1123,7 @@ typedef struct pciePriorityReg_s {
  *\r
  * On rev 0 hw, this corresponds to IRQ_EOI\r
  * On rev 1 hw, unsupported (but see @ref pcieTiConfIrqEoiReg_t)\r
+ * On rev 2 hw, this corresponds to IRQ_EOI\r
  *\r
  * @{\r
  */\r
@@ -978,6 +1137,7 @@ typedef struct pcieIrqEOIReg_s {
    *\r
    * On rev 0 hw, this corresponds to EOI\r
    * On rev 1 hw, unsupported (but see @ref pcieTiConfIrqEoiReg_t::lineNumber)\r
+   * On rev 2 hw, this corresponds to EOI\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -991,6 +1151,7 @@ typedef struct pcieIrqEOIReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI_IRQ\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MMR_IRQ\r
  *\r
  * @{\r
  */\r
@@ -1001,8 +1162,9 @@ typedef struct pcieMsiIrqReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI_IRQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MMR_IRQ\r
    *\r
-   * Field size: 32 bits\r
+   * Field size: 32 bits (rev 0) or 31 bits (rev 2)\r
    */\r
   uint32_t msiIrq;\r
 } pcieMsiIrqReg_t;\r
@@ -1014,6 +1176,7 @@ typedef struct pcieMsiIrqReg_s {
  *\r
  * On rev 0 hw, this corresponds to EP_IRQ_SET\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_SET\r
  *\r
  * @{\r
  */\r
@@ -1027,6 +1190,7 @@ typedef struct pcieEpIrqSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to EP_IRQ_SET\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LEGACY_IRQ_SET_0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1040,6 +1204,7 @@ typedef struct pcieEpIrqSetReg_s {
  *\r
  * On rev 0 hw, this corresponds to EP_IRQ_CLR\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_CLR\r
  *\r
  * @{\r
  */\r
@@ -1053,6 +1218,7 @@ typedef struct pcieEpIrqClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to EP_IRQ_CLR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LEGACY_IRQ_CLR_0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1066,6 +1232,7 @@ typedef struct pcieEpIrqClrReg_s {
  *\r
  * On rev 0 hw, this corresponds to EP_IRQ_STATUS\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_IRQ_STATUS\r
  *\r
  * @{\r
  */\r
@@ -1076,6 +1243,7 @@ typedef struct pcieEpIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to EP_IRQ_STATUS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LEGACY_IRQ_STATUS_0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1089,6 +1257,7 @@ typedef struct pcieEpIrqStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to GPR# where # = 0..3\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to GPR# where # = 0..3\r
  *\r
  * @{\r
  */\r
@@ -1099,6 +1268,7 @@ typedef struct pcieGenPurposeReg_s {
    *\r
    * On rev 0 hw, this corresponds to GENERIC# where # = 0..3\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to GENERIC# where # = 0..3\r
    *\r
    * Field size: 32 bit\r
    */\r
@@ -1112,6 +1282,7 @@ typedef struct pcieGenPurposeReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS_RAW where # = 0..7\r
  * On rev 1 hw, unsupported (but similar to @ref pciePlconfMsiCtrlIntStatusReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS_RAW where # = 0..7\r
  *\r
  * @{\r
  */\r
@@ -1124,6 +1295,7 @@ typedef struct pcieMsiIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS_RAW where # = 0..7\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS_RAW where # = 0..7\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -1138,6 +1310,7 @@ typedef struct pcieMsiIrqStatusRawReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS where # = 0..7\r
  * On rev 1 hw, unsupported (but similar to @ref pciePlconfMsiCtrlIntStatusReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS where # = 0..7\r
  *\r
  * @{\r
  */\r
@@ -1148,6 +1321,7 @@ typedef struct pcieMsiIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI#_IRQ_STATUS where # = 0..7\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MMR#_IRQ_STATUS where # = 0..7\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -1161,6 +1335,7 @@ typedef struct pcieMsiIrqStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_SET where # = 0..7\r
  * On rev 1 hw, unsupported (but similar to @ref pcieTiConfIrqEnableSetMsiReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_SET where # = 0..7\r
  *\r
  * @{\r
  */\r
@@ -1171,6 +1346,7 @@ typedef struct pcieMsiIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_SET where # = 0..7\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_SET where # = 0..7\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -1184,6 +1360,7 @@ typedef struct pcieMsiIrqEnableSetReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_CLR where # = 0..7\r
  * On rev 1 hw, unsupported (but similar to @ref pcieTiConfIrqEnableClrMsiReg_t)\r
+ * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_CLR where # = 0..7\r
  *\r
  * @{\r
  */\r
@@ -1194,6 +1371,7 @@ typedef struct pcieMsiIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI#_IRQ_ENABLE_CLR where # = 0..7\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MMR#_IRQ_ENABLE_CLR where # = 0..7\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -1207,6 +1385,7 @@ typedef struct pcieMsiIrqEnableClrReg_s {
  *\r
  * On rev 0 hw, this corresponds to LEGACY_#_IRQ_STATUS_RAW where # = A..D (0-3)\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_STATUS_RAW where # = A..D (0-3)\r
  *\r
  * @{\r
  */\r
@@ -1217,6 +1396,7 @@ typedef struct pcieLegacyIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_# where # = A..D\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INT_# where # = A..D\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1231,6 +1411,7 @@ typedef struct pcieLegacyIrqStatusRawReg_s {
  *\r
  * On rev 0 hw, this corresponds to LEGACY_#_IRQ_STATUS where # = A..D (0-3)\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_STATUS where # = A..D (0-3)\r
  *\r
  * @{\r
  */\r
@@ -1244,6 +1425,7 @@ typedef struct pcieLegacyIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_# where # = A..D\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INT_# where # = A..D\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1257,6 +1439,7 @@ typedef struct pcieLegacyIrqStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to LEGACY_#_IRQ_ENABLE_SET where # = A..D (0-3)\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_ENABLE_SET where # = A..D (0-3)\r
  *\r
  * @{\r
  */\r
@@ -1267,6 +1450,7 @@ typedef struct pcieLegacyIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_# where # = A..D\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INT_# where # = A..D\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1280,6 +1464,7 @@ typedef struct pcieLegacyIrqEnableSetReg_s {
  *\r
  * On rev 0 hw, this corresponds to LEGACY_#_IRQ_ENABLE_CLR where # = A..D (0-3)\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to LEGACY_#_IRQ_ENABLE_CLR where # = A..D (0-3)\r
  *\r
  * @{\r
  */\r
@@ -1290,6 +1475,7 @@ typedef struct pcieLegacyIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_# where # = A..D\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INT_# where # = A..D\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1303,6 +1489,7 @@ typedef struct pcieLegacyIrqEnableClrReg_s {
  *\r
  * On rev 0 hw, this corresponds to ERR_IRQ_STATUS_RAW\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_STATUS_RAW\r
  *\r
  * @{\r
  */\r
@@ -1313,6 +1500,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AER\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_AER_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1322,6 +1510,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AXI\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1331,6 +1520,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_CORR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_CORR_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1340,6 +1530,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_NONFATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_NONFATAL_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1349,6 +1540,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_FATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_FATAL_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1358,6 +1550,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_SYS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_SYS_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1371,6 +1564,7 @@ typedef struct pcieErrIrqStatusRawReg_s {
  *\r
  * On rev 0 hw, this corresponds to ERR_IRQ_STATUS\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_STATUS\r
  *\r
  * @{\r
  */\r
@@ -1381,6 +1575,7 @@ typedef struct pcieErrIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AER\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_AER\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1390,6 +1585,7 @@ typedef struct pcieErrIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AXI\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1399,6 +1595,7 @@ typedef struct pcieErrIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_CORR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_CORR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1408,6 +1605,7 @@ typedef struct pcieErrIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_NONFATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_NONFATAL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1417,6 +1615,7 @@ typedef struct pcieErrIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_FATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_FATAL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1426,6 +1625,7 @@ typedef struct pcieErrIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_SYS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_SYS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1439,6 +1639,7 @@ typedef struct pcieErrIrqStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to ERR_IRQ_ENABLE_SET\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_ENABLE_SET\r
  *\r
  * @{\r
  */\r
@@ -1449,6 +1650,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AER\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_AER\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1458,6 +1660,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AXI\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1467,6 +1670,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_CORR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_CORR_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1476,6 +1680,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_NONFATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_NONFATAL_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1485,6 +1690,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_FATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_FATAL_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1494,6 +1700,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_SYS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_SYS_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1507,6 +1714,7 @@ typedef struct pcieErrIrqEnableSetReg_s {
  *\r
  * On rev 0 hw, this corresponds to ERR_IRQ_ENABLE_CLR\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_IRQ_ENABLE_CLR\r
  *\r
  * @{\r
  */\r
@@ -1517,6 +1725,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AER\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_AER_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1526,6 +1735,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_AXI\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1535,6 +1745,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_CORR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_CORR_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1544,6 +1755,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_NONFATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_NONFATAL_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1553,6 +1765,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_FATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_FATAL_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1562,6 +1775,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_SYS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_SYS_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1575,6 +1789,7 @@ typedef struct pcieErrIrqEnableClrReg_s {
  *\r
  * On rev 0 hw, this corresponds to PMRST_IRQ_STATUS_RAW\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_STATUS_RAW\r
  *\r
  * @{\r
  */\r
@@ -1585,6 +1800,7 @@ typedef struct pciePmRstIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to LNK_RST_REQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LNK_RST_REQ_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1594,6 +1810,7 @@ typedef struct pciePmRstIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_PME\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_PME_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1603,6 +1820,7 @@ typedef struct pciePmRstIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TO_ACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TO_ACK_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1612,6 +1830,7 @@ typedef struct pciePmRstIrqStatusRawReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TURNOFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TURNOFF_RAW\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1625,6 +1844,7 @@ typedef struct pciePmRstIrqStatusRawReg_s {
  *\r
  * On rev 0 hw, this corresponds to PMRST_IRQ_STATUS\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_STATUS\r
  *\r
  * @{\r
  */\r
@@ -1635,6 +1855,7 @@ typedef struct pciePmRstIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to LNK_RST_REQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LNK_RST_REQ\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1644,6 +1865,7 @@ typedef struct pciePmRstIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_PME\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_PME\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1653,6 +1875,7 @@ typedef struct pciePmRstIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TO_ACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TO_ACK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1662,6 +1885,7 @@ typedef struct pciePmRstIrqStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TURNOFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TURNOFF\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1675,6 +1899,7 @@ typedef struct pciePmRstIrqStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to PMRST_ENABLE_SET\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_ENABLE_SET\r
  *\r
  * @{\r
  */\r
@@ -1685,6 +1910,7 @@ typedef struct pciePmRstIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to LNK_RST_REQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LNK_RST_REQ_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1694,6 +1920,7 @@ typedef struct pciePmRstIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_PME\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_PME_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1703,6 +1930,7 @@ typedef struct pciePmRstIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TO_ACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TO_ACK_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1712,6 +1940,7 @@ typedef struct pciePmRstIrqEnableSetReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TURNOFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TURNOFF_EN_SET\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1725,6 +1954,7 @@ typedef struct pciePmRstIrqEnableSetReg_s {
  *\r
  * On rev 0 hw, this corresponds to PMRST_ENABLE_CLR\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PMRST_IRQ_ENABLE_CLR\r
  *\r
  * @{\r
  */\r
@@ -1735,6 +1965,7 @@ typedef struct pciePmRstIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to LNK_RST_REQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to LNK_RST_REQ_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1744,6 +1975,7 @@ typedef struct pciePmRstIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_PME\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_PME_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1753,6 +1985,7 @@ typedef struct pciePmRstIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TO_ACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TO_ACK_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1762,6 +1995,7 @@ typedef struct pciePmRstIrqEnableClrReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_TURNOFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PM_TURNOFF_EN_CLR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1769,6 +2003,106 @@ typedef struct pciePmRstIrqEnableClrReg_s {
 } pciePmRstIrqEnableClrReg_t;\r
 /* @} */\r
 \r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Raw Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS_RAW\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqStatusRawReg_s {\r
+  uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Link Request Reset interrupt raw status\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_CLK_UPDATED_RAW\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmClkUpdated;\r
+} pciePtmIrqStatusRawReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqStatusReg_s {\r
+  uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Link Request Reset interrupt raw status\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_CLK_UPDATED\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmClkUpdated;\r
+} pciePtmIrqStatusReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Raw Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS_ENABLE_SET\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqEnableSetReg_s {\r
+  uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Link Request Reset interrupt raw status\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_CLK_UPDATED_EN_SET\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmClkUpdated;\r
+} pciePtmIrqEnableSetReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_app_structures\r
+ * @brief Specification of the Precision Time Measurement Raw Status Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to PTM_IRQ_STATUS_ENABLE_CLR\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pciePtmIrqEnableClrReg_s {\r
+  uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Link Request Reset interrupt raw status\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PTM_CLK_UPDATED_EN_CLR\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t ptmClkUpdated;\r
+} pciePtmIrqEnableClrReg_t;\r
+/* @} */\r
+\r
 /**\r
  * @ingroup pcielld_reg_app_structures\r
  * @brief Specification of the Outbound Translation Region Offset Low and Index Register\r
@@ -1776,6 +2110,8 @@ typedef struct pciePmRstIrqEnableClrReg_s {
  * On rev 0 hw, this corresponds to OB_OFFSET_INDEXn where n = 0..7\r
  * On rev 1 hw, unsupported (but similar to iATU\r
  *              starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ *              starting at @ref pciePlconfIatuIndexReg_t)\r
  *\r
  * @{\r
  */\r
@@ -1786,6 +2122,7 @@ typedef struct pcieObOffsetLoReg_s {
    *\r
    * On rev 0 hw, this corresponds to OB_OFFSETn_LO (n = 0..7)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -1795,6 +2132,7 @@ typedef struct pcieObOffsetLoReg_s {
    *\r
    * On rev 0 hw, this corresponds to OB_ENABLEn (n = 0..7)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1809,6 +2147,8 @@ typedef struct pcieObOffsetLoReg_s {
  * On rev 0 hw, this corresponds to OB_OFFSETn_HI where n = 0..7\r
  * On rev 1 hw, unsupported (but similar to iATU\r
  *              starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ *              starting at @ref pciePlconfIatuIndexReg_t)\r
  *\r
  * @{\r
  */\r
@@ -1819,6 +2159,7 @@ typedef struct pcieObOffsetHiReg_s {
    *\r
    * On rev 0 hw, this corresponds to OB_OFFSETn_HI (n = 0..7)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -1833,6 +2174,8 @@ typedef struct pcieObOffsetHiReg_s {
  * On rev 0 hw, this corresponds to IB_BARn where n = 0..3\r
  * On rev 1 hw, unsupported (but similar to iATU\r
  *              starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ *              starting at @ref pciePlconfIatuIndexReg_t)\r
  *\r
  * @{\r
  */\r
@@ -1843,6 +2186,7 @@ typedef struct pcieIbBarReg_s {
    *\r
    * On rev 0 hw, this corresponds to IB_BARn (n = 0..3)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -1858,6 +2202,8 @@ typedef struct pcieIbBarReg_s {
  * On rev 0 hw, this corresponds to IB_STARTn_LO where n = 0..3\r
  * On rev 1 hw, unsupported (but similar to iATU\r
  *              starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ *              starting at @ref pciePlconfIatuIndexReg_t)\r
  *\r
  * @{\r
  */\r
@@ -1868,6 +2214,7 @@ typedef struct pcieIbStartLoReg_s {
    *\r
    * On rev 0 hw, this corresponds to IB_STARTn_LO (n = 0..3)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 24 bits\r
    */\r
@@ -1882,6 +2229,8 @@ typedef struct pcieIbStartLoReg_s {
  * On rev 0 hw, this corresponds to IB_STARTn_LO where n = 0..3\r
  * On rev 1 hw, unsupported (but similar to iATU\r
  *              starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ *              starting at @ref pciePlconfIatuIndexReg_t)\r
  * @{\r
  */\r
 typedef struct pcieIbStartHiReg_s {\r
@@ -1891,6 +2240,7 @@ typedef struct pcieIbStartHiReg_s {
    *\r
    * On rev 0 hw, this corresponds to IB_STARTn_HI (n = 0..3)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -1905,6 +2255,8 @@ typedef struct pcieIbStartHiReg_s {
  * On rev 0 hw, this corresponds to IB_OFFSETn where n = 0..3\r
  * On rev 1 hw, unsupported (but similar to iATU\r
  *              starting at @ref pciePlconfIatuIndexReg_t)\r
+ * On rev 2 hw, unsupported (but similar to iATU\r
+ *              starting at @ref pciePlconfIatuIndexReg_t)\r
  *\r
  * @{\r
  */\r
@@ -1915,6 +2267,7 @@ typedef struct pcieIbOffsetReg_s {
    *\r
    * On rev 0 hw, this corresponds to IB_OFFSETn (n = 0..3)\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 24 bits\r
    */\r
@@ -1928,6 +2281,7 @@ typedef struct pcieIbOffsetReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCS_CFG0\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -1938,6 +2292,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_SYNC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -1947,6 +2302,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_HOLDOFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -1956,6 +2312,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_RC_DELAY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -1965,6 +2322,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_DET_DELAY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -1974,6 +2332,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_SHRT_TM\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1983,6 +2342,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_STAT186\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -1992,6 +2352,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_FIX_TERM\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2001,6 +2362,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_FIX_STD\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2010,6 +2372,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_L2_ENIDL_OFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2019,6 +2382,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_L0S_RX_OFF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2028,6 +2392,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_RXTX_ON\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2037,6 +2402,7 @@ typedef struct pciePcsCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_RXTX_RST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2050,6 +2416,7 @@ typedef struct pciePcsCfg0Reg_s {
  *\r
  * On rev 0 hw, this corresponds to PCS_CFG1\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -2060,6 +2427,7 @@ typedef struct pciePcsCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_ERR_BIT\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 10 bits\r
    */\r
@@ -2069,6 +2437,7 @@ typedef struct pciePcsCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_ERR_LN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2078,6 +2447,7 @@ typedef struct pciePcsCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_ERR_MODE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2091,6 +2461,7 @@ typedef struct pciePcsCfg1Reg_s {
  *\r
  * On rev 0 hw, this corresponds to PCS_STATUS\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -2101,6 +2472,7 @@ typedef struct pciePcsStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_REV\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -2110,6 +2482,7 @@ typedef struct pciePcsStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_LN_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2119,6 +2492,7 @@ typedef struct pciePcsStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_TX_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2128,6 +2502,7 @@ typedef struct pciePcsStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PCS_RX_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2141,6 +2516,7 @@ typedef struct pciePcsStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to SERDES_CFG0\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -2151,6 +2527,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_LOOPBACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2160,6 +2537,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_MSYNC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2169,6 +2547,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_CM\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2178,6 +2557,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_INVPAIR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2187,6 +2567,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_LOOPBACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2196,6 +2577,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_ENOC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2205,6 +2587,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_EQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -2214,6 +2597,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_CDR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -2223,6 +2607,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_LOS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -2232,6 +2617,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_ALIGN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2241,6 +2627,7 @@ typedef struct pcieSerdesCfg0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_INVPAIR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2254,6 +2641,7 @@ typedef struct pcieSerdesCfg0Reg_s {
  *\r
  * On rev 0 hw, this corresponds to SERDES_CFG1\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, unsupported\r
  *\r
  * @{\r
  */\r
@@ -2264,6 +2652,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_LOOPBACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2273,6 +2662,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_MSYNC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2282,6 +2672,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_CM\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2291,6 +2682,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_INVPAIR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2300,6 +2692,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_LOOPBACK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2309,6 +2702,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_ENOC\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2318,6 +2712,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_EQ\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -2327,6 +2722,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_CDR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -2336,6 +2732,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_LOS\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -2345,6 +2742,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_ALIGN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2354,6 +2752,7 @@ typedef struct pcieSerdesCfg1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_INVPAIR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2374,6 +2773,7 @@ typedef struct pcieSerdesCfg1Reg_s {
  *\r
  * On rev 0 hw, this corresponds to VENDOR_DEVICE_ID\r
  * On rev 1 hw, this corresponds to DEVICE_VENDORID\r
+ * On rev 2 hw, this corresponds to DEVICE_ID_VENDOR_ID_REG and TYPE1_DEV_ID_VEND_ID_REG\r
  *\r
  * @{\r
  */\r
@@ -2384,6 +2784,7 @@ typedef struct pcieVndDevIdReg_s {
    *\r
    * On rev 0 hw, this corresponds to DEVICE_ID\r
    * On rev 1 hw, this corresponds to DEVICEID\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_DEVICE_ID or DEVICE_ID_VENDOR_ID_REG\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -2393,6 +2794,7 @@ typedef struct pcieVndDevIdReg_s {
    *\r
    * On rev 0 hw, this corresponds to VENDOR_ID\r
    * On rev 1 hw, this corresponds to VENDORID\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_VENDOR_ID and VENDOR_ID\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -2407,6 +2809,7 @@ typedef struct pcieVndDevIdReg_s {
  *\r
  * On rev 0 hw, this corresponds to STATUS_COMMAND\r
  * On rev 1 hw, this corresponds to STATUS_COMMAND_REGISTER\r
+ * On rev 2 hw, this corresponds to STATUS_COMMAND_REG and TYPE1_STATUS_COMMAND_REG\r
  *\r
  * @{\r
  */\r
@@ -2419,6 +2822,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to PARITY_ERROR\r
    * On rev 1 hw, this corresponds to DETECT_PARERR\r
+   * On rev 2 hw, this corresponds to DETECTED_PARITY_ERR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2431,6 +2835,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to SIG_SYS_ERROR\r
    * On rev 1 hw, this corresponds to SIGNAL_SYSERR\r
+   * On rev 2 hw, this corresponds to SIGNALED_SYS_ERR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2443,6 +2848,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_MST_ABORT\r
    * On rev 1 hw, this corresponds to RCVD_MASTERABORT\r
+   * On rev 2 hw, this corresponds to RCVD_MASTER_ABORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2454,6 +2860,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_TGT_ABORT\r
    * On rev 1 hw, this corresponds to RCVD_TRGTABORT\r
+   * On rev 2 hw, this corresponds to RCVD_TARGET_ABORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2466,6 +2873,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to SIG_TGT_ABORT\r
    * On rev 1 hw, this corresponds to SIGNAL_TRGTABORT\r
+   * On rev 2 hw, this corresponds to SIGNALED_TARGET_ABORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2479,6 +2887,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to DEVSEL_TIME\r
+   * On rev 2 hw, this corresponds to DEV_SEL_TIMING\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -2493,6 +2902,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to DAT_PAR_ERRROR\r
    * On rev 1 hw, this corresponds to MASTERDATA_PARERR\r
+   * On rev 2 hw, this corresponds to MASTER_DPE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2506,6 +2916,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to FAST_B2B\r
+   * On rev 2 hw, this corresponds to FAST_B2B_CAP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2519,6 +2930,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to C66MHZ_CAP\r
+   * On rev 2 hw, this corresponds to FAST_66MHZ_CAP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2530,6 +2942,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to CAP_LIST\r
    * On rev 1 hw, this corresponds to CAP_LIST\r
+   * On rev 2 hw, this corresponds to CAP_LIST\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2541,6 +2954,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_STAT\r
    * On rev 1 hw, this corresponds to INTX_STATUS\r
+   * On rev 2 hw, this corresponds to INT_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2552,6 +2966,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to INTX_DIS\r
    * On rev 1 hw, this corresponds to INTX_ASSER_DIS\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_INT_EN and INT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2564,6 +2979,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to SERR_EN\r
    * On rev 1 hw, this corresponds to SERR_EN\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_SERREN and SERREN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2571,12 +2987,13 @@ typedef struct pcieStatusCmdReg_s {
   /**\r
    * @brief [ro] Bit hardwired to 0 for PCIExpress\r
    *\r
-   * Hardwired to 0 for PCIExpress.  Only defined on rev 1 hw version.\r
+   * Hardwired to 0 for PCIExpress.  Only defined on rev 1/2 hw version.\r
    *\r
    * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to IDSEL_CTRL\r
+   * On rev 2 hw, this corresponds to PCI_TYPE_IDSEL_STEPPING and IDSEL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2593,6 +3010,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to PAR_ERR_RESP\r
    * On rev 1 hw, this corresponds to PARITYERRRESP\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_PARITY_ERR_EN and PERREN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2600,12 +3018,13 @@ typedef struct pcieStatusCmdReg_s {
   /**\r
    * @brief [ro] Bit hardwired to 0 for PCIExpress\r
    *\r
-   * Hardwired to 0 for PCIExpress.  Only defined on rev 1 hw version.\r
+   * Hardwired to 0 for PCIExpress.  Only defined on rev 1/2 hw version.\r
    *\r
    * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to VGA_SNOOP\r
+   * On rev 2 hw, this corresponds to PCI_TYPE_VGA_PALETTE_SNOOP and VGAPS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2613,12 +3032,13 @@ typedef struct pcieStatusCmdReg_s {
   /**\r
    * @brief [ro] Bit hardwired to 0 for PCIExpress\r
    *\r
-   * Hardwired to 0 for PCIExpress.  Only defined on rev 1 hw version.\r
+   * Hardwired to 0 for PCIExpress.  Only defined on rev 1/2 hw version.\r
    *\r
    * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to MEMWR_INVA\r
+   * On rev 2 hw, this corresponds to PCI_TYPE_MWI_ENABLE / MWI_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2626,12 +3046,13 @@ typedef struct pcieStatusCmdReg_s {
   /**\r
    * @brief [ro] Bit hardwired to 0 for PCIExpress\r
    *\r
-   * Hardwired to 0 for PCIExpress.  Only defined on rev 1 hw version.\r
+   * Hardwired to 0 for PCIExpress.  Only defined on rev 1/2 hw version.\r
    *\r
    * Forced to 0 on rev 0 hw read; ignored on rev 0 hw write.\r
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to SPEC_CYCLE_EN\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_SPECIAL_CYCLE_OPERATION and SCO\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2641,6 +3062,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to BUS_MS\r
    * On rev 1 hw, this corresponds to BUSMASTER_EN\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_BUS_MASTER_EN and BME\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2650,6 +3072,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to MEM_SP\r
    * On rev 1 hw, this corresponds to MEM_SPACE_EN\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_MEM_SPACE_EN and MSE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2662,6 +3085,7 @@ typedef struct pcieStatusCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to IO_SP\r
    * On rev 1 hw, this corresponds to IO_SPACE_EN\r
+   * On rev 2 hw, this corresponds to PCI_TYPE0_IO_EN / IO_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2676,6 +3100,7 @@ typedef struct pcieStatusCmdReg_s {
  *\r
  * On rev 0 hw, this corresponds to CLASSCODE_REVID\r
  * On rev 1 hw, this corresponds to CLASSCODE_REVISIONID\r
+ * On rev 2 hw, this corresponds to CLASS_CODE_REVISION_ID\r
  *\r
  * @{\r
  */\r
@@ -2685,11 +3110,12 @@ typedef struct pcieRevIdReg_s {
    * @brief [ro] Class Code\r
    *\r
    * On rev 0 hw, the register presents this as 24 bits.\r
-   * On rev 1 hw, the register presetns as 3 8bit fields, but they will all be\r
+   * On rev 1/2 hw, the register presents as 3 8bit fields, but they will all be\r
    * packed/unpacked from classCode for backward/forward compatibility.\r
    *\r
    * On rev 0 hw, this corresponds to CLASSCODE\r
    * On rev 1 hw, this corresponds to BASE_CLS_CD, SUBCLS_CD and PROG_IF_CODE\r
+   * On rev 2 hw, this corresponds to BASE_CLASS_CODE, SUBCLASS_CODE and PROGRAM_INTERFACE\r
    *\r
    * Field size: 24 bits\r
    */\r
@@ -2699,6 +3125,7 @@ typedef struct pcieRevIdReg_s {
    *\r
    * On rev 0 hw, this corresponds to REVID\r
    * On rev 1 hw, this corresponds to REVID\r
+   * On rev 2 hw, this corresponds to REVID\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -2721,6 +3148,7 @@ typedef struct pcieRevIdReg_s {
  *\r
  * On rev 0 hw, this corresponds to BARn\r
  * On rev 1 hw, this corresponds to BARn\r
+ * On rev 2 hw, this corresponds to BAR_REGn\r
  *\r
  * @{\r
  */\r
@@ -2732,6 +3160,7 @@ typedef struct pcieBarReg_s {
    * Rev 0 hw: 28 bits are modifiable\r
    * Rev 1 hw: only upper 12 bits are modifyable (eg 16-27).  Rest are read-only.  If users tries\r
    * to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
+   * Rev 2 hw: 28 bits are modifiable\r
    *\r
    * Field size: 28 bits\r
    */\r
@@ -2821,6 +3250,7 @@ typedef struct pcieBar32bitReg_s {
  *\r
  * On rev 0 hw, this corresponds to BIST_HEADER\r
  * On rev 1 hw, this corresponds to BIST_HEAD_LAT_CACH\r
+ * On rev 2 hw, this corresponds to BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG\r
  *\r
  * @{\r
  */\r
@@ -2835,6 +3265,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to BIST_CAP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2848,6 +3279,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to START_BIST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -2861,6 +3293,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to COMP_CODE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -2872,6 +3305,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to BIST\r
+   * On rev 2 hw, this corresponds to BIST\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -2881,6 +3315,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to MULFUN_DEV\r
    * On rev 1 hw, this corresponds to MFD\r
+   * On rev 2 hw, this corresponds to MULTI_FUNC\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -2895,6 +3330,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to HDR_TYPE\r
    * On rev 1 hw, this corresponds to HEAD_TYP\r
+   * On rev 1 hw, this corresponds to HEADER_TYPE\r
    *\r
    * Field size: 7 bits\r
    */\r
@@ -2904,6 +3340,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to LAT_TMR\r
    * On rev 1 hw, this corresponds to MSTR_LAT_TIM\r
+   * On rev 2 hw, this corresponds to LATENCY_MASTER_TIMER\r
    *\r
    * Field size:  8 bits\r
    */\r
@@ -2913,6 +3350,7 @@ typedef struct pcieBistReg_s {
    *\r
    * On rev 0 hw, this corresponds to CACHELN_SIZ\r
    * On rev 1 hw, this corresponds to CACH_LN_SZE\r
+   * On rev 2 hw, this corresponds to CACHE_LINE_SIZE\r
    *\r
    * Field size:  8 bits\r
    */\r
@@ -2957,10 +3395,11 @@ typedef struct pcieType0Bar32bitIdx_s {
 \r
 /**\r
  * @ingroup pcielld_reg_cfg_type0_structures\r
- * @brief Specification of the Subsystem Vendor ID Register\r
+ * @brief Specification of the Cardbus CIS pointer register\r
  *\r
  * On rev 0 hw, unsupported\r
  * On rev 1 hw, this corresponds to CARDBUS_CIS_POINTER\r
+ * On rev 2 hw, this corresponds to CARDBUS_CIS_PTR_REG\r
  *\r
  * @{\r
  */\r
@@ -2969,7 +3408,7 @@ typedef struct pcieCardbusCisPointerReg_s {
   /**\r
    * @brief [rw] Cardbus CIS pointer (CS)\r
    *\r
-   * This register is only used in rev 1 hw.  It is physically present but marked reserved\r
+   * This register is only used in rev 1/2 hw.  It is physically present but marked reserved\r
    * in rev 0 hardware, so this structure/API isn't used.\r
    *\r
    * Field size: 32 bits\r
@@ -2984,6 +3423,7 @@ typedef struct pcieCardbusCisPointerReg_s {
  *\r
  * On rev 0 hw, this corresponds to SUBSYS_VNDR_ID\r
  * On rev 1 hw, this corresponds to SUBID_SUBVENDORID\r
+ * On rev 2 hw, this corresponds to SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG\r
  *\r
  * @{\r
  */\r
@@ -2994,6 +3434,7 @@ typedef struct pcieSubIdReg_s {
    *\r
    * On rev 0 hw, this corresponds to SUBSYS_ID\r
    * On rev 1 hw, this corresponds to SUBSYS_DEV_ID_N\r
+   * On rev 2 hw, this corresponds to SUBSYS_DEV_ID\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -3003,6 +3444,7 @@ typedef struct pcieSubIdReg_s {
    *\r
    * On rev 0 hw, this corresponds to SUBSYS_VEN_ID\r
    * On rev 1 hw, this corresponds to SUBSYS_VENDOR_ID_N\r
+   * On rev 2 hw, this corresponds to SUBSYS_VENDOR_ID\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -3016,6 +3458,7 @@ typedef struct pcieSubIdReg_s {
  *\r
  * On rev 0 hw, this corresponds to EXPNSN_ROM\r
  * On rev 1 hw, this corresponds to EXPANSION_ROM_BAR\r
+ * On rev 2 hw, this corresponds to EXP_ROM_BASE_ADDR_REG\r
  *\r
  * @{\r
  */\r
@@ -3029,8 +3472,11 @@ typedef struct pcieExpRomReg_s {
    * Rev 1 hw: only upper 16 bits are modifyable (eg 16-31).  Lower 5 bits are\r
    * r/o.  Attempt to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
    *\r
+   * Rev 2 hw: entire 21 bits are r/w\r
+   *\r
    * On rev 0 hw, this corresponds to EXP_ROM_BASE_ADDR and EXROM_ADDRESS_RO\r
    * On rev 1 hw, this corresponds to EXROM_ADDRESS\r
+   * On rev 2 hw, this corresponds to EXP_ROM_BASE_ADDRES\r
    *\r
    * Field size: 21 bits\r
    */\r
@@ -3040,6 +3486,7 @@ typedef struct pcieExpRomReg_s {
    *\r
    * On rev 0 hw, this corresponds to EXP_ROM_EN\r
    * On rev 1 hw, this corresponds to EXROM_EN\r
+   * On rev 2 hw, this corresponds to ROM_BAR_ENABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3054,6 +3501,7 @@ typedef struct pcieExpRomReg_s {
  *\r
  * On rev 0 hw, this corresponds to CAP_PTR\r
  * On rev 1 hw, this corresponds to CAPPTR\r
+ * On rev 2 hw, this corresponds to PCI_CAP_PTR_REG\r
  *\r
  * @{\r
  */\r
@@ -3066,6 +3514,7 @@ typedef struct pcieCapPtrReg_s {
    *\r
    * On rev 0 hw, this corresponds to CAP_PTR\r
    * On rev 1 hw, this corresponds to CAPPTR\r
+   * On rev 2 hw, this corresponds to CAP_POINTER\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3079,6 +3528,7 @@ typedef struct pcieCapPtrReg_s {
  *\r
  * On rev 0 hw, this corresponds to INT_PIN\r
  * On rev 1 hw, this corresponds to INTERRUPT\r
+ * On rev 2 hw, this corresponds to MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG\r
  *\r
  * @{\r
  */\r
@@ -3102,6 +3552,7 @@ typedef struct pcieIntPinReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_PIN\r
    * On rev 1 hw, this corresponds to INT_PIN\r
+   * On rev 2 hw, this corresponds to INT_PIN\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3111,6 +3562,7 @@ typedef struct pcieIntPinReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_LINE\r
    * On rev 1 hw, this corresponds to INT_LIN\r
+   * On rev 2 hw, this corresponds to INT_LIN\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3132,6 +3584,8 @@ typedef struct pcieIntPinReg_s {
  *\r
  * This structure is used to access a Root Complex BAR. For more details, please refer to @ref pcieBarReg_t.\r
  *\r
+ * On rev 2 hw, not supported (use IATU instead)\r
+ *\r
  * @{\r
  */\r
 typedef struct pcieType1BarIdx_s {\r
@@ -3149,6 +3603,8 @@ typedef struct pcieType1BarIdx_s {
  *\r
  * This structure is used to access a Root Complex BAR. For more details, please refer to @ref pcieBar32bitReg_t.\r
  *\r
+ * On rev 2 hw, not supported (use IATU instead)\r
+ *\r
  * @{\r
  */\r
 typedef struct pcieType1Bar32bitIdx_s {\r
@@ -3163,6 +3619,7 @@ typedef struct pcieType1Bar32bitIdx_s {
  *\r
  * On rev 0 hw, this corresponds to BIST_HEADER\r
  * On rev 1 hw, this corresponds to BIST_HEAD_LAT_CACH\r
+ * On rev 2 hw, this corresponds to TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG\r
  *\r
  * @{\r
  */\r
@@ -3175,6 +3632,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to BIST_CAP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3186,6 +3644,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to START_BIST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3197,6 +3656,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to COMP_CODE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -3206,6 +3666,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to BIST\r
+   * On rev 2 hw, this corresponds to BIST\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3215,6 +3676,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to MULFUN_DEV\r
    * On rev 1 hw, this corresponds to MFD\r
+   * On rev 2 hw, this corresponds to MULTI_FUNC\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3227,6 +3689,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to HDR_TYPE\r
    * On rev 1 hw, this corresponds to HEAD_TYP\r
+   * On rev 2 hw, this corresponds to HEADER_TYPE\r
    *\r
    * Field size: 7 bits\r
    */\r
@@ -3236,6 +3699,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to LAT_TMR\r
    * On rev 1 hw, this corresponds to MSTR_LAT_TIM\r
+   * On rev 2 hw, this corresponds to LATENCY_MASTER_TIMER\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3245,6 +3709,7 @@ typedef struct pcieType1BistHeaderReg_s {
    *\r
    * On rev 0 hw, this corresponds to CACHELN_SIZE\r
    * On rev 1 hw, this corresponds to CACH_LN_SIZE\r
+   * On rev 2 hw, this corresponds to CACHE_LINE_SIZE\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3258,6 +3723,7 @@ typedef struct pcieType1BistHeaderReg_s {
  *\r
  * On rev 0 hw, this corresponds to BUSNUM\r
  * On rev 1 hw, this corresponds to BUS_NUM_REG\r
+ * On rev 2 hw, this corresponds to SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG\r
  *\r
  * @{\r
  */\r
@@ -3268,6 +3734,7 @@ typedef struct pcieType1BusNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to SEC_LAT_TMR\r
    * On rev 1 hw, this corresponds to SEC_LAT_TIMER\r
+   * On rev 2 hw, this corresponds to SEC_LAT_TIMER\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3278,6 +3745,7 @@ typedef struct pcieType1BusNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to SUB_BUS_NUM\r
    * On rev 1 hw, this corresponds to SUBORD_BUS_NUM\r
+   * On rev 2 hw, this corresponds to SUB_BUS\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3287,6 +3755,7 @@ typedef struct pcieType1BusNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to SEC_BUS_NUM\r
    * On rev 1 hw, this corresponds to SEC_BUS_NUM\r
+   * On rev 2 hw, this corresponds to SEC_BUS\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3297,6 +3766,7 @@ typedef struct pcieType1BusNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRI_BUS_NUM\r
    * On rev 1 hw, this corresponds to PRIM_BUS_NUM\r
+   * On rev 2 hw, this corresponds to PRIM_BUS\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3310,6 +3780,7 @@ typedef struct pcieType1BusNumReg_s {
  *\r
  * On rev 0 hw, this corresponds to SECSTAT\r
  * On rev 1 hw, this corresponds to IOBASE_LIMIT_SEC_STATUS\r
+ * On rev 2 hw, this corresponds to SEC_STAT_IO_LIMIT_IO_BASE_REG\r
  *\r
  * @{\r
  */\r
@@ -3323,6 +3794,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to DTCT_PERROR\r
    * On rev 1 hw, this corresponds to DET_PAR_ERR\r
+   * On rev 2 hw, this corresponds to SEC_STAT_DPE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3335,6 +3807,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_SYS_ERROR\r
    * On rev 1 hw, this corresponds to RCVD_SYS_ERR\r
+   * On rev 2 hw, this corresponds to SEC_STAT_RCVD_SYS_ERR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3347,6 +3820,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_MST_ABORT\r
    * On rev 1 hw, this corresponds to RCVD_MSTR_ABORT\r
+   * On rev 2 hw, this corresponds to SEC_STAT_RCVD_MSTR_ABRT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3359,6 +3833,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to RX_TGT_ABORT\r
    * On rev 1 hw, this corresponds to RCVD_TRGT_ABORT\r
+   * On rev 2 hw, this corresponds to SEC_STAT_RCVD_TRGT_ABRT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3371,6 +3846,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_TGT_ABORT\r
    * On rev 1 hw, this corresponds to SGNLD_TRGT_ABORT\r
+   * On rev 2 hw, this corresponds to SEC_STAT_SIG_TRGT_ABRT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3380,6 +3856,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to DEVSEL_TIMING\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -3395,6 +3872,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to MST_DPERR\r
    * On rev 1 hw, this corresponds to MSTR_DATA_PRTY_ERR\r
+   * On rev 2 hw, this corresponds to SEC_STAT_MDPE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3404,6 +3882,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to FAST_B2B_CAP\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3413,6 +3892,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to C66MHZ_CAPA\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3422,6 +3902,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to IO_LIMIT\r
    * On rev 1 hw, this corresponds to IO_SPACE_LIMIT\r
+   * On rev 2 hw, this corresponds to IO_LIMIT\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -3435,6 +3916,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to IO_LIMIT_ADDR\r
    * On rev 1 hw, this corresponds to IODECODE_32\r
+   * On rev 2 hw, this corresponds to IO_DECODE_BITS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3444,6 +3926,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to IO_BASE\r
    * On rev 1 hw, this corresponds to IO_SPACE_BASE\r
+   * On rev 2 hw, this corresponds to IO_BASE\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -3457,6 +3940,7 @@ typedef struct pcieType1SecStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to IO_BASE_ADDR\r
    * On rev 1 hw, this corresponds to IODECODE_32_0\r
+   * On rev 2 hw, this corresponds to IO_DECODE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3470,6 +3954,7 @@ typedef struct pcieType1SecStatReg_s {
  *\r
  * On rev 0 hw, this corresponds to MEMSPACE\r
  * On rev 1 hw, this corresponds to MEM_BASE_LIMIT\r
+ * On rev 2 hw, this corresponds to MEM_LIMIT_MEM_BASE_REG\r
  *\r
  * @{\r
  */\r
@@ -3480,6 +3965,7 @@ typedef struct pcieType1MemspaceReg_s {
    *\r
    * On rev 0 hw, this corresponds to MEM_LIMIT\r
    * On rev 1 hw, this corresponds to MEM_LIMIT_ADDR\r
+   * On rev 2 hw, this corresponds to MEM_LIMIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -3489,6 +3975,7 @@ typedef struct pcieType1MemspaceReg_s {
    *\r
    * On rev 0 hw, this corresponds to MEM_BASE\r
    * On rev 1 hw, this corresponds to MEM_BASE_ADDR\r
+   * On rev 2 hw, this corresponds to MEM_BASE\r
    *\r
    * Field size: 12 bit\r
    */\r
@@ -3503,6 +3990,7 @@ typedef struct pcieType1MemspaceReg_s {
  *\r
  * On rev 0 hw, this corresponds to PREFETCH_MEM\r
  * On rev 1 hw, this corresponds to PREF_MEM_BASE_LIMIT\r
+ * On rev 2 hw, this corresponds to PREF_MEM_LIMIT_PREF_MEM_BASE_REG\r
  *\r
  * @{\r
  */\r
@@ -3515,6 +4003,7 @@ typedef struct pciePrefMemReg_s {
    *\r
    * On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
    * On rev 1 hw, this corresponds to PREF_MEM_ADDR\r
+   * On rev 2 hw, this corresponds to PREF_MEM_LIMIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -3529,6 +4018,7 @@ typedef struct pciePrefMemReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRE_LIMIT_ADDR\r
    * On rev 1 hw, this corresponds to MEMDECODE_64\r
+   * On rev 2 hw, this corresponds to MEM_LIMIT_DECODE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3540,6 +4030,7 @@ typedef struct pciePrefMemReg_s {
    *\r
    * On rev 0 hw, this corresponds to PREFETCH_BASE\r
    * On rev 1 hw, this corresponds to UPPPREF_MEM_ADDR\r
+   * On rev 2 hw, this corresponds to PREF_MEM_BASE\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -3554,6 +4045,7 @@ typedef struct pciePrefMemReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRE_BASE_ADDR\r
    * On rev 1 hw, this corresponds to MEMDECODE_64_0\r
+   * On rev 2 hw, this corresponds to PREF_MEM_DECODE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3568,6 +4060,7 @@ typedef struct pciePrefMemReg_s {
  *\r
  * On rev 0 hw, this corresponds to PREFETCH_BASE\r
  * On rev 1 hw, this corresponds to UPPER_32BIT_PREF_BASEADDR\r
+ * On rev 2 hw, this corresponds to PREF_BASE_UPPER_REG\r
  *\r
  * @{\r
  */\r
@@ -3581,6 +4074,7 @@ typedef struct pciePrefBaseUpperReg_s {
    *\r
    * On rev 0 hw, this corresponds to PREFETCH_BASE\r
    * On rev 1 hw, this corresponds to ADDRUPP\r
+   * On rev 2 hw, this corresponds to PREF_MEM_BASE_UPPER\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -3594,6 +4088,7 @@ typedef struct pciePrefBaseUpperReg_s {
  *\r
  * On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
  * On rev 1 hw, this corresponds to UPPER_32BIT_PREF_LIMITADDR\r
+ * On rev 2 hw, this corresponds to PREF_LIMIT_UPPER_REG\r
  *\r
  * @{\r
  */\r
@@ -3607,6 +4102,7 @@ typedef struct pciePrefLimitUpperReg_s {
    *\r
    * On rev 0 hw, this corresponds to PREFETCH_LIMIT\r
    * On rev 1 hw, this corresponds to ADDRUPP_LIMIT\r
+   * On rev 2 hw, this corresponds to PREF_MEM_LIMIT_UPPER\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -3620,6 +4116,7 @@ typedef struct pciePrefLimitUpperReg_s {
  *\r
  * On rev 0 hw, this corresponds to IOSPACE\r
  * On rev 1 hw, this corresponds to IO_BASE_LIMIT\r
+ * On rev 2 hw, this corresponds to IO_LIMIT_UPPER_IO_BASE_UPPER_REG\r
  *\r
  * @{\r
  */\r
@@ -3632,6 +4129,7 @@ typedef struct pcieType1IOSpaceReg_s {
    *\r
    * On rev 0 hw, this corresponds to IOBASE\r
    * On rev 1 hw, this corresponds to UPP16_IOBASE\r
+   * On rev 2 hw, this corresponds to IO_BASE_UPPER\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -3643,6 +4141,7 @@ typedef struct pcieType1IOSpaceReg_s {
    *\r
    * On rev 0 hw, this corresponds to IOLIMIT\r
    * On rev 1 hw, this corresponds to UPP16_IOLIMIT\r
+   * On rev 2 hw, this corresponds to IO_LIMIT_UPPER\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -3656,6 +4155,7 @@ typedef struct pcieType1IOSpaceReg_s {
  *\r
  * On rev 0 hw, this corresponds to CAP_PTR\r
  * On rev 1 hw, this corresponds to CAPPTR\r
+ * On rev 2 hw, this corresponds to TYPE1_CAP_PTR_REG\r
  *\r
  * @{\r
  */\r
@@ -3669,6 +4169,7 @@ typedef struct pcieType1CapPtrReg_s {
    *\r
    * On rev 0 hw, this corresponds to CAP_PTR\r
    * On rev 1 hw, this corresponds to CAPPTR\r
+   * On rev 2 hw, this corresponds to CAP_POINTER\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3682,6 +4183,7 @@ typedef struct pcieType1CapPtrReg_s {
  *\r
  * On rev 0 hw, this corresponds to EXPNSN_ROM\r
  * On rev 1 hw, this corresponds to EXPANSION_ROM_BAR\r
+ * On rev 2 hw, this corresponds to TYPE1_EXP_ROM_BASE_REG\r
  *\r
  * @{\r
  */\r
@@ -3693,9 +4195,11 @@ typedef struct pcieType1ExpnsnRomReg_s {
    * Rev 0 hw: 21 bits are modifiable\r
    * Rev 1 hw: only upper 16 bits are modifyable (eg 16-20).  Rest are read-only.  If users tries\r
    * to modify r/o bits will return @ref pcie_RET_RO_CHANGED.\r
+   * Rev 2 hw: 21 bits are modifiable\r
    *\r
    * On rev 0 hw, this corresponds to EXP_ROM_BASE_ADDR\r
    * On rev 1 hw, this corresponds to EXROM_ADDRESS\r
+   * On rev 2 hw, this corresponds to EXP_ROM_BASE_ADDRESS\r
    *\r
    * Field size: 21CAPPTR bits [0-0x1FFFFF]\r
    */\r
@@ -3705,6 +4209,7 @@ typedef struct pcieType1ExpnsnRomReg_s {
    *\r
    * On rev 0 hw, this corresponds to EXP_ROM_EN\r
    * On rev 1 hw, this corresponds to EXP_ROM_EN\r
+   * On rev 2 hw, this corresponds to ROM_BAR_ENABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3718,6 +4223,7 @@ typedef struct pcieType1ExpnsnRomReg_s {
  *\r
  * On rev 0 hw, this corresponds to BRIDGE_INT\r
  * On rev 1 hw, this corresponds to BRIDGE_INT\r
+ * On rev 2 hw, this corresponds to BRIDGE_CTRL_INT_PIN_INT_LINE_REG\r
  *\r
  * @{\r
  */\r
@@ -3730,6 +4236,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to SERREN_STATUS\r
    * On rev 1 hw, this corresponds to DT_SERR_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3741,6 +4248,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to TIMER_STATUS\r
    * On rev 1 hw, this corresponds to DT_STS\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3752,6 +4260,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to SEC_TIMER\r
    * On rev 1 hw, this corresponds to SEC_DT\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3763,6 +4272,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRI_TIMER\r
    * On rev 1 hw, this corresponds to PRI_DT\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3774,6 +4284,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to B2B_EN\r
    * On rev 1 hw, this corresponds to FAST_B2B_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3783,6 +4294,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to SEC_BUS_RST\r
    * On rev 1 hw, this corresponds to SEC_BUS_RST\r
+   * On rev 2 hw, this corresponds to SBR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3794,6 +4306,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to MST_ABORT_MODE\r
    * On rev 1 hw, this corresponds to MST_ABT_MODE\r
+   * On rev 2 hw, this corresponds to MSTR_ABORT_MODE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3803,6 +4316,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to VGA_DECODE\r
    * On rev 1 hw, this corresponds to VGA_16B_DEC\r
+   * On rev 2 hw, this corresponds to VGA_16B_DEC\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3812,6 +4326,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to VGA_EN\r
    * On rev 1 hw, this corresponds to VGA_EN\r
+   * On rev 2 hw, this corresponds to VGA_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3821,6 +4336,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to ISA_EN\r
    * On rev 1 hw, this corresponds to ISA_EN\r
+   * On rev 2 hw, this corresponds to ISA_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3832,6 +4348,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to SERR_EN\r
    * On rev 1 hw, this corresponds to SERR_EN\r
+   * On rev 2 hw, this corresponds to SERR_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3844,6 +4361,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to PERR_RESP_EN\r
    * On rev 1 hw, this corresponds to PERR_RESP_EN\r
+   * On rev 2 hw, this corresponds to PERE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -3864,6 +4382,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_PIN\r
    * On rev 1 hw, this corresponds to INT_PIN\r
+   * On rev 2 hw, this corresponds to INT_PIN\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3873,6 +4392,7 @@ typedef struct pcieType1BridgeIntReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_LINE\r
    * On rev 1 hw, this corresponds to INT_LIN\r
+   * On rev 2 hw, this corresponds to INT_LINE\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -3890,6 +4410,7 @@ typedef struct pcieType1BridgeIntReg_s {
  *\r
  * On rev 0 hw, this corresponds to PMCAP  for EP and RC\r
  * On rev 1 hw, this corresponds to PM_CAP for EP only\r
+ * On rev 2 hw, this corresponds to CAP_ID_NXT_PTR_REG for EP and RC\r
  *\r
  * @{\r
  */\r
@@ -3910,6 +4431,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_SUPP_N\r
    * On rev 1 hw, this corresponds to PME_SP\r
+   * On rev 2 hw, this corresponds to PME_SUPPORT\r
    *\r
    * Field size: 5 bits\r
    *\r
@@ -3920,6 +4442,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to D2_SUPP_N\r
    * On rev 1 hw, this corresponds to D2_SP\r
+   * On rev 2 hw, this corresponds to D2_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -3930,6 +4453,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to D1_SUPP_N\r
    * On rev 1 hw, this corresponds to D1_SP\r
+   * On rev 2 hw, this corresponds to D1_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -3940,6 +4464,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to AUX_CURR_N\r
    * On rev 1 hw, this corresponds to AUX_CUR\r
+   * On rev 2 hw, this corresponds to AUX_CURR\r
    *\r
    * Field size: 3 bits\r
    *\r
@@ -3950,6 +4475,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to DSI_N\r
    * On rev 1 hw, this corresponds to DSI\r
+   * On rev 2 hw, this corresponds to DSI\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -3958,8 +4484,9 @@ typedef struct pciePMCapReg_s {
   /**\r
    * @brief [ro] PME clock.  Hardwired to zero.\r
    *\r
-   * On rev 0 hw, this corresponds to D2_SUPP_N\r
-   * On rev 1 hw, this corresponds to D2_SP\r
+   * On rev 0 hw, this corresponds to PME_CLK\r
+   * On rev 1 hw, this corresponds to PME_CLK\r
+   * On rev 2 hw, this corresponds to PME_CLK\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -3970,6 +4497,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_SPEC_VER\r
    * On rev 1 hw, this corresponds to PMC_VER\r
+   * On rev 2 hw, this corresponds to PM_SPEC_VER\r
    *\r
    * Field size: 3 bits\r
    *\r
@@ -3982,6 +4510,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_NEXT_PTR\r
    * On rev 1 hw, this corresponds to PM_NX_PTR\r
+   * On rev 2 hw, this corresponds to PM_NEXT_POINTER\r
    *\r
    * Field size: 8 bits\r
    *\r
@@ -3992,6 +4521,7 @@ typedef struct pciePMCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_CAP_ID\r
    * On rev 1 hw, this corresponds to CAP_ID\r
+   * On rev 2 hw, this corresponds to PM_CAP_ID\r
    *\r
    * Field size: 8 bits\r
    *\r
@@ -4006,6 +4536,7 @@ typedef struct pciePMCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to PM_CTL_STAT for EP and RC\r
  * On rev 1 hw, this corresponds to PM_CSR for EP only\r
+ * On rev 2 hw, this corresponds to CON_STATUS_REG for EP and RC only\r
  *\r
  * @{\r
  */\r
@@ -4016,6 +4547,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to DATA_REG\r
    * On rev 1 hw, this corresponds to DATA1\r
+   * On rev 2 hw, this corresponds to DATA_REG_ADD_INFO\r
    *\r
    * Field size: 8 bits\r
    *\r
@@ -4026,6 +4558,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to CLK_CTRL_EN\r
    * On rev 1 hw, this corresponds to BP_CCE\r
+   * On rev 2 hw, this corresponds to BUS_PWR_CLK_CON_EN\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -4036,6 +4569,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to B2_B3_SUPPORT\r
    * On rev 1 hw, this corresponds to B2B3_SP\r
+   * On rev 2 hw, this corresponds to B2_B3_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -4046,6 +4580,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_STATUS\r
    * On rev 1 hw, this corresponds to PME_STATUS\r
+   * On rev 2 hw, this corresponds to PME_STATUS\r
    *\r
    * Write 1 to clear.\r
    *\r
@@ -4058,6 +4593,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to DATA_SCALE\r
    * On rev 1 hw, this corresponds to DATA_SCALE\r
+   * On rev 2 hw, this corresponds to DATA_SCALE\r
    *\r
    * Field size: 2 bits\r
    *\r
@@ -4068,6 +4604,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to DATA_SELECT\r
    * On rev 1 hw, this corresponds to DATA_SEL\r
+   * On rev 2 hw, this corresponds to DATA_SELECT\r
    *\r
    * Field size: 4 bits\r
    *\r
@@ -4076,8 +4613,9 @@ typedef struct pciePMCapCtlStatReg_s {
   /**\r
    * @brief [rw] PME Enable. Value of 1 indicates device is enabled to generate PME.\r
    *\r
-   * On rev 0 hw, this corresponds to PM_CAP_ID\r
-   * On rev 1 hw, this corresponds to CAP_ID\r
+   * On rev 0 hw, this corresponds to PME_EN\r
+   * On rev 1 hw, this corresponds to PME_EN\r
+   * On rev 2 hw, this corresponds to PME_ENABLE\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -4088,8 +4626,9 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * It is set to disable reset during a transition from D3 to D0.\r
    *\r
-   * On rev 0 hw, this corresponds to PME_EN\r
-   * On rev 1 hw, this corresponds to PME_EN\r
+   * On rev 0 hw, this corresponds to NO_SOFT_RST\r
+   * On rev 1 hw, this corresponds to NSR\r
+   * On rev 2 hw, this corresponds to NO_SOFT_RST\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -4107,6 +4646,7 @@ typedef struct pciePMCapCtlStatReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_STATE\r
    * On rev 1 hw, this corresponds to PM_STATE\r
+   * On rev 2 hw, this corresponds to POWER_STATE\r
    *\r
    * Field size: 2 bits\r
    *\r
@@ -4125,16 +4665,40 @@ typedef struct pciePMCapCtlStatReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI_CAP for EP and RC\r
  * On rev 1 hw, this corresponds to MSI_CAP for EP only\r
+ * On rev 2 hw, this corresponds to PCI_MSI_CAP_ID_NEXT_CTRL_REG for EP only\r
  *\r
  * @{\r
  */\r
 typedef struct pcieMsiCapReg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] MSI Per Vector Masking supported\r
+   *\r
+   * on rev 0 hw: unsupported\r
+   * on rev 1 hw: unsupported\r
+   * On rev 2 hw, this corresponds to PCI_MSI_EXT_DATA_EN\r
+   *\r
+   * Field size: 1 bit\r
+   *\r
+   */\r
+  uint8_t extDataEn;\r
+  /**\r
+   * @brief [ro] Extended message data capable\r
+   *\r
+   * on rev 0 hw: unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCI_MSI_EXT_DATA_CAP\r
+   *\r
+   * Field size: 1 bit\r
+   *\r
+   */\r
+  uint8_t extDataCap;\r
   /**\r
    * @brief [ro] MSI Per Vector Masking supported\r
    *\r
    * on rev 0 hw: unsupported\r
    * On rev 1 hw, this corresponds to PVM_EN\r
+   * On rev 2 hw, this corresponds to PCI_PVM_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -4145,6 +4709,7 @@ typedef struct pcieMsiCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to 64BIT_EN\r
    * On rev 1 hw, this corresponds to MSI_64_EN\r
+   * On rev 2 hw, this corresponds to PCI_MSI_64_BIT_ADDR_CAP\r
    *\r
    * Field size: 1 bit\r
    *\r
@@ -4169,6 +4734,7 @@ typedef struct pcieMsiCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MULT_MSG_EN\r
    * On rev 1 hw, this corresponds to MME\r
+   * On rev 2 hw, this corresponds to PCI_MSI_MULTIPLE_MSG_EN\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4191,6 +4757,7 @@ typedef struct pcieMsiCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MULT_MSG_CAP\r
    * On rev 1 hw, this corresponds to MMC\r
+   * On rev 2 hw, this corresponds to PCI_MSI_MULTIPLE_MSG_CAP\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4202,6 +4769,7 @@ typedef struct pcieMsiCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI_EN\r
    * On rev 1 hw, this corresponds to MSI_EN\r
+   * On rev 2 hw, this corresponds to PCI_MSI_ENABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4213,6 +4781,7 @@ typedef struct pcieMsiCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to NEXT_CAP\r
    * On rev 1 hw, this corresponds to MSI_NX_PTR\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_NEXT_OFFSET\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -4222,6 +4791,7 @@ typedef struct pcieMsiCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to CAP_ID\r
    * On rev 1 hw, this corresponds to CAP_ID\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_ID\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -4235,6 +4805,7 @@ typedef struct pcieMsiCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI_LOW32 for EP and RC\r
  * On rev 1 hw, this corresponds to MSI_ADD_L32 for EP only\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_04H_REG for EP only\r
  *\r
  * @{\r
  */\r
@@ -4245,6 +4816,7 @@ typedef struct pcieMsiLo32Reg_s {
    *\r
    * On rev 0 hw, this corresponds to LOW32_ADDR\r
    * On rev 1 hw, this corresponds to ADDR\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_04H\r
    *\r
    * Field size: 30 bits\r
    *\r
@@ -4259,6 +4831,7 @@ typedef struct pcieMsiLo32Reg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI_UP32 for EP and RC\r
  * On rev 1 hw, this corresponds to MSI_ADD_L32 for EP only\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_08H_REG for EP only\r
  *\r
  * @{\r
  */\r
@@ -4269,6 +4842,7 @@ typedef struct pcieMsiUp32Reg_s {
    *\r
    * On rev 0 hw, this corresponds to UP32_ADDR\r
    * On rev 1 hw, this corresponds to ADDR\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_08H\r
    *\r
    * Field size: 32 bits\r
    *\r
@@ -4283,8 +4857,7 @@ typedef struct pcieMsiUp32Reg_s {
  *\r
  * On rev 0 hw, this corresponds to MSI_DATA for EP and RC\r
  * On rev 1 hw, this corresponds to MSI_DATA for EP only\r
- *\r
- * This register is only available for rev 0 hw.\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_0CH_REG for EP only\r
  *\r
  * @{\r
  */\r
@@ -4295,6 +4868,7 @@ typedef struct pcieMsiDataReg_s {
    *\r
    * On rev 0 hw, this corresponds to MSI_DATA\r
    * On rev 1 hw, this corresponds to DATA\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_0CH\r
    *\r
    * Field size: 16 bits\r
    *\r
@@ -4303,6 +4877,59 @@ typedef struct pcieMsiDataReg_s {
 } pcieMsiDataReg_t;\r
 /* @} */\r
 \r
+/**\r
+ * @ingroup pcielld_reg_cfg_msi_structures\r
+ * @brief Specification of the MSI_CAP_OFF_14H_REG Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_10H_REG for EP only\r
+ *\r
+ * This register is only available for rev 2 hw.\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pcieMsiCapOff10H {\r
+  uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] MSI data\r
+   *\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_10H\r
+   *\r
+   * Field size: 32 bits\r
+   *\r
+   */\r
+  uint32_t data;\r
+} pcieMsiCapOff10HReg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_cfg_msi_structures\r
+ * @brief Specification of the MSI Data Register\r
+ *\r
+ * On rev 0 hw, unsupported\r
+ * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to MSI_CAP_OFF_14H_REG for EP only\r
+ *\r
+ * This register is only available for rev 2 hw.\r
+ *\r
+ * @{\r
+ */\r
+typedef struct pcieMsiCapOff14H {\r
+  uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] MSI data\r
+   *\r
+   * On rev 2 hw, this corresponds to PCI_MSI_CAP_OFF_14H\r
+   *\r
+   * Field size: 32 bits\r
+   *\r
+   */\r
+  uint32_t data;\r
+} pcieMsiCapOff14HReg_t;\r
+/* @} */\r
+\r
+\r
 /*****************************************************************************\r
  **********  PCIe CAPABILITIES  REGISTERS ************************************\r
  ****************************************************************************/\r
@@ -4314,6 +4941,7 @@ typedef struct pcieMsiDataReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_CAP\r
  * On rev 1 hw, this corresponds to PCIE_CAP\r
+ * On rev 2 hw, this corresponds to PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG\r
  *\r
  * @{\r
  */\r
@@ -4324,6 +4952,7 @@ typedef struct pciePciesCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to INT_MSG\r
    * On rev 1 hw, this corresponds to IM_NUM\r
+   * On rev 2 hw, this corresponds to PCIE_INT_MSG_NUM\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -4333,6 +4962,7 @@ typedef struct pciePciesCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to SLT_IMPL_N\r
    * On rev 1 hw, this corresponds to SLOT\r
+   * On rev 2 hw, this corresponds to PCIE_SLOT_IMP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4346,6 +4976,7 @@ typedef struct pciePciesCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to DPORT_TYPE\r
    * On rev 1 hw, this corresponds to DEV_TYPE\r
+   * On rev 2 hw, this corresponds to PCIE_DEV_PORT_TYPE\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -4355,6 +4986,7 @@ typedef struct pciePciesCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PCIE_CAP\r
    * On rev 1 hw, this corresponds to PCIE_VER\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_REG\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -4364,6 +4996,7 @@ typedef struct pciePciesCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to NEXT_CAP\r
    * On rev 1 hw, this corresponds to PCIE_NX_PTR\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_NEXT_PTR\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -4373,6 +5006,7 @@ typedef struct pciePciesCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to CAP_ID\r
    * On rev 1 hw, this corresponds to CAP_ID\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ID\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -4388,6 +5022,7 @@ typedef struct pciePciesCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to DEVICE_CAP\r
  * On rev 1 hw, this corresponds to DEV_CAP\r
+ * On rev 2 hw, this corresponds to DEVICE_CAPABILITIES_REG\r
  *\r
  * @{\r
  */\r
@@ -4400,6 +5035,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to FLR_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_FLR_CAP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4409,6 +5045,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_LIMIT_SCALE\r
    * On rev 1 hw, this corresponds to CAPT_SLOW_PWRLIMIT_SCALE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -4418,6 +5055,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_LIMIT_VALUE\r
    * On rev 1 hw, this corresponds to CAPT_SLOW_PWRLIMIT_VALUE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -4427,6 +5065,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_RPT\r
    * On rev 1 hw, this corresponds to ROLEBASED_ERRRPT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ROLE_BASED_ERR_REPORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4436,6 +5075,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to L1_LATENCY\r
    * On rev 1 hw, this corresponds to DEFAULT_EP_L1_LATENCY\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EP_L1_ACCPT_LATENCY\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4445,6 +5085,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to L0_LATENCY\r
    * On rev 1 hw, this corresponds to DEFAULT_EP_L0S_LATENCY\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EP_L0S_ACCPT_LATENCY\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4454,6 +5095,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to EXT_TAG_FLD\r
    * On rev 1 hw, this corresponds to EXTTAGFIELD_SUPPORT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EXT_TAG_SUPP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4463,6 +5105,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PHANTOM_FLD\r
    * On rev 1 hw, this corresponds to PHANTOMFUNC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PHANTOM_FUNC_SUPPORT\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -4472,6 +5115,7 @@ typedef struct pcieDeviceCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MAX_PAYLD_SZ\r
    * On rev 1 hw, this corresponds to MAX_PAYLOAD_SIZE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MAX_PAYLOAD_SIZE\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4487,6 +5131,7 @@ typedef struct pcieDeviceCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to DEV_STAT_CTRL\r
  * On rev 1 hw, this corresponds to DEV_CAS\r
+ * On rev 2 hw, this corresponds to DEVICE_CONTROL_DEVICE_STATUS\r
  *\r
  * @{\r
  */\r
@@ -4497,6 +5142,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to TPEND\r
    * On rev 1 hw, this corresponds to TRANS_PEND\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_TRANS_PENDING\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4506,6 +5152,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to AUX_PWR\r
    * On rev 1 hw, this corresponds to AUXP_DET\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_AUX_POWER_DETECTED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4515,6 +5162,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to UNSUP_RQ_DET\r
    * On rev 1 hw, this corresponds to UR_DET\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_UNSUPPORTED_REQ_DETECTED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4524,6 +5172,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to FATAL_ERR\r
    * On rev 1 hw, this corresponds to FT_DET\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_FATAL_ERR_DETECTED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4533,6 +5182,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to NFATAL_ERR\r
    * On rev 1 hw, this corresponds to NFT_DET\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_NON_FATAL_ERR_DETECTED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4542,15 +5192,27 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to CORR_ERR\r
    * On rev 1 hw, this corresponds to COR_DET\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CORR_ERR_DETECTED\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t corrEr;\r
+  /**\r
+   * @brief [rw] Initiate Function Level Reset (for EP)\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 1 hw, this corresponds to PCIE_CAP_INITIATE_FLR\r
+   *\r
+   * Field size: 3 bits\r
+   */\r
+  uint8_t initFLR;\r
   /**\r
    * @brief [rw] Maximum Read Request Size\r
    *\r
    * On rev 0 hw, this corresponds to MAX_REQ_SZ\r
    * On rev 1 hw, this corresponds to MRRS\r
+   * On rev 1 hw, this corresponds to PCIE_CAP_MAX_READ_REQ_SIZE\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4560,6 +5222,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to NO_SNOOP\r
    * On rev 1 hw, this corresponds to NOSNP_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EN_NO_SNOOP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4568,7 +5231,8 @@ typedef struct pcieDevStatCtrlReg_s {
    * @brief [rw] AUX Power PM Enable\r
    *\r
    * On rev 0 hw, this corresponds to AUX_PWR_PM_EN\r
-   * On rev 1 hw, this corresponds to AUXPM_EN\r
+   * On rev 1 hw, this corresponds to AUXM_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_AUX_POWER_PM_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4578,6 +5242,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PHANTOM_EN\r
    * On rev 1 hw, this corresponds to PHFUN_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PHANTOM_FUNC_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4587,6 +5252,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to XTAG_FIELD_EN\r
    * On rev 1 hw, this corresponds to EXTAG_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EXT_TAG_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4596,6 +5262,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to MAX_PAYLD\r
    * On rev 1 hw, this corresponds to MPS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MAX_PAYLOAD_SIZE_CS\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4605,6 +5272,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to RELAXED\r
    * On rev 1 hw, this corresponds to EN_RO\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EN_REL_ORDER\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4614,6 +5282,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to UNSUP_REQ_RP\r
    * On rev 1 hw, this corresponds to UR_RE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_UNSUPPORT_REQ_REP_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4623,6 +5292,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to FATAL_ERR_RP\r
    * On rev 1 hw, this corresponds to FT_RE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_FATAL_ERR_REPORT_E\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4632,6 +5302,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to NFATAL_ERR_RP\r
    * On rev 1 hw, this corresponds to NFT_RE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_NON_FATAL_ERR_REPORT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4641,6 +5312,7 @@ typedef struct pcieDevStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to CORR_ERR_RP\r
    * On rev 1 hw, this corresponds to COR_RE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CORR_ERR_REPORT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4656,6 +5328,7 @@ typedef struct pcieDevStatCtrlReg_s {
  *\r
  * On rev 0 hw, this corresponds to LINK_CAP\r
  * On rev 1 hw, this corresponds to LNK_CAP\r
+ * On rev 2 hw, this corresponds to LINK_CAPABILITIES_REG\r
  *\r
  * @{\r
  */\r
@@ -4666,6 +5339,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PORT_NUM\r
    * On rev 1 hw, this corresponds to PORT_NUM\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PORT_NUM\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -4675,6 +5349,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, unsuppported\r
    * On rev 1 hw, this corresponds to ASPM_OPT_COMP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ASPM_OPT_COMPLIANCE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4687,6 +5362,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to BW_NOTIFY_CAP\r
    * On rev 1 hw, this corresponds to LNK_BW_NOT_CAP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_BW_NOT_CAP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4699,6 +5375,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLL_REP_CAP\r
    * On rev 1 hw, this corresponds to DLL_ACTRPT_CAP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_DLL_ACTIVE_REP_CAP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4708,6 +5385,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to DOWN_ERR_REP_CAP\r
    * On rev 1 hw, this corresponds to UNSUP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4724,6 +5402,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to CLK_PWR_MGMT\r
    * On rev 1 hw, this corresponds to CLK_PWR_MGMT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CLOCK_POWER_MAN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4745,6 +5424,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to L1_EXIT_LAT\r
    * On rev 1 hw, this corresponds to L1_EXIT_LAT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_L1_EXIT_LATENCY\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4766,6 +5446,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to L0S_EXIT_LAT\r
    * On rev 1 hw, this corresponds to L0S_EXIT_LAT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_L0S_EXIT_LATENCY\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -4779,6 +5460,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to AS_LINK_PM\r
    * On rev 1 hw, this corresponds to AS_LINK_PM_SUPPORT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -4792,6 +5474,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MAX_LINK_WIDTH\r
    * On rev 1 hw, this corresponds to MAX_LINK_WIDTH\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MAX_LINK_WIDTH\r
    *\r
    * Field size: 6 bits\r
    */\r
@@ -4805,6 +5488,7 @@ typedef struct pcieLinkCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MAX_LINK_SPEED\r
    * On rev 1 hw, this corresponds to MAX_LINK_SPEEDS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MAX_LINK_SPEED\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -4820,6 +5504,7 @@ typedef struct pcieLinkCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to LINK_STAT_CTRL\r
  * On rev 1 hw, this corresponds to LNK_CAS\r
+ * On rev 2 hw, this corresponds to LINK_CONTROL_LINK_STATUS_REG\r
  *\r
  * @{\r
  */\r
@@ -4839,6 +5524,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_BW_STATUS\r
    * On rev 1 hw, this corresponds to LAB_STATUS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_AUTO_BW_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4863,6 +5549,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_BW_MGMT_STATUS\r
    * On rev 1 hw, this corresponds to LBW_STATUS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_BW_MAN_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4876,6 +5563,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLL_ACTIVE\r
    * On rev 1 hw, this corresponds to DLL_ACT\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_DLL_ACTIVE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4888,6 +5576,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to SLOT_CLK_CFG\r
    * On rev 1 hw, this corresponds to SLOT_CLK_CONFIG\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SLOT_CLK_CONFIG\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4897,6 +5586,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_TRAINING\r
    * On rev 1 hw, this corresponds to LINK_TRAIN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_TRAINING\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4912,6 +5602,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to NEGOTIATED_LINK_WD\r
    * On rev 1 hw, this corresponds to NEG_LW\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_NEGO_LINK_WIDTH\r
    *\r
    * Field size: 6 bits\r
    */\r
@@ -4921,15 +5612,27 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_SPEED\r
    * On rev 1 hw, this corresponds to LINK_SPEED\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_SPEED\r
    *\r
    * Field size: 4 bits\r
    */\r
   uint8_t linkSpeed;\r
+  /**\r
+   * @brief [rw]  DRS Signalling Control\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_DRS_SIGNALING_CONTROL\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t drsSigCtrl;\r
   /**\r
    * @brief [rw]  Link Autonomous Bandwidth Interrupt Enable. Not applicable and is reserved for EP\r
    *\r
    * On rev 0 hw, this corresponds to LINK_BW_INT_EN\r
    * On rev 1 hw, this corresponds to LABIE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_AUTO_BW_INT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4939,6 +5642,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_BW_MGMT_INT_EN\r
    * On rev 1 hw, this corresponds to LBMIE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_BW_MAN_INT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4948,6 +5652,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to HW_AUTO_WIDTH_DIS\r
    * On rev 1 hw, this corresponds to HAWD\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_HW_AUTO_WIDTH_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4957,6 +5662,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to CLK_PWR_MGMT_EN\r
    * On rev 1 hw, this corresponds to EN_CPM\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EN_CLK_POWER_MAN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4966,6 +5672,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to EXT_SYNC\r
    * On rev 1 hw, this corresponds to EXT_SYN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EXTENDED_SYNCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4980,6 +5687,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to COMMON_CLK_CFG\r
    * On rev 1 hw, this corresponds to COM_CLK_CFG\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_COMMON_CLK_CONFIG\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4989,6 +5697,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to RETRAIN_LINK\r
    * On rev 1 hw, this corresponds to RETRAIN_LINK\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_RETRAIN_LINK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -4998,6 +5707,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_DISABLE\r
    * On rev 1 hw, this corresponds to LINK_DIS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5010,6 +5720,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to RCB\r
    * On rev 1 hw, this corresponds to RCB\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_RCB\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5024,6 +5735,7 @@ typedef struct pcieLinkStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to ACTIVE_LINK_PM\r
    * On rev 1 hw, this corresponds to ASPM_CTRL\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -5039,6 +5751,7 @@ typedef struct pcieLinkStatCtrlReg_s {
  *\r
  * On rev 0 hw, this corresponds to SLOT_CAP\r
  * On rev 1 hw, this corresponds to SLOT_CAP\r
+ * On rev 2 hw, this corresponds to SLOT_CAPABILITIES_REG\r
  *\r
  * @{\r
  */\r
@@ -5049,6 +5762,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to SLOT_NUM\r
    * On rev 1 hw, this corresponds to PSN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PHY_SLOT_NUM\r
    *\r
    * Field size: 13 bits [0-0x1FFF]\r
    */\r
@@ -5061,6 +5775,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMD_COMP_SUPP\r
    * On rev 1 hw, this corresponds to NCCS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_NO_CMD_CPL_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5073,6 +5788,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to EML_PRESENT\r
    * On rev 1 hw, this corresponds to EIP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ELECTROMECH_INTERLOCK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5082,6 +5798,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_LMT_SCALE\r
    * On rev 1 hw, this corresponds to SPLS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SLOT_POWER_LIMIT_SCALE\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -5091,6 +5808,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_LMT_VALUE\r
    * On rev 1 hw, this corresponds to SPLV\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SLOT_POWER_LIMIT_VALUE\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -5100,6 +5818,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to HP_CAP\r
    * On rev 1 hw, this corresponds to HPC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_HOT_PLUG_CAPABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5109,6 +5828,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to HP_SURPRISE\r
    * On rev 1 hw, this corresponds to HPS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_HOT_PLUG_SURPRISE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5118,6 +5838,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_IND\r
    * On rev 1 hw, this corresponds to PIP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_POWER_INDICATOR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5127,6 +5848,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to ATTN_IND\r
    * On rev 1 hw, this corresponds to AIP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_INDICATOR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5136,6 +5858,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to MRL_SENSOR\r
    * On rev 1 hw, this corresponds to MRLSP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5148,6 +5871,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_CTL\r
    * On rev 1 hw, this corresponds to PCP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_POWER_CONTROLLER\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5157,6 +5881,7 @@ typedef struct pcieSlotCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to ATTN_BUTTON\r
    * On rev 1 hw, this corresponds to ABP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_INDICATOR_BUTTON\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5172,6 +5897,7 @@ typedef struct pcieSlotCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to SLOT_STAT_CTRL\r
  * On rev 1 hw, this corresponds to SLOT_CAS\r
+ * On rev 2 hw, this corresponds to SLOT_CONTROL_SLOT_STATUS\r
  *\r
  * @{\r
  */\r
@@ -5184,6 +5910,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLL_STATE\r
    * On rev 1 hw, this corresponds to DSC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_DLL_STATE_CHANGED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5193,6 +5920,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to EM_LOCK\r
    * On rev 1 hw, this corresponds to EIS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5202,6 +5930,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRESENCE_DET\r
    * On rev 1 hw, this corresponds to PDS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PRESENCE_DETECT_STATE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5211,6 +5940,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to MRL_STATE\r
    * On rev 1 hw, this corresponds to MRLSS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR_STATE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5222,6 +5952,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMD_COMPLETE\r
    * On rev 1 hw, this corresponds to CC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CMD_CPLD\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5233,6 +5964,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRESENCE_CHG\r
    * On rev 1 hw, this corresponds to PDC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PRESENCE_DETECTED_CHANGED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5244,6 +5976,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to MRL_CHANGE\r
    * On rev 1 hw, this corresponds to MRCSC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR_CHANGED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5255,6 +5988,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_FAULT\r
    * On rev 1 hw, this corresponds to PFD\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_POWER_FAULT_DETECTED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5266,6 +6000,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to ATTN_PRESSED\r
    * On rev 1 hw, this corresponds to ABP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_BUTTON_PRESSED\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5275,6 +6010,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLL_CHG_EN\r
    * On rev 1 hw, this corresponds to DSC_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_DLL_STATE_CHANGED_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5284,6 +6020,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to EM_LOCK_CTL\r
    * On rev 1 hw, this corresponds to EIC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5293,6 +6030,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_CTL\r
    * On rev 1 hw, this corresponds to PCC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_POWER_INDICATOR_CTRL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5302,6 +6040,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PM_IND_CTL\r
    * On rev 1 hw, this corresponds to PIC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_POWER_INDICATOR_CTRL\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -5311,6 +6050,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to ATTN_IND_CTL\r
    * On rev 1 hw, this corresponds to AIC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_INDICATOR_CTR\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -5320,6 +6060,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to HP_INT_EN\r
    * On rev 1 hw, this corresponds to HPI_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_HOT_PLUG_INT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5329,6 +6070,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMD_CMP_INT_EN\r
    * On rev 1 hw, this corresponds to CCI_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CMD_CPL_INT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5338,6 +6080,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PRS_DET_CHG_EN\r
    * On rev 1 hw, this corresponds to PDC_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PRESENCE_DETECT_CHANGE_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5347,6 +6090,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to MRL_CHG_EN\r
    * On rev 1 hw, this corresponds to MRLSC_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_MRL_SENSOR_CHANGED_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5356,6 +6100,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to PWR_FLT_DET_EN\r
    * On rev 1 hw, this corresponds to PFD_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_POWER_FAULT_DETECTED_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5365,6 +6110,7 @@ typedef struct pcieSlotStatCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to ATTN_BUTT_EN\r
    * On rev 1 hw, this corresponds to ABP_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5380,6 +6126,7 @@ typedef struct pcieSlotStatCtrlReg_s {
  *\r
  * On rev 0 hw, this corresponds to ROOT_CTRL_CAP\r
  * On rev 1 hw, this corresponds to ROOT_CAC\r
+ * On rev 2 hw, this corresponds to ROOT_CONTROL_ROOT_CAPABILITIES_REG\r
  *\r
  * @{\r
  */\r
@@ -5390,6 +6137,7 @@ typedef struct pcieRootCtrlCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to CRS_SW\r
    * On rev 1 hw, this corresponds to CRSSV\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CRS_SW_VISIBILITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5399,6 +6147,7 @@ typedef struct pcieRootCtrlCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to CRS_SW_EN\r
    * On rev 1 hw, this corresponds to CRSSV_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CRS_SW_VISIBILITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5408,6 +6157,7 @@ typedef struct pcieRootCtrlCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_INT_EN\r
    * On rev 1 hw, this corresponds to PMEI_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PME_INT_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5417,6 +6167,7 @@ typedef struct pcieRootCtrlCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to SERR_FATAL_ERR\r
    * On rev 1 hw, this corresponds to SEFE_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5426,6 +6177,7 @@ typedef struct pcieRootCtrlCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to SERR_NFATAL_ERR\r
    * On rev 1 hw, this corresponds to SENE_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5435,6 +6187,7 @@ typedef struct pcieRootCtrlCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to SERR_EN\r
    * On rev 1 hw, this corresponds to SECE_EN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5450,6 +6203,7 @@ typedef struct pcieRootCtrlCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to ROOT_STATUS\r
  * On rev 1 hw, this corresponds to ROOT_STS\r
+ * On rev 2 hw, this corresponds to ROOT_STATUS_REG\r
  *\r
  * @{\r
  */\r
@@ -5460,6 +6214,7 @@ typedef struct pcieRootStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_PEND\r
    * On rev 1 hw, this corresponds to PME_PND\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PME_PENDING\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5471,6 +6226,7 @@ typedef struct pcieRootStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_STATUS\r
    * On rev 1 hw, this corresponds to PME_STS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PME_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5482,6 +6238,7 @@ typedef struct pcieRootStatusReg_s {
    *\r
    * On rev 0 hw, this corresponds to PME_REQ_ID\r
    * On rev 1 hw, this corresponds to PME_RID\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_PME_REQ\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -5498,6 +6255,7 @@ typedef struct pcieRootStatusReg_s {
  *\r
  * On rev 0 hw, this corresponds to DEV_CAP2\r
  * On rev 1 hw, this corresponds to DEV_CAP_2\r
+ * On rev 2 hw, this corresponds to DEVICE_CAPABILITIES2_REG\r
  *\r
  * @{\r
  */\r
@@ -5508,6 +6266,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TO_DIS_SUPP\r
    * On rev 1 hw, this corresponds to CPL_TIMEOUT_DIS_SUPPORTED\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5517,6 +6276,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TO_EN\r
    * On rev 1 hw, this corresponds to CPL_TIMEOUT_RNG_SUPPORTED\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_RANGE\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -5526,6 +6286,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to ARI_FWD_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ARI_FORWARD_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5535,6 +6296,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to AOR_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ATOMIC_ROUTING_SUPP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5544,6 +6306,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to AOC32_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_32_ATOMIC_CPL_SUPP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5553,6 +6316,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to AOC64_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_64_ATOMIC_CPL_SUPP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5562,6 +6326,7 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to CASC128_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_128_CAS_CPL_SUPP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5571,30 +6336,84 @@ typedef struct pcieDevCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to NOROPR\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_NO_RO_EN_PR2PR_PAR\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t noRoPR;\r
+  /**\r
+   * @brief [ro] LTR Mechanism Supported\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LTR_SUPP\r
+   *\r
+   * Field size: 2 bit\r
+   */\r
+  uint8_t ltrSupp;\r
   /**\r
    * @brief [ro] TPH Completer Supported\r
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to TPHC_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_TPH_CMPLT_SUPPORT_0 | PCIE_CAP_TPH_CMPLT_SUPPORT_1\r
    *\r
-   * Field size: 1 bit\r
+   * Field size: 2 bit\r
    */\r
   uint8_t tphcSp;\r
-} pcieDevCap2Reg_t;\r
-/* @} */\r
-\r
-/**\r
- * @ingroup pcielld_reg_cfg_cap_structures\r
+  /**\r
+   * @brief [ro] LN System CLS\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCIE_CAP2_LN_SYS_CLS\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t lnSysCls;\r
+  /**\r
+   * @brief [ro] 10-Bit Tag Completer Supported (ep only)\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t tag10bitCompSupp;\r
+  /**\r
+   * @brief [ro] 10-Bit Tag Requester Supported\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t tag10bitReqSupp;\r
+  /**\r
+   * @brief [ro] [OBFF] Optimized Buffer Flush/fill Supported\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_OBFF_SUPPORT\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t obffSupp;\r
+\r
+} pcieDevCap2Reg_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_reg_cfg_cap_structures\r
  * @brief Specification of the Device Status and Control Register 2\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
  * On rev 0 hw, this corresponds to DEV_STAT_CTRL2\r
  * On rev 1 hw, this corresponds to DEV_CAS_2\r
+ * On rev 2 hw, this corresponds to DEVICE_CONTROL2_DEVICE_STATUS2_REG\r
  *\r
  * @{\r
  */\r
@@ -5605,6 +6424,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TO_DIS\r
    * On rev 1 hw, this corresponds to CPL_TIMEOUT_DIS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5631,6 +6451,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TO\r
    * On rev 1 hw, this corresponds to CPL_TIMEOUT_VALUE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CPL_TIMEOUT_VALUE\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -5640,6 +6461,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to ARI_FWD_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ARI_FORWARD_SUPPORT_CS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5649,6 +6471,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to AOP_REQ_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5658,6 +6481,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to AOP_EG_BLK\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5667,6 +6491,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to IDO_REQ_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5676,6 +6501,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to IDO_CPL_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5685,6 +6511,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to LTR_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5694,6 +6521,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to OBFF_EN\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5709,6 +6537,7 @@ typedef struct pcieDevStatCtrl2Reg_s {
  *\r
  * On rev 0 hw, unsupported\r
  * On rev 1 hw, this corresponds to LNK_CAP_2\r
+ * On rev 2 hw, this corresponds to LINK_CAPABILITIES2_REG\r
  *\r
  * @{\r
  */\r
@@ -5720,6 +6549,7 @@ typedef struct pcieLnkCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to SP_LS_VEC\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR\r
    *\r
    * Field size: 7 bits\r
    */\r
@@ -5729,6 +6559,7 @@ typedef struct pcieLnkCap2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to CROSSLINK_SP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CROSS_LINK_SUPPORT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5743,6 +6574,7 @@ typedef struct pcieLnkCap2Reg_s {
  *\r
  * On rev 0 hw, this corresponds to LINK_CTRL2\r
  * On rev 1 hw, this corresponds to LNK_CAS_2\r
+ * On rev 2 hw, this corresponds to LINK_CONTROL2_LINK_STATUS2_REG\r
  *\r
  * @{\r
  */\r
@@ -5756,6 +6588,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to DE_EMPH\r
    * On rev 1 hw, this corresponds to DEEMPH_LEVEL\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_CURR_DEEMPHASIS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5770,7 +6603,8 @@ typedef struct pcieLinkCtrl2Reg_s {
    * 1 = -3.5 dB\r
    *\r
    * On rev 0 hw, this corresponds to POLL_DEEMPH\r
-   * On rev 1 hw, this corresponds to COMPL_PRST_DEEMPH\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5783,6 +6617,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_SOS\r
    * On rev 1 hw, this corresponds to COMPL_SOS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_COMPLIANCE_SOS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5795,6 +6630,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to ENTR_MOD_COMPL\r
    * On rev 1 hw, this corresponds to ENT_MOD_COMPL\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ENTER_MODIFIED_COMPLIANCE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5804,6 +6640,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TX_MARGIN\r
    * On rev 1 hw, this corresponds to TX_MARGIN\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_TX_MARGIN\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -5820,6 +6657,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to SEL_DEEMPH\r
    * On rev 1 hw, this corresponds to SEL_DEEMP\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_SEL_DEEMPHASIS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5834,6 +6672,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to HW_AUTO_SPEED_DIS\r
    * On rev 1 hw, this corresponds to HW_AUTO_SP_DIS\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_HW_AUTO_SPEED_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5847,6 +6686,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to ENTR_COMPL\r
    * On rev 1 hw, this corresponds to ENTR_COMPL\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_ENTER_COMPLIANCE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5860,6 +6700,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TGT_SPEED\r
    * On rev 1 hw, this corresponds to TRGT_LINK_SPEED\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_TARGET_LINK_SPEED\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -5869,6 +6710,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to COMPL_PRST_DEEMPH\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_COMPLIANCE_PRESET\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -5878,6 +6720,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to EQ_COMPLETE\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5887,6 +6730,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to EQ_PH1\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL_P1\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5896,6 +6740,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to EQ_PH2\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL_P2\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5905,6 +6750,7 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to EQ_PH3\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_EQ_CPL_P3\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5914,10 +6760,31 @@ typedef struct pcieLinkCtrl2Reg_s {
    *\r
    * On rev 0 hw, unsupported\r
    * On rev 1 hw, this corresponds to LINK_EQ_REQ\r
+   * On rev 2 hw, this corresponds to PCIE_CAP_LINK_EQ_REQ\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t linkEqReq;\r
+  /**\r
+   * @brief [rw] Downstream Component Presence\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to DOWNSTREAM_COMPO_PRESENCE\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t downCompPres;\r
+  /**\r
+   * @brief [rw] DRS Message Received\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to DRS_MESSAGE_RECEIVED\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t drsMsgRecv;\r
 } pcieLinkCtrl2Reg_t;\r
 /* @} */\r
 \r
@@ -5933,6 +6800,7 @@ typedef struct pcieLinkCtrl2Reg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_EXTCAP\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to AER_EXT_CAP_HDR_OFF\r
  *\r
  * @{\r
  */\r
@@ -5943,6 +6811,7 @@ typedef struct pcieExtCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to NEXT_CAP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to NEXT_OFFSET\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -5952,6 +6821,7 @@ typedef struct pcieExtCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to EXT_CAP_VER\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CAP_VERSION\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -5961,6 +6831,7 @@ typedef struct pcieExtCapReg_s {
    *\r
    * On rev 0 hw, this corresponds to EXT_CAP_ID\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CAP_ID\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -5976,11 +6847,36 @@ typedef struct pcieExtCapReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_UNCERR\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNCORR_ERR_STATUS_OFF\r
  *\r
  * @{\r
  */\r
 typedef struct pcieUncErrReg_s {\r
   uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+   * @brief [rw] TLP Prefix Blocked Error Status\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to TLP_PRFX_BLOCKED_ERR_STATUS\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t tlpPrfxBlockedErrSt;\r
+  /**\r
+   * @brief [rw] Uncorrectable Internal Error Status\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INTERNAL_ERR_STATUS\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t intErrSt;\r
   /**\r
    * @brief [rw] Unsupported Request Error Status\r
    *\r
@@ -5988,6 +6884,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to UR_ERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to UNSUPPORTED_REQ_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -5999,6 +6896,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ECRC_ERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6010,6 +6908,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to MTLP_ERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MALF_TLP_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6021,6 +6920,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVR_OF_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to REC_OVERFLOW_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6032,6 +6932,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to UCMP_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to UNEXP_CMPLT_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6043,6 +6944,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_ABRT_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CMPLT_ABORT_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6054,6 +6956,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TMOT_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CMPLT_TIMEOUT_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6065,6 +6968,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to FCP_ERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FC_PROTOCOL_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6076,6 +6980,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to PSND_TLP_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to POIS_TLP_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6085,6 +6990,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to SRPS_DN_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to SURPRISE_DOWN_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6096,6 +7002,7 @@ typedef struct pcieUncErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLP_ERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to DL_PROTOCOL_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6111,16 +7018,50 @@ typedef struct pcieUncErrReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_UNCERR_MASK\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNCORR_ERR_MASK_OFF\r
  *\r
  * @{\r
  */\r
 typedef struct pcieUncErrMaskReg_s {\r
   uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+   * @brief [ro] TLP Prefix Blocked Error Mask\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to TLP_PRFX_BLOCKED_ERR_MASK\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t tlpPrfxBlockedErrMsk;\r
+ /**\r
+   * @brief [ro] AtomicOp Egress Block Mask\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ATOMIC_EGRESS_BLOCKED_ERR_MASK\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t atomicEgressBlockedErrMsk;\r
+  /**\r
+   * @brief [rw] Uncorrectable Internal Error Mask\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INTERNAL_ERR_MASK\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t intErrMsk;\r
   /**\r
    * @brief [rw] Unsupported Request Error Mask\r
    *\r
    * On rev 0 hw, this corresponds to UR_ERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to UNSUPPORTED_REQ_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6130,6 +7071,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to ECRC_ERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6139,6 +7081,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to MTLP_ERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MALF_TLP_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6148,6 +7091,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVR_OF_MASK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to REC_OVERFLOW_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6157,6 +7101,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to UCMP_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to NEXP_CMPLT_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6166,6 +7111,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_ABRT_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CMPLT_ABORT_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6175,6 +7121,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TMOT_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CMPLT_TIMEOUT_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6184,6 +7131,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to FCP_ERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FC_PROTOCOL_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6193,6 +7141,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to PSND_TLP_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to POIS_TLP_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6202,6 +7151,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to SRPS_DN_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to SURPRISE_DOWN_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6211,6 +7161,7 @@ typedef struct pcieUncErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLP_ERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to DL_PROTOCOL_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6229,11 +7180,44 @@ typedef struct pcieUncErrMaskReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_UNCERR_SVRTY\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to UNCORR_ERR_SEV_OFF\r
  *\r
  * @{\r
  */\r
 typedef struct pcieUncErrSvrtyReg_s {\r
   uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+ /**\r
+   * @brief [ro] TLP Prefix Blocked Error Mask\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to TLP_PRFX_BLOCKED_ERR_SEVERITY\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t tlpPrfxBlockedErrSvrty;\r
+ /**\r
+   * @brief [ro] AtomicOp Egress Block Mask\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t atomicEgressBlockedErrSvrty;\r
+  /**\r
+   * @brief [rw] Uncorrectable Internal Error Mask\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INTERNAL_ERR_SEVERITY\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t intErrSvrty;\r
   /**\r
    * @brief [rw] Unsupported Request Error Severity\r
    *\r
@@ -6241,6 +7225,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to UR_ERR_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to UNSUPPORTED_REQ_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6252,6 +7237,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to ECRC_ERR_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6263,6 +7249,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to MTLP_ERR_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MALF_TLP_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6274,6 +7261,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVR_OF_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to REC_OVERFLOW_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6285,6 +7273,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to UCMP_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to UNEXP_CMPLT_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6296,6 +7285,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_ABRT_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CMPLT_ABORT_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6307,6 +7297,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to CMPL_TMOT_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CMPLT_TIMEOUT_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6318,6 +7309,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to FCP_ERR_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FC_PROTOCOL_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6329,6 +7321,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to PSND_TLP_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to POIS_TLP_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6340,6 +7333,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to SRPS_DN_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to SURPRISE_DOWN_ERR_SVRITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6351,6 +7345,7 @@ typedef struct pcieUncErrSvrtyReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLP_ERR_SVRTY\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to DL_PROTOCOL_ERR_SEVERITY\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6366,11 +7361,36 @@ typedef struct pcieUncErrSvrtyReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_CERR\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORR_ERR_STATUS_OFF\r
  *\r
  * @{\r
  */\r
 typedef struct pcieCorErrReg_s {\r
   uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Header Log Overflow Error Status\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to HEADER_LOG_OVERFLOW_STATUS\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t hdrLogOverflowErrSt;\r
+  /**\r
+   * @brief [rw] Corrected Internal Error Status\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CORRECTED_INT_ERR_STATUS\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t corrIntErrSt;\r
   /**\r
    * @brief [rw] Advisory Non-Fatal Error Status\r
    *\r
@@ -6381,6 +7401,7 @@ typedef struct pcieCorErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ADV_NFERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ADVISORY_NON_FATAL_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6392,6 +7413,7 @@ typedef struct pcieCorErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to RPLY_TMR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RPL_TIMER_TIMEOUT_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6403,6 +7425,7 @@ typedef struct pcieCorErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to RPLT_RO_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to REPLAY_NO_ROLEOVER_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6414,6 +7437,7 @@ typedef struct pcieCorErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to BAD_DLLP_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to BAD_DLLP_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6425,6 +7449,7 @@ typedef struct pcieCorErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to BAD_TLP_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to BAD_TLP_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6436,6 +7461,7 @@ typedef struct pcieCorErrReg_s {
    *\r
    * On rev 0 hw, this corresponds to RCV_ERR_ST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_ERR_STATUS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6451,16 +7477,42 @@ typedef struct pcieCorErrReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_CERR_MASK\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to CORR_ERR_MASK_OFF\r
  *\r
  * @{\r
  */\r
 typedef struct pcieCorErrMaskReg_s {\r
   uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
-    /**\r
+  /**\r
+   * @brief [rw] Header Log Overflow Error Status\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to HEADER_LOG_OVERFLOW_MASK\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t hdrLogOverflowErrMsk;\r
+  /**\r
+   * @brief [rw] Corrected Internal Error Status\r
+   *\r
+   * Write 1 to clear\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CORRECTED_INT_ERR_MASK\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t corrIntErrMsk;\r
+  /**\r
    * @brief [rw] Advisory Non-Fatal Error Mask\r
    *\r
    * On rev 0 hw, this corresponds to ADV_NFERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ADVISORY_NON_FATAL_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6470,6 +7522,7 @@ typedef struct pcieCorErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to RPLY_TMR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RPL_TIMER_TIMEOUT_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6479,6 +7532,7 @@ typedef struct pcieCorErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to RPLT_RO_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to REPLAY_NO_ROLEOVER_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6488,6 +7542,7 @@ typedef struct pcieCorErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to BAD_DLLP_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to BAD_DLLP_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6497,6 +7552,7 @@ typedef struct pcieCorErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to BAD_TLP_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to BAD_TLP_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6506,6 +7562,7 @@ typedef struct pcieCorErrMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVR_ERR_MSK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_ERR_MASK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -6524,16 +7581,38 @@ typedef struct pcieCorErrMaskReg_s {
  *\r
  * On rev 0 hw, this corresponds to PCIE_ACCR\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ADV_ERR_CAP_CTRL_OFF\r
  *\r
  * @{\r
  */\r
 typedef struct pcieAccrReg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [ro] Multiple Header Recording Enable\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MULTIPLE_HEADER_EN\r
+   *\r
+   * Field size:  1bit\r
+   */\r
+  uint8_t multHdrEn;\r
+  /**\r
+   * @brief [ro] Multiple Header Recording Capable\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MULTIPLE_HEADER_CAP\r
+   *\r
+   * Field size:  1bit\r
+   */\r
+  uint8_t multHdrCap;\r
   /**\r
    * @brief [rw] ECRC Check Enable\r
    *\r
    * On rev 0 hw, this corresponds to ECRC_CHK_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_CHK_EN\r
    *\r
    * Field size:  1bit\r
    */\r
@@ -6543,6 +7622,7 @@ typedef struct pcieAccrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ECRC_CHK_CAP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_CHK_CAP\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6552,6 +7632,7 @@ typedef struct pcieAccrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ECRC_GEN_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_GEN_EN\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6561,6 +7642,7 @@ typedef struct pcieAccrReg_s {
    *\r
    * On rev 0 hw, this corresponds to ECRC_GEN_CAP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ECRC_GEN_CAP\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6573,6 +7655,7 @@ typedef struct pcieAccrReg_s {
    *\r
    * On rev 0 hw, this corresponds to FRST_ERR_PTR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FIRST_ERR_POINTER\r
    *\r
    * Field size:  5 bits\r
    */\r
@@ -6590,6 +7673,7 @@ typedef struct pcieAccrReg_s {
  *\r
  * On rev 0 hw, this corresponds to HDR_LOGn (n = 0..3)\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to HDR_LOG_n_OFF (n = 0..3)\r
  *\r
  * @{\r
  */\r
@@ -6600,7 +7684,9 @@ typedef struct pcieHdrLogReg_s {
    *\r
    * On rev 0 hw, this corresponds to HDR_DWn (n = 0..3)\r
    * On rev 1 hw, unsupported\r
-   *\r
+   * On rev 2 hw, this corresponds to (n=FIRST..FOURTH)\r
+   *              (n_DWORD_FOURTH_BYTE << 24) | (n_DWORD_THIRD_BYTE << 16) |\r
+   *              (n_DWORD_SECOND_BYTE << 8 ) | (n_DWORD_FIRST_BYTE << 0 )\r
    * Field size: 32 bits\r
    */\r
   uint32_t hdrDW;\r
@@ -6615,6 +7701,7 @@ typedef struct pcieHdrLogReg_s {
  *\r
  * On rev 0 hw, this corresponds to ROOT_ERR_CMD\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ROOT_ERR_CMD_OFF (root complex only)\r
  *\r
  * @{\r
  */\r
@@ -6625,6 +7712,7 @@ typedef struct pcieRootErrCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to FERR_RPT_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FATAL_ERR_REPORTING_EN\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6634,6 +7722,7 @@ typedef struct pcieRootErrCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to NFERR_RPT_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to NON_FATAL_ERR_REPORTING_EN\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6643,6 +7732,7 @@ typedef struct pcieRootErrCmdReg_s {
    *\r
    * On rev 0 hw, this corresponds to CERR_RPT_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to CORR_ERR_REPORTING_EN\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6658,6 +7748,7 @@ typedef struct pcieRootErrCmdReg_s {
  *\r
  * On rev 0 hw, this corresponds to ROOT_ERR_ST\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ROOT_ERR_STATUS_OFF (root complex only)\r
  *\r
  * @{\r
  */\r
@@ -6668,6 +7759,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to AER_INT_MSG\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ADV_ERR_INT_MSG_NUM\r
    *\r
    * Field size:  5 bits\r
    */\r
@@ -6679,6 +7771,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to FERR_RCV\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to _FATAL_ERR_MSG_RX\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6690,6 +7783,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to NFERR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to NON_FATAL_ERR_MSG_RX\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6701,6 +7795,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to UNCOR_FATAL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to FIRST_UNCORR_FATAL\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6712,6 +7807,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to MULT_FNF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MUL_ERR_FATAL_NON_FATAL_RX\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6723,6 +7819,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to ERR_FNF\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_FATAL_NON_FATAL_RX\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6734,6 +7831,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to MULT_COR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MUL_ERR_COR_RX\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6745,6 +7843,7 @@ typedef struct pcieRootErrStReg_s {
    *\r
    * On rev 0 hw, this corresponds to CORR_ERR\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_COR_RX\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6763,6 +7862,7 @@ typedef struct pcieRootErrStReg_s {
  *\r
  * On rev 0 hw, this corresponds to ERR_SRC_ID\r
  * On rev 1 hw, unsupported\r
+ * On rev 2 hw, this corresponds to ERR_SRC_ID_OFF\r
  *\r
  * @{\r
  */\r
@@ -6773,6 +7873,7 @@ typedef struct pcieErrSrcIDReg_s {
    *\r
    * On rev 0 hw, this corresponds to FNF_SRC_ID\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_FATAL_NON_FATAL_SOURCE_ID\r
    *\r
    * Field size:  16 bits\r
    */\r
@@ -6782,6 +7883,7 @@ typedef struct pcieErrSrcIDReg_s {
    *\r
    * On rev 0 hw, this corresponds to CORR_SRC_ID\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ERR_COR_SOURCE_ID\r
    *\r
    * Field size:  16 bits\r
    */\r
@@ -6798,6 +7900,7 @@ typedef struct pcieErrSrcIDReg_s {
  *\r
  * On rev 0 hw, this corresponds to PL_ACKTIMER\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_LAT_REL_TIM\r
+ * On rev 2 hw, this corresponds to ACK_LATENCY_TIMER_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -6833,6 +7936,8 @@ typedef struct pciePlAckTimerReg_s {
    * This is for additional internal processing for received\r
    * TLPs and transmitted DLLPs.\r
    *\r
+   * For rev 2 hw: REPLAY_TIME_LIMIT\r
+   *\r
    * Field size:  16 bits\r
    */\r
   uint16_t rplyLmt;\r
@@ -6862,6 +7967,8 @@ typedef struct pciePlAckTimerReg_s {
    * This is for additional internal processing for received\r
    * TLPs and transmitted DLLPs.\r
    *\r
+   * For rev 2 hw: ROUND_TRIP_LATENCY_TIME_LIMIT\r
+   *\r
    * Field size:  16 bits\r
    */\r
   uint16_t rndTrpLmt;\r
@@ -6874,6 +7981,7 @@ typedef struct pciePlAckTimerReg_s {
  *\r
  * On rev 0 hw, this corresponds to PL_OMSG\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_VENDOR_SPECIFIC_DLLP\r
+ * On rev 2 hw, this corresponds to VENDOR_SPEC_DLLP_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -6890,6 +7998,7 @@ typedef struct pciePlOMsgReg_s {
    *\r
    * On rev 0 hw, this corresponds to OMSG\r
    * On rev 1 hw, this corresponds to PCIECTRL_PL_VENDOR_SPECIFIC_DLLP.\r
+   * On rev 2 hw, this corresponds to VENDOR_SPEC_DLLP.\r
    *\r
    * Field size:  32 bits\r
    */\r
@@ -6903,6 +8012,7 @@ typedef struct pciePlOMsgReg_s {
  *\r
  * On rev 0 hw, this corresponds to PL_FORCE_LINK\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_PT_LNK_R\r
+ * On rev 2 hw, this corresponds to PORT_FORCE_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -6915,10 +8025,26 @@ typedef struct pciePlForceLinkReg_s {
    *\r
    * On rev 0 hw, this corresponds to LPE_CNT\r
    * On rev 1 hw, this corresponds to LOW_POWER_ENTR_CNT.\r
+   * On rev 2 hw, this is reserved.\r
    *\r
    * Field size:  8 bits\r
    */\r
   uint8_t lpeCnt;\r
+  /**\r
+   * @brief [rw] Do Deskew for SRIS\r
+   *\r
+   * Use the transitions from TS2 to Logical Idle Symbol, SKP OS to\r
+   * Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew\r
+   * for SRIS instead of using received SKP OS if\r
+   * doDeskewForSris is set to 1\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 0 & 1 hw, this is reserved\r
+   * On rev 2 hw, this corresponds to DO_DESKEW_FOR_SRIS\r
+   *\r
+   * Field size:  1 bits\r
+   */\r
+  uint8_t doDeskewForSris;\r
   /**\r
    * @brief [rw] Link State.\r
    *\r
@@ -6928,6 +8054,7 @@ typedef struct pciePlForceLinkReg_s {
    *\r
    * On rev 0 hw, this corresponds to LNK_STATE\r
    * On rev 1 hw, this corresponds to FORCED_LINK_COMMAND\r
+   * On rev 2 hw, this corresponds to LINK_STATE\r
    *\r
    * Field size:  6 bits\r
    */\r
@@ -6940,6 +8067,7 @@ typedef struct pciePlForceLinkReg_s {
    *\r
    * on rev 0 hw, this corresponds to FORCE_LINK\r
    * on rev 1 hw, this corresponds to FORCE_LINK\r
+   * on rev 2 hw, this corresponds to FORCE_EN\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -6949,6 +8077,7 @@ typedef struct pciePlForceLinkReg_s {
    *\r
    * on rev 0 hw: unsupported\r
    * on rev 1 hw, this corresponds to FORCED_LTSSM_STATE\r
+   * on rev 2 hw, this corresponds to FORCED_LTSSM\r
    *\r
    * Field size:  4 bits\r
    */\r
@@ -6958,6 +8087,7 @@ typedef struct pciePlForceLinkReg_s {
    *\r
    * on rev 0 hw, this corresponds to LINK_NUM\r
    * on rev 1 hw, this corresponds to LINK_NUM\r
+   * on rev 2 hw, this corresponds to LINK_NUM\r
    *\r
    * Field size:  8 bits\r
    */\r
@@ -6971,6 +8101,7 @@ typedef struct pciePlForceLinkReg_s {
  *\r
  * On rev 0 hw, this corresponds to ACK_FREQ\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_ACK_FREQ_ASPM\r
+ * On rev 2 hw, this corresponds to ACK_F_ASPM_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -6987,6 +8118,7 @@ typedef struct pcieAckFreqReg_s {
    *\r
    * on rev 0 hw, this corresponds to ASPM_L1\r
    * on rev 1 hw, this corresponds to L1_ENTR_WO_L0S\r
+   * on rev 2 hw, this corresponds to ENTER_ASPM\r
    *\r
    * Field size:  1 bit\r
    */\r
@@ -7010,6 +8142,7 @@ typedef struct pcieAckFreqReg_s {
    *\r
    * on rev 0 hw, this corresponds to L1_ENTRY_LATENCY\r
    * on rev 1 hw, this corresponds to L1_ENTR_LAT\r
+   * on rev 2 hw, this corresponds to L1_ENTRANCE_LATENCY\r
    *\r
    * Field size:  3 bits\r
    */\r
@@ -7034,6 +8167,7 @@ typedef struct pcieAckFreqReg_s {
    *\r
    * on rev 0 hw, this corresponds to L0S_ENTRY_LATENCY\r
    * on rev 1 hw, this corresponds to L0S_ENTR_LAT\r
+   * on rev 2 hw, this corresponds to L0S_ENTRANCE_LATENCY\r
    *\r
    * Field size:  3 bits\r
    */\r
@@ -7046,6 +8180,7 @@ typedef struct pcieAckFreqReg_s {
    *\r
    * On rev 0 hw, this corresponds to COMM_NFTS\r
    * On rev 1 hw, this corresponds to COMMON_CLK_N_FTS\r
+   * On rev 2 hw, this corresponds to COMMON_CLK_N_FTS\r
    *\r
    * Field size:  8 bits\r
    */\r
@@ -7058,6 +8193,7 @@ typedef struct pcieAckFreqReg_s {
    *\r
    * On rev 0 hw, this corresponds to NFTS\r
    * On rev 1 hw, this corresponds to N_FTS\r
+   * On rev 2 hw, this corresponds to ACK_N_FTS\r
    *\r
    * Field size:  8 bits\r
    */\r
@@ -7069,6 +8205,7 @@ typedef struct pcieAckFreqReg_s {
    *\r
    * On rev 0 hw, this corresponds to ACK_FREQ\r
    * On rev 1 hw, this corresponds to ACK_FREQ\r
+   * On rev 2 hw, this corresponds to ACK_FREQ\r
    *\r
    * Field size:  8 bits\r
    */\r
@@ -7082,6 +8219,7 @@ typedef struct pcieAckFreqReg_s {
  *\r
  * On rev 0 hw, this corresponds to PL_LINK_CTRL\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_PT_LNK_CTRL_R\r
+ * On rev 2 hw, this corresponds to PORT_LINK_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7094,6 +8232,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw: unsupported\r
    * On rev 1 hw, this corresponds to CROSSLINK_ACT\r
+   * On rev 2 hw: unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7103,6 +8242,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw: unsupported\r
    * On rev 1 hw, this corresponds to CROSSLINK_EN\r
+   * On rev 2 hw: unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7123,6 +8263,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LNK_MODE\r
    * On rev 1 hw, this corresponds to LINK_MODE\r
+   * On rev 2 hw, this corresponds to LINK_CAPABLE\r
    *\r
    * Field size: 6 bits\r
    */\r
@@ -7134,6 +8275,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_RATE\r
    * On rev 1 hw: unsupported.\r
+   * On rev 2 hw: unsupported.\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -7145,6 +8287,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to FLNK_MODE\r
    * On rev 1 hw, this corresponds to FAST_LINK\r
+   * On rev 2 hw, this corresponds to FAST_LINK_MODE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7156,6 +8299,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to DLL_EN\r
    * On rev 1 hw, this corresponds to DL_EN\r
+   * On rev 2 hw, this corresponds to DLL_LINK_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7168,6 +8312,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to RST_ASRT\r
    * On rev 1 hw, this corresponds to RESET_ASSERT\r
+   * On rev 2 hw, this corresponds to RESET_ASSERT\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7177,6 +8322,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to LPBK_EN\r
    * On rev 1 hw, this corresponds to LB_EN\r
+   * On rev 2 hw, this corresponds to LOOPBACK_ENABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7186,6 +8332,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to SCRM_DIS\r
    * On rev 1 hw, this corresponds to SCRAMBLE_DIS\r
+   * On rev 2 hw, this corresponds to SCRAMBLE_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7197,6 +8344,7 @@ typedef struct pcieLnkCtrlReg_s {
    *\r
    * On rev 0 hw, this corresponds to OMSG_REQ\r
    * On rev 1 hw, this corresponds to VEN_DLLP_REQ\r
+   * On rev 2 hw, this corresponds to VENDOR_SPECIFIC_DLLP_REQ\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7210,6 +8358,7 @@ typedef struct pcieLnkCtrlReg_s {
  *\r
  * On rev 0 hw, this corresponds to LANE_SKEW\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_LN_SKW_R\r
+ * On rev 2 hw, this corresponds to LANE_SKEW_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7222,15 +8371,45 @@ typedef struct pcieLaneSkewReg_s {
    *\r
    * On rev 0 hw, this corresponds to L2L_DESKEW\r
    * On rev 1 hw, this corresponds to DIS_L2L_SKEW\r
+   * On rev 2 hw, this corresponds to DISABLE_LANE_TO_LANE_DESKEW\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t l2Deskew;\r
+  /**\r
+   * @brief [rw] Set lanes allowed for loopback\r
+   *\r
+   * Implementation-specific Number of Lanes Set the implementation specific\r
+   * number of lanes\r
+   * Allowed values are:\r
+   * 0000b: 1 lane\r
+   * 0001b: 2 lanes\r
+   * 0011b: 4 lanes\r
+   * 0111b: 8 lanes\r
+   * 1111b: 16 lanes\r
+   * The number of lanes to be used when in Loopback\r
+   * Master The number of lanes programmed must be equal to or less\r
+   * than the valid number of lanes set in LINK_CAPABLE field You must\r
+   * configure this field before initiating Loopback by writing in the\r
+   * LOOPBACK_ENABLE field The controller will transition from\r
+   * LoopbackEntry to LoopbackActive after receiving two consecutive\r
+   * TS1 Ordered Sets with the Loopback bit asserted on the\r
+   * implementation specific number of lanes configured in this field Note:\r
+   * This register field is sticky\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to IMPLEMENT_NUM_LANES\r
+   *\r
+   * Field size: 4 bits\r
+   */\r
+  uint8_t implementNumLanes;\r
   /**\r
    * @brief [rw] Set to disable Ack and Nak DLLP transmission.\r
    *\r
    * On rev 0 hw, this corresponds to ACK_DISABLE\r
    * On rev 1 hw, this corresponds to ACKNAK_DIS\r
+   * On rev 2 hw, this corresponds to ACK_NAK_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7240,6 +8419,7 @@ typedef struct pcieLaneSkewReg_s {
    *\r
    * On rev 0 hw, this corresponds to FC_DISABLE\r
    * On rev 1 hw, this corresponds to FC_DIS\r
+   * On rev 2 hw, this corresponds to FLOW_CTRL_DISABLE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7254,6 +8434,7 @@ typedef struct pcieLaneSkewReg_s {
    *\r
    * On rev 0 hw, this corresponds to LANE_SKEW\r
    * On rev 1 hw, this corresponds to LANE_SKEW\r
+   * On rev 2 hw, this corresponds to INSERT_LANE_SKEW\r
    *\r
    * Field size: 24 bits\r
    */\r
@@ -7267,6 +8448,7 @@ typedef struct pcieLaneSkewReg_s {
  *\r
  * On rev 0 hw, this corresponds to SYM_NUM\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_SYMB_N_R\r
+ * On rev 2 hw, this corresponds to TIMER_CTRL_MAX_FUNC_NUM_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7280,6 +8462,7 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to MAX_FUNC  (3 bits)\r
    * On rev 1 hw, this corresponds to MAX_FUNC (8 bits)\r
+   * On rev 2 hw, this corresponds to MAX_FUNC_NUM (8 bits)\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -7292,6 +8475,7 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to FCWATCH_TIMER\r
    * On rev 1 hw: unsupported\r
+   * On rev 2 hw: unsupported\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -7304,6 +8488,7 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to ACK_LATENCY_TIMER\r
    * On rev 1 hw, this corresponds to ACK_LATENCY_INC\r
+   * On rev 2 hw, this corresponds to TIMER_MOD_ACK_NAK\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -7316,6 +8501,7 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to REPLAY_TIMER\r
    * On rev 1 hw, this corresponds to REPLAY_ADJ\r
+   * On rev 2 hw, this corresponds to TIMER_MOD_REPLAY_TIMER\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -7325,6 +8511,7 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to SKP_COUNT\r
    * On rev 1 hw: unsupported\r
+   * On rev 2 hw: unsupported\r
    *\r
    * Field size: 3 bits\r
    */\r
@@ -7336,6 +8523,7 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to NUM_TS2_SYMBOLS\r
    * On rev 1 hw: unsupported\r
+   * On rev 2 hw: unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -7348,10 +8536,32 @@ typedef struct pcieSymNumReg_s {
    *\r
    * On rev 0 hw, this corresponds to TS_COUNT\r
    * On rev 1 hw: unsupported\r
+   * On rev 2 hw: unsupported\r
    *\r
    * Field size: 4 bits\r
    */\r
   uint8_t tsCount;\r
+  /**\r
+   * @brief [rw] Number of TS Symbols.\r
+   *\r
+   * Set the number of TS identifier symbols that are sent in TS1 and TS2\r
+   * ordered sets.\r
+   *\r
+   * On rev 0 hw: unsupported\r
+   * On rev 1 hw: unsupported\r
+   * On rev 2 hw: FAST_LINK_SCALING_FACTOR\r
+   *\r
+   * Fast Link Timer Scaling Factor Sets the scaling factor of LTSSM\r
+   * timer when FAST_LINK_MODE field in PCIE_EP_PORT_LINK_CTRL_OFF is set to '1'\r
+   * 0: Scaling Factor is 1024 [1ms is 1us]\r
+   * 1: Scaling Factor is 256 [1ms is 4us]\r
+   * 2: Scaling Factor is 64 [1ms is 16us]\r
+   * 3: Scaling Factor is 16 [1ms is 64us]\r
+   * Not used for M-PCIe Note: This register field is sticky\r
+   *\r
+   * Field size: 3 bits\r
+   */\r
+  uint8_t fastLinkScalingFactor;\r
 } pcieSymNumReg_t;\r
 /* @} */\r
 \r
@@ -7361,6 +8571,7 @@ typedef struct pcieSymNumReg_s {
  *\r
  * On rev 0 hw, this corresponds to SYMTIMER_FLTMASK\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_SYMB_T_R\r
+ * On rev 2 hw, this corresponds to SYMBOL_TIMER_FILTER_1_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7373,6 +8584,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CFG_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_RC_CFG_DISCARD\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7382,6 +8594,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_IO_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_RC_IO_DISCARD\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7391,6 +8604,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_MSG_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_MSG_DROP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7400,6 +8614,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_ECRC_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_ECRC_DISCARD\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7409,6 +8624,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_ECRC_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_ECRC_DISCARD\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7418,6 +8634,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_LEN_TEST\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_LEN_MATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7427,6 +8644,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_ATTR_TEST\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_ATTR_MATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7436,6 +8654,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_TC_TEST\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_TC_MATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7445,6 +8664,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_FUNC_TEST\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_FUNC_MATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7454,6 +8674,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_REQID_TEST\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_REQID_MATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7463,6 +8684,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_CPL_TAGERR_TEST\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CPL_TAGERR_MATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7472,6 +8694,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_LOCKED_RD_AS_UR\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_LOCKED_RD_AS_UR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7481,6 +8704,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_RE_AS_US\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_CFG_TYPE1_RE_AS_UR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7490,6 +8714,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_UR_OUT_OF_BAR\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_UR_OUTSIDE_BAR\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7499,6 +8724,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_UR_POISON\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_UR_POIS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7508,6 +8734,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to F1_UR_FUN_MISMATCH\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_1\r
+   * On rev 2 hw: this corresponds to MASK_RADM_1.CX_FLT_MASK_UR_FUNC_MISMATCH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7517,6 +8744,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to FC_WDOG_DISABLE\r
    * On rev 1 hw, this corresponds to DIS_FC_TIM\r
+   * On rev 2 hw, this corresponds to DISABLE_FC_WD_TIMER\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7530,6 +8758,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
    *\r
    * On rev 0 hw, this corresponds to SKP_VALUE\r
    * On rev 1 hw, this corresponds to SKP_INT\r
+   * On rev 2 hw, this corresponds to SKP_INT_VAL\r
    *\r
    * Field size: 11 bits\r
    */\r
@@ -7543,6 +8772,7 @@ typedef struct pcieSymTimerFltMaskReg_s {
  *\r
  * On rev 0 hw, this corresponds to FLT_MASK2\r
  * On rev 1 hw, this corresponds to FLT_MSK_2\r
+ * On rev 2 hw, this corresponds to FILTER_MASK_2_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7550,11 +8780,52 @@ typedef struct pcieSymTimerFltMaskReg_s {
  */\r
 typedef struct pcieFltMask2Reg_s {\r
   uint32_t raw; /**<  [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] 1 = Drop PRS messages silently\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_PRS_DROP\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t dropPRS;\r
+  /**\r
+   * @brief [rw] 1 = Enable unmask TD bit if CX_STRIP_ECRC_ENABLE\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_UNMASK_TD\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t unmaskTD;\r
+  /**\r
+   * @brief [rw] 1 = Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_UNMASK_UR_POIS_TRGT0\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t unmaskUrPOIS;\r
+  /**\r
+   * @brief [rw] 1 = Drop LN Messages silently\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_LN_VENMSG1_DROP\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t dropLN;\r
   /**\r
    * @brief [rw] 1 = Enable the filter to handle flush request.\r
    *\r
    * On rev 0 hw, this corresponds to FLUSH_REQ\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_HANDLE_FLUSH\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7564,6 +8835,7 @@ typedef struct pcieFltMask2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to DLLP_ABORT\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_DABORT_4UCPL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7573,6 +8845,7 @@ typedef struct pcieFltMask2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to VMSG1_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_VENMSG1_DROP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7582,6 +8855,7 @@ typedef struct pcieFltMask2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to VMSG0_DROP\r
    * On rev 1 hw: While not in TRM, these bits are part of FLT_MSK_2\r
+   * On rev 2 hw: this corresponds to MASK_RADM_2.CX_FLT_MASK_VENMSG0_DROP\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7595,6 +8869,7 @@ typedef struct pcieFltMask2Reg_s {
  *\r
  * On rev 0 hw, this corresponds to DEBUG0\r
  * On rev 1 hw, this corresponds to reserved\r
+ * On rev 2 hw, this corresponds to PL_DEBUG0_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7607,6 +8882,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TS_LNK_CTRL\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -7616,6 +8892,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TS_LANE_K237\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7625,6 +8902,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TS_LINK_K237\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7634,6 +8912,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVD_IDLE0\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7643,6 +8922,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVD_IDLE1\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7652,6 +8932,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PIPE_TXDATA\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 16 bits\r
    */\r
@@ -7661,6 +8942,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PIPE_TXDATAK\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 2 bits\r
    */\r
@@ -7670,6 +8952,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TXB_SKIP_TX\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7679,6 +8962,7 @@ typedef struct pcieDebug0Reg_s {
    *\r
    * On rev 0 hw, this corresponds to LTSSM_STATE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 5 bits\r
    */\r
@@ -7692,6 +8976,7 @@ typedef struct pcieDebug0Reg_s {
  *\r
  * On rev 0 hw, this corresponds to DEBUG1\r
  * On rev 1 hw, this corresponds to reserved\r
+ * On rev 2 hw, this corresponds to PL_DEBUG1_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7704,6 +8989,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to SCRAMBLER_DISABLE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7713,6 +8999,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_DISABLE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7722,6 +9009,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to LINK_IN_TRAINING\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7731,6 +9019,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RCVR_REVRS_POL_EN\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7740,6 +9029,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to TRAINING_RST_N\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7749,6 +9039,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PIPE_TXDETECTRX_LB\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7758,6 +9049,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PIPE_TXELECIDLE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7767,6 +9059,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to PIPE_TXCOMPLIANCE\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7776,6 +9069,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to APP_INIT_RST\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7785,6 +9079,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RMLH_TS_LINK_NUM\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -7794,6 +9089,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to XMLH_LINK_UP\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7803,6 +9099,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RMLH_INSKIP_RCV\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7812,6 +9109,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RMLH_TS1_RCVD\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7821,6 +9119,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RMLH_TS2_RCVD\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7830,6 +9129,7 @@ typedef struct pcieDebug1Reg_s {
    *\r
    * On rev 0 hw, this corresponds to RMLH_RCVD_LANE_REV\r
    * On rev 1 hw, unsupported\r
+   * On rev 2 hw, presumed same as rev 0\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7844,6 +9144,7 @@ typedef struct pcieDebug1Reg_s {
  *\r
  * On rev 0 hw, this corresponds to PL_GEN2\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_WIDTH_SPEED_CTL\r
+ * On rev 2 hw, this corresponds to GEN2_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7851,11 +9152,27 @@ typedef struct pcieDebug1Reg_s {
  */\r
 typedef struct pcieGen2Reg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
+  /**\r
+   * @brief [rw] Electrical Idle Inference Mode at Gen1 Rate\r
+   *\r
+   *  0: Use RxElecIdle signal to infer Electrical Idle -\r
+   *  1: Use RxValid signal to infer Electrical Idle\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to GEN1_EI_INFERENCE\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t gen1EiInference;\r
   /**\r
    * @brief [rw] Set de-emphasis level for upstream (EP) ports\r
    *\r
    * On rev 0 hw, this corresponds to DEEMPH\r
    * On rev 1 hw, this corresponds to CFG_UP_SEL_DEEMPH\r
+   * On rev 2 hw, this corresponds to SEL_DEEMPHASIS\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7865,6 +9182,7 @@ typedef struct pcieGen2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CFG_TX_CMPL\r
    * On rev 1 hw, this corresponds to CFG_TX_COMPLIANCE_RCV\r
+   * On rev 1 hw, this corresponds to CONFIG_TX_COMP_RX\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7877,6 +9195,7 @@ typedef struct pcieGen2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to CFG_TX_SWING\r
    * On rev 1 hw, this corresponds to CFG_PHY_TXSWING\r
+   * On rev 2 hw, this corresponds to CONFIG_PHY_TX_CHANGE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7891,17 +9210,52 @@ typedef struct pcieGen2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to DIR_SPD\r
    * On rev 1 hw, this corresponds to CFG_DIRECTED_SPEED_CHANGE\r
+   * On rev 2 hw, this corresponds to DIRECT_SPEED_CHANGE\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t dirSpd;\r
+  /**\r
+   * @brief [rw] Enable Auto flipping of the lanes\r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to AUTO_LANE_FLIP_CTRL_EN\r
+   *\r
+   * Field size: 1 bits\r
+   */\r
+  uint8_t autoFlipEn;\r
+  /**\r
+   * @brief [rw] Predetermined Lane for Auto Flip\r
+   *\r
+   * Flip This field defines which physical\r
+   * lane is connected to logical Lane0 by the flip operation \r
+   * performed in Detect \r
+   * Allowed values are: - 3'b\r
+   * 000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/\r
+   *      2-1 or CX_NL/\r
+   *      4-1 or CX_NL/\r
+   *      8-1, depending on which lane is detected\r
+   * 001: Connect logical Lane0 to physical lane 1\r
+   * 010: Connect logical Lane0 to physical lane 3\r
+   * 011: Connect logical Lane0 to physical lane 7\r
+   * 100: Connect logical Lane0 to physical lane 15 \r
+   *\r
+   * On rev 0 hw, unsupported\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to PRE_DET_LANE\r
+   *\r
+   * Field size: 3 bits\r
+   */\r
+  uint8_t preDetLane;\r
   /**\r
    * @brief [rw]  Lane enable. 1h=x1, 2h=x2. Other values reserved.\r
    *\r
    * On rev 0 hw, this corresponds to LN_EN\r
    * On rev 1 hw, this corresponds to CFG_LANE_EN\r
+   * On rev 2 hw, this corresponds to NUM_OF_LANES\r
    *\r
-   * Field size: 9 bits\r
+   * Field size: 9 bits (5 bits rev 2)\r
    */\r
   uint16_t lnEn;\r
   /**\r
@@ -7909,6 +9263,7 @@ typedef struct pcieGen2Reg_s {
    *\r
    * On rev 0 hw, this corresponds to NUM_FTS\r
    * On rev 1 hw, this corresponds to CFG_GEN2_N_FTS\r
+   * On rev 2 hw, this corresponds to FAST_TRAINING_SEQ\r
    *\r
    * Field size: 8 bit\r
    */\r
@@ -7923,6 +9278,7 @@ typedef struct pcieGen2Reg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_OBNP_SUBREQ_CTRL\r
+ * On rev 2 hw, this corresponds to AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7933,7 +9289,9 @@ typedef struct  pciePlconfObnpSubreqCtrlReg_s {
   /**\r
    * @brief [rw] Enable AXI Multiple Outbound Decomposed NP Sub-Requests\r
    *\r
+   * On rev 0 hw: unavailable\r
    * On rev 1 hw, this corresponds to EN_OBNP_SUBREQ\r
+   * On rev 2 hw, this corresponds to OB_RD_SPLIT_BURST_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -7947,6 +9305,7 @@ typedef struct  pciePlconfObnpSubreqCtrlReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_TR_P_STS_R\r
+ * On rev 2 hw, this corresponds to TX_P_FC_CREDIT_STATUS_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7960,6 +9319,7 @@ typedef struct  pciePlconfTrPStsRReg_s {
    * @brief [ro] Transmit Posted Data FC Credits\r
    *\r
    * On rev 1 hw, this corresponds to PD_CRDT\r
+   * On rev 2 hw, this corresponds to TX_P_DATA_FC_CREDIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -7968,6 +9328,7 @@ typedef struct  pciePlconfTrPStsRReg_s {
    * @brief [ro] Transmit Posted Header FC Credits\r
    *\r
    * On rev 1 hw, this corresponds to PH_CRDT\r
+   * On rev 2 hw, this corresponds to TX_P_HEADER_FC_CREDIT\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -7982,6 +9343,7 @@ typedef struct  pciePlconfTrPStsRReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_TR_NP_STS_R\r
+ * On rev 2 hw, this corresponds to TX_NP_FC_CREDIT_STATUS_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -7995,6 +9357,7 @@ typedef struct  pciePlconfTrNpStsRReg_s {
    * @brief [ro] Transmit Non-Posted Data FC Credits\r
    *\r
    * On rev 1 hw, this corresponds to NPD_CRDT\r
+   * On rev 2 hw, this corresponds to TX_NP_DATA_FC_CREDIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -8003,6 +9366,7 @@ typedef struct  pciePlconfTrNpStsRReg_s {
    * @brief [ro] Transmit Non-Posted Header FC Credits\r
    *\r
    * On rev 1 hw, this corresponds to NPH_CRDT\r
+   * On rev 2 hw, this corresponds to TX_NP_HEADER_FC_CREDIT\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8017,6 +9381,7 @@ typedef struct  pciePlconfTrNpStsRReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_TR_C_STS_R\r
+ * On rev 2 hw, this corresponds to TX_CPL_FC_CREDIT_STATUS_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8030,6 +9395,7 @@ typedef struct  pciePlconfTrCStsRReg_s {
    * @brief [ro] Transmit Completion Data FC Credits\r
    *\r
    * On rev 1 hw, this corresponds to NPD_CRDT\r
+   * On rev 2 hw, this corresponds to TX_CPL_DATA_FC_CREDIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -8038,6 +9404,7 @@ typedef struct  pciePlconfTrCStsRReg_s {
    * @brief [ro] Transmit Completion Header FC Credits\r
    *\r
    * On rev 1 hw, this corresponds to NPH_CRDT\r
+   * On rev 2 hw, this corresponds to TX_CPL_HEADER_FC_CREDIT\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8062,6 +9429,7 @@ typedef struct  pciePlconfQStsRReg_s {
    * @brief [ro] Received TLP FC Credits Not Returned\r
    *\r
    * On rev 1 hw, this corresponds to CRDT_NOT_RTRN\r
+   * On rev 2 hw, this corresponds to RX_TLP_FC_CREDIT_NON_RETURN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8070,6 +9438,7 @@ typedef struct  pciePlconfQStsRReg_s {
    * @brief [ro] Transmit Retry Buffer Not Empty\r
    *\r
    * On rev 1 hw, this corresponds to RTYB_NOT_EMPTY\r
+   * On rev 2 hw, this corresponds to TX_RETRY_BUFFER_NE\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8078,14 +9447,52 @@ typedef struct  pciePlconfQStsRReg_s {
    * @brief [ro] Received Queue Not Empty\r
    *\r
    * On rev 1 hw, this corresponds to RCVQ_NOT_EMPTY\r
+   * On rev 2 hw, this corresponds to RX_QUEUE_NON_EMPTY\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t rcvqNotEmpty;\r
+  /**\r
+   * @brief [r/w1c] Receive Credit Queue Overflow\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_QUEUE_OVERFLOW\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t rxQueueOverflow;\r
+  /**\r
+   * @brief [r/w1c] Receive Serialization Queue Not Empty\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_SERIALIZATION_Q_NON_EMPTY\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t rxSerQNEmpty;\r
+  /**\r
+   * @brief [r/w1c] Receive Serialization Queue Write Error\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_SERIALIZATION_Q_WRITE_ERR\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t rxSerQWErr;\r
+  /**\r
+   * @brief [r/w1c] Receive Serialization Read Error\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to RX_SERIALIZATION_Q_READ_ERR\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t rxSerRErr;\r
   /**\r
    * @brief [rw] FC Latency Timer Override Value\r
    *\r
    * On rev 1 hw, this corresponds to FC_LATENCY_OVR\r
+   * On rev 2 hw, this corresponds to TIMER_MOD_FLOW_CONTROL\r
    *\r
    * Field size: 13 bits\r
    */\r
@@ -8094,6 +9501,7 @@ typedef struct  pciePlconfQStsRReg_s {
    * @brief [rw] FC Latency Timer Override Enable\r
    *\r
    * On rev 1 hw, this corresponds to FC_LATENCY_OVR_EN\r
+   * On rev 2 hw, this corresponds to TIMER_MOD_FLOW_CONTROL_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8107,6 +9515,7 @@ typedef struct  pciePlconfQStsRReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_VC_TR_A_R1\r
+ * On rev 2 hw, this corresponds to VC_TX_ARBI_1_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8120,6 +9529,7 @@ typedef struct  pciePlconfVcTrAR1Reg_s {
    * @brief [ro] WRR Weight for VC0\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC0\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_0\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8128,6 +9538,7 @@ typedef struct  pciePlconfVcTrAR1Reg_s {
    * @brief [ro] WRR Weight for VC1\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC1\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_1\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8136,6 +9547,7 @@ typedef struct  pciePlconfVcTrAR1Reg_s {
    * @brief [ro] WRR Weight for VC2\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC2\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_2\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8144,6 +9556,7 @@ typedef struct  pciePlconfVcTrAR1Reg_s {
    * @brief [ro] WRR Weight for VC3\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC3\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_3\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8157,6 +9570,7 @@ typedef struct  pciePlconfVcTrAR1Reg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_VC_TR_A_R2\r
+ * On rev 2 hw, this corresponds to VC_TX_ARBI_2_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8170,6 +9584,7 @@ typedef struct  pciePlconfVcTrAR2Reg_s {
    * @brief [ro] WRR Weight for VC4\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC4\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_4\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8178,6 +9593,7 @@ typedef struct  pciePlconfVcTrAR2Reg_s {
    * @brief [ro] WRR Weight for VC5\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC5\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_5\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8186,6 +9602,7 @@ typedef struct  pciePlconfVcTrAR2Reg_s {
    * @brief [ro] WRR Weight for VC6\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC6\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_6\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8194,6 +9611,7 @@ typedef struct  pciePlconfVcTrAR2Reg_s {
    * @brief [ro] WRR Weight for VC7\r
    *\r
    * On rev 1 hw, this corresponds to WRR_VC7\r
+   * On rev 2 hw, this corresponds to WRR_WEIGHT_VC_7\r
    *\r
    * Field size: 8 bits\r
    */\r
@@ -8207,17 +9625,19 @@ typedef struct  pciePlconfVcTrAR2Reg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_PR_Q_C\r
+ * On rev 2 hw, this corresponds to VC0_P_RX_Q_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
  * @{\r
  */\r
-typedef struct  pciePlconfVc0PrQCReg_s {\r
+typedef struct  pciePlconfVcPrQCReg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
   /**\r
    * @brief [ro] VC0 Posted Data Credits\r
    *\r
    * On rev 1 hw, this corresponds to P_DCRD\r
+   * On rev 2 hw, this corresponds to VC0_P_DATA_CREDIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -8226,14 +9646,38 @@ typedef struct  pciePlconfVc0PrQCReg_s {
    * @brief [ro] VC0 Posted Header Credits\r
    *\r
    * On rev 1 hw, this corresponds to P_HCRD\r
+   * On rev 2 hw, this corresponds to VC0_P_HEADER_CREDIT\r
    *\r
    * Field size: 8 bits\r
    */\r
   uint8_t pHcrd;\r
+  /**\r
+   * @brief [rw] VC0 Scale Posted Data Credits\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to VC0_P_DATA_SCALE\r
+   *\r
+   * Field size: 2 bits\r
+   */\r
+  uint8_t pDataScale;\r
+  /**\r
+   * @brief [rw] VC0 Scale Posted Header Credits\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to VC0_P_HDR_SCALE\r
+   *\r
+   * Field size: 2 bits\r
+   */\r
+  uint8_t pHdrScale;\r
   /**\r
    * @brief [rw] VC0 TLP Type Ordering Rules\r
    *\r
    * On rev 1 hw, this corresponds to ORDERING_RULES\r
+   * On rev 2 hw, this corresponds to TLP_TYPE_ORDERING_VC0\r
    *\r
    * <table>\r
    * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
@@ -8248,7 +9692,8 @@ typedef struct  pciePlconfVc0PrQCReg_s {
     /**\r
    * @brief [rw] VC0 TLP Type Ordering Rules\r
    *\r
-   * On rev 1 hw, this corresponds to ORDERING_RULES\r
+   * On rev 1 hw, this corresponds to STRICT_VC_PRIORITY\r
+   * On rev 2 hw, this corresponds to VC_ORDERING_RX_Q\r
    *\r
    * <table>\r
    * <tr><th>Value</th><th>Mode</th><th>description</th></tr>\r
@@ -8263,6 +9708,7 @@ typedef struct  pciePlconfVc0PrQCReg_s {
    * @brief [rw] VC0 Poster TLP Queue Mode\r
    *\r
    * On rev 1 hw, this corresponds to P_QMODE\r
+   * On rev 2 hw, unsupported\r
    *\r
    * <table>\r
    * <tr><th>Action/Value</th><th>Mode</th></tr>\r
@@ -8275,26 +9721,33 @@ typedef struct  pciePlconfVc0PrQCReg_s {
    * Field size: 3 bits\r
    */\r
   uint8_t pQmode;\r
-} pciePlconfVc0PrQCReg_t;\r
+} pciePlconfVcPrQCReg_t;\r
 /* @} */\r
 \r
+/**\r
+ * @ingroup pcielld_reg_cfg_pl_structures\r
+ * @brief backwards compatibility alias for Vc0 */\r
+typedef pciePlconfVcPrQCReg_t pciePlconfVc0PrQCReg_t;\r
+\r
 /**\r
  * @ingroup pcielld_reg_cfg_pl_structures\r
  * @brief Specification of the VC0 Non-Posted Receive Queue Control (Sticky)\r
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_NPR_Q_C\r
+ * On rev 2 hw, this corresponds to VC0_NP_RX_Q_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
  * @{\r
  */\r
-typedef struct  pciePlconfVc0NprQCReg_s {\r
+typedef struct  pciePlconfVcNprQCReg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
   /**\r
    * @brief [ro] VC0 Non-Posted Data Credits\r
    *\r
    * On rev 1 hw, this corresponds to NP_DCRD\r
+   * On rev 2 hw, this corresponds to VC0_NP_DATA_CREDIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -8303,14 +9756,38 @@ typedef struct  pciePlconfVc0NprQCReg_s {
    * @brief [ro] VC0 Non-Posted Header Credits\r
    *\r
    * On rev 1 hw, this corresponds to NP_HCRD\r
+   * On rev 2 hw, this corresponds to VC0_NP_HEADER_CREDIT\r
    *\r
    * Field size: 8 bits\r
    */\r
   uint8_t npHcrd;\r
+  /**\r
+   * @brief [rw] VC0 Scale Non-Posted Data Credits\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to VC0_NP_DATA_SCALE\r
+   *\r
+   * Field size: 2 bits\r
+   */\r
+  uint8_t npDataScale;\r
+  /**\r
+   * @brief [rw] VC0 Scale Non-Posted Header Credits\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to VC0_NP_HDR_SCALE\r
+   *\r
+   * Field size: 2 bits\r
+   */\r
+  uint8_t npHdrScale;\r
   /**\r
    * @brief [rw] VC0 Non-Poster TLP Queue Mode\r
    *\r
    * On rev 1 hw, this corresponds to NP_QMODE\r
+   * On rev 2 hw, unsupported\r
    *\r
    * <table>\r
    * <tr><th>Action/Value</th><th>Mode</th></tr>\r
@@ -8323,26 +9800,33 @@ typedef struct  pciePlconfVc0NprQCReg_s {
    * Field size: 3 bits\r
    */\r
   uint8_t npQmode;\r
-} pciePlconfVc0NprQCReg_t;\r
+} pciePlconfVcNprQCReg_t;\r
 /* @} */\r
 \r
+/**\r
+ * @ingroup pcielld_reg_cfg_pl_structures\r
+ * @brief backwards compatibility alias for Vc0 */\r
+typedef pciePlconfVcNprQCReg_t pciePlconfVc0NprQCReg_t;\r
+\r
 /**\r
  * @ingroup pcielld_reg_cfg_pl_structures\r
  * @brief Specification of the VC0 Completion Receive Queue Control (Sticky)\r
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_VC0_CR_Q_C\r
+ * On rev 1 hw, this corresponds to VC0_CPL_RX_Q_CTRL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
  * @{\r
  */\r
-typedef struct  pciePlconfVc0CrQCReg_s {\r
+typedef struct  pciePlconfVcCrQCReg_s {\r
   uint32_t raw; /**< @brief [ro] Raw image of register on read; actual value on write */\r
   /**\r
    * @brief [ro] VC0 Completion Data Credits\r
    *\r
    * On rev 1 hw, this corresponds to CPL_DCRD\r
+   * On rev 2 hw, this corresponds to VC0_NP_DATA_CREDIT\r
    *\r
    * Field size: 12 bits\r
    */\r
@@ -8351,14 +9835,38 @@ typedef struct  pciePlconfVc0CrQCReg_s {
    * @brief [ro] VC0 Completion Header Credits\r
    *\r
    * On rev 1 hw, this corresponds to CPL_HCRD\r
+   * On rev 2 hw, this corresponds to VC0_NP_HEADER_CREDIT\r
    *\r
    * Field size: 8 bits\r
    */\r
   uint8_t cplHcrd;\r
+  /**\r
+   * @brief [rw] VC0 Scale CPL Data Credits\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to VC0_CPL_DATA_SCALE\r
+   *\r
+   * Field size: 2 bits\r
+   */\r
+  uint8_t cplDataScale;\r
+  /**\r
+   * @brief [rw] VC0 Scale CPL Header Credits\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to VC0_CPL_HDR_SCALE\r
+   *\r
+   * Field size: 2 bits\r
+   */\r
+  uint8_t cplHdrScale;\r
   /**\r
    * @brief [rw] VC0 Completion TLP Queue Mode\r
    *\r
    * On rev 1 hw, this corresponds to CPL_QMODE\r
+   * On rev 2 hw, unsupported\r
    *\r
    * <table>\r
    * <tr><th>Action/Value</th><th>Mode</th></tr>\r
@@ -8371,15 +9879,21 @@ typedef struct  pciePlconfVc0CrQCReg_s {
    * Field size: 3 bits\r
    */\r
   uint8_t cplQmode;\r
-} pciePlconfVc0CrQCReg_t;\r
+} pciePlconfVcCrQCReg_t;\r
 /* @} */\r
 \r
+/**\r
+ * @ingroup pcielld_reg_cfg_pl_structures\r
+ * @brief backwards compatibility alias for Vc0 */\r
+typedef pciePlconfVcCrQCReg_t pciePlconfVc0CrQCReg_t;\r
+\r
 /**\r
  * @ingroup pcielld_reg_cfg_pl_structures\r
  * @brief Specification of the PHY Status Register (Sticky)\r
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_PHY_STS_R\r
+ * On rev 2 hw, this corresponds to PHY_STATUS_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8393,6 +9907,7 @@ typedef struct  pciePlconfPhyStsRReg_s {
    * @brief [ro] PHY Status\r
    *\r
    * On rev 1 hw, this corresponds to PHY_STS\r
+   * On rev 2 hw, this corresponds to PHY_STATUS\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8406,6 +9921,7 @@ typedef struct  pciePlconfPhyStsRReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_PHY_CTRL_R\r
+ * On rev 2 hw, this corresponds to PHY_CONTROL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8417,6 +9933,7 @@ typedef struct  pciePlconfPhyCtrlRReg_s {
    * @brief [rw] PHY Control\r
    *\r
    * On rev 1 hw, this corresponds to PHY_CTRL\r
+   * On rev 2 hw, this corresponds to PHY_CONTROL\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8431,6 +9948,7 @@ typedef struct  pciePlconfPhyCtrlRReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_ADDRESS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_ADDR_OFF\r
  *\r
  * This register may be used only for root complex modes.\r
  *\r
@@ -8442,6 +9960,7 @@ typedef struct  pciePlconfMsiCtrlAddressReg_s {
    * @brief [rw] MSI CTRL ADDRESS\r
    *\r
    * On rev 1 hw, this corresponds to MSI_CTRL_ADDRESS\r
+   * On rev 2 hw, this corresponds to MSI_CTRL_ADDR\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8456,6 +9975,7 @@ typedef struct  pciePlconfMsiCtrlAddressReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_UPPER_ADDR_OFF\r
  *\r
  * This register may be used only for root complex modes.\r
  *\r
@@ -8467,6 +9987,7 @@ typedef struct  pciePlconfMsiCtrlUpperAddressReg_s {
    * @brief [rw] MSI CTRL UPPER ADDRESS\r
    *\r
    * On rev 1 hw, this corresponds to MSI_CTRL_UPPER_ADDRESS\r
+   * On rev 2 hw, this corresponds to MSI_CTRL_UPPER_ADDR\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8483,6 +10004,7 @@ typedef struct  pciePlconfMsiCtrlUpperAddressReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_EN_OFF\r
  *\r
  * This register may be used only for root complex modes.\r
  *\r
@@ -8494,6 +10016,7 @@ typedef struct  pciePlconfMsiCtrlIntEnableReg_s {
    * @brief [rw] Status of an enabled bit (vectors) is set upon incoming MSI\r
    *\r
    * On rev 1 hw, this corresponds to MSI_CTRL_INT_ENABLE\r
+   * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_EN\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8510,6 +10033,7 @@ typedef struct  pciePlconfMsiCtrlIntEnableReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_MASK_N\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_MASK_OFF\r
  *\r
  * This register may be used only for root complex modes.\r
  *\r
@@ -8521,6 +10045,7 @@ typedef struct  pciePlconfMsiCtrlIntMaskReg_s {
    * @brief [rw] Status of a masked bit (vector) triggers no IRQ to MPU when set\r
    *\r
    * On rev 1 hw, this corresponds to MSI_CTRL_INT_MASK\r
+   * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_MASK\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8537,6 +10062,7 @@ typedef struct  pciePlconfMsiCtrlIntMaskReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_INT_STATUS_N\r
+ * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_STATUS_OFF\r
  *\r
  * This register may be used only for root complex modes.\r
  *\r
@@ -8548,6 +10074,7 @@ typedef struct  pciePlconfMsiCtrlIntStatusReg_s {
    * @brief [rw] Status of an enabled bit (vectors) is set upon incoming MSI\r
    *\r
    * On rev 1 hw, this corresponds to MSI_CTRL_INT_STATUS\r
+   * On rev 2 hw, this corresponds to MSI_CTRL_INT_0_STATUS\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8562,6 +10089,7 @@ typedef struct  pciePlconfMsiCtrlIntStatusReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_MSI_CTRL_GPIO\r
+ * On rev 2 hw, this corresponds to MSI_GPIO_IO_OFF\r
  *\r
  * This register may be used only for root complex modes.\r
  *\r
@@ -8573,6 +10101,7 @@ typedef struct  pciePlconfMsiCtrlGpioReg_s {
    * @brief [rw] MSI CTRL GPIO\r
    *\r
    * On rev 1 hw, this corresponds to MSI_CTRL_GPIO\r
+   * On rev 2 hw, this corresponds to MSI_GPIO_REG\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -8586,6 +10115,7 @@ typedef struct  pciePlconfMsiCtrlGpioReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_PIPE_LOOPBACK\r
+ * On rev 2 hw, this corresponds to PIPE_LOOPBACK_CONTROL_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8597,6 +10127,7 @@ typedef struct  pciePlconfPipeLoopbackReg_s {
    * @brief [rw] PIPE Loopback Enable\r
    *\r
    * On rev 1 hw, this corresponds to LOOPBACK_EN\r
+   * On rev 2 hw, this corresponds to PIPE_LOOPBACK\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8610,6 +10141,7 @@ typedef struct  pciePlconfPipeLoopbackReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_DBI_RO_WR_EN\r
+ * On rev 2 hw, this corresponds to MISC_CONTROL_1_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8633,10 +10165,70 @@ typedef struct  pciePlconfDbiRoWrEnReg_s {
    * </table>\r
    *\r
    * On rev 1 hw, this corresponds to CX_DBI_RO_WR_EN\r
+   * On rev 2 hw, this corresponds to DBI_RO_WR_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t cxDbiRoWrEn;\r
+  /**\r
+   * @brief [rw] Default target a received IO or MEM request with UR/CA/CRS\r
+   *\r
+   * 0: The controller drops all incoming I/O or MEM requests [after\r
+   *    corresponding error reporting] A completion with UR status will be\r
+   *    generated for non-posted requests -\r
+   * 1: The controller forwards all incoming I/O or MEM requests with\r
+   *    UR/CA/CRS status to your application Default value is\r
+   *    DEFAULT_TARGET configuration parameter Note: This register field\r
+   *    is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to DEFAULT_TARGET\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t defaultTarget;\r
+  /**\r
+   * @brief [rw] UR_CA_MASK_4_TRGT1\r
+   *\r
+   * This field only applies to request TLPs [with UR filtering status] that\r
+   * you have chosen to forward to the application [when you set\r
+   * DEFAULT_TARGET in this register] -\r
+   *\r
+   * '1' the core suppresses error logging, Error Message generation, and\r
+   * CPL generation [for non-posted requests] - You should set this if you\r
+   * have set the Default Target port logic register to '1' Default is\r
+   * CX_MASK_UR_CA_4_TRGT1 configuration parameter\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to UR_CA_MASK_4_TRGT1\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+   uint8_t urCaMask4Trgt1;\r
+  /**\r
+   * @brief [rw] Enables Simplified Replay Timer [Gen4]\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to SIMPLIFIED_REPLAY_TIMER\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+   uint8_t simpReplayTimer;\r
+  /**\r
+   * @brief [rw] When ARI is enabled, enables use of the device ID\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to ARI_DEVICE_NUMBER\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+   uint8_t ariDevNumber;\r
 } pciePlconfDbiRoWrEnReg_t;\r
 /* @} */\r
 \r
@@ -8646,6 +10238,7 @@ typedef struct  pciePlconfDbiRoWrEnReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_AXI_SLV_ERR_RESP\r
+ * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_DEFAULT_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8657,6 +10250,7 @@ typedef struct  pciePlconfAxiSlvErrRespReg_s {
    * @brief [rw] Global Slave Error Response Mapping\r
    *\r
    * On rev 1 hw, this corresponds to SLAVE_ERR_MAP\r
+   * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_GLOBAL\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8665,6 +10259,7 @@ typedef struct  pciePlconfAxiSlvErrRespReg_s {
    * @brief [rw] DIF Slave Error Response Mapping\r
    *\r
    * On rev 1 hw, this corresponds to DBI_ERR_MAP\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8673,6 +10268,7 @@ typedef struct  pciePlconfAxiSlvErrRespReg_s {
    * @brief [rw] Vendor ID Non-existent Slave Error Response Mapping\r
    *\r
    * On rev 1 hw, this corresponds to NO_VID_ERR_MAP\r
+   * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_VENDORID\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8681,10 +10277,65 @@ typedef struct  pciePlconfAxiSlvErrRespReg_s {
    * @brief [rw] Graceful Reset and Link Timeout Slave Error Response Mapping\r
    *\r
    * On rev 1 hw, this corresponds to RESET_TIMEOUT_ERR_MAP\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t resetTimeoutErrMap;\r
+  /**\r
+   * @brief [rw] CRS Slave Error Response Mapping\r
+   *\r
+   * CRS Slave Error Response Mapping Determines the AXI slave\r
+   * response for CRS completions AHB: - always returns OKAY AXI: -\r
+   * 00: OKAY\r
+   * 01: OKAY with all FFFF_FFFF data for all CRS completions\r
+   * 10: OKAY with FFFF_0001 data for CRS completions to vendor ID\r
+   *     read requests, OKAY with FFFF_FFFF data for all other CRS\r
+   *     completions\r
+   * 11: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field\r
+   *     determines the PCIe-to-AXI Slave error response mapping]\r
+   *\r
+   * This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_CRS\r
+   *\r
+   * Field size: 2 bit\r
+   */\r
+  uint8_t errorResponseCrs;\r
+  /**\r
+   * @brief [rw] AXI Slave Response Error Map\r
+   *\r
+   * AXI Slave Response Error Map Allows you to selectively map the\r
+   * errors received from the PCIe completion [for non-posted requests]\r
+   * to the AXI slave responses, slv_rresp or slv_bresp The\r
+   * recommended setting is SLVERR CRS is always mapped to OKAY -\r
+   * [bit 0] 0: UR [unsupported request] -> DECERR\r
+   *         1: UR [unsupported request] -> SLVERR\r
+   * [bit 1] 0: CRS [configuration retry status] -> DECERR\r
+   *         1: CRS [configuration retry status] -> SLVERR\r
+   * [bit 2] 0: CA [completer abort] -> DECERR\r
+   *         1: CA [completer abort] -> SLVERR\r
+   * [bit 3]: Reserved\r
+   * [bit 4]: Reserved\r
+   * [bit 5]: 0: Completion Timeout -> DECERR\r
+   *          1: Completion Timeout -> SLVERR\r
+   * The AXI bridge internally drops\r
+   * [processes internally but not passed to your application] a\r
+   * completion that has been marked by the Rx filter as UC or MLF, and\r
+   * does not pass its status directly down to the slave interface It waits\r
+   * for a timeout and then signals "Completion Timeout" to the slave\r
+   * interface The controller sets the AXI slave read databus to 0xFFFF\r
+   * for all error responses\r
+   *\r
+   * Note: This register field is sticky\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to AMBA_ERROR_RESPONSE_MAP\r
+   *\r
+   * Field size: 6 bits\r
+   */\r
+  uint8_t errorResponseMap;\r
 } pciePlconfAxiSlvErrRespReg_t;\r
 /* @} */\r
 \r
@@ -8694,6 +10345,7 @@ typedef struct  pciePlconfAxiSlvErrRespReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_AXI_SLV_TIMEOUT\r
+ * On rev 2 hw, this corresponds to AMBA_LINK_TIMEOUT_OFF\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8728,6 +10380,7 @@ typedef struct  pciePlconfAxiSlvTimeoutReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_INDEX\r
+ * On rev 2 hw: the index selection emulated in SW (all windows are available in HW all the time)\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8745,6 +10398,7 @@ typedef struct  pciePlconfIatuIndexReg_s {
    * </table>\r
    *\r
    * On rev 1 hw, this corresponds to REGION_DIRECTION\r
+   * On rev 2 hw, this is virtual sw register to demux 16 inbound/outbound regions\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8753,9 +10407,10 @@ typedef struct  pciePlconfIatuIndexReg_s {
    * @brief [rw] Region Index\r
    *\r
    * On rev 1 hw, this corresponds to REGION_INDEX\r
+   * On rev 2 hw, this is virtual sw register to demux 16 inbound/outbound regions\r
    *\r
    * Outbound region, from 0 to 15.\r
-   * Inbound region, from 0 to 3.\r
+   * Inbound region, from 0 to 3 (rev 1) or 0 to 15 (rev 2)\r
    *\r
    * Field size: 4 bits\r
    */\r
@@ -8769,6 +10424,8 @@ typedef struct  pciePlconfIatuIndexReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_1\r
+ * On rev 2 hw, this corresponds to IATU_REGION_CTRL_1_OFF_OUTBOUND and\r
+ *              IATU_REGION_CTRL_1_OFF_INBOUND\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8780,28 +10437,31 @@ typedef struct  pciePlconfIatuRegCtrl1Reg_s {
    * @brief [rw] type\r
    *\r
    * On rev 1 hw, this corresponds to TYPE\r
+   * On rev 2 hw, this corresponds to TYPE\r
    *\r
    * Outbound: TYPE applied to outgoing TLP with matching addess\r
    * Inbound: TYPE-match criteria\r
    *\r
-   * Field size: 4 bits\r
+   * Field size: 5 bits\r
    */\r
   uint8_t type;\r
   /**\r
    * @brief [rw] TC\r
    *\r
    * On rev 1 hw, this corresponds to TC\r
+   * On rev 2 hw, this corresponds to TC\r
    *\r
    * Outbound: TC applied to outgoing TLP with matching addess\r
    * Inbound: TC-match criteria (if TC_match_enable=1)\r
    *\r
-   * Field size: 4 bits\r
+   * Field size: 3 bits\r
    */\r
   uint8_t tc;\r
   /**\r
    * @brief [rw] TD\r
    *\r
    * On rev 1 hw, this corresponds to TD\r
+   * On rev 2 hw, this corresponds to TD\r
    *\r
    * Outbound: TD applied to outgoing TLP with matching addess\r
    * Inbound: TD-match criteria (if TD_match_enable=1)\r
@@ -8813,6 +10473,7 @@ typedef struct  pciePlconfIatuRegCtrl1Reg_s {
    * @brief [rw] ATTR\r
    *\r
    * On rev 1 hw, this corresponds to ATTR\r
+   * On rev 2 hw, this corresponds to ATTR\r
    *\r
    * Outbound: ATTR applied to outgoing TLP with matching addess\r
    * Inbound: ATTR-match criteria (if ATTR_match_enable=1)\r
@@ -8824,6 +10485,7 @@ typedef struct  pciePlconfIatuRegCtrl1Reg_s {
    * @brief [rw] AT\r
    *\r
    * On rev 1 hw, this corresponds to AT\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Outbound: AT applied to outgoing TLP with matching addess\r
    * Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)\r
@@ -8831,16 +10493,30 @@ typedef struct  pciePlconfIatuRegCtrl1Reg_s {
    * Field size: 2 bits\r
    */\r
   uint8_t at;\r
+  /**\r
+   * @brief [rw] Increase the maximum ATU Region size\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INCREASE_REGION_SIZE\r
+   *\r
+   * Outbound: F.N; applied to outgoing TLP (RID) with RW 0x0 matching addess\r
+   * Inbound: F.N.-match criteria for incoming TLP\r
+   *          (if Function_Number_match_enable=1)\r
+   *\r
+   * Field size: rev 1: 5 bits; rev 2: 3 bits\r
+   */\r
+  uint8_t increaseRegionSize;\r
   /**\r
    * @brief [rw] function number\r
    *\r
    * On rev 1 hw, this corresponds to FUNCTION_NUMBER\r
+   * On rev 2 hw, this corresponds to CTRL_1_FUNC_NUM\r
    *\r
    * Outbound: F.N; applied to outgoing TLP (RID) with RW 0x0 matching addess\r
    * Inbound: F.N.-match criteria for incoming TLP\r
    *          (if Function_Number_match_enable=1)\r
    *\r
-   * Field size: 5 bits\r
+   * Field size: rev 1: 5 bits; rev 2: 3 bits\r
    */\r
   uint8_t functionNumber;\r
 } pciePlconfIatuRegCtrl1Reg_t;\r
@@ -8852,6 +10528,8 @@ typedef struct  pciePlconfIatuRegCtrl1Reg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_2\r
+ * On rev 2 hw, this corresponds to IATU_REGION_CTRL_2_OFF_OUTBOUND and\r
+ *              IATU_REGION_CTRL_2_OFF_INBOUND\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -8863,6 +10541,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] MESSAGECODE\r
    *\r
    * On rev 1 hw, this corresponds to MESSAGECODE\r
+   * On rev 2 hw, this corresponds to MSG_CODE\r
    *\r
    * Outbound: MessageCode applied to outgoing message RW 0x0 TLP with\r
    *           matching addess\r
@@ -8876,6 +10555,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] BAR_NUMBER\r
    *\r
    * On rev 1 hw, this corresponds to BAR_NUMBER\r
+   * On rev 2 hw, this corresponds to incoming BAR_NUM (not used for outgoing)\r
    *\r
    * BAR number for mayching with incoming MEM, I/O TLP RW 0x0\r
    * (if Match_Mode = 1)\r
@@ -8894,10 +10574,32 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * Field size: 3 bits\r
    */\r
   uint8_t barNumber;\r
+  /**\r
+   * @brief [rw] TAG\r
+   *\r
+   * The substituted TAG field [byte 6] in the outgoing TLP header\r
+   * when TAG_SUBSTITUTE_EN is set\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to TAG for outbound only\r
+   *\r
+   * Field size: 8 bits\r
+   */\r
+  uint8_t tag;\r
+  /**\r
+   * @brief [rw] \r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to MSG_TYPE_MATCH_MODE (inbound)\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t msgTypeMatchMode;\r
   /**\r
    * @brief [rw] Enable TC match criteria on inbound TLP\r
    *\r
    * On rev 1 hw, this corresponds to TC_MATCH_ENABLE\r
+   * On rev 2 hw, this corresponds to TC_MATCH_EN (inbound)\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8906,6 +10608,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Enable TD match criteria on inbound TLP\r
    *\r
    * On rev 1 hw, this corresponds to TD_MATCH_ENABLE\r
+   * On rev 2 hw, this corresponds to TD_MATCH_EN (inbound)\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8914,6 +10617,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Enable ATTR match criteria on inbound TLP\r
    *\r
    * On rev 1 hw, this corresponds to ATTR_MATCH_ENABLE\r
+   * On rev 2 hw, this corresponds to ATTR_MATCH_EN (inbound)\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -8922,16 +10626,27 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Enable AT match criteria on inbound TLP\r
    *\r
    * On rev 1 hw, this corresponds to AT_MATCH_ENABLE\r
+   * On rev 2 hw, unsupported\r
    *\r
    * ATS NOT SUPPORTED: DO NOT USE\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t atMatchEnable;\r
+  /**\r
+   * @brief [rw] TAG Substitute Enable\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to TAG_SUBSTITUTE_EN\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t tagSubstEn;\r
   /**\r
    * @brief [rw] function number match enable\r
    *\r
    * On rev 1 hw, this corresponds to FUNCTION_NUMBER_MATCH_ENABLE\r
+   * On rev 2 hw, this corresponds to FUNC_BYPASS(outbound) or FUNC_NUM_MATCH_EN (inbound)\r
    *\r
    * Outbound: Function Number Translation Bypass\r
    * Inbound: Enable Function Number match criteria\r
@@ -8943,22 +10658,61 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] VIRTUAL FUNCTIONS NOT IMPLEMENTED\r
    *\r
    * On rev 1 hw, this corresponds to VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE\r
+   * On rev 2 hw, unsupported\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t virtualFunctionNumberMatchEnable;\r
+  /**\r
+   * @brief [rw] Serialize Non-Posted Requests\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to SNP (outbound)\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t SNP;\r
   /**\r
    * @brief [rw] Enable MessageCode match criteria on inbound TLP\r
    *\r
    * On rev 1 hw, this corresponds to MESSAGE_CODE_MATCH_ENABLE\r
+   * On rev 2 hw, this corresponds to MSG_CODE_MATCH_EN(inbound)\r
    *\r
    * Field size: 1 bit\r
    */\r
   uint8_t messageCodeMatchEnable;\r
+  /**\r
+   * @brief [rw] Inhibit TLP Payload Data for TLP's in Matched Region\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to INHIBIT_PAYLOAD\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t inhibitPayload;\r
+  /**\r
+   * @brief [rw] Header Substitute Enable (outbound)\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to HEADER_SUBSTITUTE_EN (outbound)\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t headerSubstEn;\r
+  /**\r
+   * @brief [rw] Single Address Location Translate Enable (inbound)\r
+   *\r
+   * On rev 1 hw, unsupported\r
+   * On rev 2 hw, this corresponds to SINGLE_ADDR_LOC_TRANS_EN (inbound)\r
+   *\r
+   * Field size: 1 bit\r
+   */\r
+  uint8_t singleAddrLocTransEn;\r
   /**\r
    * @brief [rw] Override HW-generated completion status when responding inbound TLP\r
    *\r
    * On rev 1 hw, this corresponds to RESPONSE_CODE\r
+   * On rev 2 hw, this corresponds to RESPONSE_CODE (inbound)\r
    *\r
    * <table>\r
    * <tr><th>Value</th><th>description</th></tr>\r
@@ -8974,6 +10728,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] fuzzy type match mode\r
    *\r
    * On rev 1 hw, this corresponds to FUZZY_TYPE_MATCH_MODE\r
+   * On rev 2 hw, this corresponds to FUZZY_TYPE_MATCH_CODE (inbound)\r
    *\r
    * Outbound: DMA Bypass Mode RW 0x0\r
    * Inbound: Relax matching on inbound TLP TYPE:\r
@@ -8989,6 +10744,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Enable the shifting of CFG CID (BDF),\r
    *\r
    * On rev 1 hw, this corresponds to CFG_SHIFT_MODE\r
+   * On rev 2 hw, this corresponds to CFG_SHIFT_MODE\r
    *\r
    * Incoming and outgoing TLP;\r
    * CFG get mapped to a contiguous 2**28 = * 256 MByte address space\r
@@ -9002,6 +10758,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Redefine match criteria as outside the defined range\r
    *\r
    * On rev 1 hw, this corresponds to INVERT_MODE\r
+   * On rev 2 hw, this corresponds to INVERT_MODE\r
    *\r
    * (instead of inside)\r
    *\r
@@ -9012,6 +10769,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Sets inbound TLP match mode\r
    *\r
    * On rev 1 hw, this corresponds to MATCH_MODE\r
+   * On rev 2 hw, this corresponds to MATCH_MODE (inbound)\r
    *\r
    * Depending on TYPE\r
    * 0x0: MEM,I/O: Address Match: as per region base & limit registers;\r
@@ -9030,6 +10788,7 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
    * @brief [rw] Enable AT for this region\r
    *\r
    * On rev 1 hw, this corresponds to REGION_ENABLE\r
+   * On rev 2 hw, this corresponds to REGION_EN\r
    *\r
    * Field size: 1 bit\r
    */\r
@@ -9044,6 +10803,8 @@ typedef struct  pciePlconfIatuRegCtrl2Reg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LOWER_BASE\r
+ * On rev 2 hw, this corresponds to IATU_LWR_BASE_ADDR_OFF_OUTBOUND and\r
+ *              IATU_LWR_BASE_ADDR_OFF_INBOUND\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -9056,20 +10817,23 @@ typedef struct  pciePlconfIatuRegLowerBaseReg_s {
    * @brief [rw] Lower Base Address (read-write part)\r
    *\r
    * On rev 1 hw, this corresponds to IATU_REG_LOWER_BASE\r
+   * On rev 2 hw, this corresponds to LWR_BASE_RW\r
    *\r
-   * Note: @ref iatuRegLowerBase is >> 12 version of address, with 0 LSBs cut off.\r
+   * Note: On rev 1 @ref iatuRegLowerBase is >> 12 version of address, with 0 LSBs cut off\r
+   * Note: On rev 2 @ref iatuRegLowerBase is >> 16 version of address, with 0 LSBs cut off\r
    *\r
-   * Field size: 20 bits\r
+   * Field size: 20 bits (rev 1) or 16 bits (rev 2)\r
    */\r
   uint32_t iatuRegLowerBase;\r
   /**\r
    * @brief [ro] Lower Base Address (read-only part)\r
    *\r
    * On rev 1 hw, this corresponds to ZERO\r
+   * On rev 2 hw, this corresponds to LWR_BASE_HW\r
    *\r
-   * This portion is always 0 to enforce 4K alignment.\r
+   * This portion is always 0 to enforce 4K alignment (rev 1) or 64K (rev 2)\r
    *\r
-   * Field size: 12 bits\r
+   * Field size: 12 bits (rev 1) or 16 bits (rev 2)\r
    */\r
   uint16_t zero;\r
 } pciePlconfIatuRegLowerBaseReg_t;\r
@@ -9081,6 +10845,8 @@ typedef struct  pciePlconfIatuRegLowerBaseReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_UPPER_BASE\r
+ * On rev 2 hw, this corresponds to IATU_UPPER_BASE_ADDR_OFF_OUTBOUND and\r
+ *              IATU_LIMIT_ADDR_OFF_INBOUND\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -9092,6 +10858,7 @@ typedef struct  pciePlconfIatuRegUpperBaseReg_s {
    * @brief [rw] Upper Base Address\r
    *\r
    * On rev 1 hw, this corresponds to IATU_REG_UPPER_BASE\r
+   * On rev 2 hw, this corresponds to UPPER_BASE_RW\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -9116,18 +10883,23 @@ typedef struct  pciePlconfIatuRegLimitReg_s {
    * @brief [ro] Region limit address\r
    *\r
    * On rev 1 hw, this corresponds to IATU_REG_LIMIT\r
+   * On rev 2 hw, this corresponds to LIMIT_ADDR_RW\r
    *\r
-   * Field size: 20 bits\r
+   * Note: On rev 1 @ref iatuRegLimit is >> 12 version of address, with 0 LSBs cut off\r
+   * Note: On rev 2 @ref iatuRegLimit is >> 16 version of address, with 0 LSBs cut off\r
+   *\r
+   * Field size: 20 bits (rev 1) or 16 bits (rev 2)\r
    */\r
   uint32_t iatuRegLimit;\r
   /**\r
    * @brief [ro] Region limit address (mask)\r
    *\r
    * On rev 1 hw, this corresponds to ONES\r
+   * On rev 2 hw, this corresponds to LIMIT_ADDR_HW\r
    *\r
-   * This portion is always 0xfff to enforce 4K portion of mask.\r
+   * This portion is always all 1s to enforce 4K alignment (rev 1) or 64K (rev 2)\r
    *\r
-   * Field size: 12 bits\r
+   * Field size: 12 bits (rev 1) or 16 bits (rev 2)\r
    */\r
   uint16_t ones;\r
 } pciePlconfIatuRegLimitReg_t;\r
@@ -9140,6 +10912,8 @@ typedef struct  pciePlconfIatuRegLimitReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_LOWER_TARGET\r
+ * On rev 2 hw, this corresponds to IATU_LWR_TARGET_ADDR_OFF_OUTBOUND and\r
+ *              IATU_LWR_TARGET_ADDR_OFF_INBOUND\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -9152,20 +10926,24 @@ typedef struct  pciePlconfIatuRegLowerTargetReg_s {
    * @brief [rw] Lower Target Address (read-write part)\r
    *\r
    * On rev 1 hw, this corresponds to IATU_REG_LOWER_TARGET\r
+   * On rev 2 hw, this corresponds to LWR_TARGET_RW_OUTBOUND and LWR_TARGET_RW\r
    *\r
-   * Note: @ref iatuRegLowerTarget is >> 12 version of address, with 0 LSBs cut off.\r
+   * Note: On rev 1 @ref iatuRegLowerTarget is >> 12 version of address, with 0 LSBs cut off\r
+   * Note: On rev 2 @ref iatuRegLowerTarget is >> 16 version of address, with 0 LSBs cut off\r
    *\r
-   * Field size: 20 bits\r
+   * Field size: 20 bits (rev 1) or 16 bits (rev 2)\r
    */\r
   uint32_t iatuRegLowerTarget;\r
   /**\r
    * @brief [ro] Lower Target Address (read-only part)\r
    *\r
    * On rev 1 hw, this corresponds to ZERO\r
+   * On rev 2 hw, this corresponds to LWR_TARGET_RW_OUTBOUND (low 16 bits) and\r
+   *              LWR_TARGET_HW\r
    *\r
-   * This portion is always 0 to enforce 4K alignment.\r
+   * This portion is always 0 to enforce 4K alignment (rev 1) or 64K (rev 2)\r
    *\r
-   * Field size: 12 bits\r
+   * Field size: 12 bits (rev 1) or 16 bits (rev 2)\r
    */\r
   uint16_t zero;\r
 } pciePlconfIatuRegLowerTargetReg_t;\r
@@ -9177,6 +10955,8 @@ typedef struct  pciePlconfIatuRegLowerTargetReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_UPPER_TARGET\r
+ * On rev 2 hw, this corresponds to IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND and\r
+ *              IATU_UPPER_TARGET_ADDR_OFF_INBOUND\r
  *\r
  * This register may be used for both endpoint and root complex modes.\r
  *\r
@@ -9188,6 +10968,7 @@ typedef struct  pciePlconfIatuRegUpperTargetReg_s {
    * @brief [rw] Upper Target Address\r
    *\r
    * On rev 1 hw, this corresponds to ATU_REG_UPPER_TARGET\r
+   * On rev 2 hw, this corresponds to UPPER_TARGET_RW\r
    *\r
    * Field size: 32 bits\r
    */\r
@@ -9201,6 +10982,7 @@ typedef struct  pciePlconfIatuRegUpperTargetReg_s {
  *\r
  * On rev 0 hw: unavailable\r
  * On rev 1 hw, this corresponds to PCIECTRL_PL_IATU_REG_CTRL_3\r
+ * On rev 2 hw: unavailable\r
  *\r
  * VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED\r
  *\r
@@ -10210,6 +11992,7 @@ typedef struct pcieRegisters_s {
   pcieIoBaseReg_t                   *ioBase;                  /**< @brief IO TLP base*/\r
   pcieTlpCfgReg_t                   *tlpCfg;                  /**< @brief TLP Config*/\r
   pcieRstCmdReg_t                   *rstCmd;                  /**< @brief Reset Command*/\r
+  pciePtmCfgReg_t                   *ptmCfg;                  /**< @brief PTM Config Command*/\r
   pciePmCmdReg_t                    *pmCmd;                   /**< @brief Power Management Command*/\r
   pciePmCfgReg_t                    *pmCfg;                   /**< @brief Power Management Config*/\r
   pcieActStatusReg_t                *actStatus;               /**< @brief Activity Status */\r
@@ -10239,6 +12022,10 @@ typedef struct pcieRegisters_s {
   pciePmRstIrqStatusReg_t           *pmRstIrqStatus;          /**< @brief Power Management and Reset Interrupt Enabled Status Register*/\r
   pciePmRstIrqEnableSetReg_t        *pmRstIrqEnableSet;       /**< @brief Power Management and Reset Interrupt Enable Set Register*/\r
   pciePmRstIrqEnableClrReg_t        *pmRstIrqEnableClr;       /**< @brief Power Management and Reset Interrupt Enable Clear Register*/\r
+  pciePtmIrqStatusRawReg_t          *ptmIrqStatusRaw;         /**< @brief Precision Time Measurement Raw Interrupt Status Register*/\r
+  pciePtmIrqStatusReg_t             *ptmIrqStatus;            /**< @brief Precision Time Measurement Interrupt Enabled Status Register*/\r
+  pciePtmIrqEnableSetReg_t          *ptmIrqEnableSet;         /**< @brief Precision Time Measurement Interrupt Enable Set Register*/\r
+  pciePtmIrqEnableClrReg_t          *ptmIrqEnableClr;         /**< @brief Precision Time Measurement Interrupt Enable Clear Register*/\r
   pcieObOffsetLoReg_t               *obOffsetLo[8];           /**< @brief Outbound Translation region offset Low*/\r
   pcieObOffsetHiReg_t               *obOffsetHi[8];           /**< @brief Outbound Translation region offset High*/\r
   pcieIbBarReg_t                    *ibBar[4];                /**< @brief Inbound Translation BAR*/\r
@@ -10296,6 +12083,8 @@ typedef struct pcieRegisters_s {
   pcieMsiLo32Reg_t                  *msiLo32;                 /**< @brief MSI Lower 32 bits */\r
   pcieMsiUp32Reg_t                  *msiUp32;                 /**< @brief MSI Upper 32 bits */\r
   pcieMsiDataReg_t                  *msiData;                 /**< @brief MSI Data */\r
+  pcieMsiCapOff10HReg_t             *msiCapOff10H;            /**< @brief MSI Cap Off 10H */\r
+  pcieMsiCapOff14HReg_t             *msiCapOff14H;            /**< @brief MSI Cap Off 14H */\r
 \r
   /*Capabilities Registers*/\r
   pciePciesCapReg_t                 *pciesCap;                /**< @brief PCI Express Capabilities Register*/\r
@@ -10350,6 +12139,9 @@ typedef struct pcieRegisters_s {
   pciePlconfVc0PrQCReg_t             *plconfVc0PrQC;          /**< @brief PCIECTRL_PL_VC0_PR_Q_C*/\r
   pciePlconfVc0NprQCReg_t            *plconfVc0NprQC;         /**< @brief PCIECTRL_PL_VC0_NPR_Q_C*/\r
   pciePlconfVc0CrQCReg_t             *plconfVc0CrQC;          /**< @brief PCIECTRL_PL_VC0_CR_Q_C*/\r
+  pciePlconfVcPrQCReg_t              *plconfVcPrQC[3];        /**< @brief for VC1..VC3 */\r
+  pciePlconfVcNprQCReg_t             *plconfVcNprQC[3];       /**< @brief for VC1..VC3 */\r
+  pciePlconfVcCrQCReg_t              *plconfVcCrQC[3];        /**< @brief for VC1..VC3 */\r
   /* note: plconfWidthSpeedCtlReg_t is mapped to gen2 above */\r
   pciePlconfPhyStsRReg_t             *plconfPhyStsR;          /**< @brief PCIECTRL_PL_PHY_STS_R*/\r
   pciePlconfPhyCtrlRReg_t            *plconfPhyCtrlR;         /**< @brief PCIECTRL_PL_PHY_CTRL_R*/\r
@@ -10547,6 +12339,13 @@ typedef struct
    * Base address of the "data" area (remote device memory) \r
    */\r
   void              *dataBase;\r
+  /**\r
+   * Reserved part of real data area due to memory mapping.  For example\r
+   * on some M4s the PCIe address is at 0x20000000 which is illegal for\r
+   * M4.  Thus its moved to 0x24000000.  In this case dataReserved\r
+   * is 0x04000000.\r
+   */\r
+  uint32_t           dataReserved;\r
   /** \r
    * Revision-dependant device params.  Look for Pciev#_DevParams in\r
    * src/v#/pcie.h.  Not all HW will have these (put NULL).\r
@@ -10573,6 +12372,8 @@ typedef struct
 {\r
   /*! Function to set PCIE to EP or RC for one device */\r
   pcieRet_e (*setInterfaceMode) (Pcie_Handle handle, pcieMode_e mode);\r
+  /*! Function to get the PCIE data area reserved size */\r
+  pcieRet_e (*getMemSpaceReserved) (Pcie_Handle handle, uint32_t *resSize);\r
   /*! Function to get the PCIE data area base address & size */\r
   pcieRet_e (*getMemSpaceRange) (Pcie_Handle handle, void **base,\r
                                  uint32_t *size);\r
@@ -10799,6 +12600,21 @@ pcieRet_e Pcie_setInterfaceMode
   pcieMode_e mode     /**< [in] PCIE Mode */\r
 );\r
 \r
+/**\r
+ *  @ingroup pcielld_api_functions\r
+ *  @brief  Pcie_getMemSpaceReserved returns amount of reserved space \r
+ *          between beginning of hardware's data area and the base returned\r
+ *          by @ref Pcie_getMemSpaceRange. \r
+ *\r
+ *  @retval  pcieRet_e status\r
+ */\r
+pcieRet_e Pcie_getMemSpaceReserved\r
+(\r
+  Pcie_Handle  handle,   /**< [in] The PCIE LLD instance identifier */\r
+  uint32_t    *resSize   /**< [out] Total size of the memory space [bytes] */\r
+);\r
+\r
+\r
 /**\r
  *  @ingroup pcielld_api_functions\r
  *  @brief  Pcie_getMemSpaceRange Returns the PCIe Internal Address\r