am5x changes broke v0 hw (k1/k2) : sdocm00121387

diff --git a/example/sample/c6657/c66/bios/pcie_sample.cfg b/example/sample/c6657/c66/bios/pcie_sample.cfg
old mode 100755 (executable)
new mode 100644 (file)
index 6e33dfa..8914672
--- a/example/sample/c6657/c66/bios/pcie_sample.cfg
+++ b/example/sample/c6657/c66/bios/pcie_sample.cfg
@@ -1,5 +1,5 @@
 /*
- *  Copyright 2012 by Texas Instruments Incorporated.
+ *  Copyright 2012-2016 by Texas Instruments Incorporated.
  *
  *  All rights reserved. Property of Texas Instruments Incorporated.
  *  Restricted rights to use, duplicate or disclose this code are
@@ -38,8 +38,7 @@ var SysStd  = xdc.useModule('xdc.runtime.SysStd');
 System.SupportProxy = SysStd;
 
 /* specify heap size */
-Memory.defaultHeapSize = 0x2000;
-Program.heap = 0x2000;
+Memory.defaultHeapSize = 0x20000;
 
 /* Load Profiling package */
 var Utils = xdc.loadPackage('ti.utils.profiling');

diff --git a/example/sample/c6678/c66/bios/pcie_sample.cfg b/example/sample/c6678/c66/bios/pcie_sample.cfg
old mode 100755 (executable)
new mode 100644 (file)
index 69cff73..69edc77
--- a/example/sample/c6678/c66/bios/pcie_sample.cfg
+++ b/example/sample/c6678/c66/bios/pcie_sample.cfg
@@ -1,5 +1,5 @@
 /*
- *  Copyright 2012 by Texas Instruments Incorporated.
+ *  Copyright 2012-2016 by Texas Instruments Incorporated.
  *
  *  All rights reserved. Property of Texas Instruments Incorporated.
  *  Restricted rights to use, duplicate or disclose this code are
@@ -38,8 +38,7 @@ var SysStd  = xdc.useModule('xdc.runtime.SysStd');
 System.SupportProxy = SysStd;
 
 /* specify heap size */
-Memory.defaultHeapSize = 0x2000;
-Program.heap = 0x2000;
+Memory.defaultHeapSize = 0x20000;
 
 /* Load Profiling package */
 var Utils = xdc.loadPackage('ti.utils.profiling');

diff --git a/example/sample/k2e/c66/bios/pcie_sample.cfg b/example/sample/k2e/c66/bios/pcie_sample.cfg
index 033e634e154b60f39be7b29c731bc787c45cbbd9..2920dabc17e374d102e06b7c9e41da0d5b46da98 100644 (file)
--- a/example/sample/k2e/c66/bios/pcie_sample.cfg
+++ b/example/sample/k2e/c66/bios/pcie_sample.cfg
@@ -1,5 +1,5 @@
 /*
- *  Copyright 2012 by Texas Instruments Incorporated.
+ *  Copyright 2012-2016 by Texas Instruments Incorporated.
  *
  *  All rights reserved. Property of Texas Instruments Incorporated.
  *  Restricted rights to use, duplicate or disclose this code are
@@ -38,8 +38,7 @@ var SysStd  = xdc.useModule('xdc.runtime.SysStd');
 System.SupportProxy = SysStd;
 
 /* specify heap size */
-Memory.defaultHeapSize = 0x2000;
-Program.heap = 0x2000;
+Memory.defaultHeapSize = 0x20000;
 
 /* Load Profiling package */
 var Utils = xdc.loadPackage('ti.utils.profiling');

diff --git a/example/sample/k2h/c66/bios/pcie_sample.cfg b/example/sample/k2h/c66/bios/pcie_sample.cfg
index fa855df86f1ab70c2dba84ae7c2c7c7ba18487fb..648a1a692989ef5229b881cbcff3f714afe56b6b 100644 (file)
--- a/example/sample/k2h/c66/bios/pcie_sample.cfg
+++ b/example/sample/k2h/c66/bios/pcie_sample.cfg
@@ -1,5 +1,5 @@
 /*
- *  Copyright 2012 by Texas Instruments Incorporated.
+ *  Copyright 2012-2016 by Texas Instruments Incorporated.
  *
  *  All rights reserved. Property of Texas Instruments Incorporated.
  *  Restricted rights to use, duplicate or disclose this code are
@@ -38,8 +38,7 @@ var SysStd  = xdc.useModule('xdc.runtime.SysStd');
 System.SupportProxy = SysStd;
 
 /* specify heap size */
-Memory.defaultHeapSize = 0x2000;
-Program.heap = 0x2000;
+Memory.defaultHeapSize = 0x20000;
 
 /* Load Profiling package */
 var Utils = xdc.loadPackage('ti.utils.profiling');

diff --git a/example/sample/k2k/c66/bios/pcie_sample.cfg b/example/sample/k2k/c66/bios/pcie_sample.cfg
index 6df218c44e02d91c86edfb733b17028d4587cee3..83eb9f1dbaffaaa38f2f998bb8ab6b6be3753282 100644 (file)
--- a/example/sample/k2k/c66/bios/pcie_sample.cfg
+++ b/example/sample/k2k/c66/bios/pcie_sample.cfg
@@ -1,5 +1,5 @@
 /*
- *  Copyright 2012 by Texas Instruments Incorporated.
+ *  Copyright 2012-2016 by Texas Instruments Incorporated.
  *
  *  All rights reserved. Property of Texas Instruments Incorporated.
  *  Restricted rights to use, duplicate or disclose this code are
@@ -38,8 +38,7 @@ var SysStd  = xdc.useModule('xdc.runtime.SysStd');
 System.SupportProxy = SysStd;
 
 /* specify heap size */
-Memory.defaultHeapSize = 0x2000;
-Program.heap = 0x2000;
+Memory.defaultHeapSize = 0x20000;
 
 /* Load Profiling package */
 var Utils = xdc.loadPackage('ti.utils.profiling');

diff --git a/example/sample/k2l/c66/bios/pcie_sample.cfg b/example/sample/k2l/c66/bios/pcie_sample.cfg
index ab63ef14e58707c6105850a4fe832a2a953b7d31..d6095191a612262fafa67fb19dfcb0c214a5f9ac 100644 (file)
--- a/example/sample/k2l/c66/bios/pcie_sample.cfg
+++ b/example/sample/k2l/c66/bios/pcie_sample.cfg
@@ -1,5 +1,5 @@
 /*
- *  Copyright 2012 by Texas Instruments Incorporated.
+ *  Copyright 2012-2016 by Texas Instruments Incorporated.
  *
  *  All rights reserved. Property of Texas Instruments Incorporated.
  *  Restricted rights to use, duplicate or disclose this code are
@@ -38,8 +38,7 @@ var SysStd  = xdc.useModule('xdc.runtime.SysStd');
 System.SupportProxy = SysStd;
 
 /* specify heap size */
-Memory.defaultHeapSize = 0x2000;
-Program.heap = 0x2000;
+Memory.defaultHeapSize = 0x20000;
 
 /* Load Profiling package */
 var Utils = xdc.loadPackage('ti.utils.profiling');

diff --git a/src/v0/pcieloc.h b/src/v0/pcieloc.h
index 4052e62b7a12e5ca86dedcb19884436b7c338bdc..4cdd68edbbfa570ea39e518e7f975566d801efc3 100644 (file)
--- a/src/v0/pcieloc.h
+++ b/src/v0/pcieloc.h
@@ -1,6 +1,6 @@
 /*\r
  *\r
- * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/ \r
+ * Copyright (C) 2010-2016 Texas Instruments Incorporated - http://www.ti.com/ \r
  * \r
  * \r
  *  Redistribution and use in source and binary forms, with or without \r
@@ -57,17 +57,17 @@ extern "C" {
 /* Common utility macros */\r
 \r
 /* Get base address for Local Configuration Space */\r
-#define pcie_get_loc_cfg_base(handle, ep_loc_base, rc_loc_base) \\r
+#define pcie_get_loc_cfg_base(appBase, ep_loc_base, rc_loc_base) \\r
   {                                                \\r
-    uint32_t temp_var = ((uint32_t)(handle)) + 0x1000U; \\r
+    uint32_t temp_var = ((uint32_t)(appBase)) + 0x1000U; \\r
     (ep_loc_base) = (CSL_Pcie_cfg_space_endpointRegs *) (temp_var); \\r
     (rc_loc_base) = (CSL_Pcie_cfg_space_rootcomplexRegs *) (temp_var); \\r
   }\r
     \r
 /* Get base address for Remote Configuration Space */\r
-#define pcie_get_rem_cfg_base(handle, ep_rem_base, rc_rem_base) \\r
+#define pcie_get_rem_cfg_base(appBase, ep_rem_base, rc_rem_base) \\r
   {                                                \\r
-    uint32_t temp_var = ((uint32_t)(handle)) + 0x2000U; \\r
+    uint32_t temp_var = ((uint32_t)(appBase)) + 0x2000U; \\r
     (ep_rem_base) = (CSL_Pcie_cfg_space_endpointRegs *) (temp_var); \\r
     (rc_rem_base) = (CSL_Pcie_cfg_space_rootcomplexRegs *) (temp_var); \\r
   }\r

diff --git a/src/v0/pciev0.c b/src/v0/pciev0.c
index eb6ce38278228ea6ba541eb040e0aa8abcf42531..111484b2605cc61ee8e3888810105aeaea1e31e4 100644 (file)
--- a/src/v0/pciev0.c
+++ b/src/v0/pciev0.c
@@ -1,6 +1,6 @@
 /*\r
  *\r
- * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/ \r
+ * Copyright (C) 2010-2016 Texas Instruments Incorporated - http://www.ti.com/ \r
  * \r
  * \r
  *  Redistribution and use in source and binary forms, with or without \r
@@ -79,10 +79,10 @@ pcieRet_e Pciev0_setInterfaceMode
   pcieMode_e  mode        /**< [in] PCIE Mode */\r
 )\r
 {\r
-  Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);\r
+  Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
 \r
-  if (bases) {\r
-     pcie_set_mode ((Pciev0_DevParams *)bases->devParams, mode);\r
+  if (cfg) {\r
+     pcie_set_mode ((Pciev0_DevParams *)cfg->devParams, mode);\r
      return pcie_RET_OK;\r
   }\r
 \r
@@ -109,9 +109,9 @@ pcieRet_e Pciev0_getMemSpaceRange
   pcie_check_handle(handle);\r
 \r
   if (base) {\r
-    Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);\r
-    if (bases) {\r
-      *base = bases->dataBase;\r
+    Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
+    if (cfg) {\r
+      *base = cfg->dataBase;\r
     } else {\r
       retVal = pcie_RET_INV_HANDLE;\r
     }\r
@@ -134,8 +134,9 @@ pcieRet_e Pciev0_readRegs
   pcieRegisters_t *readRegs  /**< [in/out] List of registers to read */\r
 )\r
 {\r
+  Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
   /* Base Address for the Application Registers */\r
-  CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle; \r
+  CSL_Pciess_appRegs *baseAppRegs;\r
 \r
   /* Base Address for the Config Space\r
      These registers can be Local/Remote and Type0(EP)/Type1(RC) */\r
@@ -151,14 +152,16 @@ pcieRet_e Pciev0_readRegs
 \r
   pcie_check_handle(handle);\r
 \r
+  baseAppRegs = cfg->cfgBase;\r
+\r
   /* Get base address for Local or Remote config space */\r
   if (location == pcie_LOCATION_LOCAL) \r
   {\r
-    pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs)\r
+    pcie_get_loc_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs)\r
   }\r
   else\r
   {\r
-    pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
+    pcie_get_rem_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) \r
   }\r
 \r
   /*****************************************************************************************\r
@@ -783,8 +786,9 @@ pcieRet_e Pciev0_writeRegs
   pcieRegisters_t *writeRegs /**< [in] List of registers to write */\r
 )\r
 {\r
+  Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
   /* Base Address for the Application Registers */\r
-  CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle; \r
+  CSL_Pciess_appRegs *baseAppRegs;\r
 \r
   /* Base Address for the Config Space\r
      These registers can be Local/Remote and Type0(EP)/Type1(RC) */\r
@@ -800,14 +804,16 @@ pcieRet_e Pciev0_writeRegs
 \r
   pcie_check_handle(handle);\r
 \r
-  /* Get base address for Local/Remote config space */\r
+  baseAppRegs = cfg->cfgBase;\r
+\r
+  /* Get base address for Local or Remote config space */\r
   if (location == pcie_LOCATION_LOCAL) \r
   {\r
-    pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
+    pcie_get_loc_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs)\r
   }\r
   else\r
   {\r
-    pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
+    pcie_get_rem_cfg_base(baseAppRegs, baseCfgEpRegs, baseCfgRcRegs) \r
   }\r
 \r
   /*****************************************************************************************\r