summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 01a395c)
raw | patch | inline | side by side (parent: 01a395c)
author | John Dowdal <jdowdal@ti.com> | |
Mon, 11 May 2015 22:13:02 +0000 (18:13 -0400) | ||
committer | John Dowdal <jdowdal@ti.com> | |
Mon, 11 May 2015 22:13:02 +0000 (18:13 -0400) |
41 files changed:
diff --git a/.gitignore b/.gitignore
index b8ff885cf69e8ddfb298e95f25a63a8af307bf33..b4befd361ee8fe02f84d4217c511a214653abceb 100644 (file)
--- a/.gitignore
+++ b/.gitignore
Settings.xdc
build/c66/
build/k2[heklg]/
+build/am57*/
docs/Doxyfile
docs/doxygen/
docs/pcieDocs.chm
diff --git a/config.bld b/config.bld
index 995aa82a83e590e788ba77957707d68ed704bc82..309556a1915e122f6ece5cf2802e7b7e39a36959 100644 (file)
--- a/config.bld
+++ b/config.bld
\r
/* List of all devices that combine to make the hyplnk library.\r
*/\r
-var devices = [ "c66", "k2k/c66", "k2h/c66",
- "k2l/c66", "k2e/c66" ];\r
+var devices = [ "c66", "k2k/c66", "k2h/c66",
+ "k2l/c66", "k2e/c66",
+ "am57x/c66" ];\r
/* order must exactly match list in "var devices" */
-var devicesCCOpt = [ "", " -DDEVICE_K2K", " -DDEVICE_K2H",
- " -DDEVICE_K2L", " -DDEVICE_K2E" ];\r
+var devicesCCOpt = [ "", " -DDEVICE_K2K", " -DDEVICE_K2H",
+ " -DDEVICE_K2L", " -DDEVICE_K2E",
+ " -DDEVICE_AM572x" ];\r
/* device name (k2?) is inserted between first an second element of this
list to construct device file name for each device */
diff --git a/example/sample/am572x/armv7/bios/PCIE_AM57X_armExampleProject.txt b/example/sample/am57x/armv7/bios/PCIE_AM57X_armExampleProject.txt
similarity index 100%
rename from example/sample/am572x/armv7/bios/PCIE_AM57X_armExampleProject.txt
rename to example/sample/am57x/armv7/bios/PCIE_AM57X_armExampleProject.txt
rename from example/sample/am572x/armv7/bios/PCIE_AM57X_armExampleProject.txt
rename to example/sample/am57x/armv7/bios/PCIE_AM57X_armExampleProject.txt
diff --git a/example/sample/am572x/armv7/bios/pcie_sample.cfg b/example/sample/am57x/armv7/bios/pcie_sample.cfg
similarity index 100%
rename from example/sample/am572x/armv7/bios/pcie_sample.cfg
rename to example/sample/am57x/armv7/bios/pcie_sample.cfg
rename from example/sample/am572x/armv7/bios/pcie_sample.cfg
rename to example/sample/am57x/armv7/bios/pcie_sample.cfg
diff --git a/example/sample/am572x/armv7/bios/pcie_sample.cmd b/example/sample/am57x/armv7/bios/pcie_sample.cmd
similarity index 100%
rename from example/sample/am572x/armv7/bios/pcie_sample.cmd
rename to example/sample/am57x/armv7/bios/pcie_sample.cmd
rename from example/sample/am572x/armv7/bios/pcie_sample.cmd
rename to example/sample/am57x/armv7/bios/pcie_sample.cmd
diff --git a/example/sample/am57x/c66/bios/PCIE_AM57XC66BiosExampleProject.txt b/example/sample/am57x/c66/bios/PCIE_AM57XC66BiosExampleProject.txt
--- /dev/null
@@ -0,0 +1,4 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/src/pcie_sample.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am57x/c66/bios/pcie_sample.cfg"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am57x/c66/bios/pcie_sample.cmd"
+-ccs.setCompilerOptions " -mv6600 -g -DDEVICE_AM572X --diag_warning=225 -I${PDK_INSTALL_PATH} -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/src" -rtsc.enableRtsc
diff --git a/example/sample/am57x/c66/bios/pcie_sample.cfg b/example/sample/am57x/c66/bios/pcie_sample.cfg
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012 by Texas Instruments Incorporated.
+ *
+ * All rights reserved. Property of Texas Instruments Incorporated.
+ * Restricted rights to use, duplicate or disclose this code are
+ * granted through contract.
+ *
+ */
+
+/* THIS FILE WAS GENERATED BY ti.sysbios.genx */
+
+/*
+ * ======== memory.cfg ========
+ *
+ */
+
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Event = xdc.useModule('ti.sysbios.knl.Event');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+var Log = xdc.useModule('xdc.runtime.Log');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* specify heap size */
+Memory.defaultHeapSize = 0x2000;
+Program.heap = 0x2000;
+
+var devType = "am572x";
+var devClass = "am57x";
+/* Load and use the PCIE packages */
+var Pcie = xdc.loadPackage('ti.drv.pcie');
+Pcie.Settings.deviceType = devClass;
+
+/*use CSL package*/
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+
+Program.stack = 0x3000; /* main() runs from this stack */
+
diff --git a/example/sample/am57x/c66/bios/pcie_sample.cmd b/example/sample/am57x/c66/bios/pcie_sample.cmd
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS
+{
+ .init_array > L2SRAM
+ .dstBufSec > L2SRAM
+}
diff --git a/example/sample/am57x/c66/bios/src/.exclude b/example/sample/am57x/c66/bios/src/.exclude
--- /dev/null
@@ -0,0 +1 @@
+This file exists to prevent Eclipse/CDT from adding the C sources contained in this directory (or below) to any enclosing project.
diff --git a/example/sample/am57x/c66/bios/src/makefile.libs b/example/sample/am57x/c66/bios/src/makefile.libs
--- /dev/null
@@ -0,0 +1,62 @@
+#
+# This file was generated based on the configuration script:
+# Z:\k2_git\keystone-2-csl-lld\ti\drv\pcie\example\sample\am57x\c66\bios\pcie_sample.cfg
+#
+# This makefile may be included in other makefiles that need to build
+# the libraries containing the compiled source files generated as
+# part of the configuration step.
+
+#
+# ======== GEN_SRC_DIR =========
+# The path to the sources generated during configuration
+#
+# This path must be either absolute or relative to the build directory.
+#
+# The absolute path to the generated source directory (at the time the
+# sources were generated) is:
+# Z:\k2_git\keystone-2-csl-lld\ti\drv\pcie\example\sample\am57x\c66\bios\src
+#
+GEN_SRC_DIR ?= ../../../ti/drv/pcie/example/sample/am57x/c66/bios/src
+
+ifeq (,$(wildcard $(GEN_SRC_DIR)))
+$(error "ERROR: GEN_SRC_DIR must be set to the directory containing the generated sources")
+endif
+
+#
+# ======== .force ========
+# The .force goal is used to force the build of any goal that names it as
+# a prerequisite
+#
+.PHONY: .force
+
+#
+# ======== library macros ========
+#
+sysbios_SRC = $(GEN_SRC_DIR)/sysbios
+sysbios_LIB = $(GEN_SRC_DIR)/sysbios/sysbios.ae66
+
+#
+# ======== dependencies ========
+#
+all: $(sysbios_LIB)
+clean: .sysbios_clean
+
+
+# ======== convenient build goals ========
+.PHONY: sysbios
+sysbios: $(GEN_SRC_DIR)/sysbios/sysbios.ae66
+
+# CDT managed make executables depend on $(OBJS)
+OBJS += $(sysbios_LIB)
+
+#
+# ======== rules ========
+#
+$(sysbios_LIB): .force
+ @echo making $@ ...
+ @$(MAKE) -C $(sysbios_SRC)
+
+.sysbios_clean:
+ @echo cleaning $(sysbios_SRC) ...
+ -@$(MAKE) --no-print-directory -C $(sysbios_SRC) clean
+
diff --git a/example/sample/am57x/c66/bios/src/sysbios/BIOS.obj b/example/sample/am57x/c66/bios/src/sysbios/BIOS.obj
new file mode 100644 (file)
index 0000000..06e8025
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/BIOS.obj differ
index 0000000..06e8025
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/BIOS.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/c62_TaskSupport_asm.obj b/example/sample/am57x/c66/bios/src/sysbios/c62_TaskSupport_asm.obj
new file mode 100644 (file)
index 0000000..515807c
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c62_TaskSupport_asm.obj differ
index 0000000..515807c
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c62_TaskSupport_asm.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/c64p_Exception_asm.obj b/example/sample/am57x/c66/bios/src/sysbios/c64p_Exception_asm.obj
new file mode 100644 (file)
index 0000000..c07751f
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Exception_asm.obj differ
index 0000000..c07751f
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Exception_asm.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm.obj b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm.obj
new file mode 100644 (file)
index 0000000..cc0c617
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm.obj differ
index 0000000..cc0c617
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm_switch.obj b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm_switch.obj
new file mode 100644 (file)
index 0000000..40ad9c1
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm_switch.obj differ
index 0000000..40ad9c1
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_asm_switch.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_disp_always.obj b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_disp_always.obj
new file mode 100644 (file)
index 0000000..c2794cf
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_disp_always.obj differ
index 0000000..c2794cf
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/c64p_Hwi_disp_always.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/dmtimer_Timer_asm.obj b/example/sample/am57x/c66/bios/src/sysbios/dmtimer_Timer_asm.obj
new file mode 100644 (file)
index 0000000..3bf284e
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/dmtimer_Timer_asm.obj differ
index 0000000..3bf284e
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/dmtimer_Timer_asm.obj differ
diff --git a/example/sample/am57x/c66/bios/src/sysbios/sysbios.ae66 b/example/sample/am57x/c66/bios/src/sysbios/sysbios.ae66
new file mode 100644 (file)
index 0000000..1671f7f
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/sysbios.ae66 differ
index 0000000..1671f7f
Binary files /dev/null and b/example/sample/am57x/c66/bios/src/sysbios/sysbios.ae66 differ
diff --git a/example/sample/am57x/src/pcie_sample_board.c b/example/sample/am57x/src/pcie_sample_board.c
--- /dev/null
@@ -0,0 +1,326 @@
+/* ============================================================================\r
+ * Copyright (c) Texas Instruments Incorporated 2015\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+\r
+/** \r
+ * @file pcie_example_board.h\r
+ *\r
+ */\r
+#include <ti/csl/soc.h>\r
+#define MEM_BARRIER_DISABLE\r
+#include <ti/csl/hw_types.h>\r
+\r
+#include "pcie_sample_board.h"\r
+\r
+/* Missing defines */\r
+#define CSL_CONTROL_CORE_MMR_LOCK_1_MMR_LOCK_1_TOUNLOCK (804367403U)\r
+#define CSL_CONTROL_CORE_MMR_LOCK_2_MMR_LOCK_2_TOUNLOCK (4149738944U)\r
+#define CSL_CONTROL_CORE_MMR_LOCK_3_MMR_LOCK_3_TOUNLOCK (3803986541U)\r
+#define CSL_CONTROL_CORE_MMR_LOCK_4_MMR_LOCK_4_TOUNLOCK (515838749U)\r
+#define CSL_CONTROL_CORE_MMR_LOCK_5_MMR_LOCK_5_TOUNLOCK (1865817605U)\r
+\r
+/* Pick base addreses based on CPU type */\r
+#ifdef _TMS320C6X\r
+#define SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE CSL_DSP_CTRL_MODULE_CORE_CORE_REGISTERS_REGS\r
+#define SOC_L3INIT_CM_CORE_BASE CSL_DSP_L3INIT_CM_CORE_REGS\r
+#define SOC_OCP2SCP3_BASE CSL_DSP_OCP2SCP3_REGS\r
+#define SOC_CKGEN_CM_CORE_BASE (CSL_DSP_CKGEN_CM_CORE_REGS - 4)\r
+#define SOC_SEC_EFUSE_REGISTERS_BASE CSL_DSP_SEC_EFUSE_REGISTERS_REGS\r
+#define SOC_L3INIT_PRM_BASE CSL_DSP_L3INIT_PRM_REGS\r
+#define SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE CSL_DSP_OCP2SCP3_USB3RX_PHY_PCIE1_REGS\r
+#else\r
+#define SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS\r
+#define SOC_L3INIT_CM_CORE_BASE CSL_MPU_L3INIT_CM_CORE_REGS\r
+#define SOC_OCP2SCP3_BASE CSL_MPU_OCP2SCP3_REGS\r
+#define SOC_CKGEN_CM_CORE_BASE (CSL_MPU_CKGEN_CM_CORE_REGS - 4)\r
+#define SOC_SEC_EFUSE_REGISTERS_BASE CSL_MPU_SEC_EFUSE_REGISTERS_REGS\r
+#define SOC_L3INIT_PRM_BASE CSL_MPU_L3INIT_PRM_REGS\r
+#define SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE CSL_MPU_OCP2SCP3_USB3RX_PHY_PCIE1_REGS\r
+#endif\r
+\r
+void PlatformUnlockMMR(void)\r
+{\r
+ /* unlock MMR1 space for region 0x0100 to 0x079F */\r
+ HW_WR_REG32(\r
+ SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +\r
+ CSL_CONTROL_CORE_MMR_LOCK_1,\r
+ CSL_CONTROL_CORE_MMR_LOCK_1_MMR_LOCK_1_TOUNLOCK);\r
+ /* unlock MMR2 space for region 0x07A0 to 0x0D9F */\r
+ HW_WR_REG32(\r
+ SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +\r
+ CSL_CONTROL_CORE_MMR_LOCK_2,\r
+ CSL_CONTROL_CORE_MMR_LOCK_2_MMR_LOCK_2_TOUNLOCK);\r
+ /* unlock MMR3 space for region 0x0DA0 to 0x0FFF */\r
+ HW_WR_REG32(\r
+ SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +\r
+ CSL_CONTROL_CORE_MMR_LOCK_3,\r
+ CSL_CONTROL_CORE_MMR_LOCK_3_MMR_LOCK_3_TOUNLOCK);\r
+ /* unlock MMR4 space for region 0x1000 to 0x13FF */\r
+ HW_WR_REG32(\r
+ SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +\r
+ CSL_CONTROL_CORE_MMR_LOCK_4,\r
+ CSL_CONTROL_CORE_MMR_LOCK_4_MMR_LOCK_4_TOUNLOCK);\r
+ /* unlock MMR5 space for region 0x1400 to 0x1FFF */\r
+ HW_WR_REG32(\r
+ SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE +\r
+ CSL_CONTROL_CORE_MMR_LOCK_5,\r
+ CSL_CONTROL_CORE_MMR_LOCK_5_MMR_LOCK_5_TOUNLOCK);\r
+} /* PlatformUnlockMMR */\r
+\r
+void PlatformPCIESS1ClockEnable(void)\r
+{\r
+ uint32_t regVal;\r
+\r
+ /*OCP2SCP1 enables accessing the PCIe PHY serial configuration*/\r
+ HW_WR_FIELD32(SOC_L3INIT_CM_CORE_BASE + CM_L3INIT_OCP2SCP1_CLKCTRL,\r
+ CM_L3INIT_OCP2SCP1_CLKCTRL_MODULEMODE,\r
+ CM_L3INIT_OCP2SCP1_CLKCTRL_MODULEMODE_AUTO);\r
+\r
+ /*OCP2SCP3 enables accessing the PCIe PHY serial configuration*/\r
+ HW_WR_FIELD32(SOC_L3INIT_CM_CORE_BASE + CM_L3INIT_OCP2SCP3_CLKCTRL,\r
+ CM_L3INIT_OCP2SCP3_CLKCTRL_MODULEMODE,\r
+ CM_L3INIT_OCP2SCP3_CLKCTRL_MODULEMODE_AUTO);\r
+\r
+ /*PCIeSS CLKSTCTRL SW WakeUp*/\r
+ HW_WR_FIELD32(SOC_L3INIT_CM_CORE_BASE + CM_PCIE_CLKSTCTRL,\r
+ CM_PCIE_CLKSTCTRL_CLKTRCTRL,\r
+ CM_PCIE_CLKSTCTRL_CLKTRCTRL_SW_WKUP);\r
+\r
+ /*L3 Init PCIeSS1 CLKCTRL SW Enable*/\r
+ HW_WR_FIELD32(SOC_L3INIT_CM_CORE_BASE + CM_PCIE_PCIESS1_CLKCTRL,\r
+ CM_PCIE_PCIESS1_CLKCTRL_MODULEMODE,\r
+ CM_PCIE_PCIESS1_CLKCTRL_MODULEMODE_ENABLED);\r
+\r
+ while ((HW_RD_REG32(SOC_L3INIT_CM_CORE_BASE + CM_PCIE_PCIESS1_CLKCTRL) &\r
+ CM_PCIE_PCIESS1_CLKCTRL_IDLEST_MASK) !=\r
+ CM_PCIE_PCIESS1_CLKCTRL_IDLEST_FUNC)\r
+ {\r
+ ;\r
+ }\r
+\r
+ /*Enable PCIe PHY optional clk*/\r
+ regVal = HW_RD_REG32(SOC_L3INIT_CM_CORE_BASE + CM_PCIE_PCIESS1_CLKCTRL);\r
+\r
+ HW_SET_FIELD(regVal, CM_PCIE_PCIESS1_CLKCTRL_OPTFCLKEN_PCIEPHY_CLK_DIV,\r
+ CM_PCIE_PCIESS1_CLKCTRL_OPTFCLKEN_PCIEPHY_CLK_DIV_FCLK_EN);\r
+\r
+ HW_SET_FIELD(regVal, CM_PCIE_PCIESS1_CLKCTRL_OPTFCLKEN_PCIEPHY_CLK,\r
+ CM_PCIE_PCIESS1_CLKCTRL_OPTFCLKEN_PCIEPHY_CLK_FCLK_EN);\r
+\r
+ HW_SET_FIELD(regVal, CM_PCIE_PCIESS1_CLKCTRL_OPTFCLKEN_32KHZ,\r
+ CM_PCIE_PCIESS1_CLKCTRL_OPTFCLKEN_32KHZ_FCLK_EN);\r
+\r
+ HW_WR_REG32(SOC_L3INIT_CM_CORE_BASE + CM_PCIE_PCIESS1_CLKCTRL, regVal);\r
+}\r
+\r
+void PlatformPCIESS1PllConfig(void)\r
+{\r
+ uint32_t regVal;\r
+\r
+ /*OCP2SCP_SYSCONFIG[1] Soft Reset*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x10U) & 0xFFFFFFFDU;\r
+\r
+ regVal |= 0x02U;\r
+\r
+ HW_WR_REG32(SOC_OCP2SCP3_BASE + 0x10U, regVal);\r
+\r
+ /*OCP2SCP_SYSSTATUS[0] Reset Done*/\r
+ while ((HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x14U) & 0x01U) != 0x01U)\r
+ {\r
+ ;\r
+ }\r
+\r
+ /*OCP2SCP_TIMING[9:7] Division Ratio = 1*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x18U) & 0xFFFFFC7FU;\r
+\r
+ regVal |= (uint32_t) 0x8U << 4U;\r
+\r
+ HW_WR_REG32(SOC_OCP2SCP3_BASE + 0x18U, regVal);\r
+\r
+ /*OCP2SCP_TIMING[3:0] (SYNC2) = 0xF*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x18U) & 0xFFFFFFF0U;\r
+\r
+ regVal |= 0xFU;\r
+\r
+ HW_WR_REG32(SOC_OCP2SCP3_BASE + 0x18U, regVal);\r
+\r
+ /*PCIe DPLL - M&N programming; CLKSEL*/\r
+ regVal = HW_RD_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKSEL_DPLL_PCIE_REF);\r
+\r
+ HW_SET_FIELD(regVal, CM_CLKSEL_DPLL_PCIE_REF_DPLL_DIV, 0x09U);\r
+\r
+ HW_SET_FIELD(regVal, CM_CLKSEL_DPLL_PCIE_REF_DPLL_MULT, 0x2EEU);\r
+\r
+ HW_WR_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKSEL_DPLL_PCIE_REF, regVal);\r
+\r
+ /*SigmaDelta SD DIV programming */\r
+ HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_CLKSEL_DPLL_PCIE_REF,\r
+ CM_CLKSEL_DPLL_PCIE_REF_DPLL_SD_DIV, 0x06U);\r
+\r
+ /*PCIe DPLL - M2 programming*/\r
+ HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_DIV_M2_DPLL_PCIE_REF,\r
+ CM_DIV_M2_DPLL_PCIE_REF_DIVHS, 0x0FU);\r
+\r
+ /*DPLL Enable*/\r
+ HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_CLKMODE_DPLL_PCIE_REF,\r
+ CM_CLKMODE_DPLL_PCIE_REF_DPLL_EN,\r
+ CM_CLKMODE_DPLL_PCIE_REF_DPLL_EN_DPLL_LOCK_MODE);\r
+\r
+ /* Check for DPLL lock status */\r
+ while (((HW_RD_REG32(SOC_CKGEN_CM_CORE_BASE + CM_IDLEST_DPLL_PCIE_REF) &\r
+ CM_IDLEST_DPLL_PCIE_REF_ST_DPLL_CLK_MASK) <<\r
+ CM_IDLEST_DPLL_PCIE_REF_ST_DPLL_CLK_SHIFT) !=\r
+ CM_IDLEST_DPLL_PCIE_REF_ST_DPLL_CLK_DPLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+\r
+ /*PCIe Tx and Rx Control of ACSPCIe*/\r
+ HW_WR_FIELD32(SOC_SEC_EFUSE_REGISTERS_BASE + CSL_CONTROL_CORE_SEC_SMA_SW_6,\r
+ CSL_CONTROL_CORE_SEC_SMA_SW_6_PCIE_TX_RX_CONTROL, 0x02U);\r
+\r
+ /*Locking APLL to 2.5GHz with 100MHz input*/\r
+ regVal = HW_RD_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKMODE_APLL_PCIE);\r
+\r
+ HW_SET_FIELD(regVal, CM_CLKMODE_APLL_PCIE_CLKDIV_BYPASS,\r
+ CM_CLKMODE_APLL_PCIE_CLKDIV_BYPASS_PCIEDIVBY2_BYPASS_1);\r
+\r
+ HW_SET_FIELD(regVal, CM_CLKMODE_APLL_PCIE_REFSEL,\r
+ CM_CLKMODE_APLL_PCIE_REFSEL_CLKREF_ADPLL);\r
+\r
+ HW_WR_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKMODE_APLL_PCIE, regVal);\r
+\r
+ HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_CLKMODE_APLL_PCIE,\r
+ CM_CLKMODE_APLL_PCIE_MODE_SELECT,\r
+ CM_CLKMODE_APLL_PCIE_MODE_SELECT_APLL_FORCE_LOCK_MODE);\r
+\r
+ /*Wait for APLL lock*/\r
+ while (((HW_RD_REG32(SOC_CKGEN_CM_CORE_BASE + CM_IDLEST_APLL_PCIE) &\r
+ CM_IDLEST_APLL_PCIE_ST_APLL_CLK_MASK) <<\r
+ CM_IDLEST_APLL_PCIE_ST_APLL_CLK_SHIFT) !=\r
+ CM_IDLEST_APLL_PCIE_ST_APLL_CLK_APLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+}\r
+\r
+void PlatformPCIESS1Reset(void)\r
+{\r
+ /*Reset PCIeSS1*/\r
+ HW_WR_FIELD32(SOC_L3INIT_PRM_BASE + RM_PCIESS_RSTCTRL,\r
+ RM_PCIESS_RSTCTRL_RST_LOCAL_PCIE1,\r
+ RM_PCIESS_RSTCTRL_RST_LOCAL_PCIE1_ASSERT);\r
+\r
+ /* Wait till PCIeSS1 is out of reset */\r
+ while (((HW_RD_REG32(SOC_L3INIT_PRM_BASE + RM_PCIESS_RSTST) &\r
+ RM_PCIESS_RSTST_RST_LOCAL_PCIE1_MASK) <<\r
+ RM_PCIESS_RSTST_RST_LOCAL_PCIE1_SHIFT) !=\r
+ RM_PCIESS_RSTST_RST_LOCAL_PCIE1_RESET_YES)\r
+ {\r
+ ;\r
+ }\r
+}\r
+\r
+void PlatformPCIESS1CtrlConfig(void)\r
+{\r
+ uint32_t regVal;\r
+\r
+ /*CONTROL MODULE PWR CTL REG status of PCIeSS1*/\r
+ regVal = HW_RD_REG32(\r
+ SOC_SEC_EFUSE_REGISTERS_BASE + CSL_CONTROL_CORE_SEC_PHY_POWER_PCIESS1);\r
+\r
+ HW_SET_FIELD(regVal, CSL_CONTROL_CORE_SEC_PHY_POWER_PCIESS1_PCIESS1_PWRCTL_CMD,\r
+ 0x03U);\r
+\r
+ HW_SET_FIELD(regVal, CSL_CONTROL_CORE_SEC_PHY_POWER_PCIESS1_PCIESS1_PWRCTL_CLKFREQ,\r
+ 0x1AU);\r
+\r
+ HW_WR_REG32(SOC_SEC_EFUSE_REGISTERS_BASE + CSL_CONTROL_CORE_SEC_PHY_POWER_PCIESS1,\r
+ regVal);\r
+\r
+ /*Set PCIeSS1 delay count*/\r
+ HW_WR_FIELD32(SOC_SEC_EFUSE_REGISTERS_BASE + CSL_CONTROL_CORE_SEC_PCIE_PCS,\r
+ CSL_CONTROL_CORE_SEC_PCIE_PCS_PCIESS1_PCS_RC_DELAY_COUNT, 0xF1U);\r
+ /*Set PCIeSS2 delay count*/\r
+ HW_WR_FIELD32(SOC_SEC_EFUSE_REGISTERS_BASE + CSL_CONTROL_CORE_SEC_PCIE_PCS,\r
+ CSL_CONTROL_CORE_SEC_PCIE_PCS_PCIESS2_PCS_RC_DELAY_COUNT, 0xF1U);\r
+}\r
+\r
+void PlatformPCIESS1PhyConfig(void)\r
+{\r
+ uint32_t regVal;\r
+\r
+ /*Program for Analog circuits in the IP.*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x0CU);\r
+ regVal &= 0x07FFFFFFU;\r
+ regVal |= ((uint32_t) 0x10U << 24U);\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x0CU, regVal);\r
+\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x0CU);\r
+ regVal &= 0xFFFC3FFFU;\r
+ regVal |= ((uint32_t) 0x10U << 12U);\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x0CU, regVal);\r
+\r
+ /*Program for digital section of the IP.*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x28U);\r
+ regVal &= 0xE30007FFU;\r
+ regVal |= 0x001B3000U;\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x28U, regVal);\r
+\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x0CU);\r
+ regVal &= 0xFFFFFF9FU;\r
+ regVal |= ((uint32_t) 0x0U << 4U);\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x0CU, regVal);\r
+\r
+ /*Determines which of the 4 EFUSE registers. Selects dll_rate2_coarsetrim*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x1CU);\r
+ regVal &= 0x3FFFFFFFU;\r
+ regVal |= ((uint32_t) 0x8U << 28U);\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x1CU, regVal);\r
+\r
+ /*\r
+ * Programs the DLL and the Phase Interpolator analog RW 0x3\r
+ * circuits to work with different clock frequencies\r
+ */\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x24U);\r
+ regVal &= 0x3FFFFFFFU;\r
+ regVal |= ((uint32_t) 0xCU << 28U);\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x24U, regVal);\r
+\r
+ /*Program IP Equalizer*/\r
+ regVal = HW_RD_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x38U);\r
+ regVal &= 0x0U;\r
+ regVal |= 0x0000F80FU;\r
+ HW_WR_REG32(SOC_OCP2SCP3_USB3RX_PHY_PCIE1_BASE + 0x38U, regVal);\r
+}\r
+\r
old mode 100644 (file)
new mode 100755 (executable)
similarity index 54%
rename from soc/am572x/src/pcie_soc.c
rename to example/sample/am57x/src/pcie_sample_board.h
index ca3ff61..41aeac6
new mode 100755 (executable)
similarity index 54%
rename from soc/am572x/src/pcie_soc.c
rename to example/sample/am57x/src/pcie_sample_board.h
index ca3ff61..41aeac6
-/**
- * @file am572x/src/pcie_soc.c
- *
- * @brief
- * This file contains the device specific configuration and initialization routines
- * for pcie Low Level Driver.
- *
- * \par
- * ============================================================================
- * @n (C) Copyright 2015, Texas Instruments, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \par
-*/
-
-/**
- * This file contains an example device configuration for the pcie LLD.
- * It is not precompiled to facilitate user modification of the file.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-
-/* CSL RL includes */
-#include <ti/csl/cslr_device.h>
-#include <ti/csl/cslr_bootcfg.h>
-
-#include <ti/csl/csl_bootcfg.h>
-
-/* pcie LLD includes */
-#include <ti/drv/pcie/device/pcie_device.h>
-#include <ti/drv/pcie/pcie.h>
-
-/** @addtogroup PCIE_LLD_DATASTRUCT
-@{
-*/
-
-/** @brief PCIE LLD initialization parameters */
-const Pcie_InitCfg pcieInitCfg =
-{
- {
- {
- {
- (void *)CSL_PCIE_SLV_CFG_REGS,
- (void *)CSL_PCIE_SLV_DATA,
- (volatile uint32_t *)&hBootCfg->DEVCFG,
- CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK,
- CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT
- },
- {
- NULL,
- NULL,
- NULL,
- 0,
- 0
- },
- {
- NULL,
- NULL,
- NULL,
- 0,
- 0
- },
- {
- NULL,
- NULL,
- NULL,
- 0,
- 0
- }
- }
- }
-};
-
-/**
-@}
-*/
-
+/* ============================================================================\r
+ * Copyright (c) Texas Instruments Incorporated 2015\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+\r
+/** \r
+ * @file pcie_example_board.h\r
+ *\r
+ */\r
+\r
+#ifndef _PCIE_SAMPLE_BOARD_H_\r
+#define _PCIE_SAMPLE_BOARD_H_\r
+\r
+void PlatformUnlockMMR(void);\r
+void PlatformPCIESS1ClockEnable(void);\r
+void PlatformPCIESS1PllConfig(void);\r
+void PlatformPCIESS1Reset(void);\r
+void PlatformPCIESS1CtrlConfig(void);\r
+void PlatformPCIESS1PhyConfig(void);\r
+\r
+#endif\r
+\r
index 5985fe414a9fd628e10cf4b1ca9a14c19bb530c9..5698db8d3e16728c33feb3786ab507647d5f0117 100644 (file)
#define System_printf printf\r
#include <stdio.h>\r
\r
+#ifndef DEVICE_AM572x\r
#include <ti/csl/csl_bootcfgAux.h>\r
-#include <ti/csl/csl_cacheAux.h>\r
-#include <ti/csl/csl_chip.h>\r
#include <ti/csl/csl_xmcAux.h>\r
#include <ti/csl/csl_serdes_pcie.h>\r
+#include <ti/csl/csl_pscAux.h>\r
+#define PCIE_REV0_HW\r
+#else\r
+#include "pcie_sample_board.h"\r
+#define PCIE_REV1_HW\r
+#endif\r
+#include <ti/csl/csl_cacheAux.h>\r
+#include <ti/csl/csl_chip.h>\r
\r
\r
#pragma DATA_SECTION(dstBuf, ".dstBufSec")\r
from CCS. It should be set either to EP or RC. */\r
pcieMode_e PcieModeGbl = pcie_EP_MODE; \r
\r
+\r
#ifndef CSL_PSC_PD_PCIE\r
#define CSL_PSC_PD_PCIE CSL_PSC_PD_PCIE_0\r
#endif\r
#define CSL_PSC_LPSC_PCIE CSL_PSC_LPSC_PCIE_0\r
#endif\r
\r
+/*****************************************************************************\r
+ * Function: Enable/Disable DBI writes\r
+ ****************************************************************************/\r
+pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable)\r
+{\r
+ pcieRegisters_t regs;\r
+ pcieRet_e retVal;\r
+#ifdef PCIE_REV0_HW\r
+ pcieCmdStatusReg_t cmdStatus;\r
+\r
+ memset (&cmdStatus, 0, sizeof(cmdStatus));\r
+ memset (®s, 0, sizeof(regs));\r
+\r
+ regs.cmdStatus = &cmdStatus;\r
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK) \r
+ {\r
+ System_printf ("Read CMD STATUS register failed!\n");\r
+ return retVal;\r
+ }\r
+ cmdStatus.dbi = enable;\r
+ \r
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK) \r
+ {\r
+ System_printf ("SET CMD STATUS register failed!\n");\r
+ return retVal;\r
+ }\r
+#else\r
+ pciePlconfDbiRoWrEnReg_t dbiRo;\r
+\r
+ memset (&dbiRo, 0, sizeof(dbiRo));\r
+ memset (®s, 0, sizeof(regs));\r
+\r
+ regs.plconfDbiRoWrEn = &dbiRo;\r
+\r
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK) \r
+ {\r
+ System_printf ("SET CMD STATUS register failed!\n");\r
+ return retVal;\r
+ }\r
+#endif\r
+ return pcie_RET_OK;\r
+} /* pcieCfgDbi */\r
+\r
/*****************************************************************************\r
* Function: Power domain configuration\r
****************************************************************************/\r
pcieRet_e pciePowerCfg(void)\r
{\r
+#ifndef DEVICE_AM572x\r
/* Turn on the PCIe power domain */\r
if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_PCIE) != PSC_PDSTATE_ON) {\r
/* Enable the domain */\r
} else {\r
System_printf ("Power domain is already enabled. You probably re-ran without device reset (which is OK)\n");\r
}\r
+#endif\r
\r
return pcie_RET_OK;\r
}\r
****************************************************************************/\r
pcieRet_e pcieSerdesCfg(void)\r
{\r
-#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L)\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \\r
+ !defined(DEVICE_AM572x)\r
uint16_t cfg;\r
-#endif\r
- \r
-#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L)\r
+\r
/* Provide PLL reference clock to SERDES inside PCIESS\r
Program PLL settings and enable PLL from PCIe SERDES.*/\r
cfg = 0x01C9; /* value based on PCIe userguide */\r
\r
CSL_BootCfgSetPCIEConfigPLL(cfg);\r
#else /* !DEVICE_K2K && !DEVICE_K2H && !DEVICE_K2E && !DEVICE_K2L */\r
+#if defined(DEVICE_AM572x)\r
+ PlatformUnlockMMR();\r
+ PlatformPCIESS1ClockEnable();\r
+ PlatformPCIESS1PllConfig();\r
+ PlatformPCIESS1CtrlConfig();\r
+ PlatformPCIESS1Reset();\r
+ PlatformPCIESS1PhyConfig();\r
+#else\r
#ifndef SIMULATOR_SUPPORT\r
CSL_SERDES_RESULT csl_retval;\r
CSL_SERDES_STATUS pllstat;\r
printf ("Debug: Serdes Setup Successfully\n");\r
#endif\r
#endif\r
+#endif\r
#endif\r
/*Wait for PLL to lock (3000 CLKIN1 cycles) */\r
cycleDelay(10000);\r
\r
/*****************************************************************************\r
* Function: Enable/Disable LTSSM (Link Training)\r
+ * This function demonstrates how one can write one binary to use either\r
+ * rev of PCIE\r
****************************************************************************/\r
pcieRet_e pcieLtssmCtrl(Pcie_Handle handle, uint8_t enable)\r
{\r
- pcieCmdStatusReg_t cmdStatus;\r
- pcieRegisters_t setRegs;\r
- pcieRegisters_t getRegs;\r
+ pcieCmdStatusReg_t cmdStatus;\r
+ pcieTiConfDeviceCmdReg_t deviceCmd;\r
+ pcieRegisters_t regs;\r
pcieRet_e retVal;\r
\r
memset (&cmdStatus, 0, sizeof(cmdStatus));\r
- memset (&setRegs, 0, sizeof(setRegs));\r
- memset (&getRegs, 0, sizeof(getRegs));\r
+ memset (&deviceCmd, 0, sizeof(deviceCmd));\r
+ memset (®s, 0, sizeof(regs));\r
\r
- getRegs.cmdStatus = &cmdStatus;\r
- if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK) \r
+ regs.cmdStatus = &cmdStatus;\r
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)\r
{\r
- System_printf ("Read CMD STATUS register failed!\n");\r
- return retVal;\r
+ if (retVal == pcie_RET_INV_REG)\r
+ {\r
+ /* The cmdStatus register doesn't exist; try the deviceCmd instead */\r
+ regs.cmdStatus = NULL;\r
+ regs.tiConfDeviceCmd = &deviceCmd;\r
+ if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)\r
+ {\r
+ System_printf ("Read CMD STATUS and DEVICE CMD registers failed!\n");\r
+ return retVal;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ System_printf ("Read CMD STATUS register failed!\n");\r
+ return retVal;\r
+ }\r
}\r
\r
if(enable)\r
- cmdStatus.ltssmEn = 1;\r
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1;\r
else \r
- cmdStatus.ltssmEn = 0;\r
+ deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0;\r
\r
- setRegs.cmdStatus = &cmdStatus; \r
- \r
- if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK) \r
+ if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, ®s)) != pcie_RET_OK)\r
{\r
System_printf ("SET CMD STATUS register failed!\n");\r
return retVal;\r
{\r
pcieRet_e retVal;\r
\r
- pcieCmdStatusReg_t cmdStatus;\r
pcieObSizeReg_t obSize;\r
pcieGen2Reg_t gen2;\r
pcieType1Bar32bitIdx_t type1Bar32bitIdx;\r
pcieRegisters_t setRegs;\r
pcieRegisters_t getRegs;\r
\r
- memset (&cmdStatus, 0, sizeof(cmdStatus));\r
memset (&obSize, 0, sizeof(obSize));\r
memset (&gen2, 0, sizeof(gen2));\r
memset (&type1Bar32bitIdx, 0, sizeof(type1Bar32bitIdx));\r
memset (&setRegs, 0, sizeof(setRegs));\r
memset (&getRegs, 0, sizeof(getRegs));\r
\r
+#ifdef PCIE_REV0_HW\r
+ /* Only required for v0 hw */\r
obSize.size = pcie_OB_SIZE_8MB;\r
setRegs.obSize = &obSize;\r
\r
System_printf ("SET OB_SIZE register failed!\n");\r
return retVal;\r
}\r
+#endif\r
\r
/* Setting PL_GEN2 */ \r
memset (&setRegs, 0, sizeof(setRegs));\r
\r
/* Configure BAR Masks */ \r
/* First need to enable writing on BAR mask registers */\r
- memset (&setRegs, 0, sizeof(setRegs));\r
- memset (&getRegs, 0, sizeof(getRegs));\r
- memset (&cmdStatus, 0, sizeof(cmdStatus));\r
-\r
- getRegs.cmdStatus = &cmdStatus;\r
- if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK) \r
- {\r
- System_printf ("Read CMD STATUS register failed!\n");\r
- return retVal;\r
- }\r
- cmdStatus.dbi = 1;\r
- setRegs.cmdStatus = &cmdStatus; \r
- \r
- if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK) \r
+ if ((retVal = pcieCfgDbi (handle, 1)) != pcie_RET_OK)\r
{\r
- System_printf ("SET CMD STATUS register failed!\n");\r
return retVal;\r
}\r
\r
/* Configure Masks*/\r
memset (&setRegs, 0, sizeof(setRegs));\r
+ memset (&getRegs, 0, sizeof(getRegs));\r
+\r
type1Bar32bitIdx.reg.reg32 = PCIE_BAR_MASK;\r
- setRegs.type1Bar32bitIdx = &type1Bar32bitIdx;\r
+ setRegs.type1BarMask32bitIdx = &type1Bar32bitIdx;\r
\r
/* BAR 0 */\r
type1Bar32bitIdx.idx = 0; /* configure BAR 0*/\r
}\r
\r
/* Disable writing on BAR Masks */\r
- memset (&setRegs, 0, sizeof(setRegs));\r
- memset (&getRegs, 0, sizeof(getRegs));\r
- memset (&cmdStatus, 0, sizeof(cmdStatus));\r
-\r
- getRegs.cmdStatus = &cmdStatus;\r
- if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK) \r
- {\r
- System_printf ("Read CMD STATUS register failed!\n");\r
- return retVal;\r
- }\r
- cmdStatus.dbi = 0;\r
- setRegs.cmdStatus = &cmdStatus; \r
- \r
- if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK) \r
+ if ((retVal = pcieCfgDbi (handle, 0)) != pcie_RET_OK)\r
{\r
- System_printf ("SET CMD STATUS register failed!\n");\r
return retVal;\r
}\r
\r
return retVal;\r
}\r
\r
+#ifdef PCIE_REV0_HW\r
/* Enable ECRC */\r
memset (&setRegs, 0, sizeof(setRegs));\r
\r
System_printf ("SET ACCR register failed!\n");\r
return retVal;\r
}\r
+#endif\r
\r
return pcie_RET_OK;\r
}\r
{\r
pcieRet_e retVal;\r
\r
- pcieCmdStatusReg_t cmdStatus;\r
pcieObSizeReg_t obSize;\r
pcieGen2Reg_t gen2;\r
pcieType0Bar32bitIdx_t type0Bar32bitIdx;\r
pcieRegisters_t setRegs;\r
pcieRegisters_t getRegs;\r
\r
- memset (&cmdStatus, 0, sizeof(cmdStatus));\r
memset (&obSize, 0, sizeof(obSize));\r
memset (&gen2, 0, sizeof(gen2));\r
memset (&type0Bar32bitIdx, 0, sizeof(type0Bar32bitIdx));\r
memset (&setRegs, 0, sizeof(setRegs));\r
memset (&getRegs, 0, sizeof(getRegs));\r
\r
+#ifdef PCIE_REV0_HW\r
+ /* Only required for rev 0 */\r
obSize.size = pcie_OB_SIZE_8MB;\r
setRegs.obSize = &obSize;\r
\r
System_printf ("SET OB_SIZE register failed!\n");\r
return retVal;\r
}\r
+#endif\r
\r
/* Setting PL_GEN2 */ \r
memset (&setRegs, 0, sizeof(setRegs));\r
\r
/* Configure BAR Masks */ \r
/* First need to enable writing on BAR mask registers */\r
- memset (&setRegs, 0, sizeof(setRegs));\r
- memset (&getRegs, 0, sizeof(getRegs));\r
- memset (&cmdStatus, 0, sizeof(cmdStatus));\r
-\r
- getRegs.cmdStatus = &cmdStatus;\r
- if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK) \r
+ if ((retVal = pcieCfgDbi (handle, 1)) != pcie_RET_OK)\r
{\r
- System_printf ("Read CMD STATUS register failed!\n");\r
return retVal;\r
}\r
- cmdStatus.dbi = 1;\r
- setRegs.cmdStatus = &cmdStatus; \r
- \r
- if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK) \r
- {\r
- System_printf ("SET CMD STATUS register failed!\n");\r
- return retVal;\r
- }\r
- \r
+\r
/* Configure Masks*/\r
+ memset (&getRegs, 0, sizeof(getRegs));\r
memset (&setRegs, 0, sizeof(setRegs));\r
type0Bar32bitIdx.reg.reg32 = PCIE_BAR_MASK;\r
- setRegs.type0Bar32bitIdx = &type0Bar32bitIdx;\r
+ setRegs.type0BarMask32bitIdx = &type0Bar32bitIdx;\r
\r
/* BAR 0 */\r
type0Bar32bitIdx.idx = 0; /* configure BAR 0*/\r
return retVal;\r
}\r
\r
- /* Disable writing on BAR Masks */\r
- memset (&setRegs, 0, sizeof(setRegs));\r
- memset (&getRegs, 0, sizeof(getRegs));\r
- memset (&cmdStatus, 0, sizeof(cmdStatus));\r
-\r
- getRegs.cmdStatus = &cmdStatus;\r
- if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK) \r
+ /* Disable DBI writes */\r
+ if ((retVal = pcieCfgDbi (handle, 0)) != pcie_RET_OK)\r
{\r
- System_printf ("Read CMD STATUS register failed!\n");\r
return retVal;\r
}\r
- cmdStatus.dbi = 0;\r
- setRegs.cmdStatus = &cmdStatus; \r
\r
- if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK) \r
- {\r
- System_printf ("SET CMD STATUS register failed!\n");\r
- return retVal;\r
- }\r
-\r
/* Enable memory access and mastership of the bus */\r
memset (&setRegs, 0, sizeof(setRegs));\r
memset (&getRegs, 0, sizeof(getRegs));\r
System_printf ("SET Device Status Control register failed!\n");\r
return retVal;\r
}\r
-\r
+ \r
+#ifdef PCIE_REV0_HW\r
/* Enable ECRC */\r
memset (&setRegs, 0, sizeof(setRegs));\r
\r
System_printf ("SET ACCR register failed!\n");\r
return retVal;\r
}\r
+#endif\r
\r
return pcie_RET_OK;\r
}\r
\r
+#ifdef PCIE_REV0_HW\r
/*****************************************************************************\r
- * Function: Configure and enable Outbound Address Translation \r
+ * Function: Configure and enable Outbound Address Translation for rev 0\r
****************************************************************************/\r
pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrHi, uint8_t region)\r
{\r
@@ -738,7 +767,7 @@ pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrH
\r
\r
/*****************************************************************************\r
- * Function: Configure and enable Inbound Address Translation \r
+ * Function: Configure and enable Inbound Address Translation for rev 0\r
****************************************************************************/\r
pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg)\r
{\r
\r
return pcie_RET_OK;\r
}\r
+#else\r
+\r
+/*****************************************************************************\r
+ * Function: Configure and enable Outbound Address Translation for rev 1\r
+ ****************************************************************************/\r
+pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrHi, uint8_t region)\r
+{\r
+ pcieAtuRegionParams_t regionParams;\r
+ pcieRet_e retVal;\r
+\r
+ if(PcieModeGbl == pcie_RC_MODE)\r
+ {\r
+ /*Configure OB region for remote configuration access space*/\r
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;\r
+ regionParams.tlpType = PCIE_TLP_TYPE_CFG;\r
+ regionParams.enableRegion = 1;\r
+\r
+ regionParams.lowerBaseAddr = PCIE_WINDOW_CFG_BASE;\r
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */\r
+ regionParams.regionWindowSize = PCIE_WINDOW_CFG_MASK;\r
+\r
+ regionParams.lowerTargetAddr = 0U;\r
+ regionParams.upperTargetAddr = 0U;\r
+\r
+ if ( (retVal = Pcie_atuRegionConfig(\r
+ handle,\r
+ pcie_LOCATION_LOCAL,\r
+ (uint32_t) 0U,\r
+ ®ionParams)) != pcie_RET_OK) \r
+ {\r
+ return retVal;\r
+ }\r
+ }\r
+\r
+ /*Configure OB region for memory transfer*/\r
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;\r
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;\r
+ regionParams.enableRegion = 1;\r
+\r
+ regionParams.lowerBaseAddr = PCIE_WINDOW_MEM_BASE;\r
+ regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */\r
+ regionParams.regionWindowSize = PCIE_WINDOW_MEM_MASK;\r
+\r
+ regionParams.lowerTargetAddr = obAddrLo;\r
+ regionParams.upperTargetAddr = obAddrHi;\r
+\r
+ return Pcie_atuRegionConfig(\r
+ handle,\r
+ pcie_LOCATION_LOCAL,\r
+ (uint32_t) 1U,\r
+ ®ionParams);\r
+}\r
+\r
+/*****************************************************************************\r
+ * Function: Configure and enable Inbound Address Translation for rev 1\r
+ ****************************************************************************/\r
+pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg)\r
+{\r
+ pcieAtuRegionParams_t regionParams;\r
+\r
+ /*Configure IB region for memory transfer*/\r
+ regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND;\r
+ regionParams.tlpType = PCIE_TLP_TYPE_MEM;\r
+ regionParams.enableRegion = 1;\r
+ regionParams.matchMode = PCIE_ATU_REGION_MATCH_MODE_ADDR;\r
+\r
+ regionParams.lowerBaseAddr = ibCfg->ibStartAddrLo;\r
+ regionParams.upperBaseAddr = ibCfg->ibStartAddrHi;\r
+ regionParams.regionWindowSize = PCIE_INBOUND_MASK;\r
+\r
+ /* This aligns the buffer to 4K, which needs to be compensated by the application */\r
+ regionParams.lowerTargetAddr = (ibCfg->ibOffsetAddr & ~0x3ffU) ;\r
+ regionParams.upperTargetAddr = 0;\r
+\r
+ return Pcie_atuRegionConfig(\r
+ handle,\r
+ pcie_LOCATION_LOCAL,\r
+ (uint32_t) 0U,\r
+ ®ionParams);\r
+}\r
+#endif\r
\r
\r
/*****************************************************************************\r
void pcieWaitLinkUp(Pcie_Handle handle)\r
{\r
pcieRegisters_t getRegs;\r
- pcieDebug0Reg_t debug0;\r
- \r
- memset (&debug0, 0, sizeof(debug0));\r
+\r
memset (&getRegs, 0, sizeof(getRegs));\r
+\r
+#ifdef PCIE_REV0_HW\r
+ pcieDebug0Reg_t ltssmStateReg;\r
+ getRegs.debug0 = <ssmStateReg;\r
+#else\r
+ pcieTiConfDeviceCmdReg_t ltssmStateReg;\r
+ getRegs.tiConfDeviceCmd = <ssmStateReg;\r
+#endif\r
+ \r
+ memset (<ssmStateReg, 0, sizeof(ltssmStateReg));\r
\r
uint8_t ltssmState = 0;\r
\r
while(ltssmState != pcie_LTSSM_L0)\r
{\r
cycleDelay(100);\r
- getRegs.debug0 = &debug0;\r
if (Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &getRegs) != pcie_RET_OK) \r
{\r
System_printf ("Read LTSSM state failed!\n");\r
return;\r
}\r
- ltssmState = debug0.ltssmState;\r
+ ltssmState = ltssmStateReg.ltssmState;\r
}\r
}\r
\r
-\r
-\r
/*****************************************************************************\r
* Function: Converts a core local L2 address to a global L2 address \r
* Input addr: L2 address to be converted to global.\r
/* Get the core number. */\r
coreNum = CSL_chipReadReg(CSL_CHIP_DNUM); \r
\r
+#ifdef DEVICE_AM572x\r
+ /* Compute the global address. */\r
+ return ((1 << 30) | (coreNum << 24) | (addr & 0x00ffffff));\r
+\r
+#else\r
/* Compute the global address. */\r
return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));\r
+#endif\r
} \r
\r
\r
void main (void)\r
{\r
TSCL = 1;\r
-#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L)\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \\r
+ !defined(DEVICE_AM572x)\r
uint16_t lock=0;\r
#endif\r
pcieRet_e retVal;\r
uint32_t i;\r
\r
/* Unlock kicker once, and don't relock, because its not multicore safe */\r
+#if !defined(DEVICE_AM572x)\r
CSL_BootCfgUnlockKicker();\r
+#endif\r
\r
System_printf ("**********************************************\n");\r
System_printf ("* PCIe Test Start *\n");\r
System_printf ("PCIe Power Up.\n");\r
\r
/* Wait until the PCIe SERDES PLL locks */\r
-#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L)\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2E) && !defined(DEVICE_K2L) && \\r
+ !defined(DEVICE_AM572x)\r
while (!lock)\r
{\r
CSL_BootCfgGetPCIEPLLLock(&lock);\r
} \r
-#endif /* !DEVICE_K2K && !DEVICE_K2H && !DEVICE_K2E && !DEVICE_K2L */\r
+#endif /* !DEVICE_K2K && !DEVICE_K2H && !DEVICE_K2E && !DEVICE_K2L && !DEVICE_AM572x */\r
\r
\r
System_printf ("PLL configured.\n");\r
\r
barCfg.location = pcie_LOCATION_LOCAL;\r
barCfg.mode = pcie_RC_MODE;\r
- barCfg.base = PCIE_IB_LO_ADDR_M;\r
+ barCfg.base = PCIE_IB_LO_ADDR_RC;\r
barCfg.prefetch = pcie_BAR_NON_PREF;\r
barCfg.type = pcie_BAR_TYPE32;\r
barCfg.memSpace = pcie_BAR_MEM_MEM;\r
- barCfg.idx = PCIE_BAR_IDX_M;\r
+ barCfg.idx = PCIE_BAR_IDX_RC;\r
\r
if ((retVal = Pcie_cfgBar(handle, &barCfg)) != pcie_RET_OK) \r
{\r
exit(1);\r
}\r
\r
- ibCfg.ibBar = PCIE_BAR_IDX_M; /* Match BAR that was configured above*/\r
- ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_M;\r
- ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_M;\r
+\r
+ ibCfg.ibBar = PCIE_BAR_IDX_RC; /* Match BAR that was configured above*/\r
+ ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_RC;\r
+ ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_RC;\r
ibCfg.ibOffsetAddr = (uint32_t)pcieConvert_CoreLocal2GlobalAddr ((uint32_t)dstBuf.buf);\r
- ibCfg.region = PCIE_IB_REGION_M; \r
+ ibCfg.region = PCIE_IB_REGION_RC; \r
\r
if ((retVal = pcieIbTransCfg(handle, &ibCfg)) != pcie_RET_OK) \r
{\r
System_printf ("Successfully configured Inbound Translation!\n");\r
}\r
\r
- if ((retVal = pcieObTransCfg (handle, PCIE_OB_LO_ADDR_M, PCIE_OB_HI_ADDR_M, PCIE_OB_REGION_M)) != pcie_RET_OK) \r
+ if ((retVal = pcieObTransCfg (handle, PCIE_OB_LO_ADDR_RC, PCIE_OB_HI_ADDR_RC, PCIE_OB_REGION_RC)) != pcie_RET_OK) \r
{\r
System_printf ("Failed to configure Outbound Address Translation (%d)\n", (int)retVal);\r
exit(1);\r
\r
barCfg.location = pcie_LOCATION_LOCAL;\r
barCfg.mode = pcie_EP_MODE;\r
- barCfg.base = PCIE_IB_LO_ADDR_S;\r
+ barCfg.base = PCIE_IB_LO_ADDR_EP;\r
barCfg.prefetch = pcie_BAR_NON_PREF;\r
barCfg.type = pcie_BAR_TYPE32;\r
barCfg.memSpace = pcie_BAR_MEM_MEM;\r
- barCfg.idx = PCIE_BAR_IDX_S;\r
+ barCfg.idx = PCIE_BAR_IDX_EP;\r
\r
if ((retVal = Pcie_cfgBar(handle, &barCfg)) != pcie_RET_OK) \r
{\r
exit(1);\r
}\r
\r
- ibCfg.ibBar = PCIE_BAR_IDX_S; /* Match BAR that was configured above*/\r
- ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_S;\r
- ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_S;\r
+ ibCfg.ibBar = PCIE_BAR_IDX_EP; /* Match BAR that was configured above*/\r
+ ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_EP;\r
+ ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_EP;\r
ibCfg.ibOffsetAddr = (uint32_t)pcieConvert_CoreLocal2GlobalAddr ((uint32_t)dstBuf.buf);\r
- ibCfg.region = PCIE_IB_REGION_S; \r
+ ibCfg.region = PCIE_IB_REGION_EP; \r
\r
if ((retVal = pcieIbTransCfg(handle, &ibCfg)) != pcie_RET_OK) \r
{\r
System_printf ("Successfully configured Inbound Translation!\n");\r
}\r
\r
- if ((retVal = pcieObTransCfg (handle, PCIE_OB_LO_ADDR_S, PCIE_OB_HI_ADDR_S, PCIE_OB_REGION_S)) != pcie_RET_OK) \r
+ if ((retVal = pcieObTransCfg (handle, PCIE_OB_LO_ADDR_EP, PCIE_OB_HI_ADDR_EP, PCIE_OB_REGION_EP)) != pcie_RET_OK) \r
{\r
System_printf ("Failed to configure Outbound Address Translation!\n", (int)retVal);\r
exit(1);\r
\r
System_printf ("Link is up.\n");\r
\r
+ if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) {\r
+ System_printf ("getMemSpaceRange failed\n", (int)retVal);\r
+ exit(1);\r
+ }\r
+#ifdef PCIE_REV1_HW\r
+ /* Adjust PCIE base to point at remote target buffer */\r
+ pcieBase = (char *)pcieBase + \r
+ PCIE_WINDOW_MEM_BASE + /* data area doesn't start at low address */\r
+ (((uint32_t)dstBuf.buf) & 0x3ff); /* dstBuf needs to be 4K aligned in addr tran */\r
+#endif\r
+\r
\r
if(PcieModeGbl == pcie_RC_MODE)\r
{\r
/**********************************************************************/\r
\r
/* Write from RC to EP */\r
- if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) {\r
- System_printf ("getMemSpaceRange failed\n", (int)retVal);\r
- exit(1);\r
- }\r
-\r
for (i=0; i<PCIE_BUFSIZE_APP; i++)\r
{\r
*((volatile uint32_t *)pcieBase + i) = srcBuf[i];\r
\r
/* Loopback to RC what was written in the DST buffer.\r
Write from EP to RC */\r
- if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) {\r
- System_printf ("getMemSpaceRange failed\n", (int)retVal);\r
- exit(1);\r
- }\r
-\r
for (i=0; i<PCIE_BUFSIZE_APP; i++)\r
{\r
*((volatile uint32_t *)pcieBase + i) = dstBuf.buf[i];\r
/* ============================================================================\r
- * Copyright (c) Texas Instruments Incorporated 2010\r
+ * Copyright (c) Texas Instruments Incorporated 2010-2015\r
* \r
* Redistribution and use in source and binary forms, with or without \r
* modification, are permitted provided that the following conditions \r
* @brief \r
* Holds all the constants and API definitions required by the example\r
* application to run. \r
- *\r
- * \par\r
- * ============================================================================\r
- * @n (C) Copyright 2010, Texas Instruments, Inc.\r
- * @n Use of this software is controlled by the terms and conditions found \r
- * @n in the license agreement under which this software has been supplied.\r
- * ===========================================================================\r
- * \par \r
*/\r
\r
#ifndef _PCIE_SAMPLE_H_\r
#include <ti/sysbios/knl/Event.h>\r
\r
/* CSL include */\r
-#include <ti/csl/csl_pscAux.h>\r
#include <ti/csl/cslr_device.h>\r
\r
/* PCIE LLD include */\r
#define PCIE_WR_PATTERN 0xFACEFACE\r
\r
/* In this example all addresses are 32bit */\r
-/* Outbound Base Address for PCIe Master */\r
-#define PCIE_OB_LO_ADDR_M 0x70000000\r
-#define PCIE_OB_HI_ADDR_M 0\r
+/* Outbound Base Address for PCIe RC */\r
+#define PCIE_OB_LO_ADDR_RC 0x70000000\r
+#define PCIE_OB_HI_ADDR_RC 0\r
+\r
+/* Inbound Base Address for PCIe RC */\r
+#define PCIE_IB_LO_ADDR_RC 0x90000000\r
+#define PCIE_IB_HI_ADDR_RC 0\r
+\r
+/* Outbound Base Address for PCIe EP */\r
+#define PCIE_OB_LO_ADDR_EP PCIE_IB_LO_ADDR_RC\r
+#define PCIE_OB_HI_ADDR_EP 0\r
+\r
+/* Inbound Base Address for PCIe EP */\r
+#define PCIE_IB_LO_ADDR_EP PCIE_OB_LO_ADDR_RC\r
+#define PCIE_IB_HI_ADDR_EP 0\r
\r
-/* Inbound Base Address for PCIe Master */\r
-#define PCIE_IB_LO_ADDR_M 0x90000000\r
-#define PCIE_IB_HI_ADDR_M 0\r
+/* Data area offset relative to PCIe base (only used rev 1) */\r
+#define PCIE_WINDOW_MEM_BASE 0x01000000U\r
+#define PCIE_WINDOW_MEM_MASK 0x00FFFFFFU\r
\r
-/* Outbound Base Address for PCIe Slave */\r
-#define PCIE_OB_LO_ADDR_S PCIE_IB_LO_ADDR_M\r
-#define PCIE_OB_HI_ADDR_S 0\r
+/* Cfg area offset relative to PCIe base (only used rev 1) */\r
+/* This MUST agree Pciev1_DeviceCfgBaseAddrs.bases! */\r
+#define PCIE_WINDOW_CFG_BASE 0x00001000U\r
+#define PCIE_WINDOW_CFG_MASK 0x00000FFFU\r
\r
-/* Inbound Base Address for PCIe Slave */\r
-#define PCIE_IB_LO_ADDR_S PCIE_OB_LO_ADDR_M\r
-#define PCIE_IB_HI_ADDR_S 0\r
+/* Inbound limit (only used rev 1) */\r
+#define PCIE_INBOUND_MASK 0x0FFFFFFFU\r
\r
/* BAR mask */\r
#define PCIE_BAR_MASK 0x0FFFFFFF\r
\r
/* BAR Index PCie*/\r
-#define PCIE_BAR_IDX_M 1\r
-#define PCIE_BAR_IDX_S 1\r
+#define PCIE_BAR_IDX_RC 1\r
+#define PCIE_BAR_IDX_EP 1\r
\r
\r
/* PCIe Regions used in the example */\r
-#define PCIE_IB_REGION_M 0\r
-#define PCIE_OB_REGION_M 0\r
-#define PCIE_IB_REGION_S 0\r
-#define PCIE_OB_REGION_S 0\r
+#define PCIE_IB_REGION_RC 0\r
+#define PCIE_OB_REGION_RC 0\r
+#define PCIE_IB_REGION_EP 0\r
+#define PCIE_OB_REGION_EP 0\r
\r
\r
\r
diff --git a/package.xs b/package.xs
--- a/package.xs
+++ b/package.xs
'k2h',\r
'k2l',\r
'k2e',\r
+ 'k2g',\r
+ 'am57x'\r
];\r
\r
/* Search for the supported devices (defined in config.bld) */\r
index 022dd452a0e40d71aa4bee7792f9a8488a6d401f..b4faaa6c2df3a269418505802e90783dfd7878f5 100644 (file)
--- a/pcie.h
+++ b/pcie.h
* This definition of Local/Remote is only applicable to PCIe configuration registers.\n\r
* It is NOT applicable to PCIe application registers. For application registers, the LLD *always* accesses\r
* LOCAL PCIe application registers.\r
+ *\r
+ * **IMPORTANT** : on Rev 1 hardware, only RC can see EP's registers through\r
+ * pcie_LOCATION_REMOTE. In order for this to work, both Pciev1_DeviceCfgBaseAddrs.remoteOffset,\r
+ * and outbound region 0 in ATU need to be configured for the *same* offset.\r
*/\r
typedef enum\r
{\r
pcie_DISABLE = 0, /**< Disable */\r
pcie_ENABLE /**< Enable */\r
} pcieState_e;\r
+\r
+/**\r
+ * @ingroup pcielld_api_constants\r
+ *\r
+ * @brief Enum to select PCIe ATU(Address translation unit) region\r
+ * direction(Inbound or Outbound).\r
+ * This enum is used while configuring inbound or outbound region.\r
+ *\r
+ * @{\r
+ */\r
+typedef enum pcieAtuRegionDir\r
+{\r
+ PCIE_ATU_REGION_DIR_OUTBOUND, /**< Select PCIe outbound region. */\r
+ PCIE_ATU_REGION_DIR_INBOUND /**< Select PCIe inbound region. */\r
+} pcieAtuRegionDir_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_api_constants\r
+ *\r
+ * @brief This enum is used to select PCIe TLP(Transaction layer packet) type\r
+ * while configuring inbound or outbound region.\r
+ *\r
+ * @{\r
+ */\r
+typedef enum pcieTlpType\r
+{\r
+ PCIE_TLP_TYPE_MEM, /**< MEM type is selected while doing memory transfer */\r
+ PCIE_TLP_TYPE_IO, /**< IO type is selected while doing I/O transfer */\r
+ PCIE_TLP_TYPE_CFG /**< CFG type is selected while doing configuration\r
+ * access */\r
+} pcieTlpType_t;\r
+/* @} */\r
+\r
+/**\r
+ * @ingroup pcielld_api_constants\r
+ *\r
+ * @brief Enum to select address or BAR match mode.\r
+ *\r
+ * @{\r
+ */\r
+typedef enum pcieAtuRegionMatchMode\r
+{\r
+ PCIE_ATU_REGION_MATCH_MODE_ADDR, /**< Inbound packets are filtered by address match mode */\r
+ PCIE_ATU_REGION_MATCH_MODE_BAR /**< Inbound packets are filtered by BAR\r
+ * match mode */\r
+} pcieAtuRegionMatchMode_t;\r
+\r
/* @} */\r
\r
\r
/**\r
* @brief [rw] 32bits word (BAR mask or BAR address)\r
*\r
+ * On rev 0 hardware, may set bar masks through either \r
+ * @ref pcieRegisters_t::type0BarMask32bitIdx or\r
+ * @ref pcieRegisters_t::type0Bar32bitIdx. The determination on \r
+ * whether its a bar mask or bar is made by current value of \r
+ * @ref pcieCmdStatusReg_s::dbi.\r
+ *\r
+ * On rev 1 hardware, MUST set bar masks only through \r
+ * @ref pcieRegisters_t::type0BarMask32bitIdx as this routes through\r
+ * DBICS2. Also, MUST set upper 32 bits using only \r
+ * @ref pcieRegisters_t::type0Bar32bitIdx to route through DBICS.\r
+ *\r
* Field size: 32 bits\r
*/\r
uint32_t reg32;\r
pcieBistReg_t *bist; /**< @brief Bist Header*/\r
pcieType0BarIdx_t *type0BarIdx; /**< @brief Type 0 (EP) BAR register*/\r
pcieType0Bar32bitIdx_t *type0Bar32bitIdx; /**< @brief Type 0 BAR 32bits register*/\r
+ pcieType0Bar32bitIdx_t *type0BarMask32bitIdx; /**< @brief Type 0 BAR mask register*/\r
pcieCardbusCisPointerReg_t *cardbusCisPointer; /**< @brief cardbus CIS pointer register*/\r
pcieSubIdReg_t *subId; /**< @brief Subsystem ID*/\r
pcieExpRomReg_t *expRom; /**< @brief Expansion ROM base addr*/\r
pcieType1BistHeaderReg_t *type1BistHeader; /**< @brief Bist Header, Latency Timer, Cache Line */\r
pcieType1BarIdx_t *type1BarIdx; /**< @brief Type 1 (RC) BAR register*/\r
pcieType1Bar32bitIdx_t *type1Bar32bitIdx; /**< @brief Type 1 BAR 32bits register*/\r
+ pcieType1Bar32bitIdx_t *type1BarMask32bitIdx; /**< @brief Type 1 bar mask register*/\r
pcieType1BusNumReg_t *type1BusNum; /**< @brief Latency Timer and Bus Number */\r
pcieType1SecStatReg_t *type1SecStat; /**< @brief Secondary Status and IO space */\r
pcieType1MemspaceReg_t *type1Memspace; /**< @brief Memory Limit*/\r
uint8_t idx;\r
} pcieBarCfg_t;\r
\r
+/**\r
+ * \brief This Structure defines the ATU region parameters\r
+ *\r
+ * These parameters are used for configuring inbound or outbound\r
+ * ATU(Address translation unit) region\r
+ */\r
+typedef struct pcieAtuRegionParams\r
+{\r
+ pcieAtuRegionDir_t regionDir;\r
+ /**< Region direction Inbound or Outbound\r
+ * Values given by enum #pcieAtuRegionDir_t\r
+ */\r
+ pcieTlpType_t tlpType;\r
+ /**< TLP(transaction layer packet) type\r
+ * Values given by enum #pcieTlpType_t\r
+ */\r
+ uint32_t enableRegion;\r
+ /**< Region enable or disable */\r
+ pcieAtuRegionMatchMode_t matchMode;\r
+ /**< Region match mode Address match or BAR match\r
+ * Values given by enum #pcieAtuRegionMatchMode_t\r
+ */\r
+ uint32_t barNumber;\r
+ /**< BAR number with which the region is associated\r
+ * Possible values for EP : 0 to 5 for 32bit and 0 to 2 for 64bit\r
+ * Possible values for RC : 0 to 1 for 32bit and 0 for 64bit\r
+ */\r
+ uint32_t lowerBaseAddr;\r
+ /**< Lower base address : should be 4K aligned\r
+ * For outbound configuration this contains outbound region offset\r
+ * For inbound configuration this contains inbound PCIe start address\r
+ */\r
+ uint32_t upperBaseAddr;\r
+ /**< Upper base address\r
+ * Higher 32 bits in case of 64 bit addressing\r
+ * Configured to 0 for 32 bit addressing\r
+ */\r
+ uint32_t regionWindowSize;\r
+ /**< Region window size\r
+ * For outbound configuration this contains outbound window size\r
+ * For inbound configuration this contains PCIe inbound window size\r
+ */\r
+ uint32_t lowerTargetAddr;\r
+ /**< Lower Target address: should be 4K aligned\r
+ * For outbound configuration this contains outbound PCIe start offset\r
+ * For inbound configuration this contains destination address\r
+ */\r
+ uint32_t upperTargetAddr;\r
+ /**< Upper target address\r
+ * Higher 32 bits in case of 64 bit addressing\r
+ * Configured to 0 for 32 bit addressing\r
+ */\r
+} pcieAtuRegionParams_t;\r
+\r
/**\r
* @ingroup pcielld_api_structures\r
* @brief Specification of Pcie_DeviceCfgBaseAddr\r
*/\r
typedef struct\r
{\r
+ /** \r
+ * Device-dependant configuration base address. If hw rev has one\r
+ * base, then it is directly here. If it has multiple bases, look in\r
+ * src/v#/pcie.h for pciev#_DeviceCfgBaseAddrs\r
+ */\r
void *cfgBase;\r
+ /** \r
+ * Base address of the "data" area (remote device memory) \r
+ */\r
void *dataBase;\r
- volatile uint32_t *pcieSSModeAddr; /**< address of PCIESSMODE register */\r
- uint32_t pcieSSModeMask; /**< mask for PCIESSMODE field in @ref pcieSSModeAddr */\r
- uint32_t pcieSSModeShift; /**< shift for PCIESSMODE field in @ref pcieSSModeAddr */\r
+ /** \r
+ * Revision-dependant device params. Look for Pciev#_DevParams in\r
+ * src/v#/pcie.h. Not all HW will have these (put NULL).\r
+ */\r
+ void *devParams; \r
} Pcie_DeviceCfgBaseAddr;\r
\r
/**\r
pcieRet_e (*cfgIbTrans) (Pcie_Handle handle, pcieIbTransCfg_t *ibCfg);\r
/*! Function to configure a BAR register */\r
pcieRet_e (*cfgBar) (Pcie_Handle handle, pcieBarCfg_t *barCfg);\r
+ /*! Function to configure an ATU region */\r
+ pcieRet_e (*cfgAtu) (Pcie_Handle handle, pcieLocation_e location, \r
+ uint32_t atuRegionIndex, \r
+ const pcieAtuRegionParams_t *atuRegionParams);\r
} Pcie_FxnTable;\r
\r
/**\r
* @ref Pcie_writeRegs to perform the actual 32bits register accesses, using\r
* @ref pcieType0Bar32bitIdx_t (for a End point BAR) or @ref pcieType1Bar32bitIdx_t (for a Root Complex BAR).\r
*\r
+ * In order to set a BAR MASK on rev 1 hw, must put it in \r
+ *\r
*\r
* @retval pcieRet_e status\r
*/\r
pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */\r
);\r
\r
+pcieRet_e Pcie_atuRegionConfig \r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieLocation_e location, /**< [in] local/remote */\r
+ uint32_t atuRegionIndex, /* [in] index number to configure */\r
+ const pcieAtuRegionParams_t *atuRegionParams /* [in] config structure */\r
+);\r
\r
/**\r
* @ingroup pcielld_api_functions\r
diff --git a/soc/am57x/src/pcie_soc.c b/soc/am57x/src/pcie_soc.c
--- /dev/null
+++ b/soc/am57x/src/pcie_soc.c
@@ -0,0 +1,177 @@
+/**
+ * @file am57x/src/pcie_soc.c
+ *
+ * @brief
+ * This file contains the device specific configuration and initialization routines
+ * for pcie Low Level Driver.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2015, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/**
+ * This file contains an example device configuration for the pcie LLD.
+ * It is not precompiled to facilitate user modification of the file.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* CSL RL includes */
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/cslr_bootcfg.h>
+
+#include <ti/csl/csl_bootcfg.h>
+
+/* pcie LLD includes */
+#include <ti/drv/pcie/soc/pcie_soc.h>
+#include <ti/drv/pcie/pcie.h>
+#include <ti/drv/pcie/src/v1/pcie.h>
+
+/** @addtogroup PCIE_LLD_DATASTRUCT
+@{
+*/
+
+/** @brief PCIE v1 calltable */
+Pcie_FxnTable fxnTablev1 =
+{
+ /*! Function to set PCIE to EP or RC for one device */
+ Pciev1_setInterfaceMode,
+ /*! Function to get the PCIE data area base address & size */
+ Pciev1_getMemSpaceRange,
+ /*! Function to read any PCIE register(s) */
+ Pciev1_readRegs,
+ /*! Function to write any PCIE register(s) */
+ Pciev1_writeRegs,
+ /*! Function to configure outbound translation registers */
+ NULL, /* not supported */
+ /*! Function to configure inbound translation registers */
+ NULL, /* not supported */
+ /*! Function to configure a BAR register */
+ Pciev1_cfgBar,
+ /*! Function to configure an ATU region */
+ Pciev1_atuRegionConfig
+};
+
+#ifdef _TMS320C6X
+Pciev1_DeviceCfgBaseAddrs cfgBaseAddrsDev1 =
+{
+ (void *)CSL_DSP_PCIE_SS1_CONF_REGS_I_RC_CFG_DBICS_REGS,
+ (void *)CSL_DSP_PCIE_SS1_CONF_REGS_I_RC_CFG_DBICS2_REGS,
+ (void *)CSL_DSP_PCIE_SS1_CONF_REGS_I_TI_CONF_REGS,
+ (void *)CSL_DSP_PCIE_SS1_CONF_REGS_I_PL_CONF_REGS,
+ (uint32_t)0x1000
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev1 =
+{
+ &cfgBaseAddrsDev1,
+ (void *)CSL_DSP_PCIE_SS1_REGS,
+ NULL
+};
+
+Pciev1_DeviceCfgBaseAddrs cfgBaseAddrsDev2 =
+{
+ (void *)CSL_DSP_PCIE_SS2_CONF_REGS_I_RC_CFG_DBICS_REGS,
+ (void *)CSL_DSP_PCIE_SS2_CONF_REGS_I_RC_CFG_DBICS2_REGS,
+ (void *)CSL_DSP_PCIE_SS2_CONF_REGS_I_TI_CONF_REGS,
+ (void *)CSL_DSP_PCIE_SS2_CONF_REGS_I_PL_CONF_REGS,
+ (uint32_t)0x1000
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev2 =
+{
+ &cfgBaseAddrsDev2,
+ (void *)CSL_DSP_PCIE_SS2_REGS,
+ NULL
+};
+
+#else /* A15 */
+
+Pciev1_DeviceCfgBaseAddrs cfgBaseAddrsDev1 =
+{
+ (void *)CSL_MPU_PCIE_SS1_CONF_REGS_I_RC_CFG_DBICS_REGS,
+ (void *)CSL_MPU_PCIE_SS1_CONF_REGS_I_RC_CFG_DBICS2_REGS,
+ (void *)CSL_MPU_PCIE_SS1_CONF_REGS_I_TI_CONF_REGS,
+ (void *)CSL_MPU_PCIE_SS1_CONF_REGS_I_PL_CONF_REGS,
+ (uint32_t)0x1000
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev1 =
+{
+ &cfgBaseAddrsDev1,
+ (void *)CSL_MPU_PCIE_SS1_REGS,
+ NULL
+};
+
+Pciev1_DeviceCfgBaseAddrs cfgBaseAddrsDev2 =
+{
+ (void *)CSL_MPU_PCIE_SS2_CONF_REGS_I_RC_CFG_DBICS_REGS,
+ (void *)CSL_MPU_PCIE_SS2_CONF_REGS_I_RC_CFG_DBICS2_REGS,
+ (void *)CSL_MPU_PCIE_SS2_CONF_REGS_I_TI_CONF_REGS,
+ (void *)CSL_MPU_PCIE_SS2_CONF_REGS_I_PL_CONF_REGS,
+ (uint32_t)0x1000
+};
+
+Pcie_DeviceCfgBaseAddr baseAddrDev1 =
+{
+ &cfgBaseAddrsDev2,
+ (void *)CSL_MPU_PCIE_SS2_REGS,
+ NULL
+};
+#endif
+
+/** @brief PCIE LLD initialization parameters */
+const Pcie_InitCfg pcieInitCfg =
+{
+ {
+ {
+ &baseAddrDev1,
+ &baseAddrDev2,
+ NULL,
+ NULL
+ },
+ {
+ &fxnTablev1,
+ &fxnTablev1,
+ NULL,
+ NULL
+ }
+ }
+};
+
+/**
+@}
+*/
+
diff --git a/soc/k2e/src/pcie_soc.c b/soc/k2e/src/pcie_soc.c
index 11c54ea1ef82113d96a60fff8632cb87fbad8e9a..c31e7a185c2f3bc27e77cbf95b31e536c6a51069 100644 (file)
--- a/soc/k2e/src/pcie_soc.c
+++ b/soc/k2e/src/pcie_soc.c
/*! Function to configure inbound translation registers */
Pciev0_cfgIbTrans,
/*! Function to configure a BAR register */
- Pciev0_cfgBar
+ Pciev0_cfgBar,
+ /*! Function to configure an ATU region */
+ NULL /* unsupported on rev 0 */
+};
+
+Pciev0_DevParams modeSelDev0 =
+{
+ (volatile uint32_t *)&hBootCfg->DEVCFG,
+ CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_MASK,
+ CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_SHIFT
};
Pcie_DeviceCfgBaseAddr baseAddrDev0 =
{
(void *)CSL_PCIE_0_SLV_CFG_REGS,
(void *)CSL_PCIE_0_SLV_DATA,
+ (void *)&modeSelDev0
+};
+
+Pciev0_DevParams modeSelDev1 =
+{
(volatile uint32_t *)&hBootCfg->DEVCFG,
- CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_MASK,
- CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_SHIFT
+ CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_MASK,
+ CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_SHIFT
};
Pcie_DeviceCfgBaseAddr baseAddrDev1 =
{
(void *)CSL_PCIE_1_SLV_CFG_REGS,
(void *)CSL_PCIE_1_SLV_DATA,
- (volatile uint32_t *)&hBootCfg->DEVCFG,
- CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_MASK,
- CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_SHIFT
+ (void *)&modeSelDev1
};
/** @brief PCIE LLD initialization parameters */
diff --git a/soc/k2h/src/pcie_soc.c b/soc/k2h/src/pcie_soc.c
index c5ddfce552cc0b403e4867b364abdabc2e85a703..2e97d7e61e0fb0435e188e51a16c3d888601ab14 100644 (file)
--- a/soc/k2h/src/pcie_soc.c
+++ b/soc/k2h/src/pcie_soc.c
/*! Function to configure inbound translation registers */
Pciev0_cfgIbTrans,
/*! Function to configure a BAR register */
- Pciev0_cfgBar
+ Pciev0_cfgBar,
+ /*! Function to configure an ATU region */
+ NULL /* unsupported on rev 0 */
};
-Pcie_DeviceCfgBaseAddr baseAddrDev0 =
+Pciev0_DevParams modeSel =
{
- (void *)CSL_PCIE_SLV_CFG_REGS,
- (void *)CSL_PCIE_SLV_DATA,
(volatile uint32_t *)&hBootCfg->DEVCFG,
CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK,
CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT
};
+Pcie_DeviceCfgBaseAddr baseAddrDev0 =
+{
+ (void *)CSL_PCIE_SLV_CFG_REGS,
+ (void *)CSL_PCIE_SLV_DATA,
+ (void *)&modeSel
+};
+
/** @brief PCIE LLD initialization parameters */
const Pcie_InitCfg pcieInitCfg =
{
diff --git a/soc/k2k/src/pcie_soc.c b/soc/k2k/src/pcie_soc.c
index 6a1efa5aa6c134f9b2f6a9ce96f365888aa72272..4ad106ba759126e670cefabbeb2b6d4a316ea8ef 100644 (file)
--- a/soc/k2k/src/pcie_soc.c
+++ b/soc/k2k/src/pcie_soc.c
/*! Function to configure inbound translation registers */
Pciev0_cfgIbTrans,
/*! Function to configure a BAR register */
- Pciev0_cfgBar
+ Pciev0_cfgBar,
+ /*! Function to configure an ATU region */
+ NULL /* unsupported on rev 0 */
};
-Pcie_DeviceCfgBaseAddr baseAddrDev0 =
+Pciev0_DevParams modeSel =
{
- (void *)CSL_PCIE_SLV_CFG_REGS,
- (void *)CSL_PCIE_SLV_DATA,
(volatile uint32_t *)&hBootCfg->DEVCFG,
CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK,
CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT
};
+Pcie_DeviceCfgBaseAddr baseAddrDev0 =
+{
+ (void *)CSL_PCIE_SLV_CFG_REGS,
+ (void *)CSL_PCIE_SLV_DATA,
+ (void *)&modeSel
+};
+
/** @brief PCIE LLD initialization parameters */
const Pcie_InitCfg pcieInitCfg =
{
diff --git a/soc/k2l/src/pcie_soc.c b/soc/k2l/src/pcie_soc.c
index 3f42191c0f16aa40d59aa90d4705fd4542835f7c..364341498139f87a41f9b9c514a0d051d94f9b34 100644 (file)
--- a/soc/k2l/src/pcie_soc.c
+++ b/soc/k2l/src/pcie_soc.c
/*! Function to configure inbound translation registers */
Pciev0_cfgIbTrans,
/*! Function to configure a BAR register */
- Pciev0_cfgBar
+ Pciev0_cfgBar,
+ /*! Function to configure an ATU region */
+ NULL /* unsupported on rev 0 */
+};
+
+Pciev0_DevParams modeSelDev0 =
+{
+ (volatile uint32_t *)&hBootCfg->DEVCFG,
+ CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_MASK,
+ CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_SHIFT
};
Pcie_DeviceCfgBaseAddr baseAddrDev0 =
{
(void *)CSL_PCIE_0_SLV_CFG_REGS,
(void *)CSL_PCIE_0_SLV_DATA,
+ (void *)&modeSelDev0
+};
+
+Pciev0_DevParams modeSelDev1 =
+{
(volatile uint32_t *)&hBootCfg->DEVCFG,
- CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_MASK,
- CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_SHIFT
+ CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_MASK,
+ CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_SHIFT
};
Pcie_DeviceCfgBaseAddr baseAddrDev1 =
{
(void *)CSL_PCIE_1_SLV_CFG_REGS,
(void *)CSL_PCIE_1_SLV_DATA,
- (volatile uint32_t *)&hBootCfg->DEVCFG,
- CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_MASK,
- CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_SHIFT
+ (void *)&modeSelDev1
};
/** @brief PCIE LLD initialization parameters */
diff --git a/src/pcie.c b/src/pcie.c
index 51f04782535231c2eb30c7ae10be94f88d8ae904..5f3e5955084b882294e7a1b0f4a3be3d4f086675 100644 (file)
--- a/src/pcie.c
+++ b/src/pcie.c
} /* Pcie_cfgBar */\r
\r
\r
+/*********************************************************************\r
+ * FUNCTION PURPOSE: Configures the ATU (address translation) unit\r
+ ********************************************************************/\r
+pcieRet_e Pcie_atuRegionConfig \r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieLocation_e location, /**< [in] local/remote */\r
+ uint32_t atuRegionIndex, /* [in] index number to configure */\r
+ const pcieAtuRegionParams_t *atuRegionParams /* [in] config structure */\r
+)\r
+{\r
+ Pcie_IntHandle h = (Pcie_IntHandle)handle;\r
+\r
+ if (! h)\r
+ {\r
+ return pcie_RET_INV_HANDLE;\r
+ }\r
+\r
+ if (! h->fxnTable.cfgAtu)\r
+ {\r
+ return pcie_RET_INV_FXNPTR;\r
+ }\r
+\r
+ return h->fxnTable.cfgAtu (handle, location, atuRegionIndex, atuRegionParams);\r
+} /* Pcie_atuRegionConfig */\r
+\r
+\r
/*********************************************************************\r
* FUNCTION PURPOSE: Returns version number\r
********************************************************************/\r
diff --git a/src/v0/pcie.h b/src/v0/pcie.h
index b0c9d6fc4c2b56d2dd9b9427df3481628712ac97..753759babd474b8a48ab22a3fe6ce610b572e67d 100644 (file)
--- a/src/v0/pcie.h
+++ b/src/v0/pcie.h
*\r
*/\r
\r
+/** revision dependant config (in soc/device.c) */\r
+typedef struct\r
+{\r
+ volatile uint32_t *pcieSSModeAddr; /**< address of PCIESSMODE register */\r
+ uint32_t pcieSSModeMask; /**< mask for PCIESSMODE field in @ref pcieSSModeAddr */\r
+ uint32_t pcieSSModeShift; /**< shift for PCIESSMODE field in @ref pcieSSModeAddr */\r
+} Pciev0_DevParams;\r
+\r
+/** \r
+ * v0 does not have multiple config addresses, it has one common base, hence\r
+ * no pciev0CfgBases.\r
+ */\r
+\r
/** v0 version of @ref Pcie_open */\r
pcieRet_e Pciev0_open \r
(\r
diff --git a/src/v0/pciev0.c b/src/v0/pciev0.c
index 6bbe23878dd27d7e4a8d16e6122555a4b81612b2..d1b1ef082396a3e765b4917aca43cb72fffeab29 100644 (file)
--- a/src/v0/pciev0.c
+++ b/src/v0/pciev0.c
* Set the mode of one interface without depending directly on device \r
* dependant registers (via device.c)\r
****************************************************************************/\r
-static void pcie_set_mode (Pcie_DeviceCfgBaseAddr *iface, pcieMode_e mode)\r
+static void pcie_set_mode (Pciev0_DevParams *iface, pcieMode_e mode)\r
{\r
uint32_t modeReg;\r
uint32_t newMode = (uint32_t)mode;\r
Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);\r
\r
if (bases) {\r
- pcie_set_mode (bases, mode);\r
+ pcie_set_mode ((Pciev0_DevParams *)bases->devParams, mode);\r
return pcie_RET_OK;\r
}\r
\r
pcie_check_result(retVal, pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg),\r
readRegs->type0Bar32bitIdx->idx));\r
}\r
+ if (readRegs->type0BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev0_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0BarMask32bitIdx->reg),\r
+ readRegs->type0BarMask32bitIdx->idx));\r
+ }\r
if (readRegs->subId) {\r
pcie_check_result(retVal, pciev0_read_subId_reg (baseCfgEpRegs, readRegs->subId));\r
}\r
pcie_check_result(retVal, pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg),\r
readRegs->type1Bar32bitIdx->idx));\r
}\r
+ if (readRegs->type1BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev0_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1BarMask32bitIdx->reg),\r
+ readRegs->type1BarMask32bitIdx->idx));\r
+ }\r
if (readRegs->type1BusNum) {\r
pcie_check_result(retVal, pciev0_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum));\r
}\r
pcie_check_result(retVal, pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg),\r
writeRegs->type0Bar32bitIdx->idx));\r
}\r
+ if (writeRegs->type0BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev0_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0BarMask32bitIdx->reg),\r
+ writeRegs->type0BarMask32bitIdx->idx));\r
+ }\r
if (writeRegs->subId) {\r
pcie_check_result(retVal, pciev0_write_subId_reg (baseCfgEpRegs, writeRegs->subId));\r
}\r
pcie_check_result(retVal, pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg),\r
writeRegs->type1Bar32bitIdx->idx));\r
}\r
+ if (writeRegs->type1BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev0_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1BarMask32bitIdx->reg),\r
+ writeRegs->type1BarMask32bitIdx->idx));\r
+ }\r
if (writeRegs->type1BusNum) {\r
pcie_check_result(retVal, pciev0_write_type1BusNum_reg (baseCfgRcRegs, writeRegs->type1BusNum));\r
}\r
return retVal;\r
} /* Pciev0_cfgBar */\r
\r
+\r
+/*********************************************************************\r
+ * FUNCTION PURPOSE: Configures an ATU (address translation) region\r
+ ********************************************************************/\r
+/* Not supported on rev 0 hw */\r
+\r
/* Nothing past this point */\r
\r
diff --git a/src/v1/foo.txt b/src/v1/foo.txt
--- a/src/v1/foo.txt
+++ /dev/null
@@ -1,108 +0,0 @@
- swReg->yMinor);
- swReg->custom);
- swReg->xMajor);
- swReg->rRtl);
- swReg->func);
- swReg->scheme);
- swReg->bu);
- swReg->idlemode);
- swReg->standbymode);
- swReg->mcoherentEn);
- swReg->lineNumber);
- swReg->errSys);
- swReg->errFatal);
- swReg->errNonfatal);
- swReg->errCor);
- swReg->errAxi);
- swReg->errEcrc);
- swReg->pmeTurnOff);
- swReg->pmeToAck);
- swReg->pmPme);
- swReg->linkReqRst);
- swReg->linkUpEvt);
- swReg->cfgBmeEvt);
- swReg->cfgMseEvt);
- swReg->errSys);
- swReg->errFatal);
- swReg->errNonfatal);
- swReg->errCor);
- swReg->errAxi);
- swReg->errEcrc);
- swReg->pmeTurnOff);
- swReg->pmeToAck);
- swReg->pmPme);
- swReg->linkReqRst);
- swReg->linkUpEvt);
- swReg->cfgBmeEvt);
- swReg->cfgMseEvt);
- swReg->errSysEn);
- swReg->errFatalEn);
- swReg->errNonfatalEn);
- swReg->errCorEn);
- swReg->errAxiEn);
- swReg->errEcrcEn);
- swReg->pmeTurnOffEn);
- swReg->pmeToAckEn);
- swReg->pmPmeEn);
- swReg->linkReqRstEn);
- swReg->linkUpEvtEn);
- swReg->cfgBmeEvtEn);
- swReg->cfgMseEvtEn);
- swReg->errSysEn);
- swReg->errFatalEn);
- swReg->errNonfatalEn);
- swReg->errCorEn);
- swReg->errAxiEn);
- swReg->errEcrcEn);
- swReg->pmeTurnOffEn);
- swReg->pmeToAckEn);
- swReg->pmPmeEn);
- swReg->linkReqRstEn);
- swReg->linkUpEvtEn);
- swReg->cfgBmeEvtEn);
- swReg->cfgMseEvtEn);
- swReg->inta);
- swReg->intb);
- swReg->intc);
- swReg->intd);
- swReg->msi);
- swReg->inta);
- swReg->intb);
- swReg->intc);
- swReg->intd);
- swReg->msi);
- swReg->intaEn);
- swReg->intbEn);
- swReg->intcEn);
- swReg->intdEn);
- swReg->msiEn);
- swReg->intaEn);
- swReg->intbEn);
- swReg->intcEn);
- swReg->intdEn);
- swReg->msiEn);
- swReg->type);
- swReg->ltssmState);
- swReg->ltssmEn);
- swReg->appReqRetryEn);
- swReg->devNum);
- swReg->busNum);
- swReg->pmeTurnOff);
- swReg->pmPme);
- swReg->l23Ready);
- swReg->reqEntrL1);
- swReg->reqExitL1);
- swReg->auxPwrDet);
- swReg->linkUp);
- swReg->reverseLanes);
- swReg->assertF0);
- swReg->deassertF0);
- swReg->msiReqGrant);
- swReg->msiFuncNum);
- swReg->msiVector);
- swReg->msiTc);
- swReg->sel);
- swReg->debug);
- swReg->invLcrc);
- swReg->invEcrc);
- swReg->fastLinkMode);
diff --git a/src/v1/pcie.h b/src/v1/pcie.h
--- /dev/null
+++ b/src/v1/pcie.h
@@ -0,0 +1,141 @@
+/*\r
+ *\r
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#ifndef _PCIEV0_H\r
+#define _PCIEV0_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* System level header files */\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+/* ============================================================== */\r
+/**\r
+ * @file ti/drv/pcie/src/v1/pcie.h\r
+ *\r
+ * @brief PCIe hw rev 0 sub-system API and Data Definitions\r
+ *\r
+ */\r
+\r
+/** \r
+ * v1 does not have revision dependant config, hence no pciev1DevParams\r
+ * no pciev0CfgBases.\r
+ */\r
+\r
+/**\r
+ * v1 has multiple config base addresses\r
+ */\r
+typedef struct\r
+{\r
+ void *rcDbics; /** @brief base address of RC/EP DBICS */\r
+ void *rcDbics2; /** @brief base address of RC/EP DBICS2 */\r
+ void *tiConf; /** @brief base address of TI_CONF area */\r
+ void *plConf; /** @brief base address of PL_CONF (port logic) area */\r
+ uint32_t remoteOffset; /** @brief offset relative to data area for remote config */\r
+} Pciev1_DeviceCfgBaseAddrs;\r
+\r
+\r
+/** v1 version of @ref Pcie_open */\r
+pcieRet_e Pciev1_open\r
+(\r
+ int deviceNum, /**< [in] PCIe device number (0,1,...) */\r
+ Pcie_Handle *pHandle /**< [out] Resulting instance handle */\r
+);\r
+\r
+/** v1 version of @ref Pcie_close */\r
+pcieRet_e Pciev1_close\r
+(\r
+ Pcie_Handle *pHandle /**< [in] The PCIE LLD instance indentifier */\r
+);\r
+\r
+/** v1 version of @ref Pcie_readRegs */\r
+pcieRet_e Pciev1_readRegs\r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieLocation_e location, /**< [in] Local or remote peripheral */\r
+ pcieRegisters_t *readRegs /**< [in/out] List of registers to read */\r
+);\r
+\r
+/** v1 version of @ref Pcie_writeRegs */\r
+pcieRet_e Pciev1_writeRegs\r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieLocation_e location, /**< [in] Local or remote peripheral */\r
+ pcieRegisters_t *writeRegs /**< [in] List of registers to write */\r
+);\r
+\r
+/** v1 version of @ref Pcie_setInterfaceMode */\r
+pcieRet_e Pciev1_setInterfaceMode\r
+(\r
+ Pcie_Handle handle, /**< [in] specified interface */\r
+ pcieMode_e mode /**< [in] PCIE Mode */\r
+);\r
+\r
+/** v1 version of @ref Pcie_getMemSpaceRange */\r
+pcieRet_e Pciev1_getMemSpaceRange\r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ void **base, /**< [out] The memory space base address */\r
+ uint32_t *size /**< [out] Total size of the memory space [bytes] */\r
+);\r
+\r
+/** v1 version of @ref Pcie_cfgBar */\r
+pcieRet_e Pciev1_cfgBar\r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */\r
+);\r
+\r
+/** v1 version of @ref Pcie_atuRegionConfig */\r
+pcieRet_e Pciev1_atuRegionConfig \r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieLocation_e location, /**< [in] local/remote */\r
+ uint32_t atuRegionIndex, /* [in] index number to configure */\r
+ const pcieAtuRegionParams_t *atuRegionParams /* [in] config structure */\r
+);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _PCIEV0_H */\r
+\r
+/* Nothing past this point */\r
+\r
diff --git a/src/v1/pciecfg.c b/src/v1/pciecfg.c
--- a/src/v1/pciecfg.c
+++ /dev/null
@@ -1,2889 +0,0 @@
-/*\r
- *\r
- * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ \r
- * \r
- * \r
- * Redistribution and use in source and binary forms, with or without \r
- * modification, are permitted provided that the following conditions \r
- * are met:\r
- *\r
- * Redistributions of source code must retain the above copyright \r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the \r
- * documentation and/or other materials provided with the \r
- * distribution.\r
- *\r
- * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-/*\r
- * File Name: pciecfg.c\r
- *\r
- * Processing/configuration functions for the PCIe Configuration Registers\r
- *\r
- */\r
-\r
-#include "pcie.h"\r
-#include "pcieloc.h"\r
-#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>\r
-#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>\r
-#include <ti/csl/cslr_pciess_app.h>\r
-\r
-\r
-/*****************************************************************************\r
- ********** PCIe CONFIG REGISTERS COMMON TO TYPE0 AND TYPE1 *****************\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * These APIs are using the endpoint (Type 0) structure and #defines, but they\r
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.\r
- * Both types have the same register layout, in the same location.\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * Read and split up the Vendor and Device Identification register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_vndDevId_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieVndDevIdReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->VENDOR_DEVICE_ID;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_VENDOR_DEVICE_ID_VENDOR_ID, reg->vndId);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_VENDOR_DEVICE_ID_DEVICE_ID, reg->devId);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_vndDevId_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Vendor and Device Identification register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_vndDevId_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieVndDevIdReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_VENDOR_DEVICE_ID_VENDOR_ID, reg->vndId);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_VENDOR_DEVICE_ID_DEVICE_ID, reg->devId);\r
-\r
- baseAddr->VENDOR_DEVICE_ID = reg->raw = new_val;;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_vndDevId_reg */\r
-\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Status and Command register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_statusCmd_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieStatusCmdReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->STATUS_COMMAND;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_PARITY_ERROR, reg->parity);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR, reg->sysError);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_RECEIVED_MASTER_ABORT, reg->mstAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_RECEIVED_TARGET_ABORT, reg->tgtAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_SIGNALED_TARGET_ABORT, reg->sigTgtAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_DATA_PARITY_ERROR, reg->parError);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_CAPABILITIES_LIST, reg->capList);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_INTERRUPT_STATUS, reg->stat);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_INTX_DISABLE, reg->dis);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_SERR_ENABLE, reg->serrEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_PARITY_ERROR_RESPONSE, reg->resp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_BUS_MASTER, reg->busMs);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_MEMORY_SPACE, reg->memSp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_IO_SPACE, reg->ioSp);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_statusCmd_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Status and Command register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_statusCmd_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieStatusCmdReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_PARITY_ERROR, reg->parity);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR, reg->sysError);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_RECEIVED_MASTER_ABORT, reg->mstAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_RECEIVED_TARGET_ABORT, reg->tgtAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_SIGNALED_TARGET_ABORT, reg->sigTgtAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_DATA_PARITY_ERROR, reg->parError);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_CAPABILITIES_LIST, reg->capList);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_INTERRUPT_STATUS, reg->stat);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_INTX_DISABLE, reg->dis);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_SERR_ENABLE, reg->serrEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_PARITY_ERROR_RESPONSE, reg->resp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_BUS_MASTER, reg->busMs);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_MEMORY_SPACE, reg->memSp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_STATUS_COMMAND_IO_SPACE, reg->ioSp);\r
-\r
- baseAddr->STATUS_COMMAND = reg->raw = new_val;;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_statusCmd_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Class Code and Revision ID register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_revId_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieRevIdReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->CLASSCODE_REVID;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CLASSCODE_REVID_CLASS_CODE, reg->classCode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CLASSCODE_REVID_REVISION_ID, reg->revId);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_revId_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Class Code and Revision ID register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_revId_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieRevIdReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_CLASSCODE_REVID_CLASS_CODE, reg->classCode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_CLASSCODE_REVID_REVISION_ID, reg->revId);\r
-\r
- baseAddr->CLASSCODE_REVID = reg->raw = new_val;;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_revId_reg */\r
-\r
-\r
-/*****************************************************************************\r
- ********** PCIe LOCAL/REMOTE CONFIG TYPE 0 REGISTERS *****************\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * Read and split up the BIST and Header register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_bist_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieBistReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->BIST_HEADER;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_BIST_CAPABLE, reg->bistCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_START_BIST, reg->startBist);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_COMPLETION_CODE, reg->compCode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_MULTI_FUNCTION_DEVICE, reg->mulfunDev);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_HEADER_TYPE, reg->hdrType);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_LATENCY_TIMER, reg->latTmr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_bist_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the BIST and Header register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_bist_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieBistReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_BIST_CAPABLE, reg->bistCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_START_BIST, reg->startBist);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_COMPLETION_CODE, reg->compCode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_MULTI_FUNCTION_DEVICE, reg->mulfunDev);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_HEADER_TYPE, reg->hdrType);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_LATENCY_TIMER, reg->latTmr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize);\r
-\r
- baseAddr->BIST_HEADER = reg->raw = new_val;;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_bist_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the BAR register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type0Bar_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieBarReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->BAR[barNum];\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, reg->base);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_PREFETCHABLE, reg->prefetch);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_TYPE, reg->type);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_MEMORY_SPACE, reg->memSpace);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type0Bar_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the BAR register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type0Bar_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieBarReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, reg->base);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_PREFETCHABLE, reg->prefetch);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_TYPE, reg->type);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_MEMORY_SPACE, reg->memSpace);\r
-\r
- baseAddr->BAR[barNum] = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type0Bar_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the BAR 32bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type0Bar32bit_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieBar32bitReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- reg->reg32 = reg->raw = baseAddr->BAR[barNum];\r
- return pcie_RET_OK;\r
-} /* pcie_read_type0Bar32bit_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the BAR 32bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type0Bar32bit_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieBar32bitReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- baseAddr->BAR[barNum] = reg->raw = reg->reg32;\r
- return pcie_RET_OK;\r
-} /* pcie_write_type0Bar32bit_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Subsystem and Subsystem Vendor ID register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_subId_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieSubIdReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->SUBSYS_VNDR_ID;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SUBSYS_VNDR_ID_SUBSYSTEM_ID, reg->subId);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SUBSYS_VNDR_ID_SUBSYSTEM_VENDOR_ID, reg->subVndId);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_subId_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Subsystem and Subsystem Vendor ID register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_subId_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieSubIdReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SUBSYS_VNDR_ID_SUBSYSTEM_ID, reg->subId);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SUBSYS_VNDR_ID_SUBSYSTEM_VENDOR_ID, reg->subVndId);\r
-\r
- baseAddr->SUBSYS_VNDR_ID = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_subId_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Expansion ROM Base Address register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_expRom_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieExpRomReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->EXPNSN_ROM;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_EXPNSN_ROM_EXPANSION_ROM_BASE_ADDRESS, reg->expRomAddr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->enable);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_expRom_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Expansion ROM Base Address register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_expRom_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieExpRomReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_EXPNSN_ROM_EXPANSION_ROM_BASE_ADDRESS, reg->expRomAddr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->enable);\r
-\r
- baseAddr->EXPNSN_ROM = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_expRom_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Capabilities Pointer register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_capPtr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieCapPtrReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->CAP_PTR;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_CAP_PTR_CAP_PTR, reg->ptr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_capPtr_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Capabilities Pointer register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_capPtr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieCapPtrReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_CAP_PTR_CAP_PTR, reg->ptr);\r
-\r
- baseAddr->CAP_PTR = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_capPtr_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Interrupt Pin register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_intPin_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieIntPinReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->INT_PIN;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_INT_PIN_INT_PIN, reg->intPin);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_INT_PIN_INT_LINE, reg->intLine);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_intPin_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Interrupt Pin register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_intPin_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieIntPinReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_INT_PIN_INT_PIN, reg->intPin);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_INT_PIN_INT_LINE, reg->intLine);\r
-\r
- baseAddr->INT_PIN = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_intPin_reg */\r
-\r
-\r
-\r
-/*****************************************************************************\r
- ********** PCIe LOCAL/REMOTE CONFIG TYPE 1 REGISTERS *****************\r
- ****************************************************************************/\r
-/*****************************************************************************\r
- * Read and split up the BIST, Header Type, Latency Time, and Cache Line Size register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1BistHeader_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1BistHeaderReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->BIST_HEADER;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_BISTCAPABLE, reg->bistCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_START_BIST, reg->startBist);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_COMPLETION_CODE, reg->compCode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_MULTI_FUNCTION_DEVICE, reg->mulFunDev);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_HEADER_TYPE, reg->hdrType);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_LATENCY_TIMER, reg->latTmr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1BistHeader_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the BIST, Header Type, Latency Time, and Cache Line Size register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1BistHeader_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1BistHeaderReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_BISTCAPABLE, reg->bistCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_START_BIST, reg->startBist);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_COMPLETION_CODE, reg->compCode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_MULTI_FUNCTION_DEVICE, reg->mulFunDev);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_HEADER_TYPE, reg->hdrType);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_LATENCY_TIMER, reg->latTmr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BIST_HEADER_CACHE_LINE_SIZE, reg->cacheLnSize);\r
-\r
- baseAddr->BIST_HEADER = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1BistHeader_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the BAR register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1Bar_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieBarReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->BAR[barNum];\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, reg->base);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_PREFETCHABLE, reg->prefetch);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_TYPE, reg->type);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_MEMORY_SPACE, reg->memSpace);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1Bar_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the BAR register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1Bar_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieBarReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, reg->base);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_PREFETCHABLE, reg->prefetch);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_TYPE, reg->type);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_MEMORY_SPACE, reg->memSpace);\r
-\r
- baseAddr->BAR[barNum] = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1Bar_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the BAR 32bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1Bar32bit_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieBar32bitReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- reg->reg32 = reg->raw = baseAddr->BAR[barNum];\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1Bar32bit_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the BAR 32bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1Bar32bit_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieBar32bitReg_t *reg,\r
- int barNum\r
-)\r
-{\r
- baseAddr->BAR[barNum] = reg->raw = reg->reg32;\r
- \r
- return pcie_RET_OK;\r
-} /* pcie_write_type1Bar32bit_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Latency Timer and Bus Number register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1BusNum_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1BusNumReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->BUSNUM;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_SECONDARY_LATENCY_TIMER, reg->secLatTmr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_SUBORDINATE_BUS_NUMBER, reg->subBusNum);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_SECONDARY_BUS_NUMBER, reg->secBusNum);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_PRIMARY_BUS_NUMBER, reg->priBusNum);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1BusNum_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Latency Timer and Bus Number register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1BusNum_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1BusNumReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_SECONDARY_LATENCY_TIMER, reg->secLatTmr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_SUBORDINATE_BUS_NUMBER, reg->subBusNum);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_SECONDARY_BUS_NUMBER, reg->secBusNum);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BUSNUM_PRIMARY_BUS_NUMBER, reg->priBusNum);\r
-\r
- baseAddr->BUSNUM = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1BusNum_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Secondary Status and IO Base/Limit Register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1SecStat_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1SecStatReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->SECSTAT;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_DTCT_PERROR, reg->dtctPError);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_RX_SYS_ERROR, reg->rxSysError);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_RX_MST_ABORT, reg->rxMstAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_RX_TGT_ABORT, reg->rxTgtAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_TX_TGT_ABORT, reg->txTgtAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_MST_DPERR, reg->mstDPErr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_LIMIT, reg->IOLimit);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_ADDRESSING, reg->IOLimitAddr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_BASE, reg->IOBase);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_ADDRESSING2, reg->IOBaseAddr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1SecStat_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Secondary Status and IO Base/Limit Register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1SecStat_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1SecStatReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_DTCT_PERROR, reg->dtctPError);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_RX_SYS_ERROR, reg->rxSysError);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_RX_MST_ABORT, reg->rxMstAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_RX_TGT_ABORT, reg->rxTgtAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_TX_TGT_ABORT, reg->txTgtAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_MST_DPERR, reg->mstDPErr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_LIMIT, reg->IOLimit);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_ADDRESSING, reg->IOLimitAddr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_BASE, reg->IOBase);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SECSTAT_IO_ADDRESSING2, reg->IOBaseAddr);\r
-\r
- baseAddr->SECSTAT = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1SecStat_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Memory Limit and Base register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1Memspace_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1MemspaceReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->MEMSPACE;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_MEMSPACE_MEMORY_LIMIT, reg->limit);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_MEMSPACE_MEMORY_BASE, reg->base);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1Memspace_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Memory Limit and Base register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1Memspace_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1MemspaceReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_MEMSPACE_MEMORY_LIMIT, reg->limit);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_MEMSPACE_MEMORY_BASE, reg->base);\r
-\r
- baseAddr->MEMSPACE = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1Memspace_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Prefetchable Memory Limit and Base register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_prefMem_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pciePrefMemReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PREFETCH_MEM;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_END_ADDRESS, reg->limit);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_MEMORY_ADDRESSING, reg->limitAddr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_STARTADDRESS, reg->base);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_MEMORY_ADDRESSING2, reg->baseAddr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_prefMem_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Prefetchable Memory Limit and Base register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_prefMem_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pciePrefMemReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_END_ADDRESS, reg->limit);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_MEMORY_ADDRESSING, reg->limitAddr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_STARTADDRESS, reg->base);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_MEM_MEMORY_ADDRESSING2, reg->baseAddr);\r
-\r
- baseAddr->PREFETCH_MEM = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_prefMem_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Prefetchable Memory Base Upper register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_prefBaseUpper_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pciePrefBaseUpperReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PREFETCH_BASE;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_BASE_BASE_ADDRESS, reg->base);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_prefBaseUp_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Prefetchable Memory Base Upper register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_prefBaseUpper_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pciePrefBaseUpperReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_BASE_BASE_ADDRESS, reg->base);\r
-\r
- baseAddr->PREFETCH_BASE = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_prefBaseUp_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Prefetchable Memory Limit Upper register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_prefLimitUpper_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pciePrefLimitUpperReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PREFETCH_LIMIT;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_LIMIT_LIMIT_ADDRESS, reg->limit);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_prefLimitUp_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Prefetchable Memory Limit Upper register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_prefLimitUpper_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pciePrefLimitUpperReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_PREFETCH_LIMIT_LIMIT_ADDRESS, reg->limit);\r
-\r
- baseAddr->PREFETCH_LIMIT = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_prefLimitUp_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the IO Base and Limit Upper 16 bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1IOSpace_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1IOSpaceReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->IOSPACE;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_IOSPACE_IOBASE, reg->IOBase);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_IOSPACE_IOLIMIT, reg->IOLimit);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1IOSpace_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the IO Base and Limit Upper 16 bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1IOSpace_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1IOSpaceReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_IOSPACE_IOBASE, reg->IOBase);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_IOSPACE_IOLIMIT, reg->IOLimit);\r
-\r
- baseAddr->IOSPACE = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1IOSpace_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Capabilities Pointer register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1CapPtr_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1CapPtrReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->CAP_PTR;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_CAP_PTR_CAP_PTR, reg->capPtr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1CapPtr_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Capabilities Pointer register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1CapPtr_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1CapPtrReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_CAP_PTR_CAP_PTR, reg->capPtr);\r
-\r
- baseAddr->CAP_PTR = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1CapPtr_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Expansion ROM Base Address register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1ExpnsnRom_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1ExpnsnRomReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->EXPNSN_ROM;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_EXPNSN_ROM_EXPANSION_ROM_BASE_ADDRESS, reg->expRomBaseAddr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->expRomEn);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1ExpnsnRom_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Expansion ROM Base Address register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1ExpnsnRom_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1ExpnsnRomReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_EXPNSN_ROM_EXPANSION_ROM_BASE_ADDRESS, reg->expRomBaseAddr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_EXPNSN_ROM_EXPANSION_ROM_ENABLE, reg->expRomEn);\r
-\r
- baseAddr->EXPNSN_ROM = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1ExpnsnRom_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Bridge Control and Interrupt register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_type1BridgeInt_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1BridgeIntReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->BRIDGE_INT;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SERREN_STATUS, reg->serrEnStatus);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_TIMER_STATUS, reg->timerStatus);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SEC_TIMER, reg->secTimer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_PRI_TIMER, reg->priTimer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_B2B_EN, reg->b2bEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SEC_BUS_RST, reg->secBusRst);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_MST_ABORT_MODE, reg->mstAbortMode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_VGA_DECODE, reg->vgaDecode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_VGA_EN, reg->vgaEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_ISA_EN, reg->isaEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SERR_EN, reg->serrEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_PERR_RESP_EN, reg->pErrRespEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_INT_PIN, reg->intPin);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_INT_LINE, reg->intLine);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_type1BridgeInt_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Bridge Control and Interrupt register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_type1BridgeInt_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieType1BridgeIntReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SERREN_STATUS, reg->serrEnStatus);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_TIMER_STATUS, reg->timerStatus);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SEC_TIMER, reg->secTimer);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_PRI_TIMER, reg->priTimer);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_B2B_EN, reg->b2bEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SEC_BUS_RST, reg->secBusRst);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_MST_ABORT_MODE, reg->mstAbortMode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_VGA_DECODE, reg->vgaDecode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_VGA_EN, reg->vgaEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_ISA_EN, reg->isaEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_SERR_EN, reg->serrEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_PERR_RESP_EN, reg->pErrRespEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_INT_PIN, reg->intPin);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BRIDGE_INT_INT_LINE, reg->intLine);\r
-\r
- baseAddr->BRIDGE_INT = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_type1BridgeInt_reg */\r
-\r
-/*****************************************************************************\r
- ********** Power Management Capability Registers ***************************\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * These APIs are using the endpoint (Type 0) structure and #defines, but they\r
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.\r
- * Both types have the same register layout, in the same location.\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * Read and split up the Power Management Capability register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_pmCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePMCapReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PMCAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PME_SUPP_N, reg->pmeSuppN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_D2_SUPP_N, reg->d2SuppN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_D1_SUPP_N, reg->d1SuppN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_AUX_CURR_N, reg->auxCurrN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_DSI_N, reg->dsiN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PME_CLK, reg->pmeClk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PME_SPEC_VER, reg->pmeSpecVer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PM_NEXT_PTR, reg->pmNextPtr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PM_CAP_ID, reg->pmCapID);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_pmCap_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Power Management Capability register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_pmCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePMCapReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PME_SUPP_N, reg->pmeSuppN);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_D2_SUPP_N, reg->d2SuppN);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_D1_SUPP_N, reg->d1SuppN);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_AUX_CURR_N, reg->auxCurrN);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_DSI_N, reg->dsiN);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PME_CLK, reg->pmeClk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PME_SPEC_VER, reg->pmeSpecVer);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PM_NEXT_PTR, reg->pmNextPtr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PMCAP_PM_CAP_ID, reg->pmCapID);\r
-\r
- baseAddr->PMCAP = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_pmCap_reg */\r
-\r
-/*****************************************************************************\r
- * Read and split up the Power Management Capabilties Control and Status register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_pmCapCtlStat_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePMCapCtlStatReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PM_CTL_STAT;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_DATA_REG, reg->dataReg);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_CLK_CTRL_EN, reg->clkCtrlEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_B2_B3_SUPPORT, reg->b2b3Support);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PME_STATUS, reg->pmeStatus);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_DATA_SCALE, reg->dataScale);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_DATA_SELECT, reg->dataSelect);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PME_EN, reg->pmeEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_NO_SOFT_RST, reg->noSoftRst);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PWR_STATE, reg->pwrState);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_pmCapCtlStat_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Power Management Capabilties Control and Status register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_pmCapCtlStat_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePMCapCtlStatReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_DATA_REG, reg->dataReg);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_CLK_CTRL_EN, reg->clkCtrlEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_B2_B3_SUPPORT, reg->b2b3Support);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PME_STATUS, reg->pmeStatus);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_DATA_SCALE, reg->dataScale);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_DATA_SELECT, reg->dataSelect);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PME_EN, reg->pmeEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_NO_SOFT_RST, reg->noSoftRst);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PM_CTL_STAT_PWR_STATE, reg->pwrState);\r
-\r
- baseAddr->PM_CTL_STAT = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_pmCapCtlStat_reg */\r
-\r
-/*****************************************************************************\r
- ********** Message Signaling Interrupt REGISTERS *************************\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * These APIs are using the endpoint (Type 0) structure and #defines, but they\r
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.\r
- * Both types have the same register layout, in the same location.\r
- ****************************************************************************/\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the MSI Capabilities register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_msiCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiCapReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->MSI_CAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_64BIT_EN, reg->en64bit);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_MULT_MSG_EN, reg->multMsgEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_MULT_MSG_CAP, reg->multMsgCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_MSI_EN, reg->msiEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_NEXT_CAP, reg->nextCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_CAP_ID, reg->capId);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_msiCap_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the MSI Capabilities register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_msiCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiCapReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_64BIT_EN, reg->en64bit);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_MULT_MSG_EN, reg->multMsgEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_MULT_MSG_CAP,reg->multMsgCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_MSI_EN, reg->msiEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_NEXT_CAP, reg->nextCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_CAP_CAP_ID, reg->capId);\r
-\r
- baseAddr->MSI_CAP = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_msiCap_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the MSI Lower 32 Bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_msiLo32_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiLo32Reg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->MSI_LOW32;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_LOW32_LOW32_ADDR, reg->addr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_msiLo32_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the MSI Lower 32 Bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_msiLo32_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiLo32Reg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_LOW32_LOW32_ADDR, reg->addr);\r
-\r
- baseAddr->MSI_LOW32 = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_msiLo32_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the MSI Upper 32 Bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_msiUp32_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiUp32Reg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->MSI_UP32;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_UP32_UP32_ADDR, reg->addr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_msiUp32_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the MSI Upper 32 Bits register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_msiUp32_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiUp32Reg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_UP32_UP32_ADDR, reg->addr);\r
-\r
- baseAddr->MSI_UP32 = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_msiUp32_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the MSI Data register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_msiData_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiDataReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->MSI_DATA;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_DATA_MSI_DATA, reg->data);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_msiData_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the MSI Data register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_msiData_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieMsiDataReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_MSI_DATA_MSI_DATA, reg->data);\r
-\r
- baseAddr->MSI_DATA = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_msiData_reg */\r
-\r
-\r
-/*****************************************************************************\r
- ********** PCIe CAPABILITIES REGISTERS **********************\r
- ****************************************************************************/\r
-\r
-\r
-/*****************************************************************************\r
- * These APIs are using the endpoint (Type 0) structure and #defines, but they\r
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.\r
- * Both types have the same register layout, in the same location.\r
- ****************************************************************************/\r
-\r
-/***************************************************************************** \r
- * Read and split up the PCIE Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_pciesCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePciesCapReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIES_CAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_INT_MSG, reg->intMsg);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_SLT_IMPL_N, reg->sltImplN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_DPORT_TYPE, reg->dportType);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_PCIE_CAP, reg->pcieCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_NEXT_CAP, reg->nextCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_CAP_ID, reg->capId);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_pciesCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the PCIE Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_pciesCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePciesCapReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_INT_MSG, reg->intMsg);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_SLT_IMPL_N, reg->sltImplN);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_DPORT_TYPE, reg->dportType);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_PCIE_CAP, reg->pcieCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_NEXT_CAP, reg->nextCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIES_CAP_CAP_ID, reg->capId);\r
-\r
- baseAddr->PCIES_CAP = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_pciesCap_reg*/\r
-\r
-/***************************************************************************** \r
- * Read and split up the Device Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_deviceCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDeviceCapReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->DEVICE_CAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_PWR_LIMIT_SCALE, reg->pwrLimitScale);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_PWR_LIMIT_VALUE, reg->pwrLimitValue);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_ERR_RPT, reg->errRpt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_L1_LATENCY, reg->l1Latency);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_L0_LATENCY, reg->l0Latency);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_EXT_TAG_FLD, reg->extTagFld);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_PHANTOM_FLD, reg->phantomFld);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_MAX_PAYLD_SZ, reg->maxPayldSz);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_deviceCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Device Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_deviceCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDeviceCapReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_PWR_LIMIT_SCALE, reg->pwrLimitScale);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_PWR_LIMIT_VALUE, reg->pwrLimitValue);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_ERR_RPT, reg->errRpt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_L1_LATENCY, reg->l1Latency);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_L0_LATENCY, reg->l0Latency);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_EXT_TAG_FLD, reg->extTagFld);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_PHANTOM_FLD, reg->phantomFld);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEVICE_CAP_MAX_PAYLD_SZ, reg->maxPayldSz);\r
-\r
- baseAddr->DEVICE_CAP = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_deviceCap_reg*/\r
-\r
-/*****************************************************************************\r
- * Read and split up the Device Status and Control register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_devStatCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDevStatCtrlReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->DEV_STAT_CTRL;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_TPEND, reg->tpend);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_AUX_PWR, reg->auxPwr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_UNSUP_RQ_DET, reg->rqDet);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_FATAL_ERR, reg->fatalEr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_NFATAL_ERR, reg->nFatalEr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_CORR_ERR, reg->corrEr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_MAX_REQ_SZ, reg->maxSz);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_NO_SNOOP, reg->noSnoop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_AUX_PWR_PM_EN, reg->auxPwrEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_PHANTOM_EN, reg->phantomEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_XTAG_FIELD_EN, reg->xtagEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_MAX_PAYLOAD, reg->maxPayld);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_RELAXED, reg->relaxed);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_UNSUP_REQ_REP, reg->reqRp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_FATAL_ERR_REP, reg->fatalErRp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_NFATAL_ERR_REP, reg->nFatalErRp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_CORR_ERR_REP, reg->corErRp);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_devStatCtrl_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Combine and write the Device Status and Control register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_devStatCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDevStatCtrlReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_TPEND, reg->tpend);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_AUX_PWR, reg->auxPwr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_UNSUP_RQ_DET, reg->rqDet);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_FATAL_ERR, reg->fatalEr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_NFATAL_ERR, reg->nFatalEr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_CORR_ERR, reg->corrEr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_MAX_REQ_SZ, reg->maxSz);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_NO_SNOOP, reg->noSnoop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_AUX_PWR_PM_EN, reg->auxPwrEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_PHANTOM_EN, reg->phantomEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_XTAG_FIELD_EN, reg->xtagEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_MAX_PAYLOAD, reg->maxPayld);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_RELAXED, reg->relaxed);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_UNSUP_REQ_REP, reg->reqRp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_FATAL_ERR_REP, reg->fatalErRp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_NFATAL_ERR_REP, reg->nFatalErRp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL_CORR_ERR_REP, reg->corErRp);\r
-\r
- baseAddr->DEV_STAT_CTRL = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_devStatCtrl_reg */\r
-\r
-/***************************************************************************** \r
- * Read and split up the Link Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_linkCap_reg\r
-( \r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLinkCapReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->LINK_CAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_PORT_NUM, reg->portNum);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_BW_NOTIFY_CAP, reg->bwNotifyCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_DLL_REP_CAP, reg->dllRepCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_DOWN_ERR_REP_CAP, reg->downErrRepCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_CLK_PWR_MGMT, reg->clkPwrMgmt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_L1_EXIT_LAT, reg->l1ExitLat);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_LOS_EXIT_LAT, reg->losExitLat);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_AS_LINK_PM, reg->asLinkPm);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_MAX_LINK_WIDTH, reg->maxLinkWidth);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_MAX_LINK_SPEED, reg->maxLinkSpeed);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_linkCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Link Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_linkCap_reg\r
-( \r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLinkCapReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_PORT_NUM, reg->portNum);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_BW_NOTIFY_CAP, reg->bwNotifyCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_DLL_REP_CAP, reg->dllRepCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_DOWN_ERR_REP_CAP, reg->downErrRepCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_CLK_PWR_MGMT, reg->clkPwrMgmt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_L1_EXIT_LAT, reg->l1ExitLat);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_LOS_EXIT_LAT, reg->losExitLat);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_AS_LINK_PM, reg->asLinkPm);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_MAX_LINK_WIDTH, reg->maxLinkWidth);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CAP_MAX_LINK_SPEED, reg->maxLinkSpeed);\r
-\r
- baseAddr->LINK_CAP = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_linkCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Link Status and Control register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_linkStatCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLinkStatCtrlReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->LINK_STAT_CTRL;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_STATUS, reg->linkBwStatus);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_MGMT_STATUS, reg->linkBwMgmtStatus);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_DLL_ACTIVE, reg->dllActive);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_SLOT_CLK_CFG, reg->slotClkCfg);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_TRAINING, reg->linkTraining);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_UNDEF, reg->undef);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_NEGOTIATED_LINK_WD, reg->negotiatedLinkWd);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_SPEED, reg->linkSpeed);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_INT_EN, reg->linkBwIntEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_MGMT_INT_EN, reg->linkBwMgmtIntEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_HW_AUTO_WIDTH_DIS, reg->hwAutoWidthDis);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_CLK_PWR_MGMT_EN, reg->clkPwrMgmtEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_EXT_SYNC, reg->extSync);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_COMMON_CLK_CFG, reg->commonClkCfg);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_RETRAIN_LINK, reg->retrainLink);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_DISABLE, reg->linkDisable);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_RCB, reg->rcb);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_ACTIVE_LINK_PM, reg->activeLinkPm);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_linkStatCtrl_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Link Status and Control register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_linkStatCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLinkStatCtrlReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_STATUS, reg->linkBwStatus);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_MGMT_STATUS, reg->linkBwMgmtStatus);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_DLL_ACTIVE, reg->dllActive);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_SLOT_CLK_CFG, reg->slotClkCfg);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_TRAINING, reg->linkTraining);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_UNDEF, reg->undef);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_NEGOTIATED_LINK_WD, reg->negotiatedLinkWd);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_SPEED, reg->linkSpeed);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_INT_EN, reg->linkBwIntEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_BW_MGMT_INT_EN, reg->linkBwMgmtIntEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_HW_AUTO_WIDTH_DIS, reg->hwAutoWidthDis);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_CLK_PWR_MGMT_EN, reg->clkPwrMgmtEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_EXT_SYNC, reg->extSync);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_COMMON_CLK_CFG, reg->commonClkCfg);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_RETRAIN_LINK, reg->retrainLink);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_LINK_DISABLE, reg->linkDisable);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_RCB, reg->rcb);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_STAT_CTRL_ACTIVE_LINK_PM, reg->activeLinkPm);\r
-\r
- baseAddr->LINK_STAT_CTRL = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_linkStatCtrl_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Slot Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_slotCap_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieSlotCapReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->SLOT_CAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_SLOT_NUM, reg->slotNum);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_CMD_COMP_SUPP, reg->cmdCompSupp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_EML_PRESENT, reg->emlPresent);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_LMT_SCALE, reg->pwrLmtScale);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_LMT_VALUE, reg->pwrLmtValue);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_HP_CAP, reg->hpCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_HP_SURPRISE, reg->hpSurprise);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_IND, reg->pwrInd);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_ATTN_IND, reg->attnInd);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_MRL_SENSOR, reg->mrlSensor);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_CTL, reg->pwrCtl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_ATTN_BUTTON, reg->attnButton);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_slotCap_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Slot Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_slotCap_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieSlotCapReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_SLOT_NUM, reg->slotNum);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_CMD_COMP_SUPP, reg->cmdCompSupp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_EML_PRESENT, reg->emlPresent);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_LMT_SCALE, reg->pwrLmtScale);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_LMT_VALUE, reg->pwrLmtValue);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_HP_CAP, reg->hpCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_HP_SURPRISE, reg->hpSurprise);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_IND, reg->pwrInd);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_ATTN_IND, reg->attnInd);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_MRL_SENSOR, reg->mrlSensor);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_PWR_CTL, reg->pwrCtl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_CAP_ATTN_BUTTON, reg->attnButton);\r
-\r
- baseAddr->SLOT_CAP = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_slotCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Slot Status and Control register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_slotStatCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieSlotStatCtrlReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->SLOT_STAT_CTRL;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_DLL_STATE, reg->dllState);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_EM_LOCK, reg->emLock);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PRESENCE_DET, reg->presenceDet);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_MRL_STATE, reg->mrlState);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_CMD_COMLETE, reg->cmdComplete);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PRESENCE_CHG, reg->presenceChg);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_MRL_CHANGE, reg->mrlChange);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PWR_FAULT, reg->pwrFault);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_PRESSED, reg->attnPressed);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_DLL_CHG_EN, reg->dllChgEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_EM_LOCK_CTL, reg->emLockCtl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PM_CTL, reg->pmCtl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PM_IND_CTL, reg->pmIndCtl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_IND_CTL, reg->attnIndCtl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_HP_INT_EN, reg->hpIntEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_CMD_CMP_INT_EN, reg->cmdCmpIntEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PRS_DET_CHG_EN, reg->prsDetChgEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_MRL_CHG_EN, reg->mrlChgEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PWR_FLT_DET_EN, reg->pwrFltDetEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_BUTT_EN, reg->attnButtEn);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_slotStatCtrl_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Slot Status and Control register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_slotStatCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieSlotStatCtrlReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_DLL_STATE, reg->dllState);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_EM_LOCK, reg->emLock);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PRESENCE_DET, reg->presenceDet);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_MRL_STATE, reg->mrlState);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_CMD_COMLETE, reg->cmdComplete);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PRESENCE_CHG, reg->presenceChg);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_MRL_CHANGE, reg->mrlChange);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PWR_FAULT, reg->pwrFault);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_PRESSED, reg->attnPressed);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_DLL_CHG_EN, reg->dllChgEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_EM_LOCK_CTL, reg->emLockCtl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PM_CTL, reg->pmCtl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PM_IND_CTL, reg->pmIndCtl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_IND_CTL, reg->attnIndCtl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_HP_INT_EN, reg->hpIntEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_CMD_CMP_INT_EN, reg->cmdCmpIntEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PRS_DET_CHG_EN, reg->prsDetChgEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_MRL_CHG_EN, reg->mrlChgEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_PWR_FLT_DET_EN, reg->pwrFltDetEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_SLOT_STAT_CTRL_ATTN_BUTT_EN, reg->attnButtEn);\r
-\r
- baseAddr->SLOT_STAT_CTRL = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_slotStatCtrl_reg*/\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Root Control and Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_rootCtrlCap_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieRootCtrlCapReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->ROOT_CTRL_CAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_CRS_SW, reg->crsSw);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_CRS_SW_EN, reg->crsSwEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_PME_INT_EN, reg->pmeIntEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_FATAL_ERR, reg->serrFatalErr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_NFATAL_ERR, reg->serrNFatalErr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_EN, reg->serrEn);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_rootCtrlCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Root Control and Capabilities register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_rootCtrlCap_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieRootCtrlCapReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_CRS_SW, reg->crsSw);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_CRS_SW_EN, reg->crsSwEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_PME_INT_EN, reg->pmeIntEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_FATAL_ERR, reg->serrFatalErr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_NFATAL_ERR, reg->serrNFatalErr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_CTRL_CAP_SERR_EN, reg->serrEn);\r
-\r
- baseAddr->ROOT_CTRL_CAP = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_rootCtrlCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Root Status and Control register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_rootStatus_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieRootStatusReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->ROOT_STATUS;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_PEND, reg->pmePend);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_STATUS, reg->pmeStatus);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_REQ_ID, reg->pmeReqID);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_rootStatus_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Root Status and Control register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_rootStatus_reg\r
-(\r
- CSL_Pcie_cfg_space_rootcomplexRegs *baseAddr, \r
- pcieRootStatusReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_PEND, reg->pmePend);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_STATUS, reg->pmeStatus);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_ROOT_STATUS_PME_REQ_ID, reg->pmeReqID);\r
-\r
- baseAddr->ROOT_STATUS = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_rootStatus_reg*/\r
-\r
-/***************************************************************************** \r
- * Read and split up the Device Capabilities 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_devCap2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDevCap2Reg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->DEV_CAP2;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_CAP2_CMPL_TO_DIS_SUPP, reg->cmplToDisSupp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_CAP2_CMPL_TO_EN, reg->cmplToEn);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_devCap2_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Device Capabilities 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_devCap2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDevCap2Reg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_CAP2_CMPL_TO_DIS_SUPP, reg->cmplToDisSupp);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_CAP2_CMPL_TO_EN, reg->cmplToEn);\r
-\r
- baseAddr->DEV_CAP2 = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_devCap2_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Device Status and Control Register 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_devStatCtrl2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDevStatCtrl2Reg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->DEV_STAT_CTRL2;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL2_CMPL_TO_DIS, reg->cmplToDis);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL2_CMPL_TO, reg->cmplTo);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_devStatCtrl2_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Device Status and Control Register 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_devStatCtrl2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDevStatCtrl2Reg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL2_CMPL_TO_DIS, reg->cmplToDis);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEV_STAT_CTRL2_CMPL_TO, reg->cmplTo);\r
-\r
- baseAddr->DEV_STAT_CTRL2 = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_devStatCtrl2_reg*/\r
-\r
-/***************************************************************************** \r
- * Read and split up the Link Control 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_linkCtrl2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLinkCtrl2Reg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->LINK_CTRL2;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_DE_EMPH, reg->deEmph);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_POLL_DEEMPH, reg->pollDeemph);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_CMPL_SOS, reg->cmplSos);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_ENTR_MOD_COMPL, reg->entrModCompl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_TX_MARGIN, reg->txMargin);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_SEL_DEEMPH, reg->selDeemph);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_HW_AUTO_SPEED_DIS, reg->hwAutoSpeedDis);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_ENTR_COMPL, reg->entrCompl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_TGT_SPEED, reg->tgtSpeed);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_linkCtrl2_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Combine and write the Link Control 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_linkCtrl2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLinkCtrl2Reg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_DE_EMPH, reg->deEmph);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_POLL_DEEMPH, reg->pollDeemph);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_CMPL_SOS, reg->cmplSos);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_ENTR_MOD_COMPL, reg->entrModCompl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_TX_MARGIN, reg->txMargin);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_SEL_DEEMPH, reg->selDeemph);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_HW_AUTO_SPEED_DIS, reg->hwAutoSpeedDis);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_ENTR_COMPL, reg->entrCompl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LINK_CTRL2_TGT_SPEED, reg->tgtSpeed);\r
-\r
- baseAddr->LINK_CTRL2 = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_linkCtrl2_reg*/\r
-\r
-\r
-/*****************************************************************************\r
- ********** PCIe EXTENDED CAPABILITIES REGISTERS **********************\r
- ****************************************************************************/\r
-\r
-/*****************************************************************************\r
- * These APIs are using the endpoint (Type 0) structure and #defines, but they\r
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.\r
- * Both types have the same register layout, in the same location.\r
- ****************************************************************************/\r
-\r
-/***************************************************************************** \r
- * Read and split up the PCIE Extended Capabilities Header register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_extCap_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieExtCapReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_EXTCAP;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_EXTCAP_NEXT_CAP, reg->nextCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_EXTCAP_EXT_CAP_VER, reg->extCapVer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_EXTCAP_EXT_CAP_ID, reg->extCapID);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_extCap_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Uncorrectable Error Status register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_uncErr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieUncErrReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_UNCERR;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_UR_ERR_ST, reg->urErrSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_ECRC_ERR_ST, reg->ecrcErrSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MTLP_ERR_ST, reg->mtlpErrSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_RCVR_OF_ST, reg->rcvrOfSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_UCMP_ST, reg->ucmpSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_CMPL_ABRT_ST, reg->cmplAbrtSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_CMPL_TMOT_ST, reg->cmplTmotSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_FCP_ERR_ST, reg->fcpErrSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_PSND_TLP_ST, reg->psndTlpSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SRPS_DN_ST, reg->srpsDnSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_DLP_ERR_ST, reg->dlpErrSt);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_uncErr_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Uncorrectable Error Status register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_uncErr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieUncErrReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_UR_ERR_ST, reg->urErrSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_ECRC_ERR_ST, reg->ecrcErrSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MTLP_ERR_ST, reg->mtlpErrSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_RCVR_OF_ST, reg->rcvrOfSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_UCMP_ST, reg->ucmpSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_CMPL_ABRT_ST, reg->cmplAbrtSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_CMPL_TMOT_ST, reg->cmplTmotSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_FCP_ERR_ST, reg->fcpErrSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_PSND_TLP_ST, reg->psndTlpSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SRPS_DN_ST, reg->srpsDnSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_DLP_ERR_ST, reg->dlpErrSt);\r
-\r
- baseAddr->PCIE_UNCERR = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_uncErr_reg*/\r
-\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Uncorrectable Error Mask register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_uncErrMask_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieUncErrMaskReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_UNCERR_MASK;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_UR_ERR_MSK, reg->urErrMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_ECRC_ERR_MSK, reg->ecrcErrMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_MTLP_ERR_MSK, reg->mtlpErrMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_RCVR_OF_MSK, reg->rcvrOfMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_UCMP_MSK, reg->ucmpMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_CMPL_ABRT_MSK, reg->cmplAbrtMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_CMPL_TMOT_MSK, reg->cmplTmotMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_FCP_ERR_MSK, reg->fcpErrMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_PSND_TLP_MSK, reg->psndTlpMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_SRPS_DN_MSK, reg->srpsDnMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_DLP_ERR_MSK, reg->dlpErrMsk);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_uncErrMask_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Uncorrectable Error Mask register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_uncErrMask_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieUncErrMaskReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_UR_ERR_MSK, reg->urErrMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_ECRC_ERR_MSK, reg->ecrcErrMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_MTLP_ERR_MSK, reg->mtlpErrMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_RCVR_OF_MSK, reg->rcvrOfMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_UCMP_MSK, reg->ucmpMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_CMPL_ABRT_MSK, reg->cmplAbrtMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_CMPL_TMOT_MSK, reg->cmplTmotMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_FCP_ERR_MSK, reg->fcpErrMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_PSND_TLP_MSK, reg->psndTlpMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_SRPS_DN_MSK, reg->srpsDnMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_MASK_DLP_ERR_MSK, reg->dlpErrMsk);\r
-\r
- baseAddr->PCIE_UNCERR_MASK = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_uncErrMask_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Uncorrectable Error Severity register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_uncErrSvrty_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieUncErrSvrtyReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_UNCERR_SVRTY;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_UR_ERR_SVRTY, reg->urErrSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_ECRC_ERR_SVRTY, reg->ecrcErrSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_MTLP_ERR_SVRTY, reg->mtlpErrSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_RCVR_OF_SVRTY, reg->rcvrOfSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_UCMP_SVRTY, reg->ucmpSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_CMPL_ABRT_SVRTY, reg->cmplAbrtSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_CMPL_TMOT_SVRTY, reg->cmplTmotSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_FCP_ERR_SVRTY, reg->fcpErrSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_PSND_TLP_SVRTY, reg->psndTlpSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_SRPS_DN_SVRTY, reg->srpsDnSvrty);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_DLP_ERR_SVRTY, reg->dlpErrSvrty);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_uncErrSvrty_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Uncorrectable Error Severity register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_uncErrSvrty_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieUncErrSvrtyReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_UR_ERR_SVRTY, reg->urErrSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_ECRC_ERR_SVRTY, reg->ecrcErrSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_MTLP_ERR_SVRTY, reg->mtlpErrSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_RCVR_OF_SVRTY, reg->rcvrOfSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_UCMP_SVRTY, reg->ucmpSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_CMPL_ABRT_SVRTY, reg->cmplAbrtSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_CMPL_TMOT_SVRTY, reg->cmplTmotSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_FCP_ERR_SVRTY, reg->fcpErrSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_PSND_TLP_SVRTY, reg->psndTlpSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_SRPS_DN_SVRTY, reg->srpsDnSvrty);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_UNCERR_SVRTY_DLP_ERR_SVRTY, reg->dlpErrSvrty);\r
-\r
- baseAddr->PCIE_UNCERR_SVRTY = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_uncErrSvrty_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Correctable Error Status register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_corErr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieCorErrReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_CERR;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_ADV_NFERR_ST, reg->advNFErrSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RPLY_TMR_ST, reg->rplyTmrSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RPLT_RO_ST, reg->rpltRoSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_BAD_DLLP_ST, reg->badDllpSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_BAD_TLP_ST, reg->badTlpSt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RCVR_ERR_ST, reg->rcvrErrSt);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_corErr_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Correctable Error Status register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_corErr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieCorErrReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_ADV_NFERR_ST, reg->advNFErrSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RPLY_TMR_ST, reg->rplyTmrSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RPLT_RO_ST, reg->rpltRoSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_BAD_DLLP_ST, reg->badDllpSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_BAD_TLP_ST, reg->badTlpSt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_RCVR_ERR_ST, reg->rcvrErrSt);\r
-\r
- baseAddr->PCIE_CERR = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_corErr_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Correctable Error Mask register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_corErrMask_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieCorErrMaskReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_CERR_MASK;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_ADV_NFERR_MSK, reg->advNFErrMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RPLY_TMR_MSK, reg->rplyTmrMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RPLT_RO_MSK, reg->rpltRoMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_BAD_DLLP_MSK, reg->badDllpMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_BAD_TLP_MSK, reg->badTlpMsk);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RCVR_ERR_MSK, reg->rcvrErrMsk);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_corErrMask_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Correctable Error Mask register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_corErrMask_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieCorErrMaskReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_ADV_NFERR_MSK, reg->advNFErrMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RPLY_TMR_MSK, reg->rplyTmrMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RPLT_RO_MSK, reg->rpltRoMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_BAD_DLLP_MSK, reg->badDllpMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_BAD_TLP_MSK, reg->badTlpMsk);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_CERR_MASK_RCVR_ERR_MSK, reg->rcvrErrMsk);\r
-\r
- baseAddr->PCIE_CERR_MASK = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_corErrMask_reg*/\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Advanced Capabilities and Control register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_accr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieAccrReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PCIE_ACCR;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_CHK_EN, reg->chkEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_CHK_CAP, reg->chkCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_GEN_EN, reg->genEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_GEN_CAP, reg->genCap);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_FRST_ERR_PTR, reg->erPtr);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_accr_reg */\r
-\r
-\r
-/*****************************************************************************\r
- * Combine and write the Advanced Capabilities and Control register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_accr_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieAccrReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_CHK_EN, reg->chkEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_CHK_CAP, reg->chkCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_GEN_EN, reg->genEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_ECRC_GEN_CAP, reg->genCap);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PCIE_ACCR_FRST_ERR_PTR, reg->erPtr);\r
-\r
- baseAddr->PCIE_ACCR = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_accr_reg */\r
-\r
-/***************************************************************************** \r
- * Read and split up the Header Log register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_hdrLog_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieHdrLogReg_t *reg,\r
- int regNum\r
-)\r
-{\r
- uint32_t val = reg->raw = reg->hdrDW = baseAddr->HDR_LOG[regNum];\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_hdrLog_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Root Error Command register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_rootErrCmd_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieRootErrCmdReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->RC_ERR_CMD;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_FERR_RPT_EN, reg->ferrRptEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_NFERR_RPT_EN, reg->nferrRptEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_CERR_RPT_EN, reg->cerrRptEn);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_rootErrCmd_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Root Error Command register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_rootErrCmd_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieRootErrCmdReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_FERR_RPT_EN, reg->ferrRptEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_NFERR_RPT_EN, reg->nferrRptEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_CMD_CERR_RPT_EN, reg->cerrRptEn);\r
-\r
- baseAddr->RC_ERR_CMD = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_rootErrCmd_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Root Error Status register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_rootErrSt_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieRootErrStReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->RC_ERR_ST;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_AER_INT_MSG, reg->aerIntMsg);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_FERR_RCV, reg->ferrRcv);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_NFERR, reg->nfErr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_UNCOR_FATAL, reg->uncorFatal);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_MULT_FNF, reg->multFnf);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_ERR_FNF, reg->errFnf);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_MULT_COR, reg->multCor);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_CORR_ERR, reg->corrErr);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_rootErrSt_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Root Error Status register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_rootErrSt_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieRootErrStReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_AER_INT_MSG, reg->aerIntMsg);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_FERR_RCV, reg->ferrRcv);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_NFERR, reg->nfErr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_UNCOR_FATAL, reg->uncorFatal);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_MULT_FNF, reg->multFnf);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_ERR_FNF, reg->errFnf);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_MULT_COR, reg->multCor);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_RC_ERR_ST_CORR_ERR, reg->corrErr);\r
-\r
- baseAddr->RC_ERR_ST = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_rootErrSt_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Error Source Identification register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_errSrcID_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieErrSrcIDReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->ERR_SRC_ID;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ERR_SRC_ID_FNF_SRC_ID, reg->fnfSrcID);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ERR_SRC_ID_CORR_SRC_ID, reg->corrSrcID);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_errSrcID_reg*/\r
-\r
-\r
-/*****************************************************************************\r
- ********** PCIe LOCAL/REMOTE PORT LOGIC REGISTERS **********************\r
- ****************************************************************************/\r
-\r
-\r
-/*****************************************************************************\r
- * These APIs are using the endpoint (Type 0) structure and #defines, but they\r
- * should be used for both EP and RC (Type 0 and Type 1) PCIe modes.\r
- * Both types have the same register layout, in the same location.\r
- ****************************************************************************/\r
-\r
-/***************************************************************************** \r
- * Read and split up the Ack Latency and Replay Timer register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_plAckTimer_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePlAckTimerReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PL_ACKTIMER;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_ACKTIMER_RPLY_LIMT, reg->rplyLmt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_ACKTIMER_RND_TRP_LMT, reg->rndTrpLmt);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_plAckTimer_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Ack Latency and Replay Timer register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_plAckTimer_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePlAckTimerReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_ACKTIMER_RPLY_LIMT, reg->rplyLmt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_ACKTIMER_RND_TRP_LMT, reg->rndTrpLmt);\r
-\r
- baseAddr->PL_ACKTIMER = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_plAckTimer_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Other Message register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_plOMsg_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePlOMsgReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = reg->oMsg = baseAddr->PL_OMSG;\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_plOMsg_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Other Message register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_plOMsg_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePlOMsgReg_t *reg \r
-)\r
-{\r
- baseAddr->PL_OMSG = reg->raw = reg->oMsg;\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_write_plOMsg_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Port Force Link register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_plForceLink_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePlForceLinkReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PL_FORCE_LINK;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LPE_CNT, reg->lpeCnt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LNK_STATE, reg->lnkState);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_FORCE_LINK, reg->forceLink);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LINK_NUM, reg->linkNum);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_plForceLink_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Port Force Link register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_plForceLink_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pciePlForceLinkReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LPE_CNT, reg->lpeCnt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LNK_STATE, reg->lnkState);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_FORCE_LINK, reg->forceLink);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_FORCE_LINK_LINK_NUM, reg->linkNum);\r
-\r
- baseAddr->PL_FORCE_LINK = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_plForceLink_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Ack Frequency register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_ackFreq_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieAckFreqReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->ACK_FREQ;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_ASPM_L1, reg->aspmL1);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_L1_ENTRY_LATENCY, reg->l1EntryLatency);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_L0S_ENTRY_LATENCY, reg->l0sEntryLatency);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_COMM_NFTS, reg->commNFts);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_NFTS, reg->nFts);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_ACK_FREQ, reg->ackFreq);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_ackFreq_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Ack Frequency register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_ackFreq_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieAckFreqReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_ASPM_L1, reg->aspmL1);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_L1_ENTRY_LATENCY, reg->l1EntryLatency);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_L0S_ENTRY_LATENCY, reg->l0sEntryLatency);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_COMM_NFTS, reg->commNFts);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_NFTS, reg->nFts);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_ACK_FREQ_ACK_FREQ, reg->ackFreq);\r
-\r
- baseAddr->ACK_FREQ = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_ackFreq_reg*/\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Port Link Control register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_lnkCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLnkCtrlReg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PL_LINK_CTRL;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_LNK_MODE, reg->lnkMode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_LNK_RATE, reg->lnkRate);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_FLNK_MODE, reg->fLnkMode);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_DLL_EN, reg->dllEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_RST_ASRT, reg->rstAsrt);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_LPBK_EN, reg->lpbkEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_SCRM_DIS, reg->scrmDis);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_OMSG_REQ, reg->msgReq);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_lnkCtrl_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Port Link Control register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_lnkCtrl_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLnkCtrlReg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_LNK_MODE, reg->lnkMode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_LNK_RATE, reg->lnkRate);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_FLNK_MODE, reg->fLnkMode);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_DLL_EN, reg->dllEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_RST_ASRT, reg->rstAsrt);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_LPBK_EN, reg->lpbkEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_SCRM_DIS, reg->scrmDis);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_LINK_CTRL_OMSG_REQ, reg->msgReq);\r
-\r
- baseAddr->PL_LINK_CTRL = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_lnkCtrl_reg */\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Lane Skew register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_laneSkew_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLaneSkewReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->LANE_SKEW;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_L2L_DESKEW, reg->l2Deskew);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_ACK_DISABLE, reg->ackDisable);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_FC_DISABLE, reg->fcDisable);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_LANE_SKEW, reg->laneSkew);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_laneSkew_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Lane Skew register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_laneSkew_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieLaneSkewReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_L2L_DESKEW, reg->l2Deskew);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_ACK_DISABLE, reg->ackDisable);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_FC_DISABLE, reg->fcDisable);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_LANE_SKEW_LANE_SKEW, reg->laneSkew);\r
-\r
- baseAddr->LANE_SKEW = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_laneSkew_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Symbol Number register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_symNum_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieSymNumReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->SYM_NUM;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_MAX_FUNC, reg->maxFunc);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_FCWATCH_TIMER, reg->fcWatchTimer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_ACK_LATENCY_TIMER, reg->ackLatencyTimer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_REPLAY_TIMER, reg->replayTimer);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_SKP_COUNT, reg->skpCount);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_NUM_TS2_SYMBOLS, reg->numTs2Symbols);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_TS_COUNT, reg->tsCount);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_symNum_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Symbol Number register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_symNum_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieSymNumReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_MAX_FUNC, reg->maxFunc);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_FCWATCH_TIMER, reg->fcWatchTimer);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_ACK_LATENCY_TIMER, reg->ackLatencyTimer);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_REPLAY_TIMER, reg->replayTimer);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_SKP_COUNT, reg->skpCount);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_NUM_TS2_SYMBOLS, reg->numTs2Symbols);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYM_NUM_TS_COUNT, reg->tsCount);\r
-\r
- baseAddr->SYM_NUM = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_symNum_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Symbol Timer and Filter Mask register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_symTimerFltMask_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieSymTimerFltMaskReg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->SYMTIMER_FLTMASK;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CFG_DROP, reg->f1CfgDrop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_IO_DROP, reg->f1IoDrop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_MSG_DROP, reg->f1MsgDrop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_ECRC_DROP, reg->f1CplEcrcDrop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_ECRC_DROP, reg->f1EcrcDrop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_LEN_TEST, reg->f1CplLenTest);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_ATTR_TEST, reg->f1CplAttrTest);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_TC_TEST, reg->f1CplTcTest);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_FUNC_TEST, reg->f1CplFuncTest);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_REQID_TEST, reg->f1CplReqIDTest);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_TAGERR_TEST, reg->f1CplTagErrTest);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_LOCKED_RD_AS_UR, reg->f1LockedRdAsUr);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CFG1_RE_AS_US, reg->f1Cfg1ReAsUs);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_UR_OUT_OF_BAR, reg->f1UrOutOfBar);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_UR_POISON, reg->f1UrPoison);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_UR_FUN_MISMATCH, reg->f1UrFunMismatch);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_FC_WDOG_DISABLE, reg->fcWdogDisable);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_SKP_VALUE, reg->skpValue);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_symTimerFltMask_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Symbol Timer and Filter Mask register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_symTimerFltMask_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieSymTimerFltMaskReg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CFG_DROP, reg->f1CfgDrop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_IO_DROP, reg->f1IoDrop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_MSG_DROP, reg->f1MsgDrop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_ECRC_DROP, reg->f1CplEcrcDrop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_ECRC_DROP, reg->f1EcrcDrop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_LEN_TEST, reg->f1CplLenTest);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_ATTR_TEST, reg->f1CplAttrTest);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_TC_TEST, reg->f1CplTcTest);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_FUNC_TEST, reg->f1CplFuncTest);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_REQID_TEST, reg->f1CplReqIDTest);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CPL_TAGERR_TEST, reg->f1CplTagErrTest);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_LOCKED_RD_AS_UR, reg->f1LockedRdAsUr);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_CFG1_RE_AS_US, reg->f1Cfg1ReAsUs);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_UR_OUT_OF_BAR, reg->f1UrOutOfBar);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_UR_POISON, reg->f1UrPoison);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_F1_UR_FUN_MISMATCH, reg->f1UrFunMismatch);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_FC_WDOG_DISABLE, reg->fcWdogDisable);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_SYMTIMER_FLTMASK_SKP_VALUE, reg->skpValue);\r
-\r
- baseAddr->SYMTIMER_FLTMASK = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_symTimerFltMask_reg*/\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Filter Mask 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_fltMask2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieFltMask2Reg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->FLT_MASK2;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_FLUSH_REQ, reg->flushReq);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_DLLP_ABORT, reg->dllpAbort);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_VMSG1_DROP, reg->vmsg1Drop);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_VMSG0_DROP, reg->vmsg0Drop);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_fltMask2_reg*/\r
-\r
-/***************************************************************************** \r
- * Combine and write the Filter Mask 2 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_write_fltMask2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieFltMask2Reg_t *reg \r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_FLUSH_REQ, reg->flushReq);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_DLLP_ABORT, reg->dllpAbort);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_VMSG1_DROP, reg->vmsg1Drop);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_FLT_MASK2_VMSG0_DROP, reg->vmsg0Drop);\r
-\r
- baseAddr->FLT_MASK2 = reg->raw = new_val;\r
-\r
- return pcie_range_check_return;\r
-} /*pcie_write_fltMask2_reg*/\r
-\r
-\r
-/*****************************************************************************\r
- * Read and split up the Debug 0 register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_debug0_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDebug0Reg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->DEBUG0;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_TS_LINK_CTRL, reg->tsLnkCtrl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_TS_LANE_K237, reg->tsLaneK237);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_TS_LINK_K237, reg->tsLinkK237);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_RCVD_IDLE0, reg->rcvdIdle0);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_RCVD_IDLE1, reg->rcvdIdle1);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_PIPE_TXDATA, reg->pipeTxData);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_PIPE_TXDATAK, reg->pipeTxDataK);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_TXB_SKIP_TX, reg->skipTx);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG0_LTSSM_STATE, reg->ltssmState);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_debug0_reg */\r
-\r
-\r
-/***************************************************************************** \r
- * Read and split up the Debug 1 register\r
- ****************************************************************************/ \r
-pcieRet_e pcie_read_debug1_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieDebug1Reg_t *reg \r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->DEBUG1;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_SCRAMBLER_DISABLE, reg->scramblerDisable);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_LINK_DISABLE, reg->linkDisable);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_LINK_IN_TRAINING, reg->linkInTraining);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RCVR_REVRS_POL_EN, reg->rcvrRevrsPolEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_TRAINING_RST_N, reg->trainingRstN);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_PIPE_TXDETECTRX_LB, reg->pipeTxdetectrxLb);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_PIPE_TXELECIDLE, reg->pipeTxelecidle);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_PIPE_TXCOMPLIANCE, reg->pipeTxcompliance);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_APP_INIT_RST, reg->appInitRst);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_TS_LINK_NUM, reg->rmlhTsLinkNum);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_XMLH_LINK_UP, reg->xmlhLinkUp);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_INSKIP_RCV, reg->rmlhInskipRcv);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_TS1_RCVD, reg->rmlhTs1Rcvd);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_TS2_RCVD, reg->rmlhTs2Rcvd);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_DEBUG1_RMLH_RCVD_LANE_REV, reg->rmlhRcvdLaneRev);\r
-\r
- return pcie_RET_OK;\r
-} /*pcie_read_debug1_reg*/\r
-\r
-/*****************************************************************************\r
- * Read and split up the Gen 2 register\r
- ****************************************************************************/\r
-pcieRet_e pcie_read_gen2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieGen2Reg_t *reg\r
-)\r
-{\r
- uint32_t val = reg->raw = baseAddr->PL_GEN2;\r
-\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_DEEMPH, reg->deemph);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_CFG_TX_CMPL, reg->txCmpl);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_CFG_TX_SWING, reg->txSwing);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_DIR_SPD, reg->dirSpd);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_LN_EN, reg->lnEn);\r
- pcie_getbits(val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_NUM_FTS, reg->numFts);\r
-\r
- return pcie_RET_OK;\r
-} /* pcie_read_gen2_reg */\r
-\r
-/*****************************************************************************\r
- * Combine and write the Gen 2 register\r
- ****************************************************************************/\r
-pcieRet_e pcie_write_gen2_reg\r
-(\r
- CSL_Pcie_cfg_space_endpointRegs *baseAddr, \r
- pcieGen2Reg_t *reg\r
-)\r
-{\r
- uint32_t new_val = reg->raw;\r
- pcie_range_check_begin;\r
-\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_DEEMPH, reg->deemph);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_CFG_TX_CMPL, reg->txCmpl);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_CFG_TX_SWING, reg->txSwing);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_DIR_SPD, reg->dirSpd);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_LN_EN, reg->lnEn);\r
- pcie_setbits(new_val, CSL_PCIE_CFG_SPACE_ENDPOINT_PL_GEN2_NUM_FTS, reg->numFts);\r
-\r
- baseAddr->PL_GEN2 = reg->raw = new_val;\r
- return pcie_range_check_return;\r
-} /* pcie_write_gen2_reg */\r
-\r
-/* Nothing past this point */\r
-\r
diff --git a/src/v1/pcieloc.h b/src/v1/pcieloc.h
index fe755a6032b83df8001345fe7407c90748cc6423..a3794f9637dd27fd3d47e3ba9112a4a49abf79e7 100644 (file)
--- a/src/v1/pcieloc.h
+++ b/src/v1/pcieloc.h
\r
/* Common utility macros */\r
\r
-/* Get base address for Local Configuration Space */\r
-#define pcie_get_loc_cfg_base(handle, ep_loc_base, rc_loc_base) \\r
- { \\r
- ep_loc_base = (CSL_EpCfgDbIcsRegs *) ((unsigned int)handle + 0x1000); \\r
- rc_loc_base = (CSL_RcCfgDbIcsRegs *) ((unsigned int)handle + 0x1000); \\r
- }\r
- \r
-/* Get base address for Remote Configuration Space */\r
-#define pcie_get_rem_cfg_base(handle, ep_rem_base, rc_rem_base) \\r
- { \\r
- ep_rem_base = (CSL_EpCfgDbIcsRegs *) ((unsigned int)handle + 0x2000); \\r
- rc_rem_base = (CSL_RcCfgDbIcsRegs *) ((unsigned int)handle + 0x2000); \\r
- }\r
-\r
-\r
-\r
/******************************************************************************\r
* Prototypes\r
******************************************************************************/\r
pcieTiConfDiagCtrlReg_t *swReg\r
);\r
\r
+/* MASK/SHIFT for backwards compatibility with old APIs */\r
+#define PCIE_EP_BAR_BASE_FULL_MASK (CSL_EPCFGDBICS_BAR_BASE_ADDR_RO_MASK | CSL_EPCFGDBICS_BAR_BASE_ADDR_RW_MASK)\r
+#define PCIE_EP_BAR_BASE_FULL_SHIFT (CSL_EPCFGDBICS_BAR_BASE_ADDR_RO_SHIFT)\r
+\r
+#define PCIE_RC_BAR_BASE_FULL_MASK (CSL_RCCFGDBICS_BAR_BASE_ADDR_RO_MASK | CSL_RCCFGDBICS_BAR_BASE_ADDR_RW_MASK)\r
+#define PCIE_RC_BAR_BASE_FULL_SHIFT (CSL_RCCFGDBICS_BAR_BASE_ADDR_RO_SHIFT)\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
diff --git a/src/v1/pciev1.c b/src/v1/pciev1.c
index 7bce1d34fee33b03102b3685331a20de7c2b6f6b..99046a7bbceee116a964897157cc9c6c2d5107b3 100644 (file)
--- a/src/v1/pciev1.c
+++ b/src/v1/pciev1.c
* Set the mode of one interface without depending directly on device \r
* dependant registers (via device.c)\r
****************************************************************************/\r
-static void pcie_set_mode (Pcie_DeviceCfgBaseAddr *iface, pcieMode_e mode)\r
+static void pcie_set_mode (Pciev1_DeviceCfgBaseAddrs *iface, pcieMode_e mode)\r
{\r
- uint32_t modeReg;\r
- uint32_t newMode = (uint32_t)mode;\r
-\r
- /* Set the mode, without depending on device specific csl files */\r
- modeReg = *iface->pcieSSModeAddr;\r
- modeReg &= ~iface->pcieSSModeMask;\r
- newMode <<= iface->pcieSSModeShift;\r
- newMode &= iface->pcieSSModeMask;\r
- modeReg |= newMode;\r
- *iface->pcieSSModeAddr = modeReg;\r
+ pcieTiConfDeviceTypeReg_t typeReg;\r
+ uint32_t regVal;\r
+\r
+ memset (&typeReg, 0, sizeof(typeReg));\r
+ switch (mode)\r
+ {\r
+ case pcie_EP_MODE:\r
+ regVal = 0;\r
+ break;\r
+ case pcie_LEGACY_EP_MODE:\r
+ regVal = 1;\r
+ break;\r
+ case pcie_RC_MODE:\r
+ default:\r
+ regVal = 4;\r
+ break;\r
+ }\r
+ typeReg.type = regVal;\r
+ pciev1_write_tiConfDeviceType_reg (iface->tiConf, &typeReg);\r
+ do {\r
+ /* Poll until complete */\r
+ pciev1_read_tiConfDeviceType_reg (iface->tiConf, &typeReg);\r
+ } while (typeReg.type != regVal);\r
} /* pcie_set_mode */\r
\r
/*****************************************************************************\r
pcieMode_e mode /**< [in] PCIE Mode */\r
)\r
{\r
- Pcie_DeviceCfgBaseAddr *bases = pcie_handle_to_cfg (handle);\r
+ Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
+ Pciev1_DeviceCfgBaseAddrs *bases = cfg->cfgBase;\r
\r
if (bases) {\r
pcie_set_mode (bases, mode);\r
pcieRegisters_t *readRegs /**< [in/out] List of registers to read */\r
)\r
{\r
+ Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
+ Pciev1_DeviceCfgBaseAddrs *bases = cfg->cfgBase;\r
+\r
/* Base Address for the Config Space\r
These registers can be Local/Remote and Type0(EP)/Type1(RC) */\r
- CSL_RcCfgDbIcsRegs *baseCfgRcRegs = NULL;\r
- CSL_EpCfgDbIcsRegs *baseCfgEpRegs = NULL; \r
- CSL_PcieRegs *baseCfgTiConfRegs = NULL;\r
- CSL_PlConfRegs *baseCfgPlRegs = NULL;\r
+ CSL_RcCfgDbIcsRegs *baseCfgRcRegs = bases->rcDbics;\r
+ CSL_EpCfgDbIcsRegs *baseCfgEpRegs = bases->rcDbics; \r
+ CSL_RcCfgDbIcsRegs *baseCfgRcCS2Regs = bases->rcDbics2;\r
+ CSL_EpCfgDbIcsRegs *baseCfgEpCS2Regs = bases->rcDbics2; \r
+ CSL_PcieRegs *baseCfgTiConfRegs = bases->tiConf;\r
+ CSL_PlConfRegs *baseCfgPlRegs = bases->plConf;\r
\r
pcieRet_e retVal = pcie_RET_OK;\r
int i;\r
pcie_check_handle(handle);\r
\r
/* Get base address for Local or Remote config space */\r
- if (location == pcie_LOCATION_LOCAL) \r
+ if (location != pcie_LOCATION_LOCAL) \r
{\r
- pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
- }\r
- else\r
- {\r
- pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
+ char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset;\r
+ uint32_t delta = 0;\r
+ baseCfgRcRegs = (CSL_RcCfgDbIcsRegs *)(remoteBase + delta);\r
+ baseCfgEpRegs = (CSL_EpCfgDbIcsRegs *)(remoteBase + delta);\r
+ delta = (char *)bases->plConf - (char *)bases->rcDbics;\r
+ baseCfgPlRegs = (CSL_PlConfRegs *) (remoteBase + delta);\r
}\r
\r
/*****************************************************************************************\r
pcie_check_result(retVal, pciev1_read_type0Bar32bit_reg (baseCfgEpRegs, &(readRegs->type0Bar32bitIdx->reg),\r
readRegs->type0Bar32bitIdx->idx));\r
}\r
+ if (readRegs->type0BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev1_read_type0Bar32bit_reg (baseCfgEpCS2Regs, &(readRegs->type0BarMask32bitIdx->reg),\r
+ readRegs->type0BarMask32bitIdx->idx));\r
+ }\r
if (readRegs->subId) {\r
pcie_check_result(retVal, pciev1_read_subId_reg (baseCfgEpRegs, readRegs->subId));\r
}\r
pcie_check_result(retVal, pciev1_read_type1Bar32bit_reg (baseCfgRcRegs, &(readRegs->type1Bar32bitIdx->reg),\r
readRegs->type1Bar32bitIdx->idx));\r
}\r
+ if (readRegs->type1BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev1_read_type1Bar32bit_reg (baseCfgRcCS2Regs, &(readRegs->type1BarMask32bitIdx->reg),\r
+ readRegs->type1BarMask32bitIdx->idx));\r
+ }\r
if (readRegs->type1BusNum) {\r
pcie_check_result(retVal, pciev1_read_type1BusNum_reg (baseCfgRcRegs, readRegs->type1BusNum));\r
}\r
}\r
\r
return retVal;\r
-} /* Pcie_readRegs */\r
+} /* Pciev1_readRegs */\r
\r
\r
/*********************************************************************\r
pcieRegisters_t *writeRegs /**< [in] List of registers to write */\r
)\r
{\r
+ Pcie_DeviceCfgBaseAddr *cfg = pcie_handle_to_cfg (handle);\r
+ Pciev1_DeviceCfgBaseAddrs *bases = cfg->cfgBase;\r
+\r
/* Base Address for the Config Space\r
These registers can be Local/Remote and Type0(EP)/Type1(RC) */\r
- CSL_RcCfgDbIcsRegs *baseCfgRcRegs = NULL;\r
- CSL_EpCfgDbIcsRegs *baseCfgEpRegs = NULL; \r
- CSL_PcieRegs *baseCfgTiConfRegs = NULL;\r
- CSL_PlConfRegs *baseCfgPlRegs = NULL;\r
+ CSL_RcCfgDbIcsRegs *baseCfgRcRegs = bases->rcDbics;\r
+ CSL_EpCfgDbIcsRegs *baseCfgEpRegs = bases->rcDbics; \r
+ CSL_RcCfgDbIcsRegs *baseCfgRcCS2Regs = bases->rcDbics2;\r
+ CSL_EpCfgDbIcsRegs *baseCfgEpCS2Regs = bases->rcDbics2; \r
+ CSL_PcieRegs *baseCfgTiConfRegs = bases->tiConf;\r
+ CSL_PlConfRegs *baseCfgPlRegs = bases->plConf;\r
\r
pcieRet_e retVal = pcie_RET_OK;\r
int i;\r
pcie_check_handle(handle);\r
\r
/* Get base address for Local/Remote config space */\r
- if (location == pcie_LOCATION_LOCAL) \r
- {\r
- pcie_get_loc_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
- }\r
- else\r
+ if (location != pcie_LOCATION_LOCAL) \r
{\r
- pcie_get_rem_cfg_base(handle, baseCfgEpRegs, baseCfgRcRegs) \r
+ char *remoteBase = (char *)cfg->dataBase + bases->remoteOffset;\r
+ uint32_t delta = 0;\r
+ baseCfgRcRegs = (CSL_RcCfgDbIcsRegs *)(remoteBase + delta);\r
+ baseCfgEpRegs = (CSL_EpCfgDbIcsRegs *)(remoteBase + delta);\r
+ delta = (char *)bases->plConf - (char *)bases->rcDbics;\r
+ baseCfgPlRegs = (CSL_PlConfRegs *) (remoteBase + delta);\r
}\r
\r
/*****************************************************************************************\r
pcie_check_result(retVal, pciev1_write_type0Bar_reg (baseCfgEpRegs, &(writeRegs->type0BarIdx->reg), \r
writeRegs->type0BarIdx->idx));\r
}\r
+ if (writeRegs->type0BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev1_write_type0Bar32bit_reg (baseCfgEpCS2Regs, &(writeRegs->type0BarMask32bitIdx->reg),\r
+ writeRegs->type0BarMask32bitIdx->idx));\r
+ }\r
if (writeRegs->type0Bar32bitIdx) {\r
pcie_check_result(retVal, pciev1_write_type0Bar32bit_reg (baseCfgEpRegs, &(writeRegs->type0Bar32bitIdx->reg),\r
writeRegs->type0Bar32bitIdx->idx));\r
pcie_check_result(retVal, pciev1_write_type1Bar_reg (baseCfgRcRegs, &(writeRegs->type1BarIdx->reg), \r
writeRegs->type1BarIdx->idx));\r
}\r
+ if (writeRegs->type1BarMask32bitIdx) {\r
+ pcie_check_result(retVal, pciev1_write_type1Bar32bit_reg (baseCfgRcCS2Regs, &(writeRegs->type1BarMask32bitIdx->reg),\r
+ writeRegs->type1BarMask32bitIdx->idx));\r
+ }\r
if (writeRegs->type1Bar32bitIdx) {\r
pcie_check_result(retVal, pciev1_write_type1Bar32bit_reg (baseCfgRcRegs, &(writeRegs->type1Bar32bitIdx->reg),\r
writeRegs->type1Bar32bitIdx->idx));\r
if (writeRegs->plconfIatuIndex) {\r
pcie_check_result(retVal, pciev1_write_plconfIatuIndex_reg (baseCfgPlRegs, writeRegs->plconfIatuIndex));\r
}\r
- if (writeRegs->plconfIatuRegCtrl1) {\r
- pcie_check_result(retVal, pciev1_write_plconfIatuRegCtrl1_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl1));\r
- }\r
if (writeRegs->plconfIatuRegCtrl2) {\r
pcie_check_result(retVal, pciev1_write_plconfIatuRegCtrl2_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl2));\r
}\r
/* Pure RO register */\r
pcie_check_result(retVal, pcie_RET_INV_REG);\r
}\r
-\r
+ /* Ctrl1 is done last since it has enable bit */\r
+ if (writeRegs->plconfIatuRegCtrl1) {\r
+ pcie_check_result(retVal, pciev1_write_plconfIatuRegCtrl1_reg (baseCfgPlRegs, writeRegs->plconfIatuRegCtrl1));\r
+ }\r
\r
/* TI CONF registers */\r
if (writeRegs->tiConfRevision) {\r
} /* Pciev1_writeRegs */\r
\r
\r
-/*********************************************************************\r
- * FUNCTION PURPOSE: Configures the Outbound Offset registers \r
- * for outbound address translation\r
- ********************************************************************/\r
-#if 0\r
-pcieRet_e Pciev1_cfgObOffset \r
-(\r
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
- uint32_t obAddrLo, /**< [in] Low Outbound address offset (32bits) */\r
- uint32_t obAddrHi, /**< [in] High Outbound address offset (32bits) */\r
- uint8_t region /**< [in] Identifies the Outbound region (0-31) */\r
-)\r
-{\r
-\r
- CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle; \r
- pcieRet_e retVal = pcie_RET_OK;\r
- pcieObOffsetLoReg_t obOffsetLo;\r
- pcieObOffsetHiReg_t obOffsetHi;\r
- uint16_t obAddrLoField;\r
-\r
- if (! pcieLObjIsValid) {\r
- return pcie_RET_NO_INIT;\r
- }\r
-\r
- pcie_check_handle(handle);\r
- \r
- memset (&obOffsetLo, 0, sizeof(obOffsetLo));\r
- memset (&obOffsetHi, 0, sizeof(obOffsetHi));\r
-\r
- pcie_getbits(obAddrLo, CSL_PCIESS_APP_OB_OFFSET_INDEX_OB_OFFSET_LO, obAddrLoField);\r
- \r
- obOffsetLo.enable = 1;\r
- obOffsetLo.offsetLo = obAddrLoField;\r
-\r
- obOffsetHi.offsetHi = obAddrHi;\r
-\r
- pcie_check_result(retVal, pciev1_write_obOffsetLo_reg(baseAppRegs, &obOffsetLo, region));\r
- pcie_check_result(retVal, pciev1_write_obOffsetHi_reg(baseAppRegs, &obOffsetHi, region));\r
-\r
- return retVal;\r
-} /* Pciev1_cfgObOffset */\r
-\r
-\r
-/*********************************************************************\r
- * FUNCTION PURPOSE: Configures the Inbound Translation registers \r
- ********************************************************************/\r
-pcieRet_e Pcie_cfgIbTrans \r
-(\r
- Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
- pcieIbTransCfg_t *ibCfg /**< [in] Inbound Translation Configuration parameters */\r
-)\r
-{\r
-\r
- CSL_Pciess_appRegs *baseAppRegs = (CSL_Pciess_appRegs *)handle; \r
- pcieRet_e retVal = pcie_RET_OK;\r
-\r
- pcieIbBarReg_t ibBar;\r
- pcieIbStartLoReg_t ibStartLo;\r
- pcieIbStartHiReg_t ibStartHi;\r
- pcieIbOffsetReg_t ibOffset;\r
- \r
- uint32_t ibStartLoField;\r
- uint32_t ibOffsetField;\r
-\r
- if (! pcieLObjIsValid) {\r
- return pcie_RET_NO_INIT;\r
- }\r
-\r
- pcie_check_handle(handle);\r
- \r
- memset (&ibBar, 0, sizeof(ibBar));\r
- memset (&ibStartLo, 0, sizeof(ibStartLo));\r
- memset (&ibStartHi, 0, sizeof(ibStartHi));\r
- memset (&ibOffset, 0, sizeof(ibOffset));\r
-\r
- ibBar.ibBar = ibCfg->ibBar;\r
- \r
- pcie_getbits(ibCfg->ibStartAddrLo, CSL_PCIESS_APP_IB_START_LO_IB_START_LO, ibStartLoField);\r
- ibStartLo.ibStartLo = ibStartLoField;\r
-\r
- ibStartHi.ibStartHi = ibCfg->ibStartAddrHi;\r
-\r
- pcie_getbits(ibCfg->ibOffsetAddr, CSL_PCIESS_APP_IB_OFFSET_IB_OFFSET, ibOffsetField);\r
- ibOffset.ibOffset = ibOffsetField;\r
- \r
-\r
- pcie_check_result(retVal, pciev1_write_ibBar_reg (baseAppRegs, &ibBar, ibCfg->region));\r
- pcie_check_result(retVal, pciev1_write_ibStartLo_reg(baseAppRegs, &ibStartLo, ibCfg->region));\r
- pcie_check_result(retVal, pciev1_write_ibStartHi_reg(baseAppRegs, &ibStartHi, ibCfg->region));\r
- pcie_check_result(retVal, pciev1_write_ibOffset_reg (baseAppRegs, &ibOffset, ibCfg->region));\r
-\r
- return retVal;\r
-} /* Pciev1_cfgIbTrans */\r
-\r
-\r
/*********************************************************************\r
* FUNCTION PURPOSE: Configures a BAR Register (32bits)\r
********************************************************************/\r
pcieBarCfg_t *barCfg /**< [in] BAR configuration parameters */\r
)\r
{\r
+ pcieRet_e retVal = pcie_RET_OK;\r
pcieType0BarIdx_t type0BarIdx; \r
pcieType1BarIdx_t type1BarIdx; \r
pcieRegisters_t setRegs;\r
uint32_t barAddrField = 0;\r
- pcieRet_e retVal = pcie_RET_OK;\r
\r
if (! pcieLObjIsValid) {\r
return pcie_RET_NO_INIT;\r
\r
if(barCfg->mode == pcie_RC_MODE)\r
{\r
- pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ROOTCOMPLEX_BAR_BASE_ADDRESS, barAddrField);\r
+ pcie_getbits(barCfg->base, PCIE_RC_BAR_BASE_FULL, barAddrField);\r
\r
type1BarIdx.reg.base = barAddrField;\r
type1BarIdx.reg.prefetch = barCfg->prefetch;\r
}\r
else\r
{\r
- pcie_getbits(barCfg->base, CSL_PCIE_CFG_SPACE_ENDPOINT_BAR_BASE_ADDRESS, barAddrField);\r
+ pcie_getbits(barCfg->base, PCIE_EP_BAR_BASE_FULL, barAddrField);\r
\r
type0BarIdx.reg.base = barAddrField;\r
type0BarIdx.reg.prefetch = barCfg->prefetch;\r
setRegs.type0BarIdx = &type0BarIdx; \r
}\r
\r
- if ((retVal = Pcie_writeRegs (handle, barCfg->location, &setRegs)) != pcie_RET_OK) \r
+ if ((retVal = Pciev1_writeRegs (handle, barCfg->location, &setRegs)) != pcie_RET_OK) \r
{\r
return retVal;\r
}\r
\r
return retVal;\r
} /* Pciev1_cfgBar */\r
-#endif\r
+\r
+\r
+/*********************************************************************\r
+ * FUNCTION PURPOSE: Configures an ATU (address translation) region\r
+ ********************************************************************/\r
+pcieRet_e Pciev1_atuRegionConfig \r
+(\r
+ Pcie_Handle handle, /**< [in] The PCIE LLD instance identifier */\r
+ pcieLocation_e location, /**< [in] local/remote */\r
+ uint32_t atuRegionIndex, /* [in] index number to configure */\r
+ const pcieAtuRegionParams_t *atuRegionParams /* [in] config structure */\r
+)\r
+{\r
+ pcieRet_e retVal = pcie_RET_OK;\r
+ pciePlconfIatuIndexReg_t index;\r
+ pciePlconfIatuRegCtrl1Reg_t ctrl1;\r
+ pciePlconfIatuRegCtrl2Reg_t ctrl2;\r
+ pciePlconfIatuRegLowerBaseReg_t lowerBase;\r
+ pciePlconfIatuRegUpperBaseReg_t upperBase;\r
+ pciePlconfIatuRegLimitReg_t limit;\r
+ pciePlconfIatuRegLowerTargetReg_t lowerTarget;\r
+ pciePlconfIatuRegUpperTargetReg_t upperTarget;\r
+ pcieRegisters_t regs;\r
+\r
+ /* Set up register pointer for interesting registers */\r
+ memset (®s, 0, sizeof(regs));\r
+ regs.plconfIatuIndex = &index;\r
+\r
+ /* Read current values for index */\r
+ if ((retVal = Pciev1_readRegs (handle, location, ®s)) != pcie_RET_OK)\r
+ {\r
+ return retVal;\r
+ }\r
+\r
+ /* Update ATU index register with new region direction and region index.\r
+ **/\r
+ switch (atuRegionParams->regionDir)\r
+ {\r
+ /* translate arguments to avoid CSL in public header files */\r
+ case PCIE_ATU_REGION_DIR_OUTBOUND:\r
+ index.regionDirection = CSL_PLCONF_IATU_INDEX_REGION_DIRECTION_OUTBOUND;\r
+ break;\r
+ case PCIE_ATU_REGION_DIR_INBOUND:\r
+ default:\r
+ index.regionDirection = CSL_PLCONF_IATU_INDEX_REGION_DIRECTION_INBOUND;\r
+ break;\r
+ }\r
+ index.regionIndex = atuRegionIndex;\r
+\r
+ /* Writeback the new values for index */\r
+ if ((retVal = Pciev1_writeRegs (handle, location, ®s)) != pcie_RET_OK)\r
+ {\r
+ return retVal;\r
+ }\r
+\r
+ regs.plconfIatuIndex = NULL;\r
+ regs.plconfIatuRegCtrl1 = &ctrl1;\r
+ regs.plconfIatuRegCtrl2 = &ctrl2;\r
+ regs.plconfIatuRegLowerBase = &lowerBase;\r
+ regs.plconfIatuRegUpperBase = &upperBase;\r
+ regs.plconfIatuRegLimit = &limit;\r
+ regs.plconfIatuRegLowerTarget = &lowerTarget;\r
+ regs.plconfIatuRegUpperTarget = &upperTarget;\r
+\r
+ /* Read current values of rest of registers for this index */\r
+ if ((retVal = Pciev1_readRegs (handle, location, ®s)) != pcie_RET_OK)\r
+ {\r
+ return retVal;\r
+ }\r
+\r
+ /* Set TLP(Transaction Layer packet) type. */\r
+ switch (atuRegionParams->tlpType)\r
+ {\r
+ case PCIE_TLP_TYPE_IO:\r
+ ctrl1.type = 2U;\r
+ break;\r
+ case PCIE_TLP_TYPE_CFG:\r
+ ctrl1.type = 4U;\r
+ break;\r
+ case PCIE_TLP_TYPE_MEM:\r
+ default:\r
+ ctrl1.type = 0U;\r
+ break;\r
+ }\r
+\r
+ /* Configure ATU control2 register. */\r
+ /* Enable region. */\r
+ ctrl2.regionEnable = atuRegionParams->enableRegion;\r
+ if (PCIE_ATU_REGION_DIR_INBOUND == atuRegionParams->regionDir)\r
+ {\r
+ /* Set match mode. */\r
+ switch (atuRegionParams->matchMode)\r
+ {\r
+ case PCIE_ATU_REGION_MATCH_MODE_ADDR:\r
+ ctrl2.matchMode = CSL_PLCONF_IATU_REG_CTRL_2_MATCH_MODE__0;\r
+ break;\r
+ case PCIE_ATU_REGION_MATCH_MODE_BAR:\r
+ default:\r
+ ctrl2.matchMode = CSL_PLCONF_IATU_REG_CTRL_2_MATCH_MODE__1;\r
+ break;\r
+ }\r
+\r
+ /* Set BAR number. */\r
+ ctrl2.barNumber = atuRegionParams->barNumber;\r
+ }\r
+\r
+ /* Configure lower base. */\r
+ lowerBase.iatuRegLowerBase = atuRegionParams->lowerBaseAddr >> 12;\r
+\r
+ /* Configure upper base. */\r
+ upperBase.iatuRegUpperBase = atuRegionParams->upperBaseAddr;\r
+\r
+ /* Configure window size. */\r
+ limit.iatuRegLimit = (atuRegionParams->lowerBaseAddr + \r
+ atuRegionParams->regionWindowSize) >> 12;\r
+\r
+ /* Configure lower target. */\r
+ lowerTarget.iatuRegLowerTarget = atuRegionParams->lowerTargetAddr >> 12;\r
+\r
+ /* Configure Upper target. */\r
+ upperTarget.iatuRegUpperTarget = atuRegionParams->upperTargetAddr;\r
+\r
+ /* Writeback the new values */\r
+ return Pciev1_writeRegs (handle, location, ®s);\r
+} /* Pciev1_atuRegionConfig */\r
\r
/* Nothing past this point */\r
\r
diff --git a/src/v1/pciev1_ep.c b/src/v1/pciev1_ep.c
index 91f5be66ae05cece1c7fd7bee8b8885056fe7b28..d8b1831162bf388e81384cb1234306c44fe38ac6 100644 (file)
--- a/src/v1/pciev1_ep.c
+++ b/src/v1/pciev1_ep.c
pcie_getbits(val, CSL_EPCFGDBICS_BAR_SPACE_DECODER, swReg->memSpace);
pcie_getbits(val, CSL_EPCFGDBICS_BAR_AS, swReg->type);
pcie_getbits(val, CSL_EPCFGDBICS_BAR_PREFETCHABLE, swReg->prefetch);
-#define PCIE_EP_BAR_BASE_FULL_MASK (CSL_EPCFGDBICS_BAR_BASE_ADDR_RO_MASK | CSL_EPCFGDBICS_BAR_BASE_ADDR_RW_MASK)
-#define PCIE_EP_BAR_BASE_FULL_SHIFT (CSL_EPCFGDBICS_BAR_BASE_ADDR_RO_SHIFT)
pcie_getbits(val, PCIE_EP_BAR_BASE_FULL, swReg->base);
return pcie_RET_OK;
diff --git a/src/v1/pciev1_plconf.c b/src/v1/pciev1_plconf.c
index 215fb8e0ccd3f650e23785f6dc6fc8ba19abe5b3..b50e63c46a559caf1ccf9efa1f9d77690f9d8740 100644 (file)
--- a/src/v1/pciev1_plconf.c
+++ b/src/v1/pciev1_plconf.c
/*****************************************************************************
* Read and split up the PL CONF Vendor Specific DLLP register
****************************************************************************/
-pcieRet_e pciev1_read_plconfVendorSpecificDllp_reg
+pcieRet_e pciev1_read_plOMsg_reg
(
CSL_PlConfRegs *baseAddr,
pciePlOMsgReg_t *swReg
diff --git a/src/v1/pciev1_rc.c b/src/v1/pciev1_rc.c
index 9b112f735d83abd0f00dfcaddf542d6e5a0f9b7a..2c18a44e2b9d855c3d038568518e337fc83ab7bb 100644 (file)
--- a/src/v1/pciev1_rc.c
+++ b/src/v1/pciev1_rc.c
pcie_getbits(val, CSL_RCCFGDBICS_BAR_SPACE_INDICATOR, swReg->memSpace);
pcie_getbits(val, CSL_RCCFGDBICS_BAR_AS, swReg->type);
pcie_getbits(val, CSL_RCCFGDBICS_BAR_PREFETCHABLE, swReg->prefetch);
-#define PCIE_RC_BAR_BASE_FULL_MASK (CSL_RCCFGDBICS_BAR_BASE_ADDR_RO_MASK | CSL_RCCFGDBICS_BAR_BASE_ADDR_RW_MASK)
-#define PCIE_RC_BAR_BASE_FULL_SHIFT (CSL_RCCFGDBICS_BAR_BASE_ADDR_RO_SHIFT)
pcie_getbits(val, PCIE_RC_BAR_BASE_FULL, swReg->base);
return pcie_RET_OK;
diff --git a/src/v1/pciev1_top.c b/src/v1/pciev1_top.c
--- a/src/v1/pciev1_top.c
+++ /dev/null
@@ -1,2 +0,0 @@
-
-