PRSDK-7730: pm: TISCI_SEC to SEC change for build fix

Build fix for TISCI_SEC to SEC, prefix removal.

Signed-off-by: Piyali Goswami <piyali_g@ti.com>

diff --git a/examples/clkrate_manager/V0/pmtest_testsList.h b/examples/clkrate_manager/V0/pmtest_testsList.h
index 9232ec70dce20f4a3909fee2cff36762717ef039..8ce99cbaf04c0f60926f780a6111efbbee7a4685 100755 (executable)
--- a/examples/clkrate_manager/V0/pmtest_testsList.h
+++ b/examples/clkrate_manager/V0/pmtest_testsList.h
@@ -2096,71 +2096,6 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_WKUP_ESM0_BUS_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX1_INV_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_VBUS_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI1_ICLK_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI0_RCLK_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX2_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX2_INV_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI0_ICLK_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_HPB_CLKX1_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI0_DQS_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI1_DQS_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI1_RCLK_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI0_OCLK_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_MCU_FSS0,\r
-        TISCI_DEV_MCU_FSS0_BUS_OSPI1_OCLK_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_GIC0,\r
         TISCI_DEV_GIC0_BUS_VCLK_CLK,\r
@@ -3340,11 +3275,6 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_NAVSS0_BUS_ICSS_G0CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_NAVSS0,\r
-        TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_NAVSS0,\r
         TISCI_DEV_NAVSS0_BUS_MSMC0CLK,\r
@@ -3355,21 +3285,11 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_NAVSS0,\r
-        TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_NAVSS0,\r
         TISCI_DEV_NAVSS0_BUS_MODSS_VD2CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_NAVSS0,\r
-        TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_NAVSS0,\r
         TISCI_DEV_NAVSS0_BUS_PDMA_MAIN1CLK,\r
@@ -3395,11 +3315,6 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_NAVSS0_BUS_ICSS_G1CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_NAVSS0,\r
-        TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_MCU_NAVSS0,\r
         TISCI_DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK,\r
@@ -3420,22 +3335,11 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK,\r
         0\r
     },\r
-    /*TODO: PCIE0/1*/\r
-    {\r
-        TISCI_DEV_PCIE0,\r
-        TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_PCIE0,\r
         TISCI_DEV_PCIE0_BUS_PCIE_CBA_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_PCIE0,\r
-        TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_PCIE0,\r
         TISCI_DEV_PCIE0_BUS_PCIE_TXI0_CLK,\r
@@ -3451,16 +3355,6 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_PCIE0,\r
-        TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_PCIE0,\r
-        TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_PCIE0,\r
         TISCI_DEV_PCIE0_BUS_PCIE_TXR1_CLK,\r
@@ -3471,21 +3365,11 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_PCIE0_BUS_PCIE_TXR0_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_PCIE1,\r
-        TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_PCIE1,\r
         TISCI_DEV_PCIE1_BUS_PCIE_CBA_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_PCIE1,\r
-        TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_PCIE1,\r
         TISCI_DEV_PCIE1_BUS_PCIE_TXI0_CLK,\r
@@ -3501,16 +3385,6 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_PCIE1,\r
-        TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_PCIE1,\r
-        TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_PCIE1,\r
         TISCI_DEV_PCIE1_BUS_PCIE_TXR0_CLK,\r
@@ -4283,405 +4157,6 @@ Pmtest_inputClk_t gPmtest_setFreqTestList[] =
         TISCI_DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK,\r
         0\r
     },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SCL3,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SCL2,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SCL1,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SCL0,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG2_RGMII2_TCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OSPI1CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG1_RGMII1_TCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_REFCLK1P,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OSPI1LBCLKO,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        12500000\r
-    },\r
-    /* Check for other supported clkrates for HFOSC0_CLKOUT */\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        25000000\r
-    },\r
-    /* TODO: MCU_PLLCTL_OBSCLK*/\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        400000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        80000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        96000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        48000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        /* Spec is confusing for CLK_32K_RC*/\r
-        32000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        200000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        133333333\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        100000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        200000000\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        333333333\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OBSCLK,\r
-        32768\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG2_RGMII1_TCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_REFCLK1M,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_OBSCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG0_RGMII1_TCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OSPI0CLK,\r
-        0\r
-    },\r
-    /* TODO : Check the freq of DSS_PLL_CLKOUT .Depends on display resolution ?? */\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_DSS0PCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG0_RGMII2_TCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_WKUP_SCL0,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_REFCLK0P,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_REFCLK0M,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OSPI0LBCLKO,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_CLKOUT,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_SCL0,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SYSCLKOUT,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_SYSCLKOUT,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG1_RGMII1_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG1_RGMII2_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_GPMCCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP2AHCLKX,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP2AHCLKR,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG2_RGMII2_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_CPTS_RFT_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP0ACLKR,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP0ACLKX,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_EXT_REFCLK1,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG0_RGMII2_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OSPI0DQS,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_USB0REFCLKP,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_DSS0EXTPCLKIN,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SPI1CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP2ACLKR,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP1ACLKX,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP1ACLKR,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP2ACLKX,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_RMII1_REFCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_RGMII1_TCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_SPI0CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_SPI1CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG0_RGMII1_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SPI2CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_WKUP_TCK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SPI3CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_USB0REFCLKM,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_RGMII1_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP0AHCLKR,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_EXT_REFCLK0,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP0AHCLKX,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_CCDC0_PCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_HFOSC1_CLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCU_OSPI1DQS,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP1AHCLKX,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PCIE1REFCLKM,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_MCASP1AHCLKR,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PCIE1REFCLKP,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_PRG2_RGMII1_RCLK,\r
-        0\r
-    },\r
-    {\r
-        TISCI_DEV_BOARD0,\r
-        TISCI_DEV_BOARD0_BUS_SPI0CLK,\r
-        0\r
-    },\r
     {\r
         TISCI_DEV_COMPUTE_CLUSTER_MSMC0,\r
         TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK,\r

diff --git a/examples/systemconfig/main_dmsc.c b/examples/systemconfig/main_dmsc.c
index 84068a12610d1ebce1674ee75cf991941313a63d..d178ef46f5b73a0049b21174591b8ae1c4392e7b 100755 (executable)
--- a/examples/systemconfig/main_dmsc.c
+++ b/examples/systemconfig/main_dmsc.c
@@ -153,7 +153,6 @@ uint32_t gModuleNum[] = {
     TISCI_DEV_ESM0,
     TISCI_DEV_MCU_ESM0,
     TISCI_DEV_WKUP_ESM0,
-    TISCI_DEV_MCU_FSS0,
     TISCI_DEV_GIC0,
     TISCI_DEV_GPIO0,
     TISCI_DEV_GPIO1,
@@ -329,15 +328,6 @@ uint32_t gModuleNum[] = {
     TISCI_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0,
     TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0,
     TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0,
-    TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU,
-    TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA,
-    TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC,
-    TISCI_DEV_DUMMY_IP_LPSC_DMSC,
-    TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA,
-    TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN,
-    TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP,
-    TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU,
-    TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA,
     TISCI_DEV_MCU_ARMSS0_CPU1
 };
 
@@ -397,7 +387,6 @@ char * gModuleNames[] =
     "TISCI_DEV_ESM0",
     "TISCI_DEV_MCU_ESM0",
     "TISCI_DEV_WKUP_ESM0",
-    "TISCI_DEV_MCU_FSS0",
     "TISCI_DEV_GIC0",
     "TISCI_DEV_GPIO0",
     "TISCI_DEV_GPIO1",
@@ -575,8 +564,8 @@ char * gModuleNames[] =
     "TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0",
     "TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU",
     "TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA",
-    "TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC",
-    "TISCI_DEV_DUMMY_IP_LPSC_DMSC",
+    "TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD",
+    "TISCI_DEV_DUMMY_IP_LPSC_DMSC_VD",
     "TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA",
     "TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN",
     "TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP",
@@ -1336,8 +1325,8 @@ void alwaysDisabledConfig(void)
             (TISCI_DEV_MCU_RTI0 == gModuleNum[idx]) ||
             (TISCI_DEV_MCU_RTI1 == gModuleNum[idx]) ||
             (TISCI_DEV_WKUP_UART0 == gModuleNum[idx]) ||
-            (TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC == gModuleNum[idx]) ||
-            (TISCI_DEV_DUMMY_IP_LPSC_DMSC == gModuleNum[idx]))
+            (TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD == gModuleNum[idx]) ||
+            (TISCI_DEV_DUMMY_IP_LPSC_DMSC_VD == gModuleNum[idx]))
         {
             continue;
         }
@@ -1462,7 +1451,7 @@ void retentionConfig(void)
             (TISCI_DEV_COMPUTE_CLUSTER_A53_2 == gModuleNum[idx]) ||
             (TISCI_DEV_COMPUTE_CLUSTER_A53_3 == gModuleNum[idx]) ||
 #endif
-            (TISCI_DEV_DUMMY_IP_LPSC_DMSC == gModuleNum[idx]))
+            (TISCI_DEV_DUMMY_IP_LPSC_DMSC_VD == gModuleNum[idx]))
         {
             continue;
         }

diff --git a/include/dmsc/V0/pmlib_clocktree.h b/include/dmsc/V0/pmlib_clocktree.h
index 1a53f55f2f02f46f127770153b09e59a42d40622..1e7079b50d575e5b92fa7492ba5fccb0e6b0d2f3 100755 (executable)
--- a/include/dmsc/V0/pmlib_clocktree.h
+++ b/include/dmsc/V0/pmlib_clocktree.h
@@ -1169,8 +1169,8 @@ extern "C" {
         (0U)    \
     },  \
     {   \
-        "TISCI_DEV_NAVSS0_TISCI_SEC_PROXY0",  \
-        TISCI_DEV_NAVSS0_TISCI_SEC_PROXY0,    \
+        "TISCI_DEV_NAVSS0_SEC_PROXY0",  \
+        TISCI_DEV_NAVSS0_SEC_PROXY0,    \
         (1036U),    \
         (0U)    \
     },  \
@@ -1205,8 +1205,8 @@ extern "C" {
         (0U)    \
     },  \
     {   \
-        "TISCI_DEV_MCU_NAVSS0_TISCI_SEC_PROXY0",  \
-        TISCI_DEV_MCU_NAVSS0_TISCI_SEC_PROXY0,    \
+        "TISCI_DEV_MCU_NAVSS0_SEC_PROXY0",  \
+        TISCI_DEV_MCU_NAVSS0_SEC_PROXY0,    \
         (1036U),    \
         (0U)    \
     },  \

diff --git a/src/pmrtos/dmsc/V0/PowerDMSC_deviceInit.c b/src/pmrtos/dmsc/V0/PowerDMSC_deviceInit.c
index 2a667cfbf546921a2c0420081c48c354e01cd8c4..056407058cc822b6e5bae0b9de353b55c06ce002 100755 (executable)
--- a/src/pmrtos/dmsc/V0/PowerDMSC_deviceInit.c
+++ b/src/pmrtos/dmsc/V0/PowerDMSC_deviceInit.c
@@ -246,13 +246,13 @@ pmlibSysConfigPowerStateParams_t gInputTable[] =
     {TISCI_DEV_NAVSS0_TIMER_MGR0,                       PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_NAVSS0_TIMER_MGR1,                       PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_NAVSS0_PROXY0,                           PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
-    {TISCI_DEV_NAVSS0_TISCI_SEC_PROXY0,                 PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+    {TISCI_DEV_NAVSS0_SEC_PROXY0,                 PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_NAVSS0_RINGACC0,                         PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_NAVSS0_UDMAP0,                           PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0,                  PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0,                PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_MCU_NAVSS0_PROXY0,                       PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
-    {TISCI_DEV_MCU_NAVSS0_TISCI_SEC_PROXY0,             PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+    {TISCI_DEV_MCU_NAVSS0_SEC_PROXY0,             PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_MCU_NAVSS0_MCRC0,                        PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_MCU_NAVSS0_UDMAP0,                       PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
     {TISCI_DEV_MCU_NAVSS0_RINGACC0,                     PMLIB_SYS_CONFIG_ALWAYS_ENABLED},