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raw | patch | inline | side by side (parent: b32923a)
author | Piyali Goswami <piyali_g@ti.com> | |
Mon, 18 Nov 2019 16:11:18 +0000 (21:41 +0530) | ||
committer | Piyali Goswami <piyali_g@ti.com> | |
Mon, 18 Nov 2019 16:14:20 +0000 (21:44 +0530) |
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
index 1dfc35113c3e0417d4f444c2824d9198cf5475dd..1a53f55f2f02f46f127770153b09e59a42d40622 100755 (executable)
(16U), \
(1U) \
}, \
- { \
- "TISCI_NO_DEV", \
- TISCI_NO_DEV, \
- (0U), \
- (0U) \
- }, \
{ \
"TISCI_DEV_MCU_CPSW0", \
TISCI_DEV_MCU_CPSW0, \
(420U), \
(1U) \
}, \
- { \
- "TISCI_DEV_MCU_FSS0", \
- TISCI_DEV_MCU_FSS0, \
- (421U), \
- (21U) \
- }, \
{ \
"TISCI_DEV_GIC0", \
TISCI_DEV_GIC0, \
(923U), \
(113U) \
}, \
- { \
- "TISCI_NO_DEV", \
- TISCI_NO_DEV, \
- (0U), \
- (0U) \
- }, \
{ \
"TISCI_DEV_MCU_ARMSS0_CPU0", \
TISCI_DEV_MCU_ARMSS0_CPU0, \
(0U) \
}, \
{ \
- "TISCI_DEV_NAVSS0_SEC_PROXY0", \
- TISCI_DEV_NAVSS0_SEC_PROXY0, \
+ "TISCI_DEV_NAVSS0_TISCI_SEC_PROXY0", \
+ TISCI_DEV_NAVSS0_TISCI_SEC_PROXY0, \
(1036U), \
(0U) \
}, \
(0U) \
}, \
{ \
- "TISCI_DEV_MCU_NAVSS0_SEC_PROXY0", \
- TISCI_DEV_MCU_NAVSS0_SEC_PROXY0, \
+ "TISCI_DEV_MCU_NAVSS0_TISCI_SEC_PROXY0", \
+ TISCI_DEV_MCU_NAVSS0_TISCI_SEC_PROXY0, \
(1036U), \
(0U) \
}, \
(3U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU", \
- TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU, \
+ "TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA", \
- TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA, \
+ "TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC", \
- TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC, \
+ "TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_DMSC", \
- TISCI_DEV_DUMMY_IP_LPSC_DMSC, \
+ "TISCI_DEV_DUMMY_IP_LPSC_DMSC_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_DMSC_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA", \
- TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA, \
+ "TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN", \
- TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN, \
+ "TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP", \
- TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP, \
+ "TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU", \
- TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU, \
+ "TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD, \
(1080U), \
(0U) \
}, \
{ \
- "TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA", \
- TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA, \
+ "TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD", \
+ TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD, \
(1080U), \
(0U) \
}, \
index ba420344281b2b5ebb3660ccb5ef05227bb7339b..0b7894f5b93d814ac39de0702b7f673d089ac9aa 100755 (executable)
#if defined (SOC_J721E)
const pmlibClkTreeDevice_t gPmlib_clkRateDevices[PMLIB_NUMBER_OF_DEVICES] = PMLIB_CLOCKTREE_DEVICES;
#else
-const pmlibClkTreeDevice_t gPmlib_clkRateDevices[TISCI_DEV_MAX] = PMLIB_CLOCKTREE_DEVICES;
+const pmlibClkTreeDevice_t gPmlib_clkRateDevices[PMLIB_NUMBER_OF_DEVICES] = PMLIB_CLOCKTREE_DEVICES;
#endif
/* ========================================================================== */
index ba94af623b0625c1553cbb402b326a2245f639d7..7a5792434c2e36f34a4f35fa9dc430bbb5ab7011 100755 (executable)
bool enablePolicy; /* power policy is enable during idle loop */
bool perfInitialized; /* performance control enabled */
uint8_t constraintCounts[Power_NUMCONSTRAINTS]; /* constraint count */
- uint32_t dependencyCount[TISCI_DEV_MAX]; /* Dependency count */
+ uint32_t dependencyCount[PMLIB_NUMBER_OF_DEVICES]; /* Dependency count */
/* for every module element */
HwiP_Handle hwi; /* Hwi handle tied to thermal alert */
int intNum; /* processor interrupt number tied to thermal
modId = resourceId;
- if(modId > TISCI_DEV_MAX)
+ if(modId > PMLIB_NUMBER_OF_DEVICES)
{
retVal = Power_INVALIDINPUT;
/* This is a error case, resourceId is invalid */
modId = resourceId;
/* Check if the resource id is valid*/
- if(modId > TISCI_DEV_MAX)
+ if(modId > PMLIB_NUMBER_OF_DEVICES)
{
retVal = Power_INVALIDINPUT;
}
modId = resourceId;
/* Check if the resource id is valid*/
- if(modId > TISCI_DEV_MAX)
+ if(modId > PMLIB_NUMBER_OF_DEVICES)
{
retVal = Power_INVALIDINPUT;
}
index 32e5f7d14a4322da0c66eb0716cf03accf991a99..2a667cfbf546921a2c0420081c48c354e01cd8c4 100755 (executable)
{TISCI_DEV_ESM0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_ESM0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_WKUP_ESM0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_MCU_FSS0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_MCU_FSS0_FSAS_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_MCU_FSS0_HYPERBUS0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_MCU_FSS0_OSPI_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_MCU_FSS0_OSPI_1, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_GIC0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_GPIO0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_GPIO1, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_NAVSS0_TIMER_MGR0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_NAVSS0_TIMER_MGR1, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_NAVSS0_PROXY0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_NAVSS0_SEC_PROXY0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_NAVSS0_TISCI_SEC_PROXY0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_NAVSS0_RINGACC0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_NAVSS0_UDMAP0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_NAVSS0_PROXY0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_MCU_NAVSS0_SEC_PROXY0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_MCU_NAVSS0_TISCI_SEC_PROXY0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_NAVSS0_MCRC0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_NAVSS0_UDMAP0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MCU_NAVSS0_RINGACC0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
{TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_DMSC, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
- {TISCI_DEV_MCU_ARMSS0_CPU1, PMLIB_SYS_CONFIG_ALWAYS_ENABLED},
+ {TISCI_DEV_MCU_ARMSS0_CPU1, PMLIB_SYS_CONFIG_ALWAYS_ENABLED}
};
const uint32_t numTableEntries = sizeof (gInputTable) /