summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 0e61676)
raw | patch | inline | side by side (parent: 0e61676)
author | Frank Livingston <frank-livingston@ti.com> | |
Mon, 20 May 2019 15:23:26 +0000 (10:23 -0500) | ||
committer | Frank Livingston <frank-livingston@ti.com> | |
Mon, 20 May 2019 15:23:26 +0000 (10:23 -0500) |
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
example/apps/icssg_pwm/firmware/src/iepPwm.c | patch | blob | history | |
example/apps/icssg_pwm/firmware/src/iepPwm.h | patch | blob | history |
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.c b/example/apps/icssg_pwm/firmware/src/iepPwm.c
index 233ef65b1cf489212d2fd35883a0b59b57515397..0584ff4d0ed6ce71365ce061fcb753a8e21824cc 100644 (file)
/* Active state Toggle:0000, Trip state HiZ:0000, Initial state L/L:0101 */
#define SNGL_PWM_STATE_INIT \
((PWM_ACT_TOGGLE<<10) | (PWM_ACT_TOGGLE<<8) | (PWM_TRIP_HIZ<<6) | (PWM_TRIP_HIZ<<4) | (PWM_INIT_LO<<2) | (PWM_INIT_LO<<0))
-/* Differential PWM Initial State Configuration register for "sacrificial" PWM */
/* Differential PWM Initial State Configuration register */
/* Active state Toggle:0000, Trip state HiZ:0000, Initial state H/L:1001 */
#define DIFF_PWM_STATE_INIT \
/* DC_old = 100, DC_new = y */
{LATCH_ACTION_Latch_New,
LHS_ACTION_None,
- RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate},
+ RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate},
/* DC_old = 100, DC_new = 0 */
{LATCH_ACTION_Latch_0,
LHS_ACTION_Set_CmpSr_EarlyInPrd_And_EnableSrUpdate,
status = initIepPwmCmpxShReg(pIcssgIepPwmObj);
if (status == IEP_STS_NERR) {
- /* Update State to Right-Hand Side */
+ /* Update State to Left-Hand Side */
pIcssgIepPwmObj->iepPwmState = IEP_SM_STATE_LHS;
}
else {
)
{
Uint32 *pIepPwmDcCountRhs;
+ Uint16 *pIepPwmDbCount;
Uint16 *pIepPwmSnglUpdEn;
Uint8 *pIepPwmDiffUpdEn;
volatile uint32_t **pIepCmpSrAddr;
Uint32 iepPwmPeriodCount;
IepPwmRhsAction *pIepPwmRhsAction;
- Uint32 dcLhsY;
+ Uint32 dcRhsY;
volatile uint32_t *pCmpSr;
Uint8 pwmIdx, dPwmIdx;
/* Get latched IEP PWM DC RHS count array */
pIepPwmDcCountRhs = &pIcssgIepPwmObj->iepPwmDcCountRhs[0];
+ /* Get Deadband count array */
+ pIepPwmDbCount = &pIcssgIepPwmObj->iepPwmDbCount[0];
/* Get Single-Ended & Differential PWM Update Enable */
pIepPwmSnglUpdEn = &pIcssgIepPwmObj->iepPwmSnglUpdEn;
pIepPwmDiffUpdEn = &pIcssgIepPwmObj->iepPwmDiffUpdEn;
pwmIdx = dPwmIdx << 1;
switch(pIepPwmRhsAction[pwmIdx])
{
- case RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate:
- dcLhsY = pIepPwmDcCountRhs[pwmIdx];
+ case RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate:
+ dcRhsY = pIepPwmDcCountRhs[pwmIdx];
pCmpSr = pIepCmpSrAddr[pwmIdx];
- *pCmpSr = dcLhsY; /* Write LHS value to CMP Shadow Register */
+ *pCmpSr = dcRhsY; /* Write RHS value to CMP Shadow Register */
pwmIdx++;
pCmpSr = pIepCmpSrAddr[pwmIdx];
- *pCmpSr = dcLhsY; /* Write LHS value to CMP Shadow Register */
+ *pCmpSr = dcRhsY + pIepPwmDbCount[dPwmIdx]; /* Write RHS value to CMP Shadow Register */
- *pIepPwmDiffUpdEn |= 1<<dPwmIdx; /* Enable CMP SR update */
+ *pIepPwmDiffUpdEn |= 1<<dPwmIdx; /* Enable CMP SR update */
break;
case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate:
- dcLhsY = pIepPwmDcCountRhs[pwmIdx];
+ dcRhsY = pIepPwmDcCountRhs[pwmIdx];
/* Write same LHS value to both CMP Shadow Registers in differential pair */
pCmpSr = pIepCmpSrAddr[pwmIdx];
- *pCmpSr = iepPwmPeriodCount;
+ *pCmpSr = iepPwmPeriodCount; /* Write value greater than Period to Shadow Register */
pwmIdx++;
pCmpSr = pIepCmpSrAddr[pwmIdx];
- *pCmpSr = iepPwmPeriodCount;
+ *pCmpSr = iepPwmPeriodCount; /* Write value greater than Period to Shadow Register */
/* Enable CMP SR update */
- *pIepPwmDiffUpdEn &= ~(1<<dPwmIdx); /* Disable CMP SR update */
+ *pIepPwmDiffUpdEn &= ~(1<<dPwmIdx); /* Disable CMP SR update */
break;
case RHS_ACTION_None:
{
switch (pIepPwmRhsAction[pwmIdx])
{
- case RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate:
- dcLhsY = pIepPwmDcCountRhs[pwmIdx];
+ case RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate:
+ dcRhsY = pIepPwmDcCountRhs[pwmIdx];
pCmpSr = pIepCmpSrAddr[pwmIdx];
- *pCmpSr = dcLhsY; /* Write LHS value to CMP Shadow Register */
+ *pCmpSr = dcRhsY; /* Write RHS value to CMP Shadow Register */
*pIepPwmSnglUpdEn |= 1<<pwmIdx; /* Enable CMP SR update */
break;
case RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate:
pCmpSr = pIepCmpSrAddr[pwmIdx];
- *pCmpSr = iepPwmPeriodCount; /* Write LHS value to CMP Shadow Register */
+ *pCmpSr = iepPwmPeriodCount; /* Write value greater than Period to CMP Shadow Register */
*pIepPwmSnglUpdEn &= ~(1<<pwmIdx); /* Disable CMP SR update */
break;
case RHS_ACTION_None:
diff --git a/example/apps/icssg_pwm/firmware/src/iepPwm.h b/example/apps/icssg_pwm/firmware/src/iepPwm.h
index c10d0b1fe3a6eb500c5364d31e2c2c409bdbb0ff..c52631b00b99e4fff3608e06c201c2c822f24f8b 100644 (file)
RHS_ACTION_None = 0,
/* RHS Action: Set IEP CMP Shadow Register to new value Y &
enable Shadow Register update */
- RHS_ACTION_Set_CmpSr_DcLhsY_And_EnableSrUpdate = 1,
+ RHS_ACTION_Set_CmpSr_DcRhsY_And_EnableSrUpdate = 1,
/* RHS Action: Set IEP CMP Shadow Register > CMP0 Period &
enable Shadow Register update */
RHS_ACTION_Set_CmpSr_GtPrd_And_DisableSrUpdate = 2