1 /dts-v1/;
3 /* Policy assigning all resources to RM instances running on DSP. */
5 / {
6 /* Valid instance list contains instance names used within TI example projects
7 * utilizing RM. The list can be modified as needed by applications integrating
8 * RM. For an RM instance to be given permissions the name used to initialize it
9 * must be present in this list */
10 valid-instances = "RM_Server",
11 "RM_Client0",
12 "RM_Client1",
13 "RM_Client2",
14 "RM_Client3",
15 "RM_Client4",
16 "RM_Client5",
17 "RM_Client6",
18 "RM_Client7";
20 qmss {
21 control-qm1 {
22 assignments = <0 1>, "iu = (*)";
23 };
24 control-qm2 {
25 assignments = <0 1>, "iu = (*)";
26 };
28 linkram-control-qm1 {
29 assignments = <0 1>, "iu = (*)";
30 };
31 linkram-control-qm2 {
32 assignments = <0 1>, "iu = (*)";
33 };
35 linkram-qm1 {
36 /* hw allows max of 512K descriptors */
37 assignments = <0x00000000 0x00080000>, "iu = (*)";
38 };
39 linkram-qm2 {
40 /* hw allows max of 512K descriptors */
41 assignments = <0x00000000 0x00080000>, "iu = (*)";
42 };
44 memory-regions-qm1 {
45 assignments = <0 64>, "iu = (*)";
46 };
47 memory-regions-qm2 {
48 assignments = <0 64>, "iu = (*)";
49 };
51 /* Queues match device specification and/or csl_qm_queue.h regardless of split or joint mode */
52 LOW_PRIORITY_QUEUE-qm1 {
53 assignments = <0 512>, "iu = (*)";
54 };
55 AIF_QUEUE-qm1 {
56 assignments = <512 128>, "iu = (*)";
57 };
58 PASS_QUEUE-qm1 {
59 assignments = <640 9>, "iu = (*)";
60 };
61 INTC_QUEUE-qm1 {
62 assignments = <652 6>, "iu = (*)";
63 };
64 INTC_SET2_QUEUE-qm1 {
65 assignments = <658 8>, "iu = (*)";
66 };
67 INTC_SET3_QUEUE-qm1 {
68 assignments = <666 6>, "iu = (*)";
69 };
70 SRIO_QUEUE-qm1 {
71 assignments = <672 16>, "iu = (*)";
72 };
73 FFTC_A_QUEUE-qm1 {
74 assignments = <688 4>, "iu = (*)";
75 };
76 FFTC_B_QUEUE-qm1 {
77 assignments = <692 4>, "iu = (*)";
78 };
79 HIGH_PRIORITY_QUEUE-qm1 {
80 assignments = <704 32>, "iu = (*)";
81 };
82 STARVATION_COUNTER_QUEUE-qm1 {
83 assignments = <736 64>, "iu = (*)";
84 };
85 INFRASTRUCTURE_QUEUE-qm1 {
86 assignments = <800 32>, "iu = (*)";
87 };
88 TRAFFIC_SHAPING_QUEUE-qm1 {
89 assignments = <832 32>, "iu = (*)";
90 };
91 BCP_QUEUE-qm1 {
92 assignments = <864 8>, "iu = (*)";
93 };
94 FFTC_C_QUEUE-qm1 {
95 assignments = <872 4>, "iu = (*)";
96 };
97 FFTC_D_QUEUE-qm1 {
98 assignments = <876 4>, "iu = (*)";
99 };
100 FFTC_E_QUEUE-qm1 {
101 assignments = <880 4>, "iu = (*)";
102 };
103 FFTC_F_QUEUE-qm1 {
104 assignments = <884 4>, "iu = (*)";
105 };
106 GENERAL_PURPOSE_QUEUE-qm1 {
107 assignments = <896 7296>, "iu = (*)";
108 };
109 LOW_PRIORITY_QUEUE-qm2 {
110 assignments = <8192 512>, "iu = (*)";
111 };
112 INTC_SET4_QUEUE-qm2 {
113 assignments = <8844 20>, "iu = (*)";
114 };
115 GIC400_QUEUE-qm2 {
116 assignments = <8704 32>, "iu = (*)";
117 };
118 EDMA_4_QUEUE-qm2 {
119 assignments = <8736 8>, "iu = (*)";
120 };
121 HLINK_BROADCAST_QUEUE-qm2 {
122 assignments = <8744 8>, "iu = (*)";
123 };
124 XGE_QUEUE-qm2 {
125 assignments = <8752 8>, "iu = (*)";
126 };
127 HLINK_0_QUEUE-qm2 {
128 assignments = <8796 16>, "iu = (*)";
129 };
130 DXB_QUEUE-qm2 {
131 assignments = <8836 8>, "iu = (*)";
132 };
133 HLINK_1_QUEUE-qm2 {
134 assignments = <8864 16>, "iu = (*)";
135 };
136 HIGH_PRIORITY_QUEUE-qm2 {
137 assignments = <8896 32>, "iu = (*)";
138 };
139 STARVATION_COUNTER_QUEUE-qm2 {
140 assignments = <8928 64>, "iu = (*)";
141 };
142 QM2_INFRASTRUCTURE_QUEUE-qm2 {
143 assignments = <8992 32>, "iu = (*)";
144 };
145 GENERAL_PURPOSE_QUEUE-qm2 {
146 assignments = <9024 7360>, "iu = (*)";
147 };
149 firmware-pdsp {
150 assignments = <0 8>, "iu = (*)";
151 };
152 accumulator0-ch { /* accumulator using first INTD */
153 assignments = <0 48>, "iu = (*)";
154 };
155 accumulator1-ch { /* accumulator using second INTD */
156 assignments = <0 48>, "iu = (*)";
157 };
158 }; /* qmss */
160 cppi {
161 srio-rx-ch {
162 assignments = <0 16>, "iu = (*)";
163 };
164 srio-tx-ch {
165 assignments = <0 16>, "iu = (*)";
166 };
167 srio-rx-flow-id {
168 assignments = <0 20>, "iu = (*)";
169 };
171 aif-rx-ch {
172 assignments = <0 129>, "iu = (*)";
173 };
174 aif-tx-ch {
175 assignments = <0 129>, "iu = (*)";
176 };
177 aif-rx-flow-id {
178 assignments = <0 129>, "iu = (*)";
179 };
181 fftc-a-rx-ch {
182 assignments = <0 4>, "iu = (*)";
183 };
184 fftc-a-tx-ch {
185 assignments = <0 4>, "iu = (*)";
186 };
187 fftc-a-rx-flow-id {
188 assignments = <0 8>, "iu = (*)";
189 };
191 fftc-b-rx-ch {
192 assignments = <0 4>, "iu = (*)";
193 };
194 fftc-b-tx-ch {
195 assignments = <0 4>, "iu = (*)";
196 };
197 fftc-b-rx-flow-id {
198 assignments = <0 8>, "iu = (*)";
199 };
201 fftc-c-rx-ch {
202 assignments = <0 4>, "iu = (*)";
203 };
204 fftc-c-tx-ch {
205 assignments = <0 4>, "iu = (*)";
206 };
207 fftc-c-rx-flow-id {
208 assignments = <0 8>, "iu = (*)";
209 };
211 fftc-d-rx-ch {
212 assignments = <0 4>, "iu = (*)";
213 };
214 fftc-d-tx-ch {
215 assignments = <0 4>, "iu = (*)";
216 };
217 fftc-d-rx-flow-id {
218 assignments = <0 8>, "iu = (*)";
219 };
221 fftc-e-rx-ch {
222 assignments = <0 4>, "iu = (*)";
223 };
224 fftc-e-tx-ch {
225 assignments = <0 4>, "iu = (*)";
226 };
227 fftc-e-rx-flow-id {
228 assignments = <0 8>, "iu = (*)";
229 };
231 fftc-f-rx-ch {
232 assignments = <0 4>, "iu = (*)";
233 };
234 fftc-f-tx-ch {
235 assignments = <0 4>, "iu = (*)";
236 };
237 fftc-f-rx-flow-id {
238 assignments = <0 8>, "iu = (*)";
239 };
241 pass-rx-ch {
242 assignments = <0 24>, "iu = (*)";
243 };
244 pass-tx-ch {
245 assignments = <0 9>, "iu = (*)";
246 };
247 pass-rx-flow-id {
248 assignments = <0 32>, "iu = (*)";
249 };
251 qmss-qm1-rx-ch {
252 assignments = <0 32>, "iu = (*)";
253 };
254 qmss-qm1-tx-ch {
255 assignments = <0 32>, "iu = (*)";
256 };
257 qmss-qm1-rx-flow-id {
258 assignments = <0 64>, "iu = (*)";
259 };
261 qmss-qm2-rx-ch {
262 assignments = <0 32>, "iu = (*)";
263 };
264 qmss-qm2-tx-ch {
265 assignments = <0 32>, "iu = (*)";
266 };
267 qmss-qm2-rx-flow-id {
268 assignments = <0 64>, "iu = (*)";
269 };
271 bcp-rx-ch {
272 assignments = <0 8>, "iu = (*)";
273 };
274 bcp-tx-ch {
275 assignments = <0 8>, "iu = (*)";
276 };
277 bcp-rx-flow-id {
278 assignments = <0 64>, "iu = (*)";
279 };
281 xge-rx-ch {
282 assignments = <0 16>, "iu = (*)";
283 };
284 xge-tx-ch {
285 assignments = <0 8>, "iu = (*)";
286 };
287 xge-rx-flow-id {
288 assignments = <0 32>, "iu = (*)";
289 };
290 }; /* cppi */
292 pa {
293 pa-lut {
294 assignments = <0 5>, "iu = (*)";
295 };
296 pa-firmware {
297 assignments = <0 1>, "iu = (*)";
298 };
299 pa-32bUsrStats {
300 assignments = <64 384>, "iu = (*)";
301 };
302 pa-64bUsrStats {
303 assignments = <0 64>, "iu = (*)";
304 };
305 }; /* pa */
307 };