1 /dts-v1/;
3 /* Policy assigning all resources to RM instances running on DSP. */
5 / {
6 /* Valid instance list contains instance names used within TI example projects
7 * utilizing RM. The list can be modified as needed by applications integrating
8 * RM. For an RM instance to be given permissions the name used to initialize it
9 * must be present in this list */
10 valid-instances = "RM_Server",
11 "RM_Client0",
12 "RM_Client1",
13 "RM_Client2",
14 "RM_Client3",
15 "RM_Client4",
16 "RM_Client5",
17 "RM_Client6",
18 "RM_Client7";
20 qmss {
21 control-qm1 {
22 assignments = <0 1>, "iu = (*)";
23 };
24 control-qm2 {
25 assignments = <0 1>, "iu = (*)";
26 };
28 linkram-control-qm1 {
29 assignments = <0 1>, "iu = (*)";
30 };
31 linkram-control-qm2 {
32 assignments = <0 1>, "iu = (*)";
33 };
35 linkram-qm1 {
36 assignments = <0x00000000 0xFFFFFFFF>, "iu = (*)";
37 };
38 linkram-qm2 {
39 assignments = <0x00000000 0xFFFFFFFF>, "iu = (*)";
40 };
42 memory-regions-qm1 {
43 assignments = <0 64>, "iu = (*)";
44 };
45 memory-regions-qm2 {
46 assignments = <0 64>, "iu = (*)";
47 };
49 LOW_PRIORITY_QUEUE-qm1 {
50 assignments = <0 512>, "iu = (*)";
51 };
52 AIF_QUEUE-qm1 {
53 assignments = <512 128>, "iu = (*)";
54 };
55 PASS_QUEUE-qm1 {
56 assignments = <640 9>, "iu = (*)";
57 };
58 INTC_QUEUE-qm1 {
59 assignments = <652 6>, "iu = (*)";
60 };
61 SRIO_QUEUE-qm1 {
62 assignments = <672 16>, "iu = (*)";
63 };
64 FFTC_A_QUEUE-qm1 {
65 assignments = <688 4>, "iu = (*)";
66 };
67 FFTC_B_QUEUE-qm1 {
68 assignments = <692 4>, "iu = (*)";
69 };
70 HIGH_PRIORITY_QUEUE-qm1 {
71 assignments = <704 32>, "iu = (*)";
72 };
73 STARVATION_COUNTER_QUEUE-qm1 {
74 assignments = <736 64>, "iu = (*)";
75 };
76 INFRASTRUCTURE_QUEUE-qm1 {
77 assignments = <800 32>, "iu = (*)";
78 };
79 TRAFFIC_SHAPING_QUEUE-qm1 {
80 assignments = <832 32>, "iu = (*)";
81 };
82 BCP_QUEUE-qm1 {
83 assignments = <864 8>, "iu = (*)";
84 };
85 FFTC_C_QUEUE-qm1 {
86 assignments = <872 4>, "iu = (*)";
87 };
88 FFTC_D_QUEUE-qm1 {
89 assignments = <876 4>, "iu = (*)";
90 };
91 FFTC_E_QUEUE-qm1 {
92 assignments = <880 4>, "iu = (*)";
93 };
94 FFTC_F_QUEUE-qm1 {
95 assignments = <884 4>, "iu = (*)";
96 };
97 GENERAL_PURPOSE_QUEUE-qm1 {
98 assignments = <896 7296>, "iu = (*)";
99 };
100 LOW_PRIORITY_QUEUE-qm2 {
101 assignments = <8192 512>, "iu = (*)";
102 };
103 GIC400_QUEUE-qm2 {
104 assignments = <8704 32>, "iu = (*)";
105 };
106 EDMA_4_QUEUE-qm2 {
107 assignments = <8736 8>, "iu = (*)";
108 };
109 HLINK_BROADCAST_QUEUE-qm2 {
110 assignments = <8744 8>, "iu = (*)";
111 };
112 XGE_QUEUE-qm2 {
113 assignments = <8752 8>, "iu = (*)";
114 };
115 HLINK_0_QUEUE-qm2 {
116 assignments = <8760 16>, "iu = (*)";
117 };
118 DXB_QUEUE-qm2 {
119 assignments = <8836 8>, "iu = (*)";
120 };
121 HLINK_1_QUEUE-qm2 {
122 assignments = <8864 16>, "iu = (*)";
123 };
124 HIGH_PRIORITY_QUEUE-qm2 {
125 assignments = <8896 32>, "iu = (*)";
126 };
127 STARVATION_COUNTER_QUEUE-qm2 {
128 assignments = <8928 64>, "iu = (*)";
129 };
130 QM2_INFRASTRUCTURE_QUEUE-qm2 {
131 assignments = <8992 32>, "iu = (*)";
132 };
133 GENERAL_PURPOSE_QUEUE-qm2 {
134 assignments = <9024 7360>, "iu = (*)";
135 };
137 firmware-pdsp {
138 assignments = <0 8>, "iu = (*)";
139 };
140 accumulator-ch {
141 assignments = <0 48>, "iu = (*)";
142 };
143 }; /* qmss */
145 cppi {
146 srio-rx-ch {
147 assignments = <0 16>, "iu = (*)";
148 };
149 srio-tx-ch {
150 assignments = <0 16>, "iu = (*)";
151 };
152 srio-rx-flow-id {
153 assignments = <0 20>, "iu = (*)";
154 };
156 aif-rx-ch {
157 assignments = <0 129>, "iu = (*)";
158 };
159 aif-tx-ch {
160 assignments = <0 129>, "iu = (*)";
161 };
162 aif-rx-flow-id {
163 assignments = <0 129>, "iu = (*)";
164 };
166 fftc-a-rx-ch {
167 assignments = <0 4>, "iu = (*)";
168 };
169 fftc-a-tx-ch {
170 assignments = <0 4>, "iu = (*)";
171 };
172 fftc-a-rx-flow-id {
173 assignments = <0 8>, "iu = (*)";
174 };
176 fftc-b-rx-ch {
177 assignments = <0 4>, "iu = (*)";
178 };
179 fftc-b-tx-ch {
180 assignments = <0 4>, "iu = (*)";
181 };
182 fftc-b-rx-flow-id {
183 assignments = <0 8>, "iu = (*)";
184 };
186 fftc-c-rx-ch {
187 assignments = <0 4>, "iu = (*)";
188 };
189 fftc-c-tx-ch {
190 assignments = <0 4>, "iu = (*)";
191 };
192 fftc-c-rx-flow-id {
193 assignments = <0 8>, "iu = (*)";
194 };
196 fftc-d-rx-ch {
197 assignments = <0 4>, "iu = (*)";
198 };
199 fftc-d-tx-ch {
200 assignments = <0 4>, "iu = (*)";
201 };
202 fftc-d-rx-flow-id {
203 assignments = <0 8>, "iu = (*)";
204 };
206 fftc-e-rx-ch {
207 assignments = <0 4>, "iu = (*)";
208 };
209 fftc-e-tx-ch {
210 assignments = <0 4>, "iu = (*)";
211 };
212 fftc-e-rx-flow-id {
213 assignments = <0 8>, "iu = (*)";
214 };
216 fftc-f-rx-ch {
217 assignments = <0 4>, "iu = (*)";
218 };
219 fftc-f-tx-ch {
220 assignments = <0 4>, "iu = (*)";
221 };
222 fftc-f-rx-flow-id {
223 assignments = <0 8>, "iu = (*)";
224 };
226 pass-rx-ch {
227 assignments = <0 24>, "iu = (*)";
228 };
229 pass-tx-ch {
230 assignments = <0 9>, "iu = (*)";
231 };
232 pass-rx-flow-id {
233 assignments = <0 32>, "iu = (*)";
234 };
236 qmss-qm1-rx-ch {
237 assignments = <0 32>, "iu = (*)";
238 };
239 qmss-qm1-tx-ch {
240 assignments = <0 32>, "iu = (*)";
241 };
242 qmss-qm1-rx-flow-id {
243 assignments = <0 64>, "iu = (*)";
244 };
246 qmss-qm2-rx-ch {
247 assignments = <0 32>, "iu = (*)";
248 };
249 qmss-qm2-tx-ch {
250 assignments = <0 32>, "iu = (*)";
251 };
252 qmss-qm2-rx-flow-id {
253 assignments = <0 64>, "iu = (*)";
254 };
256 bcp-rx-ch {
257 assignments = <0 8>, "iu = (*)";
258 };
259 bcp-tx-ch {
260 assignments = <0 8>, "iu = (*)";
261 };
262 bcp-rx-flow-id {
263 assignments = <0 64>, "iu = (*)";
264 };
265 }; /* cppi */
267 pa {
268 pa-lut {
269 assignments = <0 5>, "iu = (*)";
270 };
271 pa-firmware {
272 assignments = <0 1>, "iu = (*)";
273 };
274 }; /* pa */
276 };