1 /dts-v1/;
3 /* Policy assigning all resources to RM instances running on DSP. */
5 / {
6 /* Valid instance list contains instance names used within TI example projects
7 * utilizing RM. The list can be modified as needed by applications integrating
8 * RM. For an RM instance to be given permissions the name used to initialize it
9 * must be present in this list */
10 valid-instances = "RM_Server",
11 "RM_Client0",
12 "RM_Client1",
13 "RM_Client2",
14 "RM_Client3",
15 "RM_Client4",
16 "RM_Client5",
17 "RM_Client6",
18 "RM_Client7";
20 qmss {
21 control-qm1 {
22 assignments = <0 1>, "iu = (*)";
23 };
24 control-qm2 {
25 assignments = <0 1>, "iu = (*)";
26 };
28 linkram-control-qm1 {
29 assignments = <0 1>, "iu = (*)";
30 };
31 linkram-control-qm2 {
32 assignments = <0 1>, "iu = (*)";
33 };
35 linkram-int-qm1 {
36 /* hw allows max of 32K "internal" descriptors */
37 assignments = <0x00000000 0x00008000>, "iu = (*)";
38 };
39 linkram-int-qm2 {
40 /* hw allows max of 32K "internal" descriptors */
41 assignments = <0x00000000 0x00008000>, "iu = (*)";
42 };
43 linkram-ext-qm1 {
44 /* hw allows max of 480K "external" descriptors */
45 assignments = <0x00008000 0x00078000>, "iu = (*)";
46 };
47 linkram-ext-qm2 {
48 /* hw allows max of 480K "external" descriptors */
49 assignments = <0x00008000 0x00078000>, "iu = (*)";
50 };
52 memory-regions-qm1 {
53 assignments = <0 64>, "iu = (*)";
54 };
55 memory-regions-qm2 {
56 assignments = <0 64>, "iu = (*)";
57 };
59 /* Queues match device specification and/or csl_qm_queue.h regardless of split or joint mode */
60 LOW_PRIORITY_QUEUE-qm1 {
61 assignments = <0 512>, "iu = (*)";
62 };
63 AIF_QUEUE-qm1 {
64 assignments = <512 128>, "iu = (*)";
65 };
66 PASS_QUEUE-qm1 {
67 assignments = <640 9>, "iu = (*)";
68 };
69 INTC_QUEUE-qm1 {
70 assignments = <652 6>, "iu = (*)";
71 };
72 INTC_SET2_QUEUE-qm1 {
73 assignments = <658 8>, "iu = (*)";
74 };
75 INTC_SET3_QUEUE-qm1 {
76 assignments = <666 6>, "iu = (*)";
77 };
78 SRIO_QUEUE-qm1 {
79 assignments = <672 16>, "iu = (*)";
80 };
81 FFTC_A_QUEUE-qm1 {
82 assignments = <688 4>, "iu = (*)";
83 };
84 FFTC_B_QUEUE-qm1 {
85 assignments = <692 4>, "iu = (*)";
86 };
87 HIGH_PRIORITY_QUEUE-qm1 {
88 assignments = <704 32>, "iu = (*)";
89 };
90 STARVATION_COUNTER_QUEUE-qm1 {
91 assignments = <736 64>, "iu = (*)";
92 };
93 INFRASTRUCTURE_QUEUE-qm1 {
94 assignments = <800 32>, "iu = (*)";
95 };
96 TRAFFIC_SHAPING_QUEUE-qm1 {
97 assignments = <832 32>, "iu = (*)";
98 };
99 BCP_QUEUE-qm1 {
100 assignments = <864 8>, "iu = (*)";
101 };
102 FFTC_C_QUEUE-qm1 {
103 assignments = <872 4>, "iu = (*)";
104 };
105 FFTC_D_QUEUE-qm1 {
106 assignments = <876 4>, "iu = (*)";
107 };
108 FFTC_E_QUEUE-qm1 {
109 assignments = <880 4>, "iu = (*)";
110 };
111 FFTC_F_QUEUE-qm1 {
112 assignments = <884 4>, "iu = (*)";
113 };
114 GENERAL_PURPOSE_QUEUE-qm1 {
115 assignments = <896 3199>, "iu = (*)",
116 <4095 1>, "iue = (*)", /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
117 <4096 4095>, "iu = (*)",
118 <8191 1>, "iue = (*)"; /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
119 };
120 LOW_PRIORITY_QUEUE-qm2 {
121 assignments = <8192 512>, "iu = (*)";
122 };
123 INTC_SET4_QUEUE-qm2 {
124 assignments = <8844 20>, "iu = (*)";
125 };
126 GIC400_QUEUE-qm2 {
127 assignments = <8704 32>, "iu = (*)";
128 };
129 EDMA_4_QUEUE-qm2 {
130 assignments = <8736 8>, "iu = (*)";
131 };
132 HLINK_BROADCAST_QUEUE-qm2 {
133 assignments = <8744 8>, "iu = (*)";
134 };
135 XGE_QUEUE-qm2 {
136 assignments = <8752 8>, "iu = (*)";
137 };
138 HLINK_0_QUEUE-qm2 {
139 assignments = <8796 16>, "iu = (*)";
140 };
141 DXB_QUEUE-qm2 {
142 assignments = <8836 8>, "iu = (*)";
143 };
144 HLINK_1_QUEUE-qm2 {
145 assignments = <8864 16>, "iu = (*)";
146 };
147 HIGH_PRIORITY_QUEUE-qm2 {
148 assignments = <8896 32>, "iu = (*)";
149 };
150 STARVATION_COUNTER_QUEUE-qm2 {
151 assignments = <8928 64>, "iu = (*)";
152 };
153 QM2_INFRASTRUCTURE_QUEUE-qm2 {
154 assignments = <8992 32>, "iu = (*)";
155 };
156 GENERAL_PURPOSE_QUEUE-qm2 {
157 assignments = <9024 3263>, "iu = (*)",
158 <12287 1>, "iue = (*)", /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
159 <12288 4095>, "iu = (*)",
160 <16383 1>, "iue = (*)"; /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
161 };
163 firmware-pdsp {
164 assignments = <0 8>, "iu = (*)";
165 };
166 accumulator0-ch { /* accumulator using first INTD */
167 assignments = <0 48>, "iu = (*)";
168 };
169 accumulator1-ch { /* accumulator using second INTD */
170 assignments = <0 48>, "iu = (*)";
171 };
172 }; /* qmss */
174 cppi {
175 srio-hw-open {
176 assignments = <0 1>, "iu = (*)";
177 };
178 srio-rx-ch {
179 assignments = <0 16>, "iu = (*)";
180 };
181 srio-tx-ch {
182 assignments = <0 16>, "iu = (*)";
183 };
184 srio-rx-flow-id {
185 assignments = <0 20>, "iu = (*)";
186 };
188 aif-hw-open {
189 assignments = <0 1>, "iu = (*)";
190 };
191 aif-rx-ch {
192 assignments = <0 129>, "iu = (*)";
193 };
194 aif-tx-ch {
195 assignments = <0 129>, "iu = (*)";
196 };
197 aif-rx-flow-id {
198 assignments = <0 129>, "iu = (*)";
199 };
201 fftc-a-hw-open {
202 assignments = <0 1>, "iu = (*)";
203 };
204 fftc-a-rx-ch {
205 assignments = <0 4>, "iu = (*)";
206 };
207 fftc-a-tx-ch {
208 assignments = <0 4>, "iu = (*)";
209 };
210 fftc-a-rx-flow-id {
211 assignments = <0 8>, "iu = (*)";
212 };
214 fftc-b-hw-open {
215 assignments = <0 1>, "iu = (*)";
216 };
217 fftc-b-rx-ch {
218 assignments = <0 4>, "iu = (*)";
219 };
220 fftc-b-tx-ch {
221 assignments = <0 4>, "iu = (*)";
222 };
223 fftc-b-rx-flow-id {
224 assignments = <0 8>, "iu = (*)";
225 };
227 fftc-c-hw-open {
228 assignments = <0 1>, "iu = (*)";
229 };
230 fftc-c-rx-ch {
231 assignments = <0 4>, "iu = (*)";
232 };
233 fftc-c-tx-ch {
234 assignments = <0 4>, "iu = (*)";
235 };
236 fftc-c-rx-flow-id {
237 assignments = <0 8>, "iu = (*)";
238 };
240 fftc-d-hw-open {
241 assignments = <0 1>, "iu = (*)";
242 };
243 fftc-d-rx-ch {
244 assignments = <0 4>, "iu = (*)";
245 };
246 fftc-d-tx-ch {
247 assignments = <0 4>, "iu = (*)";
248 };
249 fftc-d-rx-flow-id {
250 assignments = <0 8>, "iu = (*)";
251 };
253 fftc-e-hw-open {
254 assignments = <0 1>, "iu = (*)";
255 };
256 fftc-e-rx-ch {
257 assignments = <0 4>, "iu = (*)";
258 };
259 fftc-e-tx-ch {
260 assignments = <0 4>, "iu = (*)";
261 };
262 fftc-e-rx-flow-id {
263 assignments = <0 8>, "iu = (*)";
264 };
266 fftc-f-hw-open {
267 assignments = <0 1>, "iu = (*)";
268 };
269 fftc-f-rx-ch {
270 assignments = <0 4>, "iu = (*)";
271 };
272 fftc-f-tx-ch {
273 assignments = <0 4>, "iu = (*)";
274 };
275 fftc-f-rx-flow-id {
276 assignments = <0 8>, "iu = (*)";
277 };
279 pass-hw-open {
280 assignments = <0 1>, "iu = (*)";
281 };
282 pass-rx-ch {
283 assignments = <0 24>, "iu = (*)";
284 };
285 pass-tx-ch {
286 assignments = <0 9>, "iu = (*)";
287 };
288 pass-rx-flow-id {
289 assignments = <0 32>, "iu = (*)";
290 };
292 qmss-qm1-hw-open {
293 assignments = <0 1>, "iu = (*)";
294 };
295 qmss-qm1-rx-ch {
296 assignments = <0 32>, "iu = (*)";
297 };
298 qmss-qm1-tx-ch {
299 assignments = <0 32>, "iu = (*)";
300 };
301 qmss-qm1-rx-flow-id {
302 assignments = <0 64>, "iu = (*)";
303 };
305 qmss-qm2-hw-open {
306 assignments = <0 1>, "iu = (*)";
307 };
308 qmss-qm2-rx-ch {
309 assignments = <0 32>, "iu = (*)";
310 };
311 qmss-qm2-tx-ch {
312 assignments = <0 32>, "iu = (*)";
313 };
314 qmss-qm2-rx-flow-id {
315 assignments = <0 64>, "iu = (*)";
316 };
318 bcp-hw-open {
319 assignments = <0 1>, "iu = (*)";
320 };
321 bcp-rx-ch {
322 assignments = <0 8>, "iu = (*)";
323 };
324 bcp-tx-ch {
325 assignments = <0 8>, "iu = (*)";
326 };
327 bcp-rx-flow-id {
328 assignments = <0 64>, "iu = (*)";
329 };
331 xge-hw-open {
332 assignments = <0 1>, "iu = (*)";
333 };
334 xge-rx-ch {
335 assignments = <0 16>, "iu = (*)";
336 };
337 xge-tx-ch {
338 assignments = <0 8>, "iu = (*)";
339 };
340 xge-rx-flow-id {
341 assignments = <0 32>, "iu = (*)";
342 };
343 }; /* cppi */
345 pa {
346 pa-lut {
347 assignments = <0 5>, "iu = (*)";
348 };
349 pa-firmware {
350 assignments = <0 1>, "iu = (*)";
351 };
352 pa-32bUsrStats {
353 assignments = <0 512>, "iu = (*)";
354 };
355 pa-64bUsrStats {
356 assignments = <0 256>, "iu = (*)";
357 };
358 }; /* pa */
360 srio {
361 srio-dio-sockets {
362 assignments = <0 8>, "iu = (*)";
363 };
364 srio-type9-type11-sockets {
365 assignments = <0 64>, "iu = (*)";
366 };
367 srio-type9-type11-mappings {
368 assignments = <0 64>, "iu = (*)";
369 };
370 srio-lsus {
371 assignments = <0 8>, "iu = (*)";
372 };
373 srio-init-hw {
374 assignments = <0 1>, "iu = (*)";
375 };
376 };
377 };