8a17e8360762674032b58ab1012b576146ca9fb9
1 /dts-v1/;
3 /* Policy assigning all resources to RM instances running on DSP. */
5 / {
6 /* Valid instance list contains instance names used within TI example projects
7 * utilizing RM. The list can be modified as needed by applications integrating
8 * RM. For an RM instance to be given permissions the name used to initialize it
9 * must be present in this list */
10 valid-instances = "RM_Server",
11 "RM_Client0",
12 "RM_Client1",
13 "RM_Client2",
14 "RM_Client3",
15 "RM_Client4",
16 "RM_Client5",
17 "RM_Client6",
18 "RM_Client7";
20 qmss {
21 control-qm1 {
22 assignments = <0 1>, "iu = (*)";
23 };
24 control-qm2 {
25 assignments = <0 1>, "iu = (*)";
26 };
28 linkram-control-qm1 {
29 assignments = <0 1>, "iu = (*)";
30 };
31 linkram-control-qm2 {
32 assignments = <0 1>, "iu = (*)";
33 };
35 linkram-int-qm1 {
36 /* hw allows max of 32K "internal" descriptors */
37 assignments = <0x00000000 0x00008000>, "iu = (*)";
38 };
39 linkram-int-qm2 {
40 /* hw allows max of 32K "internal" descriptors */
41 assignments = <0x00000000 0x00008000>, "iu = (*)";
42 };
43 linkram-ext-qm1 {
44 /* hw allows max of 480K "external" descriptors */
45 assignments = <0x00008000 0x00078000>, "iu = (*)";
46 };
47 linkram-ext-qm2 {
48 /* hw allows max of 480K "external" descriptors */
49 assignments = <0x00008000 0x00078000>, "iu = (*)";
50 };
52 memory-regions-qm1 {
53 assignments = <0 64>, "iu = (*)";
54 };
55 memory-regions-qm2 {
56 assignments = <0 64>, "iu = (*)";
57 };
59 /* Queues match device specification and/or csl_qm_queue.h regardless of split or joint mode */
60 LOW_PRIORITY_QUEUE-qm1 {
61 assignments = <0 512>, "iu = (*)";
62 };
63 AIF_QUEUE-qm1 {
64 assignments = <512 128>, "iu = (*)";
65 };
66 PASS_QUEUE-qm1 {
67 assignments = <640 9>, "iu = (*)";
68 };
69 INTC_QUEUE-qm1 {
70 assignments = <652 6>, "iu = (*)";
71 };
72 INTC_SET2_QUEUE-qm1 {
73 assignments = <658 8>, "iu = (*)";
74 };
75 INTC_SET3_QUEUE-qm1 {
76 assignments = <666 6>, "iu = (*)";
77 };
78 SRIO_QUEUE-qm1 {
79 assignments = <672 16>, "iu = (*)";
80 };
81 FFTC_A_QUEUE-qm1 {
82 assignments = <688 4>, "iu = (*)";
83 };
84 FFTC_B_QUEUE-qm1 {
85 assignments = <692 4>, "iu = (*)";
86 };
87 HIGH_PRIORITY_QUEUE-qm1 {
88 assignments = <704 32>, "iu = (*)";
89 };
90 STARVATION_COUNTER_QUEUE-qm1 {
91 assignments = <736 64>, "iu = (*)";
92 };
93 INFRASTRUCTURE_QUEUE-qm1 {
94 assignments = <800 32>, "iu = (*)";
95 };
96 TRAFFIC_SHAPING_QUEUE-qm1 {
97 assignments = <832 32>, "iu = (*)";
98 };
99 BCP_QUEUE-qm1 {
100 assignments = <864 8>, "iu = (*)";
101 };
102 FFTC_C_QUEUE-qm1 {
103 assignments = <872 4>, "iu = (*)";
104 };
105 FFTC_D_QUEUE-qm1 {
106 assignments = <876 4>, "iu = (*)";
107 };
108 FFTC_E_QUEUE-qm1 {
109 assignments = <880 4>, "iu = (*)";
110 };
111 FFTC_F_QUEUE-qm1 {
112 assignments = <884 4>, "iu = (*)";
113 };
114 GENERAL_PURPOSE_QUEUE-qm1 {
115 assignments = <896 7296>, "iu = (*)";
116 };
117 LOW_PRIORITY_QUEUE-qm2 {
118 assignments = <8192 512>, "iu = (*)";
119 };
120 INTC_SET4_QUEUE-qm2 {
121 assignments = <8844 20>, "iu = (*)";
122 };
123 GIC400_QUEUE-qm2 {
124 assignments = <8704 32>, "iu = (*)";
125 };
126 EDMA_4_QUEUE-qm2 {
127 assignments = <8736 8>, "iu = (*)";
128 };
129 HLINK_BROADCAST_QUEUE-qm2 {
130 assignments = <8744 8>, "iu = (*)";
131 };
132 XGE_QUEUE-qm2 {
133 assignments = <8752 8>, "iu = (*)";
134 };
135 HLINK_0_QUEUE-qm2 {
136 assignments = <8796 16>, "iu = (*)";
137 };
138 DXB_QUEUE-qm2 {
139 assignments = <8836 8>, "iu = (*)";
140 };
141 HLINK_1_QUEUE-qm2 {
142 assignments = <8864 16>, "iu = (*)";
143 };
144 HIGH_PRIORITY_QUEUE-qm2 {
145 assignments = <8896 32>, "iu = (*)";
146 };
147 STARVATION_COUNTER_QUEUE-qm2 {
148 assignments = <8928 64>, "iu = (*)";
149 };
150 QM2_INFRASTRUCTURE_QUEUE-qm2 {
151 assignments = <8992 32>, "iu = (*)";
152 };
153 GENERAL_PURPOSE_QUEUE-qm2 {
154 assignments = <9024 7360>, "iu = (*)";
155 };
157 firmware-pdsp {
158 assignments = <0 8>, "iu = (*)";
159 };
160 accumulator0-ch { /* accumulator using first INTD */
161 assignments = <0 48>, "iu = (*)";
162 };
163 accumulator1-ch { /* accumulator using second INTD */
164 assignments = <0 48>, "iu = (*)";
165 };
166 }; /* qmss */
168 cppi {
169 srio-rx-ch {
170 assignments = <0 16>, "iu = (*)";
171 };
172 srio-tx-ch {
173 assignments = <0 16>, "iu = (*)";
174 };
175 srio-rx-flow-id {
176 assignments = <0 20>, "iu = (*)";
177 };
179 aif-rx-ch {
180 assignments = <0 129>, "iu = (*)";
181 };
182 aif-tx-ch {
183 assignments = <0 129>, "iu = (*)";
184 };
185 aif-rx-flow-id {
186 assignments = <0 129>, "iu = (*)";
187 };
189 fftc-a-rx-ch {
190 assignments = <0 4>, "iu = (*)";
191 };
192 fftc-a-tx-ch {
193 assignments = <0 4>, "iu = (*)";
194 };
195 fftc-a-rx-flow-id {
196 assignments = <0 8>, "iu = (*)";
197 };
199 fftc-b-rx-ch {
200 assignments = <0 4>, "iu = (*)";
201 };
202 fftc-b-tx-ch {
203 assignments = <0 4>, "iu = (*)";
204 };
205 fftc-b-rx-flow-id {
206 assignments = <0 8>, "iu = (*)";
207 };
209 fftc-c-rx-ch {
210 assignments = <0 4>, "iu = (*)";
211 };
212 fftc-c-tx-ch {
213 assignments = <0 4>, "iu = (*)";
214 };
215 fftc-c-rx-flow-id {
216 assignments = <0 8>, "iu = (*)";
217 };
219 fftc-d-rx-ch {
220 assignments = <0 4>, "iu = (*)";
221 };
222 fftc-d-tx-ch {
223 assignments = <0 4>, "iu = (*)";
224 };
225 fftc-d-rx-flow-id {
226 assignments = <0 8>, "iu = (*)";
227 };
229 fftc-e-rx-ch {
230 assignments = <0 4>, "iu = (*)";
231 };
232 fftc-e-tx-ch {
233 assignments = <0 4>, "iu = (*)";
234 };
235 fftc-e-rx-flow-id {
236 assignments = <0 8>, "iu = (*)";
237 };
239 fftc-f-rx-ch {
240 assignments = <0 4>, "iu = (*)";
241 };
242 fftc-f-tx-ch {
243 assignments = <0 4>, "iu = (*)";
244 };
245 fftc-f-rx-flow-id {
246 assignments = <0 8>, "iu = (*)";
247 };
249 pass-rx-ch {
250 assignments = <0 24>, "iu = (*)";
251 };
252 pass-tx-ch {
253 assignments = <0 9>, "iu = (*)";
254 };
255 pass-rx-flow-id {
256 assignments = <0 32>, "iu = (*)";
257 };
259 qmss-qm1-rx-ch {
260 assignments = <0 32>, "iu = (*)";
261 };
262 qmss-qm1-tx-ch {
263 assignments = <0 32>, "iu = (*)";
264 };
265 qmss-qm1-rx-flow-id {
266 assignments = <0 64>, "iu = (*)";
267 };
269 qmss-qm2-rx-ch {
270 assignments = <0 32>, "iu = (*)";
271 };
272 qmss-qm2-tx-ch {
273 assignments = <0 32>, "iu = (*)";
274 };
275 qmss-qm2-rx-flow-id {
276 assignments = <0 64>, "iu = (*)";
277 };
279 bcp-rx-ch {
280 assignments = <0 8>, "iu = (*)";
281 };
282 bcp-tx-ch {
283 assignments = <0 8>, "iu = (*)";
284 };
285 bcp-rx-flow-id {
286 assignments = <0 64>, "iu = (*)";
287 };
289 xge-rx-ch {
290 assignments = <0 16>, "iu = (*)";
291 };
292 xge-tx-ch {
293 assignments = <0 8>, "iu = (*)";
294 };
295 xge-rx-flow-id {
296 assignments = <0 32>, "iu = (*)";
297 };
298 }; /* cppi */
300 pa {
301 pa-lut {
302 assignments = <0 5>, "iu = (*)";
303 };
304 pa-firmware {
305 assignments = <0 1>, "iu = (*)";
306 };
307 pa-32bUsrStats {
308 assignments = <0 512>, "iu = (*)";
309 };
310 pa-64bUsrStats {
311 assignments = <0 256>, "iu = (*)";
312 };
313 }; /* pa */
315 srio {
316 srio-dio-sockets {
317 assignments = <0 8>, "iu = (*)";
318 };
319 srio-type9-type11-sockets {
320 assignments = <0 64>, "iu = (*)";
321 };
322 srio-type9-type11-mappings {
323 assignments = <0 64>, "iu = (*)";
324 };
325 srio-lsus {
326 assignments = <0 8>, "iu = (*)";
327 };
328 srio-init-hw {
329 assignments = <0 1>, "iu = (*)";
330 };
331 };
332 };