assignments = <0 1>, "iu = (*)";
};
- linkram-qm1 {
- /* hw allows max of 512K descriptors */
- assignments = <0x00000000 0x00080000>, "iu = (*)";
+ linkram-int-qm1 {
+ /* hw allows max of 32K "internal" descriptors */
+ assignments = <0x00000000 0x00008000>, "iu = (*)";
};
- linkram-qm2 {
- /* hw allows max of 512K descriptors */
- assignments = <0x00000000 0x00080000>, "iu = (*)";
+ linkram-int-qm2 {
+ /* hw allows max of 32K "internal" descriptors */
+ assignments = <0x00000000 0x00008000>, "iu = (*)";
+ };
+ linkram-ext-qm1 {
+ /* hw allows max of 480K "external" descriptors */
+ assignments = <0x00008000 0x00078000>, "iu = (*)";
+ };
+ linkram-ext-qm2 {
+ /* hw allows max of 480K "external" descriptors */
+ assignments = <0x00008000 0x00078000>, "iu = (*)";
};
memory-regions-qm1 {
assignments = <884 4>, "iu = (*)";
};
GENERAL_PURPOSE_QUEUE-qm1 {
- assignments = <896 7296>, "iu = (*)";
+ assignments = <896 3199>, "iu = (*)",
+ <4095 1>, "iue = (*)", /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
+ <4096 4095>, "iu = (*)",
+ <8191 1>, "iue = (*)"; /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
};
LOW_PRIORITY_QUEUE-qm2 {
assignments = <8192 512>, "iu = (*)";
assignments = <8992 32>, "iu = (*)";
};
GENERAL_PURPOSE_QUEUE-qm2 {
- assignments = <9024 7360>, "iu = (*)";
- };
+ assignments = <9024 3263>, "iu = (*)",
+ <12287 1>, "iue = (*)", /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
+ <12288 4095>, "iu = (*)",
+ <16383 1>, "iue = (*)"; /* Queues ending in 0xfff can't be used as return queue (hw reserved) */
+ };
firmware-pdsp {
assignments = <0 8>, "iu = (*)";
}; /* qmss */
cppi {
+ srio-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
srio-rx-ch {
assignments = <0 16>, "iu = (*)";
};
assignments = <0 20>, "iu = (*)";
};
+ aif-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
aif-rx-ch {
assignments = <0 129>, "iu = (*)";
};
assignments = <0 129>, "iu = (*)";
};
+ fftc-a-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
fftc-a-rx-ch {
assignments = <0 4>, "iu = (*)";
};
assignments = <0 8>, "iu = (*)";
};
+ fftc-b-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
fftc-b-rx-ch {
assignments = <0 4>, "iu = (*)";
};
assignments = <0 8>, "iu = (*)";
};
+ fftc-c-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
fftc-c-rx-ch {
assignments = <0 4>, "iu = (*)";
};
assignments = <0 8>, "iu = (*)";
};
+ fftc-d-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
fftc-d-rx-ch {
assignments = <0 4>, "iu = (*)";
};
assignments = <0 8>, "iu = (*)";
};
+ fftc-e-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
fftc-e-rx-ch {
assignments = <0 4>, "iu = (*)";
};
assignments = <0 8>, "iu = (*)";
};
+ fftc-f-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
fftc-f-rx-ch {
assignments = <0 4>, "iu = (*)";
};
assignments = <0 8>, "iu = (*)";
};
+ pass-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
pass-rx-ch {
assignments = <0 24>, "iu = (*)";
};
assignments = <0 32>, "iu = (*)";
};
+ qmss-qm1-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
qmss-qm1-rx-ch {
assignments = <0 32>, "iu = (*)";
};
assignments = <0 64>, "iu = (*)";
};
+ qmss-qm2-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
qmss-qm2-rx-ch {
assignments = <0 32>, "iu = (*)";
};
assignments = <0 64>, "iu = (*)";
};
+ bcp-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
bcp-rx-ch {
assignments = <0 8>, "iu = (*)";
};
assignments = <0 64>, "iu = (*)";
};
+ xge-hw-open {
+ assignments = <0 1>, "iu = (*)";
+ };
xge-rx-ch {
assignments = <0 16>, "iu = (*)";
};
pa-firmware {
assignments = <0 1>, "iu = (*)";
};
+ pa-32bUsrStats {
+ assignments = <0 512>, "iu = (*)";
+ };
+ pa-64bUsrStats {
+ assignments = <0 256>, "iu = (*)";
+ };
}; /* pa */
-
+
+ srio {
+ srio-dio-sockets {
+ assignments = <0 8>, "iu = (*)";
+ };
+ srio-type9-type11-sockets {
+ assignments = <0 64>, "iu = (*)";
+ };
+ srio-type9-type11-mappings {
+ assignments = <0 64>, "iu = (*)";
+ };
+ srio-lsus {
+ assignments = <0 8>, "iu = (*)";
+ };
+ srio-init-hw {
+ assignments = <0 1>, "iu = (*)";
+ };
+ };
};