summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 79c8e84)
raw | patch | inline | side by side (parent: 79c8e84)
| author | Aravind Batni <aravindbr@ti.com> | |
| Fri, 16 Oct 2015 18:37:56 +0000 (14:37 -0400) | ||
| committer | Aravind Batni <aravindbr@ti.com> | |
| Fri, 16 Oct 2015 18:37:56 +0000 (14:37 -0400) |
22 files changed:
diff --git a/test/c6657/c66/bios/dsp_client.cfg b/test/c6657/c66/bios/dsp_client.cfg
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012-2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x20000;
+BIOS.libType = BIOS.LibType_Custom;
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.deleteTerminatedTasks = true;
+
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+Idle.addFunc('&VirtQueue_cacheWb');
+
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+System.SupportProxy = SysMin;
+
+var Diags = xdc.useModule('xdc.runtime.Diags');
+
+xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+
+print ("Program.cpu.deviceName = " + Program.cpu.deviceName);
+print ("Program.platformName = " + Program.platformName);
+
+var VirtQueue = xdc.useModule('ti.ipc.family.tci6638.VirtQueue');
+var Interrupt = xdc.useModule('ti.ipc.family.tci6638.Interrupt');
+
+/* Note: MultiProc_self is set during VirtQueue_init based on DNUM. */
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* K2H - TMS320TCI6636 */
+MultiProc.setConfig(null, ["HOST", "CORE0", "CORE1", "CORE2", "CORE3",
+ "CORE4", "CORE5", "CORE6", "CORE7"]);
+Program.sectMap[".text:_c_int00"] = new Program.SectionSpec();
+Program.sectMap[".text:_c_int00"].loadSegment = "L2SRAM";
+Program.sectMap[".text:_c_int00"].loadAlign = 0x400;
+
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+Hwi.enableException = true;
+
+/* This makes the vrings address range 0xa0000000 to 0xa1ffffff uncachable.
+ We assume the rest is to be left cacheable.
+ Per sprugw0b.pdf
+ 0184 8280h MAR160 Memory Attribute Register 160 A000 0000h - A0FF FFFFh
+ 0184 8284h MAR161 Memory Attribute Register 161 A100 0000h - A1FF FFFFh
+*/
+var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
+/* Mark external memory used by kernel as uncached so that IPC vring CMA
+ * region can operate properly when exchanging messages between DSP and ARM.
+ * Marking entire DDR3 as uncached since the memory used by kernel can
+ * change between device revisions. Need to find better way of doing this. */
+Cache.setMarMeta(0x80000000, 0x7FFFFFFF, 0xC);
+
+Program.global.sysMinBufSize = 0x8000;
+SysMin.bufSize = Program.global.sysMinBufSize;
+
+/* Enable Memory Translation module that operates on the Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+/* Make sure RemoteProc's .resource_table doesn't conflict with secure kernel when
+ * on secure board. Secure kernel is located from 0x00800000 - 0x00810000 */
+Resource.loadAddr = 0x00810000;
+
+/* COMMENT OUT TO SHUT OFF LOG FOR BENCHMARKS: */
+/*
+Diags.setMaskMeta("ti.ipc.family.tci6638.Interrupt", Diags.USER1,
+ Diags.ALWAYS_ON);
+Diags.setMaskMeta("ti.ipc.family.tci6638.VirtQueue", Diags.USER1,
+ Diags.ALWAYS_ON);
+Diags.setMaskMeta("ti.ipc.transports.TransportRpmsg",
+ Diags.INFO|Diags.USER1|Diags.STATUS,
+ Diags.ALWAYS_ON);
+Diags.setMaskMeta("ti.ipc.namesrv.NameServerRemoteRpmsg", Diags.INFO,
+ Diags.ALWAYS_ON);
+*/
+
+Hwi.enableException = true;
+
+xdc.loadPackage('ti.ipc.ipcmgr');
+BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
+
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var params = new HeapBuf.Params;
+params.align = 8;
+params.blockSize = 512;
+params.numBlocks = 256;
+var msgHeap = HeapBuf.create(params);
+
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.registerHeapMeta(msgHeap, 0);
+
+var Assert = xdc.useModule('xdc.runtime.Assert');
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Text = xdc.useModule('xdc.runtime.Text');
+Text.isLoaded = true;
+
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+VirtioSetup.common$.diags_INFO = Diags.RUNTIME_OFF;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+
+xdc.loadPackage('ti.ipc.transports').profile = 'release';
+
+/* PDK packages */
+var devType = "c6657"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+MessageQ.SetupTransportProxy = VirtioSetup;
+
+var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
+var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+NameServer.SetupProxy = NsRemote;
+
+var TransportRpmsg = xdc.useModule('ti.ipc.transports.TransportRpmsg');
+
diff --git a/test/c6657/c66/bios/rmMem_evmc6657_C66BiosTestProject.txt b/test/c6657/c66/bios/rmMem_evmc6657_C66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,13 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_mem_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/c6657/global-resource-list.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/c6657/policy_dsp-only.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/static-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/linux-evm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_transport_setup.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_mem_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6657 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6657/c66/bios/rmShared_evmc6657_C66BiosTestProject.txt b/test/c6657/c66/bios/rmShared_evmc6657_C66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,9 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_shared_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/linux-evm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_shared_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_shared_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6657 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6657/c66/bios/rm_evmc6657_C66BiosTestProject.txt b/test/c6657/c66/bios/rm_evmc6657_C66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,10 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/linux-evm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/static-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6657 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6657/c66/bios/rm_evmc6657_C66DspMtBiosTestProject.txt b/test/c6657/c66/bios/rm_evmc6657_C66DspMtBiosTestProject.txt
--- /dev/null
@@ -0,0 +1,8 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_dsp_mt_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6657/c66/bios/rm_test_sc.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6657 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6657/c66/bios/rm_mem_test.cfg b/test/c6657/c66/bios/rm_mem_test.cfg
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0", "CORE1"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x80000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+/* Okay for these to be in L2 since it's only read once at startup */
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+Program.sectMap[".sharedPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedPolicy"] = "L2SRAM";
+
+Program.sectMap[".rm"] = new Program.SectionSpec();
+Program.sectMap[".rm"] = "MSMCSRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* Shared Memory base address and length */
+var SHAREDMEM = 0x0C000000;
+var SHAREDMEMSIZE = 0x00100000;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: SHAREDMEM,
+ len: SHAREDMEMSIZE,
+ ownerProcId: 0,
+ isValid: true,
+ name: "DDR2 RAM",
+ });
+
+/* PDK packages */
+var devType = "c6657"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6657/c66/bios/rm_osal.c b/test/c6657/c66/bios/rm_osal.c
--- /dev/null
@@ -0,0 +1,274 @@
+/**
+ * @file rm_osal.c
+ *
+ * @brief
+ * This is the OS abstraction layer used by the Resource Manager.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012-2015, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* Standard Includes */
+#include <stdarg.h>
+
+/* XDC Includes */
+#include <xdc/std.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+/* BIOS Includes */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+/* CSL includes */
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_xmcAux.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+uint32_t rmMallocCounter = 0;
+uint32_t rmFreeCounter = 0;
+
+int32_t rmByteAlloc = 0;
+int32_t rmByteFree = 0;
+
+/**********************************************************************
+ *************************** OSAL Functions **************************
+ **********************************************************************/
+
+/* FUNCTION PURPOSE: Allocates memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to allocate a memory block of the
+ * specified size.
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ rmMallocCounter++;
+ rmByteAlloc += num_bytes;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/* FUNCTION PURPOSE: Frees memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to free a memory block of the
+ * specified size.
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ /* Increment the free counter. */
+ rmFreeCounter++;
+ rmByteFree += size;
+ Memory_free(NULL, ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a multi-threaded critical
+ * section. Function protects against
+ *
+ * access from multiple threads on single core
+ */
+void *Osal_rmMtCsEnter(void *mtSemObj)
+{
+ Semaphore_pend((Semaphore_Handle)mtSemObj, BIOS_WAIT_FOREVER);
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a multi-threaded critical
+ * section protected using Osal_rmMtCsEnter() API.
+ */
+void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
+{
+ Semaphore_post((Semaphore_Handle)mtSemObj);
+}
+
+/* FUNCTION PURPOSE: Cache invalidate
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Cache writeback
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Creates a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/* FUNCTION PURPOSE: Blocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to block a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/* FUNCTION PURPOSE: unBlocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to unblock a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/* FUNCTION PURPOSE: Deletes a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to delete a task blocking object
+ * provided to a RM instance
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/* FUNCTION PURPOSE: Prints a variable list
+ ***********************************************************************
+ * DESCRIPTION: The function is used to print a string to the console
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
diff --git a/test/c6657/c66/bios/rm_shared_osal.c b/test/c6657/c66/bios/rm_shared_osal.c
--- /dev/null
@@ -0,0 +1,298 @@
+/**
+ * @file rm_osal.c
+ *
+ * @brief
+ * This is the OS abstraction layer used by the Resource Manager.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012-2013, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* Standard Includes */
+#include <stdarg.h>
+
+/* XDC Includes */
+#include <xdc/std.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+/* BIOS Includes */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+/* IPC includes */
+#include <ti/ipc/SharedRegion.h>
+
+/* CSL includes */
+#include <ti/csl/csl_semAux.h>
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_xmcAux.h>
+
+/* RM Includes */
+#include <ti/drv/rm/rm_osal.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+/* Try to avoid conflict with GateMP in rm_shared_test.c */
+#define RM_HW_SEM 4
+#define RM_MALLOC_FREE_SEM 5
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+/* Put memory tracking variables in MSMCSRAM to track all allocations
+ * using the Shared Server. Define the variables so they don't cross
+ * any cache line boundaries. */
+#pragma DATA_SECTION (rmMallocCounter, ".rmSharedHandleTest");
+#pragma DATA_ALIGN (rmMallocCounter, 128)
+uint32_t rmMallocCounter[4] = {0,0,0,0};
+#pragma DATA_SECTION (rmFreeCounter, ".rmSharedHandleTest");
+#pragma DATA_ALIGN (rmFreeCounter, 128)
+uint32_t rmFreeCounter[4] = {0,0,0,0};
+
+/**********************************************************************
+ *************************** OSAL Functions **************************
+ **********************************************************************/
+
+/* FUNCTION PURPOSE: Allocates memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to allocate a memory block of the
+ * specified size.
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ while ((CSL_semAcquireDirect (RM_MALLOC_FREE_SEM)) == 0);
+ Osal_rmBeginMemAccess(rmMallocCounter, sizeof(rmMallocCounter));
+ /* Increment the allocation counter. */
+ rmMallocCounter[0]++;
+ Osal_rmEndMemAccess(rmMallocCounter, sizeof(rmMallocCounter));
+ CSL_semReleaseSemaphore (RM_MALLOC_FREE_SEM);
+
+ /* Allocate memory. */
+ return Memory_alloc(SharedRegion_getHeap(0), num_bytes, 0, &errorBlock);
+}
+
+/* FUNCTION PURPOSE: Frees memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to free a memory block of the
+ * specified size.
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ while ((CSL_semAcquireDirect (RM_MALLOC_FREE_SEM)) == 0);
+ /* Increment the free counter. */
+ Osal_rmBeginMemAccess(rmFreeCounter, sizeof(rmFreeCounter));
+ rmFreeCounter[0]++;
+ Osal_rmEndMemAccess(rmFreeCounter, sizeof(rmFreeCounter));
+ CSL_semReleaseSemaphore (RM_MALLOC_FREE_SEM);
+
+ /* Free memory */
+ Memory_free(SharedRegion_getHeap(0), ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+ /* Get the hardware semaphore for protection against multiple core access */
+ while ((CSL_semAcquireDirect (RM_HW_SEM)) == 0);
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+ /* Release the hardware semaphore */
+ CSL_semReleaseSemaphore (RM_HW_SEM);
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a multi-threaded critical
+ * section. Function protects against
+ *
+ * access from multiple threads on single core
+ */
+void *Osal_rmMtCsEnter(void *mtSemObj)
+{
+
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a multi-threaded critical
+ * section protected using Osal_rmMtCsEnter() API.
+ */
+void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Cache invalidate
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+/* FUNCTION PURPOSE: Cache writeback
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+/* FUNCTION PURPOSE: Creates a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/* FUNCTION PURPOSE: Blocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to block a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/* FUNCTION PURPOSE: unBlocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to unblock a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/* FUNCTION PURPOSE: Deletes a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to delete a task blocking object
+ * provided to a RM instance
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/* FUNCTION PURPOSE: Prints a variable list
+ ***********************************************************************
+ * DESCRIPTION: The function is used to print a string to the console
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
diff --git a/test/c6657/c66/bios/rm_shared_test.cfg b/test/c6657/c66/bios/rm_shared_test.cfg
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0", "CORE1"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x10000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+Program.sectMap[".rmSharedHandleTest"] = new Program.SectionSpec();
+Program.sectMap[".rmSharedHandleTest"] = "MSMCSRAM";
+
+/* Read once when RM_SHARED_SERVER is initialized */
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: 0x0C000000,
+ len: 0x00100000,
+ ownerProcId: 0,
+ isValid: true,
+ name: "sharemem",
+ });
+
+/* PDK packages */
+var devType = "c6657"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6657/c66/bios/rm_test.cfg b/test/c6657/c66/bios/rm_test.cfg
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0", "CORE1"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x10000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* Shared Memory base address and length */
+var SHAREDMEM = 0x0C000000;
+var SHAREDMEMSIZE = 0x00100000;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: SHAREDMEM,
+ len: SHAREDMEMSIZE,
+ ownerProcId: 0,
+ isValid: true,
+ name: "DDR2 RAM",
+ });
+
+/* PDK packages */
+var devType = "c6657"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6657/c66/bios/rm_test_sc.cfg b/test/c6657/c66/bios/rm_test_sc.cfg
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x10000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* Shared Memory base address and length */
+var SHAREDMEM = 0x0C000000;
+var SHAREDMEMSIZE = 0x00100000;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: SHAREDMEM,
+ len: SHAREDMEMSIZE,
+ ownerProcId: 0,
+ isValid: true,
+ name: "DDR2 RAM",
+ });
+
+/* PDK packages */
+var devType = "c6657"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6678/c66/bios/dsp_client.cfg b/test/c6678/c66/bios/dsp_client.cfg
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012-2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x20000;
+BIOS.libType = BIOS.LibType_Custom;
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.deleteTerminatedTasks = true;
+
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+Idle.addFunc('&VirtQueue_cacheWb');
+
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+System.SupportProxy = SysMin;
+
+var Diags = xdc.useModule('xdc.runtime.Diags');
+
+xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+
+print ("Program.cpu.deviceName = " + Program.cpu.deviceName);
+print ("Program.platformName = " + Program.platformName);
+
+var VirtQueue = xdc.useModule('ti.ipc.family.tci6638.VirtQueue');
+var Interrupt = xdc.useModule('ti.ipc.family.tci6638.Interrupt');
+
+/* Note: MultiProc_self is set during VirtQueue_init based on DNUM. */
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* K2H - TMS320TCI6636 */
+MultiProc.setConfig(null, ["HOST", "CORE0", "CORE1", "CORE2", "CORE3",
+ "CORE4", "CORE5", "CORE6", "CORE7"]);
+Program.sectMap[".text:_c_int00"] = new Program.SectionSpec();
+Program.sectMap[".text:_c_int00"].loadSegment = "L2SRAM";
+Program.sectMap[".text:_c_int00"].loadAlign = 0x400;
+
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+Hwi.enableException = true;
+
+/* This makes the vrings address range 0xa0000000 to 0xa1ffffff uncachable.
+ We assume the rest is to be left cacheable.
+ Per sprugw0b.pdf
+ 0184 8280h MAR160 Memory Attribute Register 160 A000 0000h - A0FF FFFFh
+ 0184 8284h MAR161 Memory Attribute Register 161 A100 0000h - A1FF FFFFh
+*/
+var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
+/* Mark external memory used by kernel as uncached so that IPC vring CMA
+ * region can operate properly when exchanging messages between DSP and ARM.
+ * Marking entire DDR3 as uncached since the memory used by kernel can
+ * change between device revisions. Need to find better way of doing this. */
+Cache.setMarMeta(0x80000000, 0x7FFFFFFF, 0xC);
+
+Program.global.sysMinBufSize = 0x8000;
+SysMin.bufSize = Program.global.sysMinBufSize;
+
+/* Enable Memory Translation module that operates on the Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+/* Make sure RemoteProc's .resource_table doesn't conflict with secure kernel when
+ * on secure board. Secure kernel is located from 0x00800000 - 0x00810000 */
+Resource.loadAddr = 0x00810000;
+
+/* COMMENT OUT TO SHUT OFF LOG FOR BENCHMARKS: */
+/*
+Diags.setMaskMeta("ti.ipc.family.tci6638.Interrupt", Diags.USER1,
+ Diags.ALWAYS_ON);
+Diags.setMaskMeta("ti.ipc.family.tci6638.VirtQueue", Diags.USER1,
+ Diags.ALWAYS_ON);
+Diags.setMaskMeta("ti.ipc.transports.TransportRpmsg",
+ Diags.INFO|Diags.USER1|Diags.STATUS,
+ Diags.ALWAYS_ON);
+Diags.setMaskMeta("ti.ipc.namesrv.NameServerRemoteRpmsg", Diags.INFO,
+ Diags.ALWAYS_ON);
+*/
+
+Hwi.enableException = true;
+
+xdc.loadPackage('ti.ipc.ipcmgr');
+BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
+
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var params = new HeapBuf.Params;
+params.align = 8;
+params.blockSize = 512;
+params.numBlocks = 256;
+var msgHeap = HeapBuf.create(params);
+
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.registerHeapMeta(msgHeap, 0);
+
+var Assert = xdc.useModule('xdc.runtime.Assert');
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Text = xdc.useModule('xdc.runtime.Text');
+Text.isLoaded = true;
+
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+VirtioSetup.common$.diags_INFO = Diags.RUNTIME_OFF;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+
+xdc.loadPackage('ti.ipc.transports').profile = 'release';
+
+/* PDK packages */
+var devType = "c6678"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+MessageQ.SetupTransportProxy = VirtioSetup;
+
+var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
+var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+NameServer.SetupProxy = NsRemote;
+
+var TransportRpmsg = xdc.useModule('ti.ipc.transports.TransportRpmsg');
+
diff --git a/test/c6678/c66/bios/rmMem_evmc6678_C66BiosTestProject.txt b/test/c6678/c66/bios/rmMem_evmc6678_C66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,13 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_mem_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/c6678/global-resource-list.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/device/c6678/policy_dsp_arm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/static-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/linux-evm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_transport_setup.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_mem_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6678 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6678/c66/bios/rmShared_evmc6678_C66BiosTestProject.txt b/test/c6678/c66/bios/rmShared_evmc6678_C66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,9 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_shared_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/linux-evm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_shared_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_shared_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6678 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6678/c66/bios/rm_evmc6678_C66BiosTestProject.txt b/test/c6678/c66/bios/rm_evmc6678_C66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,10 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/linux-evm.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/static-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6678 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6678/c66/bios/rm_evmc6678_C66DspMtBiosTestProject.txt b/test/c6678/c66/bios/rm_evmc6678_C66DspMtBiosTestProject.txt
--- /dev/null
@@ -0,0 +1,8 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/src/rm_dsp_mt_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/global-resources.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/dts_files/server-policy.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/c6678/c66/bios/rm_test_sc.cfg"
+-ccs.setCompilerOptions "-mv6600 -g -DSOC_C6678 --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm"
+-rtsc.enableRtsc
+
diff --git a/test/c6678/c66/bios/rm_mem_test.cfg b/test/c6678/c66/bios/rm_mem_test.cfg
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0", "CORE1"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x80000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+/* Okay for these to be in L2 since it's only read once at startup */
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+Program.sectMap[".sharedPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedPolicy"] = "L2SRAM";
+
+Program.sectMap[".rm"] = new Program.SectionSpec();
+Program.sectMap[".rm"] = "MSMCSRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* Shared Memory base address and length */
+var SHAREDMEM = 0x0C000000;
+var SHAREDMEMSIZE = 0x00100000;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: SHAREDMEM,
+ len: SHAREDMEMSIZE,
+ ownerProcId: 0,
+ isValid: true,
+ name: "DDR2 RAM",
+ });
+
+/* PDK packages */
+var devType = "c6678"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6678/c66/bios/rm_osal.c b/test/c6678/c66/bios/rm_osal.c
--- /dev/null
@@ -0,0 +1,274 @@
+/**
+ * @file rm_osal.c
+ *
+ * @brief
+ * This is the OS abstraction layer used by the Resource Manager.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012-2015, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* Standard Includes */
+#include <stdarg.h>
+
+/* XDC Includes */
+#include <xdc/std.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+/* BIOS Includes */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+/* CSL includes */
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_xmcAux.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+uint32_t rmMallocCounter = 0;
+uint32_t rmFreeCounter = 0;
+
+int32_t rmByteAlloc = 0;
+int32_t rmByteFree = 0;
+
+/**********************************************************************
+ *************************** OSAL Functions **************************
+ **********************************************************************/
+
+/* FUNCTION PURPOSE: Allocates memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to allocate a memory block of the
+ * specified size.
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ rmMallocCounter++;
+ rmByteAlloc += num_bytes;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/* FUNCTION PURPOSE: Frees memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to free a memory block of the
+ * specified size.
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ /* Increment the free counter. */
+ rmFreeCounter++;
+ rmByteFree += size;
+ Memory_free(NULL, ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a multi-threaded critical
+ * section. Function protects against
+ *
+ * access from multiple threads on single core
+ */
+void *Osal_rmMtCsEnter(void *mtSemObj)
+{
+ Semaphore_pend((Semaphore_Handle)mtSemObj, BIOS_WAIT_FOREVER);
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a multi-threaded critical
+ * section protected using Osal_rmMtCsEnter() API.
+ */
+void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
+{
+ Semaphore_post((Semaphore_Handle)mtSemObj);
+}
+
+/* FUNCTION PURPOSE: Cache invalidate
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Cache writeback
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/* FUNCTION PURPOSE: Creates a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/* FUNCTION PURPOSE: Blocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to block a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/* FUNCTION PURPOSE: unBlocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to unblock a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/* FUNCTION PURPOSE: Deletes a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to delete a task blocking object
+ * provided to a RM instance
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/* FUNCTION PURPOSE: Prints a variable list
+ ***********************************************************************
+ * DESCRIPTION: The function is used to print a string to the console
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
diff --git a/test/c6678/c66/bios/rm_shared_osal.c b/test/c6678/c66/bios/rm_shared_osal.c
--- /dev/null
@@ -0,0 +1,298 @@
+/**
+ * @file rm_osal.c
+ *
+ * @brief
+ * This is the OS abstraction layer used by the Resource Manager.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012-2013, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* Standard Includes */
+#include <stdarg.h>
+
+/* XDC Includes */
+#include <xdc/std.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+/* BIOS Includes */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+/* IPC includes */
+#include <ti/ipc/SharedRegion.h>
+
+/* CSL includes */
+#include <ti/csl/csl_semAux.h>
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_xmcAux.h>
+
+/* RM Includes */
+#include <ti/drv/rm/rm_osal.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+/* Try to avoid conflict with GateMP in rm_shared_test.c */
+#define RM_HW_SEM 4
+#define RM_MALLOC_FREE_SEM 5
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+/* Put memory tracking variables in MSMCSRAM to track all allocations
+ * using the Shared Server. Define the variables so they don't cross
+ * any cache line boundaries. */
+#pragma DATA_SECTION (rmMallocCounter, ".rmSharedHandleTest");
+#pragma DATA_ALIGN (rmMallocCounter, 128)
+uint32_t rmMallocCounter[4] = {0,0,0,0};
+#pragma DATA_SECTION (rmFreeCounter, ".rmSharedHandleTest");
+#pragma DATA_ALIGN (rmFreeCounter, 128)
+uint32_t rmFreeCounter[4] = {0,0,0,0};
+
+/**********************************************************************
+ *************************** OSAL Functions **************************
+ **********************************************************************/
+
+/* FUNCTION PURPOSE: Allocates memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to allocate a memory block of the
+ * specified size.
+ */
+void *Osal_rmMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ while ((CSL_semAcquireDirect (RM_MALLOC_FREE_SEM)) == 0);
+ Osal_rmBeginMemAccess(rmMallocCounter, sizeof(rmMallocCounter));
+ /* Increment the allocation counter. */
+ rmMallocCounter[0]++;
+ Osal_rmEndMemAccess(rmMallocCounter, sizeof(rmMallocCounter));
+ CSL_semReleaseSemaphore (RM_MALLOC_FREE_SEM);
+
+ /* Allocate memory. */
+ return Memory_alloc(SharedRegion_getHeap(0), num_bytes, 0, &errorBlock);
+}
+
+/* FUNCTION PURPOSE: Frees memory
+ ***********************************************************************
+ * DESCRIPTION: The function is used to free a memory block of the
+ * specified size.
+ */
+void Osal_rmFree (void *ptr, uint32_t size)
+{
+ while ((CSL_semAcquireDirect (RM_MALLOC_FREE_SEM)) == 0);
+ /* Increment the free counter. */
+ Osal_rmBeginMemAccess(rmFreeCounter, sizeof(rmFreeCounter));
+ rmFreeCounter[0]++;
+ Osal_rmEndMemAccess(rmFreeCounter, sizeof(rmFreeCounter));
+ CSL_semReleaseSemaphore (RM_MALLOC_FREE_SEM);
+
+ /* Free memory */
+ Memory_free(SharedRegion_getHeap(0), ptr, size);
+}
+
+/* FUNCTION PURPOSE: Critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ */
+void *Osal_rmCsEnter(void)
+{
+ /* Get the hardware semaphore for protection against multiple core access */
+ while ((CSL_semAcquireDirect (RM_HW_SEM)) == 0);
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ */
+void Osal_rmCsExit(void *CsHandle)
+{
+ /* Release the hardware semaphore */
+ CSL_semReleaseSemaphore (RM_HW_SEM);
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section enter
+ ***********************************************************************
+ * DESCRIPTION: The function is used to enter a multi-threaded critical
+ * section. Function protects against
+ *
+ * access from multiple threads on single core
+ */
+void *Osal_rmMtCsEnter(void *mtSemObj)
+{
+
+ return NULL;
+}
+
+/* FUNCTION PURPOSE: Multi-threaded critical section exit
+ ***********************************************************************
+ * DESCRIPTION: The function is used to exit a multi-threaded critical
+ * section protected using Osal_rmMtCsEnter() API.
+ */
+void Osal_rmMtCsExit(void *mtSemObj, void *CsHandle)
+{
+
+}
+
+/* FUNCTION PURPOSE: Cache invalidate
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ */
+void Osal_rmBeginMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+/* FUNCTION PURPOSE: Cache writeback
+ ***********************************************************************
+ * DESCRIPTION: The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ */
+void Osal_rmEndMemAccess(void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+/* FUNCTION PURPOSE: Creates a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to create a task blocking object
+ * capable of blocking the task a RM instance is running
+ * within
+ */
+void *Osal_rmTaskBlockCreate(void)
+{
+ Semaphore_Params semParams;
+
+ Semaphore_Params_init(&semParams);
+ return((void *)Semaphore_create(0, &semParams, NULL));
+}
+
+/* FUNCTION PURPOSE: Blocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to block a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskBlock(void *handle)
+{
+ Semaphore_pend((Semaphore_Handle)handle, BIOS_WAIT_FOREVER);
+}
+
+/* FUNCTION PURPOSE: unBlocks a RM instance
+ ***********************************************************************
+ * DESCRIPTION: The function is used to unblock a task whose context a
+ * RM instance is running within.
+ */
+void Osal_rmTaskUnblock(void *handle)
+{
+ Semaphore_post((Semaphore_Handle)handle);
+}
+
+/* FUNCTION PURPOSE: Deletes a task blocking object
+ ***********************************************************************
+ * DESCRIPTION: The function is used to delete a task blocking object
+ * provided to a RM instance
+ */
+void Osal_rmTaskBlockDelete(void *handle)
+{
+ Semaphore_delete((Semaphore_Handle *)&handle);
+}
+
+/* FUNCTION PURPOSE: Prints a variable list
+ ***********************************************************************
+ * DESCRIPTION: The function is used to print a string to the console
+ */
+void Osal_rmLog (char *fmt, ... )
+{
+ VaList ap;
+
+ va_start(ap, fmt);
+ System_vprintf(fmt, ap);
+ va_end(ap);
+}
+
diff --git a/test/c6678/c66/bios/rm_shared_test.cfg b/test/c6678/c66/bios/rm_shared_test.cfg
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0", "CORE1"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x10000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+Program.sectMap[".rmSharedHandleTest"] = new Program.SectionSpec();
+Program.sectMap[".rmSharedHandleTest"] = "MSMCSRAM";
+
+/* Read once when RM_SHARED_SERVER is initialized */
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: 0x0C000000,
+ len: 0x00100000,
+ ownerProcId: 0,
+ isValid: true,
+ name: "sharemem",
+ });
+
+/* PDK packages */
+var devType = "c6678"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6678/c66/bios/rm_test.cfg b/test/c6678/c66/bios/rm_test.cfg
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0", "CORE1"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x10000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* Shared Memory base address and length */
+var SHAREDMEM = 0x0C000000;
+var SHAREDMEMSIZE = 0x00100000;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: SHAREDMEM,
+ len: SHAREDMEMSIZE,
+ ownerProcId: 0,
+ isValid: true,
+ name: "DDR2 RAM",
+ });
+
+/* PDK packages */
+var devType = "c6678"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+
diff --git a/test/c6678/c66/bios/rm_test_sc.cfg b/test/c6678/c66/bios/rm_test_sc.cfg
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * */
+
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/*
+ * Get the list of names that the build device supports.
+ * I.e. ["CORE0", "CORE1", "CORE2" ... ]
+ */
+var nameList = ["CORE0"];
+
+/*
+ * Since this is a single-image example, we don't (at build-time) which
+ * processor we're building for. We therefore supply 'null'
+ * as the local procName and allow IPC to set the local procId at runtime.
+ */
+MultiProc.setConfig(null, nameList);
+
+/*
+ * The SysStd System provider is a good one to use for debugging
+ * but does not have the best performance. Use xdc.runtime.SysMin
+ * for better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Modules explicitly used in the application */
+var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+/* BIOS/XDC modules */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.heapSize = 0x10000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+
+Program.sectMap[".sharedGRL"] = new Program.SectionSpec();
+Program.sectMap[".sharedGRL"] = "L2SRAM";
+
+Program.sectMap[".sharedGlobalPolicy"] = new Program.SectionSpec();
+Program.sectMap[".sharedGlobalPolicy"] = "L2SRAM";
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* Shared Memory base address and length */
+var SHAREDMEM = 0x0C000000;
+var SHAREDMEMSIZE = 0x00100000;
+
+/*
+ * Need to define the shared region. The IPC modules use this
+ * to make portable pointers. All processors need to add this
+ * call with their base address of the shared memory region.
+ * If the processor cannot access the memory, do not add it.
+ */
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+SharedRegion.translate = false;
+SharedRegion.setEntryMeta(0,
+ { base: SHAREDMEM,
+ len: SHAREDMEMSIZE,
+ ownerProcId: 0,
+ isValid: true,
+ name: "DDR2 RAM",
+ });
+
+/* PDK packages */
+var devType = "c6678"
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+