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raw | patch | inline | side by side (parent: 237fddf)
raw | patch | inline | side by side (parent: 237fddf)
| author | Justin Sobota <jsobota@ti.com> | |
| Mon, 15 Oct 2012 19:46:18 +0000 (15:46 -0400) | ||
| committer | Justin Sobota <jsobota@ti.com> | |
| Mon, 15 Oct 2012 19:46:18 +0000 (15:46 -0400) |
28 files changed:
| Settings.xdc | [deleted file] | patch | blob | history |
| docs/Doxyfile | [deleted file] | patch | blob | history |
| include/Module.xs | [new file with mode: 0644] | patch | blob |
| include/rm_pvt.h | [new file with mode: 0644] | patch | blob |
| package.bld | patch | blob | history | |
| resource_table/Module.xs | [new file with mode: 0644] | patch | blob |
| resource_table/default_resource_table.c | [new file with mode: 0644] | patch | blob |
| resource_table/dsp_plus_arm_resource_table.c | [new file with mode: 0644] | patch | blob |
| resource_table/shared_resources.h | [moved from rmver.h with 56% similarity] | patch | blob | history |
| resource_table_defs.h | [new file with mode: 0644] | patch | blob |
| rm.h | [new file with mode: 0644] | patch | blob |
| rm_osal.h | [new file with mode: 0644] | patch | blob |
| setupenv.bat | patch | blob | history | |
| src/Module.xs | [new file with mode: 0644] | patch | blob |
| src/rm.c | [new file with mode: 0644] | patch | blob |
| test/Module.xs | [new file with mode: 0644] | patch | blob |
| test/README.txt | [new file with mode: 0644] | patch | blob |
| test/cppi_test/rm_test_cppi.c | [new file with mode: 0644] | patch | blob |
| test/pa_test/rm_test_pa.c | [new file with mode: 0644] | patch | blob |
| test/qmss_test/rm_test_qmss.c | [new file with mode: 0644] | patch | blob |
| test/rm_linker.cmd | [new file with mode: 0644] | patch | blob |
| test/rm_osal.c | [new file with mode: 0644] | patch | blob |
| test/rm_osal.h | [new file with mode: 0644] | patch | blob |
| test/rm_test.c | [new file with mode: 0644] | patch | blob |
| test/rm_test.cfg | [new file with mode: 0644] | patch | blob |
| test/rm_test.h | [new file with mode: 0644] | patch | blob |
| test/rm_test_resource.c | [new file with mode: 0644] | patch | blob |
| test/rm_testproject.txt | [new file with mode: 0644] | patch | blob |
diff --git a/Settings.xdc b/Settings.xdc
--- a/Settings.xdc
+++ /dev/null
@@ -1,7 +0,0 @@
-
-
-module Settings
-{
- config string rmlldVersionString = "01.00.00.11";
-}
-
diff --git a/docs/Doxyfile b/docs/Doxyfile
--- a/docs/Doxyfile
+++ /dev/null
@@ -1,293 +0,0 @@
-
-# Doxyfile 1.5.6
-
-#---------------------------------------------------------------------------
-# Project related configuration options
-#---------------------------------------------------------------------------
-DOXYFILE_ENCODING = UTF-8
-PROJECT_NAME = "RM Low Level Driver"
-PROJECT_NUMBER = 1.0.0.11
-OUTPUT_DIRECTORY = ./docs/doxygen
-CREATE_SUBDIRS = NO
-OUTPUT_LANGUAGE = English
-BRIEF_MEMBER_DESC = YES
-REPEAT_BRIEF = YES
-ABBREVIATE_BRIEF = "The $name class" \
- "The $name widget" \
- "The $name file" \
- is \
- provides \
- specifies \
- contains \
- represents \
- a \
- an \
- the
-ALWAYS_DETAILED_SEC = NO
-INLINE_INHERITED_MEMB = NO
-FULL_PATH_NAMES = NO
-STRIP_FROM_PATH =
-STRIP_FROM_INC_PATH =
-SHORT_NAMES = NO
-JAVADOC_AUTOBRIEF = NO
-QT_AUTOBRIEF = NO
-MULTILINE_CPP_IS_BRIEF = NO
-DETAILS_AT_TOP = NO
-INHERIT_DOCS = YES
-SEPARATE_MEMBER_PAGES = NO
-TAB_SIZE = 8
-ALIASES =
-OPTIMIZE_OUTPUT_FOR_C = YES
-OPTIMIZE_OUTPUT_JAVA = NO
-OPTIMIZE_FOR_FORTRAN = NO
-OPTIMIZE_OUTPUT_VHDL = NO
-BUILTIN_STL_SUPPORT = NO
-CPP_CLI_SUPPORT = NO
-SIP_SUPPORT = NO
-IDL_PROPERTY_SUPPORT = YES
-DISTRIBUTE_GROUP_DOC = NO
-SUBGROUPING = YES
-TYPEDEF_HIDES_STRUCT = NO
-#---------------------------------------------------------------------------
-# Build related configuration options
-#---------------------------------------------------------------------------
-EXTRACT_ALL = NO
-EXTRACT_PRIVATE = NO
-EXTRACT_STATIC = YES
-EXTRACT_LOCAL_CLASSES = YES
-EXTRACT_LOCAL_METHODS = NO
-EXTRACT_ANON_NSPACES = NO
-HIDE_UNDOC_MEMBERS = YES
-HIDE_UNDOC_CLASSES = YES
-HIDE_FRIEND_COMPOUNDS = NO
-HIDE_IN_BODY_DOCS = NO
-INTERNAL_DOCS = NO
-CASE_SENSE_NAMES = NO
-HIDE_SCOPE_NAMES = NO
-SHOW_INCLUDE_FILES = YES
-INLINE_INFO = YES
-SORT_MEMBER_DOCS = YES
-SORT_BRIEF_DOCS = NO
-SORT_GROUP_NAMES = NO
-SORT_BY_SCOPE_NAME = NO
-GENERATE_TODOLIST = YES
-GENERATE_TESTLIST = YES
-GENERATE_BUGLIST = YES
-GENERATE_DEPRECATEDLIST= YES
-ENABLED_SECTIONS =
-MAX_INITIALIZER_LINES = 30
-SHOW_USED_FILES = YES
-SHOW_DIRECTORIES = NO
-SHOW_FILES = YES
-SHOW_NAMESPACES = YES
-FILE_VERSION_FILTER =
-#---------------------------------------------------------------------------
-# configuration options related to warning and progress messages
-#---------------------------------------------------------------------------
-QUIET = NO
-WARNINGS = YES
-WARN_IF_UNDOCUMENTED = YES
-WARN_IF_DOC_ERROR = YES
-WARN_NO_PARAMDOC = NO
-WARN_FORMAT = "$file:$line: $text"
-WARN_LOGFILE =
-#---------------------------------------------------------------------------
-# configuration options related to the input files
-#---------------------------------------------------------------------------
-INPUT =
-INPUT_ENCODING = UTF-8
-FILE_PATTERNS = *.c \
- *.cc \
- *.cxx \
- *.cpp \
- *.c++ \
- *.d \
- *.java \
- *.ii \
- *.ixx \
- *.ipp \
- *.i++ \
- *.inl \
- *.h \
- *.hh \
- *.hxx \
- *.hpp \
- *.h++ \
- *.idl \
- *.odl \
- *.cs \
- *.php \
- *.php3 \
- *.inc \
- *.m \
- *.mm \
- *.dox \
- *.py \
- *.f90 \
- *.f \
- *.vhd \
- *.vhdl
-RECURSIVE = YES
-EXCLUDE = YES \
- ./example \
- ./test \
- ./package \
- ./packages
-EXCLUDE_SYMLINKS = NO
-EXCLUDE_PATTERNS = cslr_*.h
-EXCLUDE_SYMBOLS =
-EXAMPLE_PATH =
-EXAMPLE_PATTERNS = *
-EXAMPLE_RECURSIVE = NO
-IMAGE_PATH =
-INPUT_FILTER =
-FILTER_PATTERNS =
-FILTER_SOURCE_FILES = NO
-#---------------------------------------------------------------------------
-# configuration options related to source browsing
-#---------------------------------------------------------------------------
-SOURCE_BROWSER = NO
-INLINE_SOURCES = NO
-STRIP_CODE_COMMENTS = YES
-REFERENCED_BY_RELATION = NO
-REFERENCES_RELATION = NO
-REFERENCES_LINK_SOURCE = YES
-USE_HTAGS = NO
-VERBATIM_HEADERS = NO
-#---------------------------------------------------------------------------
-# configuration options related to the alphabetical class index
-#---------------------------------------------------------------------------
-ALPHABETICAL_INDEX = NO
-COLS_IN_ALPHA_INDEX = 5
-IGNORE_PREFIX =
-#---------------------------------------------------------------------------
-# configuration options related to the HTML output
-#---------------------------------------------------------------------------
-GENERATE_HTML = YES
-HTML_OUTPUT = html
-HTML_FILE_EXTENSION = .html
-HTML_HEADER = ./docs/tiheader.htm
-HTML_FOOTER = ./docs/tifooter.htm
-HTML_STYLESHEET =
-HTML_ALIGN_MEMBERS = YES
-GENERATE_HTMLHELP = YES
-GENERATE_DOCSET = NO
-DOCSET_FEEDNAME = "Doxygen generated docs"
-DOCSET_BUNDLE_ID = org.doxygen.Project
-HTML_DYNAMIC_SECTIONS = NO
-CHM_FILE = ..\..\rmlldDocs.chm
-HHC_LOCATION = hhc.exe
-GENERATE_CHI = NO
-CHM_INDEX_ENCODING =
-BINARY_TOC = NO
-TOC_EXPAND = NO
-DISABLE_INDEX = NO
-ENUM_VALUES_PER_LINE = 4
-GENERATE_TREEVIEW = NONE
-TREEVIEW_WIDTH = 250
-FORMULA_FONTSIZE = 10
-#---------------------------------------------------------------------------
-# configuration options related to the LaTeX output
-#---------------------------------------------------------------------------
-GENERATE_LATEX = NO
-LATEX_OUTPUT = latex
-LATEX_CMD_NAME = latex
-MAKEINDEX_CMD_NAME = makeindex
-COMPACT_LATEX = NO
-PAPER_TYPE = a4wide
-EXTRA_PACKAGES =
-LATEX_HEADER =
-PDF_HYPERLINKS = YES
-USE_PDFLATEX = YES
-LATEX_BATCHMODE = NO
-LATEX_HIDE_INDICES = NO
-#---------------------------------------------------------------------------
-# configuration options related to the RTF output
-#---------------------------------------------------------------------------
-GENERATE_RTF = NO
-RTF_OUTPUT = rtf
-COMPACT_RTF = NO
-RTF_HYPERLINKS = NO
-RTF_STYLESHEET_FILE =
-RTF_EXTENSIONS_FILE =
-#---------------------------------------------------------------------------
-# configuration options related to the man page output
-#---------------------------------------------------------------------------
-GENERATE_MAN = NO
-MAN_OUTPUT = man
-MAN_EXTENSION = .3
-MAN_LINKS = NO
-#---------------------------------------------------------------------------
-# configuration options related to the XML output
-#---------------------------------------------------------------------------
-GENERATE_XML = NO
-XML_OUTPUT = xml
-XML_SCHEMA =
-XML_DTD =
-XML_PROGRAMLISTING = YES
-#---------------------------------------------------------------------------
-# configuration options for the AutoGen Definitions output
-#---------------------------------------------------------------------------
-GENERATE_AUTOGEN_DEF = NO
-#---------------------------------------------------------------------------
-# configuration options related to the Perl module output
-#---------------------------------------------------------------------------
-GENERATE_PERLMOD = NO
-PERLMOD_LATEX = NO
-PERLMOD_PRETTY = YES
-PERLMOD_MAKEVAR_PREFIX =
-#---------------------------------------------------------------------------
-# Configuration options related to the preprocessor
-#---------------------------------------------------------------------------
-ENABLE_PREPROCESSING = YES
-MACRO_EXPANSION = NO
-EXPAND_ONLY_PREDEF = NO
-SEARCH_INCLUDES = YES
-INCLUDE_PATH =
-INCLUDE_FILE_PATTERNS =
-PREDEFINED =
-EXPAND_AS_DEFINED =
-SKIP_FUNCTION_MACROS = YES
-#---------------------------------------------------------------------------
-# Configuration::additions related to external references
-#---------------------------------------------------------------------------
-TAGFILES =
-GENERATE_TAGFILE =
-ALLEXTERNALS = NO
-EXTERNAL_GROUPS = YES
-PERL_PATH = /usr/bin/perl
-#---------------------------------------------------------------------------
-# Configuration options related to the dot tool
-#---------------------------------------------------------------------------
-CLASS_DIAGRAMS = NO
-MSCGEN_PATH =
-HIDE_UNDOC_RELATIONS = YES
-HAVE_DOT = NO
-DOT_FONTNAME = FreeSans
-DOT_FONTPATH =
-CLASS_GRAPH = YES
-COLLABORATION_GRAPH = YES
-GROUP_GRAPHS = YES
-UML_LOOK = NO
-TEMPLATE_RELATIONS = NO
-INCLUDE_GRAPH = YES
-INCLUDED_BY_GRAPH = YES
-CALL_GRAPH = NO
-CALLER_GRAPH = NO
-GRAPHICAL_HIERARCHY = YES
-DIRECTORY_GRAPH = YES
-DOT_IMAGE_FORMAT = png
-DOT_PATH =
-DOTFILE_DIRS =
-DOT_GRAPH_MAX_NODES = 50
-MAX_DOT_GRAPH_DEPTH = 1000
-DOT_TRANSPARENT = YES
-DOT_MULTI_TARGETS = NO
-GENERATE_LEGEND = YES
-DOT_CLEANUP = YES
-#---------------------------------------------------------------------------
-# Configuration::additions related to the search engine
-#---------------------------------------------------------------------------
-SEARCHENGINE = NO
-
-
diff --git a/include/Module.xs b/include/Module.xs
--- /dev/null
+++ b/include/Module.xs
@@ -0,0 +1,29 @@
+/******************************************************************************
+ * FILE PURPOSE: RM LLD include files.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for RM LLD include directory
+ *
+ * Copyright (C) 2012, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to add all the header files in the include
+ * directory into the package.
+ **************************************************************************/
+function modBuild()
+{
+ /* Add all the .h files to the release package. */
+ var testFiles = libUtility.listAllFiles (".h", "include", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+}
+
diff --git a/include/rm_pvt.h b/include/rm_pvt.h
--- /dev/null
+++ b/include/rm_pvt.h
@@ -0,0 +1,330 @@
+/*
+ * file rm_pvt.h
+ *
+ * Private data structures of Resource Manager Low Level Driver.
+ *
+ * ============================================================================
+ * (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+#ifndef RM_PVT_H_
+#define RM_PVT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Device Include */
+#include <c6x.h>
+
+/* RM includes */
+#include <ti/drv/rm/rm_public_lld.h>
+
+/* CSL includes */
+#include <ti/csl/csl_qm_queue.h>
+
+/* QMSS Resource Information */
+#define RM_QMSS_FIRMWARE_PDSPS 2
+#define RM_QMSS_QUEUES 8192
+#define RM_QMSS_MEM_REGIONS 20
+#define RM_QMSS_LINKING_RAM_RANGES 40 /* Twice as many memory regions */
+#define RM_QMSS_ACCUM_CH 48
+#define RM_QMSS_QOS_CLUSTER 8
+#define RM_QMSS_QOS_QUEUES 64
+
+#define RM_QMSS_LINKING_RAM_RANGE_INIT (0xFFFFFFFF)
+
+/* CPPI Resource Information */
+
+/* Set CPPI DMA increments based on which DMAs are present for the device */
+
+/* Set AIF increment if present */
+#ifdef QMSS_MAX_AIF_QUEUE
+#define RM_CPPI_AIF_INC 1
+#else
+#define RM_CPPI_AIF_INC 0
+#endif
+/* Set FFTC A increment if present */
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+#define RM_CPPI_FFTC_A_INC 1
+#else
+#define RM_CPPI_FFTC_A_INC 0
+#endif
+/* Set FFTC B increment if present */
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+#define RM_CPPI_FFTC_B_INC 1
+#else
+#define RM_CPPI_FFTC_B_INC 0
+#endif
+/* Set PASS increment if present */
+#ifdef QMSS_MAX_PASS_QUEUE
+#define RM_CPPI_PASS_INC 1
+#else
+#define RM_CPPI_PASS_INC 0
+#endif
+/* Set FFTC C increment if present */
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+#define RM_CPPI_FFTC_C_INC 1
+#else
+#define RM_CPPI_FFTC_C_INC 0
+#endif
+/* Set BCP increment if present */
+#ifdef QMSS_MAX_BCP_QUEUE
+#define RM_CPPI_BCP_INC 1
+#else
+#define RM_CPPI_BCP_INC 0
+#endif
+
+/* Base number of DMAs for all devices. */
+#define RM_CPPI_BASE_DMAS 2
+/* Set max DMAs, adding additional DMAs if present */
+#define RM_CPPI_MAX_DMAS (RM_CPPI_BASE_DMAS + RM_CPPI_AIF_INC + RM_CPPI_FFTC_A_INC + \
+ RM_CPPI_FFTC_B_INC + RM_CPPI_PASS_INC + RM_CPPI_FFTC_C_INC + \
+ RM_CPPI_BCP_INC)
+
+/* Set DMA indices based on which DMAs are present in device */
+#define RM_CPPI_SRIO_DMA_ID 0
+#define RM_CPPI_AIF_DMA_ID (RM_CPPI_SRIO_DMA_ID + RM_CPPI_AIF_INC)
+#define RM_CPPI_FFTC_A_DMA_ID (RM_CPPI_AIF_DMA_ID + RM_CPPI_FFTC_A_INC)
+#define RM_CPPI_FFTC_B_DMA_ID (RM_CPPI_FFTC_A_DMA_ID + RM_CPPI_FFTC_B_INC)
+#define RM_CPPI_PASS_DMA_ID (RM_CPPI_FFTC_B_DMA_ID + RM_CPPI_PASS_INC)
+#define RM_CPPI_QMSS_DMA_ID (RM_CPPI_PASS_DMA_ID + 1)
+#define RM_CPPI_FFTC_C_DMA_ID (RM_CPPI_QMSS_DMA_ID + RM_CPPI_FFTC_C_INC)
+#define RM_CPPI_BCP_DMA_ID (RM_CPPI_FFTC_C_DMA_ID + RM_CPPI_BCP_INC)
+
+#define RM_CPPI_SRIO_TX_CH 16
+#define RM_CPPI_AIF_TX_CH 129
+#define RM_CPPI_FFTC_A_TX_CH 4
+#define RM_CPPI_FFTC_B_TX_CH 4
+#define RM_CPPI_PASS_TX_CH 9
+#define RM_CPPI_QMSS_TX_CH 32
+#define RM_CPPI_FFTC_C_TX_CH 4
+#define RM_CPPI_BCP_TX_CH 8
+
+#define RM_CPPI_SRIO_RX_CH 16
+#define RM_CPPI_AIF_RX_CH 129
+#define RM_CPPI_FFTC_A_RX_CH 4
+#define RM_CPPI_FFTC_B_RX_CH 4
+#define RM_CPPI_PASS_RX_CH 24
+#define RM_CPPI_QMSS_RX_CH 32
+#define RM_CPPI_FFTC_C_RX_CH 4
+#define RM_CPPI_BCP_RX_CH 8
+
+#define RM_CPPI_SRIO_FLOW 20
+#define RM_CPPI_AIF_FLOW 129
+#define RM_CPPI_FFTC_A_FLOW 8
+#define RM_CPPI_FFTC_B_FLOW 8
+#define RM_CPPI_PASS_FLOW 32
+#define RM_CPPI_QMSS_FLOW 64
+#define RM_CPPI_FFTC_C_FLOW 8
+#define RM_CPPI_BCP_FLOW 64
+
+/* PA Resource Information */
+#define RM_PA_LUT 5
+
+/* Permissions Access Defines and Macros */
+#define RM_RESOURCE_PERM_INIT_SHIFT 0
+#define RM_RESOURCE_PERM_USE_SHIFT 1
+
+#define RM_GET_RESOURCE_FLAG(flag) ((flag) >> ((DNUM) << 1))
+
+#define RM_GET_RESOURCE_INIT_FLAG(flag) ((RM_GET_RESOURCE_FLAG (flag) >> RM_RESOURCE_PERM_INIT_SHIFT) & 1)
+#define RM_GET_RESOURCE_USE_FLAG(flag) ((RM_GET_RESOURCE_FLAG (flag) >> RM_RESOURCE_PERM_USE_SHIFT) & 1)
+
+#define RM_GET_PERMISSIONS(perms) (perms >> DNUM)
+
+#define RM_RANGE_CHECK(start, end, max, ret_val) \
+do { \
+ if ((start > end) || (end > max)) \
+ { \
+ return ret_val; \
+ } \
+} while(0)
+
+/* RM standard permission structure definition */
+typedef struct
+{
+ /** Initialization permissions
+ * Bit 0 - Core 0 init permission
+ * Bit 1 - Core 1 init permission
+ * Bit 2 - Core 2 init permission
+ * Bit 3 - Core 3 init permission
+ */
+ uint32_t initPerms;
+ /** Usage permissions
+ * Bit 0 - Core 0 use permission
+ * Bit 1 - Core 1 use permission
+ * Bit 2 - Core 2 use permission
+ * Bit 3 - Core 3 use permission
+ */
+ uint32_t usePerms;
+} Rm_Perms;
+
+/* RM permissions structure for Linking RAM regions */
+typedef struct
+{
+ /** Linking RAM start index for these permissions */
+ uint32_t startIndex;
+ /** Linking RAM end index for these permissions */
+ uint32_t endIndex;
+ /** Permissions for the range */
+ Rm_Perms rangePerms;
+} Rm_qmssLinkingRamPerms;
+
+/* RM permissions structure for CPPI DMA channels and flows */
+typedef struct
+{
+ /** Array of pointers to each DMAs channel or flow permissions
+ * From CPPI LLD - DMA 0 = SRIO
+ * DMA 1 = AIF
+ * DMA 2 = FFTC A
+ * DMA 3 = FFTC B
+ * DMA 4 = PASS
+ * DMA 5 = QMSS
+ * DMA 6 = FFTC C
+ * DMA 7 = BCP
+ *
+ * Note: Some DMAs may not be supported based on the device */
+ Rm_Perms *dmaPermPtrs[RM_CPPI_MAX_DMAS];
+} Rm_CppiChAndFlowPerms;
+
+/* RM Cache Line Alignment Defines and Macros */
+
+#define RM_MAX_CACHE_ALIGN 128 /* Maximum alignment for cache line size */
+
+/* This macro generates compilier error if postulate is false, so
+ * allows 0 overhead compile time size check. This "works" when
+ * the expression contains sizeof() which otherwise doesn't work
+ * with preprocessor */
+#define RM_COMPILE_TIME_SIZE_CHECK(postulate) \
+ do { \
+ typedef struct { \
+ uint8_t NegativeSizeIfPostulateFalse[((int)(postulate))*2 - 1];\
+ } PostulateCheck_t; \
+ } \
+ while (0)
+
+/* Macro to pad out internal permission structures to multiple of RM_MAX_CACHE_ALIGN bytes
+ * The macro prevent something else from being placed on same cache line as the permission.
+ * arrays. Note that pad[0] is illegal, so must add full RM_MAX_CACHE_ALIGN if structure
+ * is already padded by chance. */
+#define RM_ALIGN_PERMISSIONS_ARRAY(numElements, permStructType) ( \
+ (((sizeof(permStructType) * (numElements)) % RM_MAX_CACHE_ALIGN) == 0) ? (numElements) : \
+ ((numElements) + \
+ (RM_MAX_CACHE_ALIGN - \
+ ((sizeof(permStructType) * (numElements)) % RM_MAX_CACHE_ALIGN))/sizeof(permStructType)))
+
+/* RM Global Sync Object (unpadded) */
+typedef struct
+{
+ /** Rm_init/Rm_start synchronization object. */
+ uint8_t globalSyncObj;
+} Rm_Sync_Obj_Unpadded;
+
+/* RM Global Sync Object (padded) */
+typedef struct
+{
+ /** Data structure without padding, so sizeof() can compute padding */
+ Rm_Sync_Obj_Unpadded obj;
+ /** Pad out to end of RM_MAX_CACHE_ALIGN bytes to prevent something else
+ * from being placed on same cache line as Rm_Synci_Obj. Note that
+ * pad[0] is illegal, so must add full RM_MAX_CACHE_ALIGN if structure
+ * is already padded by chance. */
+ uint8_t pad[RM_MAX_CACHE_ALIGN -
+ (sizeof(Rm_Sync_Obj_Unpadded) % RM_MAX_CACHE_ALIGN)];
+} Rm_Sync_Obj;
+
+
+/* RM Global permissions object definition. (unpadded) */
+typedef struct
+{
+ /** Store the QMSS PDSP firmware permissions */
+ Rm_Perms *qmssPdspFirmwarePerms;
+ /** Store a pointer to the QMSS queue permissions array */
+ Rm_Perms *qmssQueuePerms;
+ /** Store a pointer to the QMSS memory region permissions array */
+ Rm_Perms *qmssMemRegionPerms;
+ /** Store the QMSS Linking RAM Control permissions */
+ Rm_Perms qmssLinkRamControlPerms;
+ /** Store a pointer to the QMSS linking RAM permissions list */
+ Rm_qmssLinkingRamPerms *qmssLinkRamPerms;
+ /** Store a pointer to the QMSS accumulator channel permissions array */
+ Rm_Perms *qmssAccumChPerms;
+ /** Store the QMSS QOS PDSP timer permissions */
+ Rm_Perms qmssQosPdspTimerPerms;
+ /** Store a pointer to the QMSS QOS cluster permissions array */
+ Rm_Perms *qmssQosClusterPerms;
+ /** Store a pointer to the QMSS QOS queue permissions array */
+ Rm_Perms *qmssQosQueuePerms;
+ /** Store the structure of pointers to the CPPI transmit channel permissions array */
+ Rm_CppiChAndFlowPerms cppiTxChPerms;
+ /** Store the structure of pointers to the CPPI receive channel permissions array */
+ Rm_CppiChAndFlowPerms cppiRxChPerms;
+ /** Store the structure of pointers to the CPPI flow permissions array */
+ Rm_CppiChAndFlowPerms cppiFlowPerms;
+ /** Store the PA firmware permissions */
+ Rm_Perms paFirmwarePerms;
+ /** Store a pointer to the PA lookup table permissions array */
+ Rm_Perms *paLutPerms;
+}Rm_GlobalPermissionsObj_Unpadded;
+
+/* RM Global Permissions Object (padded) */
+typedef struct
+{
+ /** Data structure without padding, so sizeof() can compute padding */
+ Rm_GlobalPermissionsObj_Unpadded obj;
+ /** Pad out to end of RM_MAX_CACHE_ALIGN bytes to prevent something else
+ * from being placed on same cache line as Rm_Synci_Obj. Note that
+ * pad[0] is illegal, so must add full RM_MAX_CACHE_ALIGN if structure
+ * is already padded by chance. */
+ uint8_t pad[RM_MAX_CACHE_ALIGN -
+ (sizeof(Rm_GlobalPermissionsObj_Unpadded) % RM_MAX_CACHE_ALIGN)];
+} Rm_GlobalPermissionsObj;
+
+extern void Rm_permissionTableInit(void);
+extern void Rm_setTablePermissions (const Rm_Resource *resourceEntry, Rm_Perms *rmPermsArray, uint32_t len);
+extern Rm_Result Rm_populatePermissionTable(const Rm_Resource *rmResourceTable);
+extern void Rm_updatePermissionTable(void);
+extern Rm_Result Rm_getInitPermissions (Rm_Perms *resourcePermissions);
+extern Rm_Result Rm_getUsePermissions (Rm_Perms *resourcePermissions);
+
+/* Permission checker handlers */
+extern Rm_Result Rm_initPermissionChecker (Rm_ResourceInfo *resourceData);
+extern Rm_Result Rm_usePermissionChecker (Rm_ResourceInfo *resourceData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RM_PVT_H_ */
+
diff --git a/package.bld b/package.bld
index e2dd851c4f022dbe87c64c605acbf39403098246..e1c996a5ed045b9ff46a040f6bedf8c948ceceac 100644 (file)
--- a/package.bld
+++ b/package.bld
* Copyright (C) 2012, Texas Instruments, Inc.\r
*****************************************************************************/\r
\r
+/* List of all subdirectories that combine to make the RM LLD Package. */\r
+var subDirectories = [ "src", "docs", "include", "test", "resource_table"];\r
+\r
/* Determine if we need to create the InstallJammer Application or not? \r
* RM LLD Deliverables be either of the following formats:\r
* - TAR Ball Package\r
* uncompression into a temporary directory. XDC Tools with xdc-rXX support the ZIP archiver. */\r
//Pkg.attrs = {archiver : "zip"};\r
\r
+/* Cycle through all the sub-directories and build all the files */\r
+for (var i = 0; i < subDirectories.length; i++) \r
+{\r
+ /* Load the capsule in the sub directory. */\r
+ var caps = xdc.loadCapsule (subDirectories[i]+"/Module.xs");\r
+\r
+ print ("Building directory " + subDirectories[i]);\r
+\r
+ /* Build the capsule. */\r
+ caps.modBuild();\r
+\r
+ /* Package the module.xs files for building via package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = subDirectories[i]+"/Module.xs";\r
+}\r
\r
/* Package the remaining files */\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "config.bld";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xdc";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "rm.h";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "rm_public_lld.h";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "resource_table_defs.h";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "rm_osal.h";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "rmver.h";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "rmver.h.xdt";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/Doxyfile";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxyfile.xdt";\r
Pkg.otherFiles[Pkg.otherFiles.length++] = "build/buildlib.xs";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "makefile";\r
\r
/* Generate Users Manual Doxyfile */\r
var tplt = xdc.loadTemplate("./docs/doxyfile.xdt");\r
diff --git a/resource_table/Module.xs b/resource_table/Module.xs
--- /dev/null
+++ b/resource_table/Module.xs
@@ -0,0 +1,33 @@
+/******************************************************************************
+ * FILE PURPOSE: RM LLD resource table specific files.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for RM LLD resource table specific files.
+ *
+ * Copyright (C) 2012, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to add all the source files in the resource_table
+ * directory into the package.
+ **************************************************************************/
+function modBuild()
+{
+ /* Add all the .c files to the release package. */
+ var configFiles = libUtility.listAllFiles (".c", "resource_table", true);
+ for (var k = 0 ; k < configFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];
+
+ /* Add all the .h files to the release package. */
+ var configFiles = libUtility.listAllFiles (".h", "resource_table", true);
+ for (var k = 0 ; k < configFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];
+}
diff --git a/resource_table/default_resource_table.c b/resource_table/default_resource_table.c
--- /dev/null
@@ -0,0 +1,586 @@
+/**
+ * @file default_resource_table.c
+ *
+ * @brief
+ * This file contains the default resource table definition for the RM LLD which
+ * assigns all resources to the DSP.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* Resource table defines */
+#include <ti/drv/rm/resource_table_defs.h>
+
+/** @addtogroup RM_LLD_RESOURCE_TABLE
+@{
+*/
+
+/** @brief QMSS DPSP default start and end ranges */
+#define QMSS_PDSP_DEFAULT_START_RANGE (0u)
+#define QMSS_PDSP_DEFAULT_END_RANGE (2u)
+/** @brief QMSS queue default start and end ranges */
+#define QMSS_QUEUE_DEFAULT_START_RANGE (0u)
+#define QMSS_QUEUE_DEFAULT_END_RANGE (8192u)
+/** @brief QMSS memory region default start and end ranges */
+#define QMSS_MEM_REGION_DEFAULT_START_RANGE (0u)
+#define QMSS_MEM_REGION_DEFAULT_END_RANGE (19u)
+/** @brief QMSS Linking RAM default start and end ranges */
+#define QMSS_LINK_RAM_DEFAULT_START_RANGE (0x00000000)
+#define QMSS_LINK_RAM_DEFAULT_END_RANGE (0xFFFFFFFF)
+/** @brief QMSS Accumulator channels default start and end ranges */
+#define QMSS_ACCUM_CH_DEFAULT_START_RANGE (0u)
+#define QMSS_ACCUM_CH_DEFAULT_END_RANGE (47u)
+/** @brief QMSS QOS clusters default start and end ranges */
+#define QMSS_QOS_CLUSTER_DEFAULT_START_RANGE (0u)
+#define QMSS_QOS_CLUSTER_DEFAULT_END_RANGE (7u)
+/** @brief QMSS QOS queue default start and end ranges */
+#define QMSS_QOS_QUEUE_DEFAULT_START_RANGE (0u)
+#define QMSS_QOS_QUEUE_DEFAULT_END_RANGE (63u)
+
+/** @brief CPPI SRIO tx channels default start and end ranges */
+#define CPPI_SRIO_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_TX_CH_DEFAULT_END_RANGE (15u)
+/** @brief CPPI SRIO rx channels default start and end ranges */
+#define CPPI_SRIO_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_RX_CH_DEFAULT_END_RANGE (15u)
+/** @brief CPPI SRIO rx flows default start and end ranges */
+#define CPPI_SRIO_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_FLOW_DEFAULT_END_RANGE (19u)
+/** @brief CPPI AIF tx channels default start and end ranges */
+#define CPPI_AIF_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_TX_CH_DEFAULT_END_RANGE (128u)
+/** @brief CPPI AIF rx channels default start and end ranges */
+#define CPPI_AIF_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_RX_CH_DEFAULT_END_RANGE (128u)
+/** @brief CPPI AIF rx flows default start and end ranges */
+#define CPPI_AIF_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_FLOW_DEFAULT_END_RANGE (128u)
+/** @brief CPPI FFTC_A tx channels default start and end ranges */
+#define CPPI_FFTC_A_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_TX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_A rx channels default start and end ranges */
+#define CPPI_FFTC_A_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_RX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_A rx flows default start and end ranges */
+#define CPPI_FFTC_A_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_FLOW_DEFAULT_END_RANGE (7u)
+/** @brief CPPI FFTC_B tx channels default start and end ranges */
+#define CPPI_FFTC_B_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_TX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_B rx channels default start and end ranges */
+#define CPPI_FFTC_B_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_RX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_B rx flows default start and end ranges */
+#define CPPI_FFTC_B_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_FLOW_DEFAULT_END_RANGE (7u)
+/** @brief CPPI PASS tx channels default start and end ranges */
+#define CPPI_PASS_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_TX_CH_DEFAULT_END_RANGE (8u)
+/** @brief CPPI PASS rx channels default start and end ranges */
+#define CPPI_PASS_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_RX_CH_DEFAULT_END_RANGE (23u)
+/** @brief CPPI PASS rx flows default start and end ranges */
+#define CPPI_PASS_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_FLOW_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS tx channels default start and end ranges */
+#define CPPI_QMSS_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_TX_CH_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS rx channels default start and end ranges */
+#define CPPI_QMSS_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_RX_CH_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS rx flows default start and end ranges */
+#define CPPI_QMSS_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_FLOW_DEFAULT_END_RANGE (63u)
+/** @brief CPPI BCP tx channels default start and end ranges */
+#define CPPI_BCP_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_TX_CH_DEFAULT_END_RANGE (7u)
+/** @brief CPPI BCP rx channels default start and end ranges */
+#define CPPI_BCP_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_RX_CH_DEFAULT_END_RANGE (7u)
+/** @brief CPPI BCP rx flows default start and end ranges */
+#define CPPI_BCP_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_FLOW_DEFAULT_END_RANGE (63u)
+
+/** @brief PA LUT entry default start and end ranges */
+#define PA_LUT_ENTRY_DEFAULT_START_RANGE (0u)
+#define PA_LUT_ENTRY_DEFAULT_END_RANGE (4u)
+
+/** @brief RM LLD resource table permissions
+ * Must be cache line aligned. Select pragma format based on language */
+#ifdef __cplusplus
+#pragma DATA_ALIGN (128)
+#else
+#pragma DATA_ALIGN (rmResourceTable, 128)
+#endif
+const Rm_Resource rmResourceTable[] =
+{
+ /* Magic Number structure to verify RM can read the resource table */
+
+ {
+ /** DSP QMSS Firmware access */
+ RM_RESOURCE_MAGIC_NUMBER,
+ /** No start range */
+ 0u,
+ /** No end range */
+ 0u,
+ /** No init permissions */
+ 0u,
+ /** No use permissions */
+ 0u,
+ },
+
+ /* QMSS Resource Definitions */
+
+ {
+ /** DSP QMSS PDSP Firmware access */
+ RM_RESOURCE_QMSS_FIRMWARE_PDSP,
+ /** PDSP start range */
+ QMSS_PDSP_DEFAULT_START_RANGE,
+ /** PDSP end range */
+ QMSS_PDSP_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_QUEUE_DEFAULT_START_RANGE,
+ /** Queue end range */
+ QMSS_QUEUE_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS Memory Region */
+ RM_RESOURCE_QMSS_MEMORY_REGION,
+ /** Memory Region start range*/
+ QMSS_MEM_REGION_DEFAULT_START_RANGE,
+ /** Memory Region end range */
+ QMSS_MEM_REGION_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS Linking RAM Control access */
+ RM_RESOURCE_QMSS_LINKING_RAM_CONTROL,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS Linking RAM access */
+ RM_RESOURCE_QMSS_LINKING_RAM,
+ /** Linking RAM start range*/
+ QMSS_LINK_RAM_DEFAULT_START_RANGE,
+ /** Linking RAM end range */
+ QMSS_LINK_RAM_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS accumulator channels */
+ RM_RESOURCE_QMSS_ACCUMULATOR_CH,
+ /** Accumulator channel start range*/
+ QMSS_ACCUM_CH_DEFAULT_START_RANGE,
+ /** Accumulator channel end range */
+ QMSS_ACCUM_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS QOS PDSP Timer */
+ RM_RESOURCE_QMSS_QOS_PDSP_TIMER,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS QOS clusters */
+ RM_RESOURCE_QMSS_QOS_CLUSTER,
+ /** QOS cluster start range*/
+ QMSS_QOS_CLUSTER_DEFAULT_START_RANGE,
+ /** QOS cluster end range */
+ QMSS_QOS_CLUSTER_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS QOS queues */
+ RM_RESOURCE_QMSS_QOS_QUEUE,
+ /** QOS queues start range*/
+ QMSS_QOS_QUEUE_DEFAULT_START_RANGE,
+ /** QOS queues end range */
+ QMSS_QOS_QUEUE_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /* CPPI Resource Definitions */
+
+ {
+ /** DSP CPPI SRIO tx channels */
+ RM_RESOURCE_CPPI_SRIO_TX_CH,
+ /** CPPI SRIO tx channel start range*/
+ CPPI_SRIO_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI SRIO tx channel end range */
+ CPPI_SRIO_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI SRIO rx channels */
+ RM_RESOURCE_CPPI_SRIO_RX_CH,
+ /** CPPI SRIO rx channel start range*/
+ CPPI_SRIO_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI SRIO rx channel end range */
+ CPPI_SRIO_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI SRIO rx flows */
+ RM_RESOURCE_CPPI_SRIO_FLOW,
+ /** CPPI SRIO rx flow start range*/
+ CPPI_SRIO_FLOW_DEFAULT_START_RANGE,
+ /** CPPI SRIO rx flow end range */
+ CPPI_SRIO_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI AIF tx channels */
+ RM_RESOURCE_CPPI_AIF_TX_CH,
+ /** CPPI AIF tx channel start range*/
+ CPPI_AIF_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI AIF tx channel end range */
+ CPPI_AIF_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI AIF rx channels */
+ RM_RESOURCE_CPPI_AIF_RX_CH,
+ /** CPPI AIF rx channel start range*/
+ CPPI_AIF_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI AIF rx channel end range */
+ CPPI_AIF_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI AIF rx flows */
+ RM_RESOURCE_CPPI_AIF_FLOW,
+ /** CPPI AIF rx flow start range*/
+ CPPI_AIF_FLOW_DEFAULT_START_RANGE,
+ /** CPPI AIF rx flow end range */
+ CPPI_AIF_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A tx channels */
+ RM_RESOURCE_CPPI_FFTC_A_TX_CH,
+ /** CPPI FFTC_A tx channel start range*/
+ CPPI_FFTC_A_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A tx channel end range */
+ CPPI_FFTC_A_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A rx channels */
+ RM_RESOURCE_CPPI_FFTC_A_RX_CH,
+ /** CPPI FFTC_A rx channel start range*/
+ CPPI_FFTC_A_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A rx channel end range */
+ CPPI_FFTC_A_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A rx flows */
+ RM_RESOURCE_CPPI_FFTC_A_FLOW,
+ /** CPPI FFTC_A rx flow start range*/
+ CPPI_FFTC_A_FLOW_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A rx flow end range */
+ CPPI_FFTC_A_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B tx channels */
+ RM_RESOURCE_CPPI_FFTC_B_TX_CH,
+ /** CPPI FFTC_B tx channel start range*/
+ CPPI_FFTC_B_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B tx channel end range */
+ CPPI_FFTC_B_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B rx channels */
+ RM_RESOURCE_CPPI_FFTC_B_RX_CH,
+ /** CPPI FFTC_B rx channel start range*/
+ CPPI_FFTC_B_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B rx channel end range */
+ CPPI_FFTC_B_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B rx flows */
+ RM_RESOURCE_CPPI_FFTC_B_FLOW,
+ /** CPPI FFTC_B rx flow start range*/
+ CPPI_FFTC_B_FLOW_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B rx flow end range */
+ CPPI_FFTC_B_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI PASS tx channels */
+ RM_RESOURCE_CPPI_PASS_TX_CH,
+ /** CPPI PASS tx channel start range*/
+ CPPI_PASS_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI PASS tx channel end range */
+ CPPI_PASS_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI PASS rx channels */
+ RM_RESOURCE_CPPI_PASS_RX_CH,
+ /** CPPI PASS rx channel start range*/
+ CPPI_PASS_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI PASS rx channel end range */
+ CPPI_PASS_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI PASS rx flows */
+ RM_RESOURCE_CPPI_PASS_FLOW,
+ /** CPPI PASS rx flow start range*/
+ CPPI_PASS_FLOW_DEFAULT_START_RANGE,
+ /** CPPI PASS rx flow end range */
+ CPPI_PASS_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS tx channels */
+ RM_RESOURCE_CPPI_QMSS_TX_CH,
+ /** CPPI QMSS tx channel start range*/
+ CPPI_QMSS_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI QMSS tx channel end range */
+ CPPI_QMSS_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS rx channels */
+ RM_RESOURCE_CPPI_QMSS_RX_CH,
+ /** CPPI QMSS rx channel start range*/
+ CPPI_QMSS_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI QMSS rx channel end range */
+ CPPI_QMSS_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS rx flows */
+ RM_RESOURCE_CPPI_QMSS_FLOW,
+ /** CPPI QMSS rx flow start range*/
+ CPPI_QMSS_FLOW_DEFAULT_START_RANGE,
+ /** CPPI QMSS rx flow end range */
+ CPPI_QMSS_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI BCP tx channels */
+ RM_RESOURCE_CPPI_BCP_TX_CH,
+ /** CPPI BCP tx channel start range*/
+ CPPI_BCP_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI BCP tx channel end range */
+ CPPI_BCP_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI BCP rx channels */
+ RM_RESOURCE_CPPI_BCP_RX_CH,
+ /** CPPI BCP rx channel start range*/
+ CPPI_BCP_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI BCP rx channel end range */
+ CPPI_BCP_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI BCP rx flows */
+ RM_RESOURCE_CPPI_BCP_FLOW,
+ /** CPPI BCP rx flow start range*/
+ CPPI_BCP_FLOW_DEFAULT_START_RANGE,
+ /** CPPI BCP rx flow end range */
+ CPPI_BCP_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /* PA Resource Definitions */
+
+ {
+ /** DSP QMSS Firmware access */
+ RM_RESOURCE_PA_FIRMWARE,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP PA Look-up entry tables */
+ RM_RESOURCE_PA_LUT_ENTRY,
+ /** PA Look-up entry start range*/
+ PA_LUT_ENTRY_DEFAULT_START_RANGE,
+ /** PA Look-up entry end range */
+ PA_LUT_ENTRY_DEFAULT_END_RANGE,
+ /** Full init permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /* Final entry structure for RM to find the last entry of resource table */
+
+ {
+ /** Final entry */
+ RM_RESOURCE_FINAL_ENTRY,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** No init permissions */
+ 0u,
+ /** No use permissions */
+ 0u,
+ },
+
+ /* Extra entries added to avoid a cache invalidate wiping out data placed after array
+ * Seven extra entries covers an extra cache line */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 1 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 2 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 3 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 4 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 5 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 6 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u} /* extra entry: 7 */
+};
+
+/**
+@}
+*/
+
diff --git a/resource_table/dsp_plus_arm_resource_table.c b/resource_table/dsp_plus_arm_resource_table.c
--- /dev/null
@@ -0,0 +1,808 @@
+/**
+ * @file tci6614_resource_table.c
+ *
+ * @brief
+ * This file contains the resource table for the TMDXEVM6614LXE.
+ *
+ * Resources in this file are shared between the DSP and ARM. This file can
+ * be modified by system integrators but please ensure that any modification
+ * is inline with Linux Device Tree.
+ *
+ * The file is created to give the DSP access to all system resources except
+ * the resources specified by 'default' Linux device tree.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* Resource table defines */
+#include <ti/drv/rm/resource_table_defs.h>
+
+/* CSL Include */
+#include <ti/csl/csl_qm_queue.h>
+
+/** @addtogroup RM_LLD_RESOURCE_TABLE
+@{
+*/
+
+/** @brief QMSS DPSP default start and end ranges */
+#define QMSS_PDSP_DEFAULT_START_RANGE (0u)
+#define QMSS_PDSP_DEFAULT_END_RANGE (2u)
+/** @brief QMSS queue default start and end ranges */
+#define QMSS_QUEUE_DEFAULT_START_RANGE (0u)
+#define QMSS_QUEUE_DEFAULT_END_RANGE (8192u)
+/** @brief QMSS memory region default start and end ranges */
+#define QMSS_MEM_REGION_DEFAULT_START_RANGE (0u)
+#define QMSS_MEM_REGION_DEFAULT_END_RANGE (19u)
+/** @brief QMSS Linking RAM default start and end ranges */
+#define QMSS_LINK_RAM_DEFAULT_START_RANGE (0x00000000)
+#define QMSS_LINK_RAM_DEFAULT_END_RANGE (0xFFFFFFFF)
+/** @brief QMSS Accumulator channels default start and end ranges */
+#define QMSS_ACCUM_CH_DEFAULT_START_RANGE (0u)
+#define QMSS_ACCUM_CH_DEFAULT_END_RANGE (47u)
+/** @brief QMSS QOS clusters default start and end ranges */
+#define QMSS_QOS_CLUSTER_DEFAULT_START_RANGE (0u)
+#define QMSS_QOS_CLUSTER_DEFAULT_END_RANGE (7u)
+/** @brief QMSS QOS queue default start and end ranges */
+#define QMSS_QOS_QUEUE_DEFAULT_START_RANGE (0u)
+#define QMSS_QOS_QUEUE_DEFAULT_END_RANGE (63u)
+
+/** @brief CPPI SRIO tx channels default start and end ranges */
+#define CPPI_SRIO_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_TX_CH_DEFAULT_END_RANGE (15u)
+/** @brief CPPI SRIO rx channels default start and end ranges */
+#define CPPI_SRIO_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_RX_CH_DEFAULT_END_RANGE (15u)
+/** @brief CPPI SRIO rx flows default start and end ranges */
+#define CPPI_SRIO_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_FLOW_DEFAULT_END_RANGE (19u)
+/** @brief CPPI AIF tx channels default start and end ranges */
+#define CPPI_AIF_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_TX_CH_DEFAULT_END_RANGE (128u)
+/** @brief CPPI AIF rx channels default start and end ranges */
+#define CPPI_AIF_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_RX_CH_DEFAULT_END_RANGE (128u)
+/** @brief CPPI AIF rx flows default start and end ranges */
+#define CPPI_AIF_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_FLOW_DEFAULT_END_RANGE (128u)
+/** @brief CPPI FFTC_A tx channels default start and end ranges */
+#define CPPI_FFTC_A_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_TX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_A rx channels default start and end ranges */
+#define CPPI_FFTC_A_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_RX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_A rx flows default start and end ranges */
+#define CPPI_FFTC_A_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_FLOW_DEFAULT_END_RANGE (7u)
+/** @brief CPPI FFTC_B tx channels default start and end ranges */
+#define CPPI_FFTC_B_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_TX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_B rx channels default start and end ranges */
+#define CPPI_FFTC_B_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_RX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_B rx flows default start and end ranges */
+#define CPPI_FFTC_B_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_FLOW_DEFAULT_END_RANGE (7u)
+/** @brief CPPI PASS tx channels default start and end ranges */
+#define CPPI_PASS_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_TX_CH_DEFAULT_END_RANGE (8u)
+/** @brief CPPI PASS rx channels default start and end ranges */
+#define CPPI_PASS_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_RX_CH_DEFAULT_END_RANGE (23u)
+/** @brief CPPI PASS rx flows default start and end ranges */
+#define CPPI_PASS_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_FLOW_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS tx channels default start and end ranges */
+#define CPPI_QMSS_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_TX_CH_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS rx channels default start and end ranges */
+#define CPPI_QMSS_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_RX_CH_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS rx flows default start and end ranges */
+#define CPPI_QMSS_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_FLOW_DEFAULT_END_RANGE (63u)
+/** @brief CPPI BCP tx channels default start and end ranges */
+#define CPPI_BCP_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_TX_CH_DEFAULT_END_RANGE (7u)
+/** @brief CPPI BCP rx channels default start and end ranges */
+#define CPPI_BCP_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_RX_CH_DEFAULT_END_RANGE (7u)
+/** @brief CPPI BCP rx flows default start and end ranges */
+#define CPPI_BCP_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_FLOW_DEFAULT_END_RANGE (63u)
+
+/** @brief PA LUT entry default start and end ranges */
+#define PA_LUT_ENTRY_DEFAULT_START_RANGE (0u)
+#define PA_LUT_ENTRY_DEFAULT_END_RANGE (4u)
+
+/** @brief ARM Linux General Purpose Queue range (Derived from the device tree) */
+#define ARM_LINUX_GENERAL_PURPOSE_QUEUE_BASE 4000
+#define ARM_LINUX_GENERAL_PURPOSE_NUM_QUEUES 64
+
+#define ARM_LINUX_INFRASTRUCTURE_NUM_QUEUES 12
+#define ARM_LINUX_CPPI_QMSS_TX_CH_NUM 12
+#define ARM_LINUX_CPPI_QMSS_RX_CH_NUM 12
+#define ARM_LINUX_CPPI_QMSS_FLOW 12
+
+/** @brief ARM Linux UDMA driver Low priority accumulator queue and channel range
+ * ARM UDMA driver uses:
+ * 0-127 low priority accumulator queues
+ * 32-35 low priority accumulator channels
+ * 728-735 high priority accumulator queues
+ * 672 SRIO queue for RapidIO
+ * 24-31 high priority accumulator channels
+ */
+#define ARM_LINUX_LOW_PRIO_ACCUM_QUEUES_NUM 128
+#define ARM_LINUX_LOW_PRIO_ACCUM_CH_BASE 32
+#define ARM_LINUX_LOW_PRIO_ACCUM_CH_NUM 4
+#define ARM_LINUX_HIGH_PRIO_ACCUM_QUEUES_BASE 728
+#define ARM_LINUX_HIGH_PRIO_ACCUM_CH_BASE 24
+
+/** @brief ARM Linux General Purpose Queue range (Derived from the device tree) */
+#define ARM_LINUX_MEMORY_REGION_BASE 12
+#define ARM_LINUX_MEMORY_REGION_NUMBER 3
+
+/** @brief ARM Linux SRIO Queues for RapidIO (Derived from the device tree) */
+#define ARM_LINUX_RAPIDIO_QUEUE_NUM 1
+
+/** @brief RM LLD resource table permissions
+ * Must be cache line aligned. Select pragma format based on language */
+#ifdef __cplusplus
+#pragma DATA_ALIGN (128)
+#else
+#pragma DATA_ALIGN (rmResourceTable, 128)
+#endif
+const Rm_Resource rmResourceTable[] =
+{
+ /* Magic Number structure to verify RM can read the resource table */
+ {
+ /** DSP QMSS Firmware access */
+ RM_RESOURCE_MAGIC_NUMBER,
+ /** No start range */
+ 0u,
+ /** No end range */
+ 0u,
+ /** No init permissions */
+ 0u,
+ /** No use permissions */
+ 0u,
+ },
+
+ /* QMSS Resource Definitions */
+
+ /******************************************************************************
+ * DSP has all access to the linking RAM indexes.
+ ******************************************************************************/
+ {
+ /** DSP QMSS Linking RAM access */
+ RM_RESOURCE_QMSS_LINKING_RAM,
+ /** Linking RAM start range*/
+ QMSS_LINK_RAM_DEFAULT_START_RANGE,
+ /** Linking RAM end range */
+ QMSS_LINK_RAM_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /*******************************************************************************
+ * The Queues are divided as follows:
+ * - ARM gets low priority accumulator queues 0-127
+ * - AIF, FFTC-A, FFTC-B and BCP queues are completely owned by the DSP and
+ * this should never be changed.
+ * - PASS Queues are actually shared and both ARM & DSP will be using these
+ * queues.
+ * - All INTC (Direct Interrupt Queues) are owned by the DSP.
+ * - All Accumulator Queues are owned by the DSP.
+ * - All Starvation Queues are owned by the DSP.
+ * - SRIO queue 672 is ARM's.
+ * - High priority accumulator queues 728-735 are ARM, the rest are DSP
+ * - Account for the Linux General Purpose Queue usage and give all other
+ * general purpose queues to the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS queue access: Low priority queues 128-511 are owned by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_LOW_PRIORITY_QUEUE_BASE + ARM_LINUX_LOW_PRIO_ACCUM_QUEUES_NUM,
+ /** Queue end range */
+ QMSS_LOW_PRIORITY_QUEUE_BASE + QMSS_MAX_LOW_PRIORITY_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: AIF Queues are owned by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_AIF_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_AIF_QUEUE_BASE + QMSS_MAX_AIF_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: PASS Queues are actually shared between the DSP and ARM */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_PASS_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_PASS_QUEUE_BASE + QMSS_MAX_PASS_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: All the Direct Interrupt Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_INTC_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_INTC_QUEUE_BASE + QMSS_MAX_INTC_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: SRIO Queues 673 - 687 are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_SRIO_QUEUE_BASE + ARM_LINUX_RAPIDIO_QUEUE_NUM,
+ /** Queue end range */
+ QMSS_SRIO_QUEUE_BASE + QMSS_MAX_SRIO_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: FFTC-A Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_FFTC_A_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_FFTC_A_QUEUE_BASE + QMSS_MAX_FFTC_A_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: FFTC-B Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_FFTC_B_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_FFTC_B_QUEUE_BASE + QMSS_MAX_FFTC_B_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: BCP Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_BCP_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_BCP_QUEUE_BASE + QMSS_MAX_BCP_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: The first 24 queues are used by the DSP. The remaining are
+ * used by ARM Linux*/
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_HIGH_PRIORITY_QUEUE_BASE,
+ /** Queue end range */
+ ARM_LINUX_HIGH_PRIO_ACCUM_QUEUES_BASE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: All the starvation queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_STARVATION_COUNTER_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_STARVATION_COUNTER_QUEUE_BASE + QMSS_MAX_STARVATION_COUNTER_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: Infrastructure Queues reserved by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_INFRASTRUCTURE_QUEUE_BASE + ARM_LINUX_INFRASTRUCTURE_NUM_QUEUES,
+ /** Queue end range */
+ QMSS_INFRASTRUCTURE_QUEUE_BASE + QMSS_MAX_INFRASTRUCTURE_QUEUE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: General Purpose Queues reserved by the DSP */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_GENERAL_PURPOSE_QUEUE_BASE,
+ /** Queue end range */
+ ARM_LINUX_GENERAL_PURPOSE_QUEUE_BASE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: General Purpose Queues reserved by the DSP */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ ARM_LINUX_GENERAL_PURPOSE_QUEUE_BASE + ARM_LINUX_GENERAL_PURPOSE_NUM_QUEUES,
+ /** Queue end range */
+ QMSS_QUEUE_DEFAULT_END_RANGE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * ARM has access to a certain number of memory regions while all other memory
+ * regions are assigned to the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS Memory Region */
+ RM_RESOURCE_QMSS_MEMORY_REGION,
+ /** Memory Region start range*/
+ QMSS_MEM_REGION_DEFAULT_START_RANGE,
+ /** Memory Region end range */
+ ARM_LINUX_MEMORY_REGION_BASE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS Memory Region */
+ RM_RESOURCE_QMSS_MEMORY_REGION,
+ /** Memory Region start range*/
+ ARM_LINUX_MEMORY_REGION_BASE + ARM_LINUX_MEMORY_REGION_NUMBER,
+ /** Memory Region end range */
+ QMSS_MEM_REGION_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * The accumulator channels are divided between the DSP and ARM Linux.
+ * - channels 0-23 are DSPs
+ * - channels 24-35 are ARM Linux
+ * - channels 36-47 are DSPs
+ ******************************************************************************/
+ {
+ /** DSP QMSS high priority accumulator channels 0-19 */
+ RM_RESOURCE_QMSS_ACCUMULATOR_CH,
+ /** Accumulator channel start range 0 */
+ QMSS_ACCUM_CH_DEFAULT_START_RANGE,
+ /** Accumulator channel end range 23 */
+ ARM_LINUX_HIGH_PRIO_ACCUM_CH_BASE - 1,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS low priority accumulator channels 36-47 */
+ RM_RESOURCE_QMSS_ACCUMULATOR_CH,
+ /** Accumulator channel start range 36 */
+ ARM_LINUX_LOW_PRIO_ACCUM_CH_BASE + ARM_LINUX_LOW_PRIO_ACCUM_CH_NUM,
+ /** Accumulator channel end range 47 */
+ QMSS_ACCUM_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * QOS PDSP Timers are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS QOS PDSP Timer */
+ RM_RESOURCE_QMSS_QOS_PDSP_TIMER,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * The QOS Queues & Clusters are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS QOS clusters */
+ RM_RESOURCE_QMSS_QOS_CLUSTER,
+ /** QOS cluster start range*/
+ QMSS_QOS_CLUSTER_DEFAULT_START_RANGE,
+ /** QOS cluster end range */
+ QMSS_QOS_CLUSTER_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP QMSS QOS queues */
+ RM_RESOURCE_QMSS_QOS_QUEUE,
+ /** QOS queues start range*/
+ QMSS_QOS_QUEUE_DEFAULT_START_RANGE,
+ /** QOS queues end range */
+ QMSS_QOS_QUEUE_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /* CPPI Resource Definitions */
+
+ /******************************************************************************
+ * All SRIO resources are currently owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI SRIO tx channels */
+ RM_RESOURCE_CPPI_SRIO_TX_CH,
+ /** CPPI SRIO tx channel start range*/
+ CPPI_SRIO_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI SRIO tx channel end range */
+ CPPI_SRIO_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI SRIO rx channels */
+ RM_RESOURCE_CPPI_SRIO_RX_CH,
+ /** CPPI SRIO rx channel start range*/
+ CPPI_SRIO_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI SRIO rx channel end range */
+ CPPI_SRIO_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI SRIO rx flows */
+ RM_RESOURCE_CPPI_SRIO_FLOW,
+ /** CPPI SRIO rx flow start range*/
+ CPPI_SRIO_FLOW_DEFAULT_START_RANGE,
+ /** CPPI SRIO rx flow end range */
+ CPPI_SRIO_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * All AIF2 resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI AIF tx channels */
+ RM_RESOURCE_CPPI_AIF_TX_CH,
+ /** CPPI AIF tx channel start range*/
+ CPPI_AIF_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI AIF tx channel end range */
+ CPPI_AIF_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI AIF rx channels */
+ RM_RESOURCE_CPPI_AIF_RX_CH,
+ /** CPPI AIF rx channel start range*/
+ CPPI_AIF_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI AIF rx channel end range */
+ CPPI_AIF_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI AIF rx flows */
+ RM_RESOURCE_CPPI_AIF_FLOW,
+ /** CPPI AIF rx flow start range*/
+ CPPI_AIF_FLOW_DEFAULT_START_RANGE,
+ /** CPPI AIF rx flow end range */
+ CPPI_AIF_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * All FFTC-A resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI FFTC_A tx channels */
+ RM_RESOURCE_CPPI_FFTC_A_TX_CH,
+ /** CPPI FFTC_A tx channel start range*/
+ CPPI_FFTC_A_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A tx channel end range */
+ CPPI_FFTC_A_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A rx channels */
+ RM_RESOURCE_CPPI_FFTC_A_RX_CH,
+ /** CPPI FFTC_A rx channel start range*/
+ CPPI_FFTC_A_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A rx channel end range */
+ CPPI_FFTC_A_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A rx flows */
+ RM_RESOURCE_CPPI_FFTC_A_FLOW,
+ /** CPPI FFTC_A rx flow start range*/
+ CPPI_FFTC_A_FLOW_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A rx flow end range */
+ CPPI_FFTC_A_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * All FFTC-B resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI FFTC_B tx channels */
+ RM_RESOURCE_CPPI_FFTC_B_TX_CH,
+ /** CPPI FFTC_B tx channel start range*/
+ CPPI_FFTC_B_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B tx channel end range */
+ CPPI_FFTC_B_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B rx channels */
+ RM_RESOURCE_CPPI_FFTC_B_RX_CH,
+ /** CPPI FFTC_B rx channel start range*/
+ CPPI_FFTC_B_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B rx channel end range */
+ CPPI_FFTC_B_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B rx flows */
+ RM_RESOURCE_CPPI_FFTC_B_FLOW,
+ /** CPPI FFTC_B rx flow start range*/
+ CPPI_FFTC_B_FLOW_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B rx flow end range */
+ CPPI_FFTC_B_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * All PASS Tx and Rx channels are allocated to the ARM.
+ * PASS Flow 30 and 31 is allocated to ARM
+ ******************************************************************************/
+ {
+ /** DSP CPPI PASS rx flows */
+ RM_RESOURCE_CPPI_PASS_FLOW,
+ /** CPPI PASS rx flow start range*/
+ CPPI_PASS_FLOW_DEFAULT_START_RANGE,
+ /** CPPI PASS rx flow end range */
+ CPPI_PASS_FLOW_DEFAULT_END_RANGE - 2,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /*******************************************************************************
+ * The CPPI Transmit and Receive Channels are divided as follows:-
+ * - CPPI Tx Channel 0 is given to ARM
+ * - CPPI Rx Channel 0 is given to ARM
+ * - CPPI Transmit Flow 0 is given to ARM (Used by Virtual Eth Driver)
+ * - All other CPPI Tx & Rx Channels and flows are for the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI QMSS tx channels */
+ RM_RESOURCE_CPPI_QMSS_TX_CH,
+ /** CPPI QMSS tx channel start range*/
+ CPPI_QMSS_TX_CH_DEFAULT_START_RANGE + ARM_LINUX_CPPI_QMSS_TX_CH_NUM,
+ /** CPPI QMSS tx channel end range */
+ CPPI_QMSS_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS rx channels */
+ RM_RESOURCE_CPPI_QMSS_RX_CH,
+ /** CPPI QMSS rx channel start range*/
+ CPPI_QMSS_RX_CH_DEFAULT_START_RANGE + ARM_LINUX_CPPI_QMSS_RX_CH_NUM,
+ /** CPPI QMSS rx channel end range */
+ CPPI_QMSS_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS rx flows */
+ RM_RESOURCE_CPPI_QMSS_FLOW,
+ /** CPPI QMSS rx flow start range*/
+ CPPI_QMSS_FLOW_DEFAULT_START_RANGE + ARM_LINUX_CPPI_QMSS_FLOW,
+ /** CPPI QMSS rx flow end range */
+ CPPI_QMSS_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /******************************************************************************
+ * All BCP resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI BCP tx channels */
+ RM_RESOURCE_CPPI_BCP_TX_CH,
+ /** CPPI BCP tx channel start range*/
+ CPPI_BCP_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI BCP tx channel end range */
+ CPPI_BCP_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI BCP rx channels */
+ RM_RESOURCE_CPPI_BCP_RX_CH,
+ /** CPPI BCP rx channel start range*/
+ CPPI_BCP_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI BCP rx channel end range */
+ CPPI_BCP_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+ {
+ /** DSP CPPI BCP rx flows */
+ RM_RESOURCE_CPPI_BCP_FLOW,
+ /** CPPI BCP rx flow start range*/
+ CPPI_BCP_FLOW_DEFAULT_START_RANGE,
+ /** CPPI BCP rx flow end range */
+ CPPI_BCP_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /* PA Resource Definitions */
+
+ /*******************************************************************************
+ * PA LUT Rules: LUT1-0 is owned by the ARM all else by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP PA Look-up entry tables */
+ RM_RESOURCE_PA_LUT_ENTRY,
+ /** PA Look-up entry start range*/
+ PA_LUT_ENTRY_DEFAULT_START_RANGE + 1,
+ /** PA Look-up entry end range */
+ PA_LUT_ENTRY_DEFAULT_END_RANGE,
+ /** Full init permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ /** Full use permissions for all DSPs */
+ RM_RESOURCE_ALL_DSPS_FULL_PERMS,
+ },
+
+ /* Final entry structure for RM to find the last entry of resource table */
+
+ {
+ /** Final entry */
+ RM_RESOURCE_FINAL_ENTRY,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** No init permissions */
+ 0u,
+ /** No use permissions */
+ 0u,
+ },
+
+ /* Extra entries added to avoid a cache invalidate wiping out data placed after array
+ * Seven extra entries covers an extra cache line */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 1 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 2 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 3 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 4 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 5 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 6 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u} /* extra entry: 7 */
+};
+
+/**
+@}
+*/
+
+
diff --git a/rmver.h b/resource_table/shared_resources.h
similarity index 56%
rename from rmver.h
rename to resource_table/shared_resources.h
index e3be464baa5d846466ca270d54aa7cd9abbcced8..04adca3413c5adec3202eed513bd76d5f05c2517 100644 (file)
rename from rmver.h
rename to resource_table/shared_resources.h
index e3be464baa5d846466ca270d54aa7cd9abbcced8..04adca3413c5adec3202eed513bd76d5f05c2517 100644 (file)
--- a/rmver.h
-#ifndef _RMVER_H
-#define _RMVER_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ============================================================= */
/**
- * @file rmver.h
+ * @file shared_resources.h
*
- * path ti/drv/rm/rmver.h
+ * @brief
+ * This file specifies resources that are shared between the ARM and DSP.
*
- * @brief Resource Manager LLD Version Definitions
+ * The resource table specifies resources that are useable by the DSP to the RM LLD.
+ * This file is used to inform DSP applications of resources which are shared with the ARM
+ * out of the useable resources specified in the resource table.
*
- * ============================================================
- * Copyright (c) Texas Instruments Incorporated 2009-2012
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
+ * \par
*/
-/**
- * @brief This is the RM LLD Version. Versions numbers are encoded in the following
- * format:
- * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
- */
-#define RM_LLD_VERSION_ID (0x0100000B)
-
-/**
- * @brief This is the version string which describes the RM LLD along with the
- * date and build information.
- */
-#define RM_LLD_VERSION_STR "RM LLD Revision: 01.00.00.11"
-
+/** @addtogroup RM_LLD_SHARED_RESOURCES
+@{
+*/
-#ifdef __cplusplus
-}
-#endif
-
+/** @brief Default NETFP fail route configuration flow ID. When there is no match with the
+ NETFP rules the failed packets are passed to the ARM. The value is currently
+ specified in the Linux device tree. Any modifications in the Linux device tree
+ need to be synchronized with the modifications here. */
+#define RM_SHARED_NETFP_FAIL_RT_FLOW_ID (30u)
+/** @brief Default NETFP fail route configuration queue number. When there is no match with the
+ NETFP rules the failed packets are passed to the ARM. The value is currently
+ specified in the Linux device tree. Any modifications in the Linux device tree
+ need to be synchronized with the modifications here. */
+#define RM_SHARED_NETFP_FAIL_RT_FLOW_ID (650u)
-#endif /* _RMVER_H */
+/**
+@}
+*/
diff --git a/resource_table_defs.h b/resource_table_defs.h
--- /dev/null
+++ b/resource_table_defs.h
@@ -0,0 +1,191 @@
+/**
+ * @file resource_table_defs.h
+ *
+ * @brief
+ * This file defines the identifiers used to populate the resource table used
+ * by the RM LLD to divy resources.
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2012 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+#ifndef __RESOURCE_TABLE_DEFS_H__
+#define __RESOURCE_TABLE_DEFS_H__
+
+/* c99 include */
+#include <stdint.h>
+
+/**
+@addtogroup RM_LLD_RESOURCE_TABLE
+@{
+*/
+
+/** RM LLD Resource Table Resource Identifiers */
+/** This value should be first entry in the resource table. Used to verify RM can read the resource table. */
+#define RM_RESOURCE_MAGIC_NUMBER (0x76543210)
+/** This value should be last entry in the resource table. Used by RM to find last entry in resource table. */
+#define RM_RESOURCE_FINAL_ENTRY (0xFFFFFFFF)
+
+/** Start of QMSS resource identifiers */
+#define RM_RESOURCE_QMSS_BASE 0
+/** QMSS Firmware PDSP write permissions */
+#define RM_RESOURCE_QMSS_FIRMWARE_PDSP (RM_RESOURCE_QMSS_BASE+1)
+/** QMSS queues. This identifier will be expanded to identify all queue types in the near future */
+#define RM_RESOURCE_QMSS_QUEUE (RM_RESOURCE_QMSS_BASE+2)
+/** QMSS Memory regions */
+#define RM_RESOURCE_QMSS_MEMORY_REGION (RM_RESOURCE_QMSS_BASE+3)
+/** QMSS Linking RAM Control */
+#define RM_RESOURCE_QMSS_LINKING_RAM_CONTROL (RM_RESOURCE_QMSS_BASE+4)
+/** QMSS Linking RAM indices */
+#define RM_RESOURCE_QMSS_LINKING_RAM (RM_RESOURCE_QMSS_BASE+5)
+/** QMSS accumulator channels */
+#define RM_RESOURCE_QMSS_ACCUMULATOR_CH (RM_RESOURCE_QMSS_BASE+6)
+/** QMSS QOS PDSP timer */
+#define RM_RESOURCE_QMSS_QOS_PDSP_TIMER (RM_RESOURCE_QMSS_BASE+7)
+/** QMSS QOS clusters */
+#define RM_RESOURCE_QMSS_QOS_CLUSTER (RM_RESOURCE_QMSS_BASE+8)
+/** QMSS QOS queues */
+#define RM_RESOURCE_QMSS_QOS_QUEUE (RM_RESOURCE_QMSS_BASE+9)
+
+/** Start of CPPI resource identifiers */
+#define RM_RESOURCE_CPPI_BASE 64
+/** CPPI SRIO transmit channel */
+#define RM_RESOURCE_CPPI_SRIO_TX_CH (RM_RESOURCE_CPPI_BASE+1)
+/** CPPI SRIO receive channel */
+#define RM_RESOURCE_CPPI_SRIO_RX_CH (RM_RESOURCE_CPPI_BASE+2)
+/** CPPI SRIO flow */
+#define RM_RESOURCE_CPPI_SRIO_FLOW (RM_RESOURCE_CPPI_BASE+3)
+/** CPPI AIF transmit channel */
+#define RM_RESOURCE_CPPI_AIF_TX_CH (RM_RESOURCE_CPPI_BASE+4)
+/** CPPI AIF receive channel */
+#define RM_RESOURCE_CPPI_AIF_RX_CH (RM_RESOURCE_CPPI_BASE+5)
+/** CPPI AIF flow */
+#define RM_RESOURCE_CPPI_AIF_FLOW (RM_RESOURCE_CPPI_BASE+6)
+/** CPPI FFTC_A transmit channel */
+#define RM_RESOURCE_CPPI_FFTC_A_TX_CH (RM_RESOURCE_CPPI_BASE+7)
+/** CPPI FFTC_A receive channel */
+#define RM_RESOURCE_CPPI_FFTC_A_RX_CH (RM_RESOURCE_CPPI_BASE+8)
+/** CPPI FFTC_A flow */
+#define RM_RESOURCE_CPPI_FFTC_A_FLOW (RM_RESOURCE_CPPI_BASE+9)
+/** CPPI FFTC_B transmit channel */
+#define RM_RESOURCE_CPPI_FFTC_B_TX_CH (RM_RESOURCE_CPPI_BASE+10)
+/** CPPI FFTC_B receive channel */
+#define RM_RESOURCE_CPPI_FFTC_B_RX_CH (RM_RESOURCE_CPPI_BASE+11)
+/** CPPI FFTC_B flow */
+#define RM_RESOURCE_CPPI_FFTC_B_FLOW (RM_RESOURCE_CPPI_BASE+12)
+/** CPPI PASS transmit channel */
+#define RM_RESOURCE_CPPI_PASS_TX_CH (RM_RESOURCE_CPPI_BASE+13)
+/** CPPI PASS receive channel */
+#define RM_RESOURCE_CPPI_PASS_RX_CH (RM_RESOURCE_CPPI_BASE+14)
+/** CPPI PASS flow */
+#define RM_RESOURCE_CPPI_PASS_FLOW (RM_RESOURCE_CPPI_BASE+15)
+/** CPPI QMSS transmit channel */
+#define RM_RESOURCE_CPPI_QMSS_TX_CH (RM_RESOURCE_CPPI_BASE+16)
+/** CPPI QMSS receive channel */
+#define RM_RESOURCE_CPPI_QMSS_RX_CH (RM_RESOURCE_CPPI_BASE+17)
+/** CPPI QMSS flow */
+#define RM_RESOURCE_CPPI_QMSS_FLOW (RM_RESOURCE_CPPI_BASE+18)
+/** CPPI FFTC_C transmit channel */
+#define RM_RESOURCE_CPPI_FFTC_C_TX_CH (RM_RESOURCE_CPPI_BASE+19)
+/** CPPI FFTC_C receive channel */
+#define RM_RESOURCE_CPPI_FFTC_C_RX_CH (RM_RESOURCE_CPPI_BASE+20)
+/** CPPI FFTC_C flow */
+#define RM_RESOURCE_CPPI_FFTC_C_FLOW (RM_RESOURCE_CPPI_BASE+21)
+/** CPPI BCP transmit channel */
+#define RM_RESOURCE_CPPI_BCP_TX_CH (RM_RESOURCE_CPPI_BASE+22)
+/** CPPI BCP receive channel */
+#define RM_RESOURCE_CPPI_BCP_RX_CH (RM_RESOURCE_CPPI_BASE+23)
+/** CPPI BCP flow */
+#define RM_RESOURCE_CPPI_BCP_FLOW (RM_RESOURCE_CPPI_BASE+24)
+
+/** Start of CPPI resource identifiers */
+#define RM_RESOURCE_PA_BASE 128
+/** PA Firmware write permissions */
+#define RM_RESOURCE_PA_FIRMWARE (RM_RESOURCE_PA_BASE+1)
+/** PA look-up table entry */
+#define RM_RESOURCE_PA_LUT_ENTRY (RM_RESOURCE_PA_BASE+2)
+
+/** RM LLD Resource Table Permission Codes */
+/** Init or use permission allowed */
+#define RM_RESOURCE_PERM_DENIED 0x0
+/** Init or use permission denied */
+#define RM_RESOURCE_PERM_ALLOWED 0x1
+
+/** Resource entry flags bitfield DSP shift macro */
+#define RM_RESOURCE_FLAG_DSP_SHIFT(dspNum, perms) \
+ (((uint32_t) perms) << dspNum)
+
+/** Full Permissions - All DSPs can use and initialize resource */
+#define RM_RESOURCE_ALL_DSPS_FULL_PERMS \
+ ((RM_RESOURCE_FLAG_DSP_SHIFT(0, RM_RESOURCE_PERM_ALLOWED)) | \
+ (RM_RESOURCE_FLAG_DSP_SHIFT(1, RM_RESOURCE_PERM_ALLOWED)) | \
+ (RM_RESOURCE_FLAG_DSP_SHIFT(2, RM_RESOURCE_PERM_ALLOWED)) | \
+ (RM_RESOURCE_FLAG_DSP_SHIFT(3, RM_RESOURCE_PERM_ALLOWED)))
+
+/**
+ * @brief Resource Table resource definition structure
+ */
+typedef struct
+{
+ /** Resouce identifier. */
+ uint32_t resourceId;
+ /** Start range for identified resource */
+ uint32_t resourceStart;
+ /** End range for identified resource */
+ uint32_t resourceEnd;
+ /** Resource initialization permission flags
+ * Bits 0 : DSP 0 Permission Bit
+ * Bits 1 : DSP 1 Permission Bit
+ * Bits 2 : DSP 2 Permission Bit
+ * Bits 3 : DSP 3 Permission Bit
+ * Bits 31-8 : UNUSED
+ */
+ uint32_t resourceInitFlags;
+ /** Resource usage permission flags
+ * Bits 0 : DSP 0 Permission Bit
+ * Bits 1 : DSP 1 Permission Bit
+ * Bits 2 : DSP 2 Permission Bit
+ * Bits 3 : DSP 3 Permission Bit
+ * Bits 31-8 : UNUSED
+ */
+ uint32_t resourceUseFlags;
+} Rm_Resource;
+
+/**
+@}
+*/
+
+#endif /* __RESOURCE_TABLE_DEFS_H__ */
+
+
+
diff --git a/rm.h b/rm.h
--- /dev/null
+++ b/rm.h
@@ -0,0 +1,209 @@
+/**
+ * @file rm.h
+ *
+ * @brief
+ * This is the RM LLD include file.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+#ifndef RM_H_
+#define RM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* RM resource table defs include file */
+#include <ti/drv/rm/rmver.h>
+#include <ti/drv/rm/rm_public_lld.h>
+#include <ti/drv/rm/resource_table_defs.h>
+
+/** @mainpage Resource Manager Low Level Driver
+ *
+ * @section intro Introduction
+ *
+ * The Resource Manager low level driver (RM LLD) is designed to provide initialization and permissions checking
+ * for LLD resources. A system integrator can specify DSP permissions for LLD resources within the system.
+ * The resource permissions are stored in the RM LLD and used to validate resource requests from supported LLDs.
+ * Currently, the RM LLD supports permissions for the following LLDs
+ * - QMSS
+ * - CPPI
+ * - PA
+ * For information on the specific resources supported with each LLD please see @ref RM_LLD_RESOURCE_TABLE.
+ *
+ * The system integrator must specify the supported LLD resource permissions for all DSPs prior to compile time.
+ * An array of @ref Rm_Resource objects must be created. Each @ref Rm_Resource entry in the array specifies
+ * a resource type, start and end range for the resource, and the initialization and usage permissions for the
+ * resource for each DSP. For an example resource table definitions please see the @ref rmResourceTable array
+ * defined in the resource_table\ directory. This resource table assigns full initialization and usage permissions
+ * to all DSPs for all supported resources. Please note that the resouce table must start with the
+ * @ref RM_RESOURCE_MAGIC_NUMBER entry and end with the @ref RM_RESOURCE_FINAL_ENTRY. These
+ * first and last entries are used the RM LLD to validate and parse the resource table.
+ *
+ * The RM LLD must be initialized and started prior to all supported LLD initialization and start routines. The
+ * @ref Rm_init function should be invoked, and passed a pointer to the integrator defined resource table, on the
+ * master DSP core in the system. All other DSP cores should invoke the @ref Rm_start API. The @ref Rm_init
+ * function first initializes the internal permission tables to deny all DSPs access to all resources. Next the
+ * @ref Rm_init function parses the resource table provided and copies all specified permissions into the internal
+ * tables. When the permission transfer completes the @ref Rm_init function writes a global synchronization
+ * object which the @ref Rm_start functions are spinning on. The slave cores that have invoked @ref Rm_start
+ * will stop spinning once the global synchronization has been written. At this time @ref Rm_start will invalidate
+ * all internal permission tables so that no further cache invalidate operations need to be performed when
+ * checking resource permissions in the data path. The upfront cache invalidate operation is possible because
+ * the RM LLD does not allow dynamic resource permission modifications. The permissions defined by the system
+ * integrator and loaded during RM initialization are static throughout the system up-time.
+ *
+ * The RM LLD must be registered with a supported LLD in order for the supported LLD to perform resource
+ * permission checks. If the RM LLD is not registered with a supported LLD the LLD will operate as if the RM LLD
+ * is not there. This maintains full backwards compatability with existing applications not using the RM LLD. In order
+ * to register the RM LLD with supported LLDs the following steps should be taken
+ * - Get a @ref Rm_Handle via the @ref Rm_getHandle API on each DSP that uses the RM LLD.
+ * - Register the RM LLD with the supported LLDs by passing the @ref Rm_Handle to the
+ * LLD's <<LLD name>>_startCfg API. Again, this should be performed on all DSP cores using the RM LLD.
+ * Note: The master core for the QMSS LLD should have the @ref Rm_Handle registered via the Qmss_init API.
+ * After registering the RM LLD with supported LLDs all supported LLD resources covered by the RM LLD will invoke
+ * permission check callouts to the RM. A permission denied or approved response will be given back to the
+ * invoking LLD based on the permissions stored in the RM LLD for the resource.
+ *
+ * All internal RM LLD permission tables are placed into a single memory section called ".rm". This memory section
+ * MUST be placed in shared memory (MSMC or DDR). The permission tables are shared between all DSPs utilizing
+ * the RM LLD.
+ *
+ * In summary, the initialization flow if the RM LLD is to be utilized should look like the following:
+ *
+ * Master DSP Core:
+ * - Call @ref Rm_init passing in the system integrator defined resource table
+ * - Call @ref Rm_getHandle
+ * - Call supported LLD _init or _create functions (for QMSS pass the @ref Rm_Handle inside the
+ * Qmss_GlobalConfigParams structure)
+ * - Call supported LLD _startCfg functions passing the @ref Rm_Handle as an argument
+ *
+ * Slave DSP Cores:
+ * - Call @ref Rm_start
+ * - Call @ref Rm_getHandle
+ * - Call supported LLD _start functions (if supported)
+ * - Call supported LLD _startCfg functions passing the @ref Rm_Handle as an argument
+ *
+ */
+
+/* Define RM_LLD_API as a master group in Doxygen format and add all RM LLD API
+ definitions to this group. */
+/** @defgroup RM_LLD_API RM LLD Module API
+ * @{
+ */
+/** @} */
+
+/**
+@defgroup RM_LLD_SYMBOL RM Low Level Driver Symbols Defined
+@ingroup RM_LLD_API
+*/
+/**
+@defgroup RM_LLD_ENUM RM Low Level Driver Enums
+@ingroup RM_LLD_API
+*/
+/**
+@defgroup RM_LLD_RESOURCE_TABLE RM LLD Resource Table Definition Symbols and Structures
+@ingroup RM_LLD_API
+*/
+/**
+@defgroup RM_LLD_SHARED_RESOURCES RM LLD ARM and DSP Shared Resources
+@ingroup RM_LLD_API
+*/
+/**
+@defgroup RM_LLD_DATASTRUCT RM Low Level Driver Data Structures
+@ingroup RM_LLD_API
+*/
+/**
+@defgroup RM_LLD_FUNCTION RM Low Level Driver Functions
+@ingroup RM_LLD_API
+*/
+/**
+@defgroup RM_LLD_OSAL RM Low Level Driver OSAL Functions
+@ingroup RM_LLD_API
+*/
+
+/**
+@addtogroup RM_LLD_SYMBOL
+@{
+*/
+
+/** RM LLD Return And Error Codes */
+/** RM Resource Okay Return Base */
+#define RM_OK 0
+
+/** RM LLD Error Base */
+#define RM_ERROR (-64)
+/** RM LLD failed to populate internal permission tables */
+#define RM_ERROR_PERMISSION_TABLE_POPULATION_FAILED (RM_ERROR-1)
+/** RM LLD Table entry population failure */
+#define RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE (RM_ERROR-2)
+
+/** Master/Slave synchronization defines */
+/** Permissions table not valid */
+#define RM_PERMISSION_TABLE_NOT_VALID 0
+/** Permissions table valid */
+#define RM_PERMISSION_TABLE_VALID 1
+
+/**
+@}
+*/
+
+/** @addtogroup RM_LLD_DATASTRUCT
+@{
+*/
+
+/**
+ * @brief RM Handle for LLDs
+ */
+typedef void *Rm_Handle;
+
+/**
+@}
+*/
+
+/* Exported functions available to application */
+extern Rm_Result Rm_init (const Rm_Resource *rmResourceTable);
+extern Rm_Result Rm_start (void);
+extern Rm_Handle Rm_getHandle(void);
+extern uint32_t Rm_getVersion (void);
+extern const char* Rm_getVersionStr (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RM_H_ */
+
diff --git a/rm_osal.h b/rm_osal.h
--- /dev/null
+++ b/rm_osal.h
@@ -0,0 +1,283 @@
+/**
+ * @file rm_osal.h
+ *
+ * @brief
+ * This is the sample OS Adaptation layer which is used by the RM low level
+ * driver. The OSAL layer can be ported in either of the following
+ * manners to a native OS:
+ *
+ * <b> Approach 1: </b>
+ * @n Use Prebuilt Libraries
+ * - Ensure that the provide an implementation of all
+ * Osal_XXX API for their native OS.
+ * - Link the prebuilt libraries with their application.
+ * - Refer to the "example" directory for an example of this
+ * @n <b> Pros: </b>
+ * - Customers can reuse prebuilt TI provided libraries
+ * @n <b> Cons: </b>
+ * - Level of indirection in the API to get to the actual OS call
+ *
+ * <b> Approach 2: </b>
+ * @n Rebuilt Library
+ * - Create a copy of this file and modify it to directly
+ * inline the native OS calls
+ * - Rebuild the RM low level drivver library; ensure that the Include
+ * path points to the directory where the copy of this file
+ * has been provided.
+ * - Please refer to the "test" directory for an example of this
+ * @n <b> Pros: </b>
+ * - Optimizations can be done to remove the level of indirection
+ * @n <b> Cons: </b>
+ * - RM LLD Libraries need to be rebuilt by the customer.
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2012 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+#ifndef __RM_OSAL_H__
+#define __RM_OSAL_H__
+
+/** @addtogroup RM_LLD_OSAL
+ @{ */
+
+/**********************************************************************
+ ************************* Extern Declarations ************************
+ **********************************************************************/
+
+/* #include <string.h> is here because there used to be
+ * memcpy/memset prototypes here. This #include prevents warnings in
+ * other code that unintentionally worked because of these prototypes
+ */
+#include <string.h>
+
+extern void* Osal_rmMalloc (uint32_t num_bytes);
+extern void Osal_rmFree (void *ptr, uint32_t size);
+extern void* Osal_rmCsEnter (void);
+extern void Osal_rmCsExit (void *CsHandle);
+extern void* Osal_rmMtCsEnter (void);
+extern void Osal_rmMtCsExit (void *CsHandle);
+extern void Osal_rmLog (char *fmt, ... );
+extern void Osal_rmBeginMemAccess (void *ptr, uint32_t size);
+extern void Osal_rmEndMemAccess (void *ptr, uint32_t size);
+
+/**
+ * @brief The macro is used by the RM LLD to allocate memory of specified
+ * size
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void* Osal_rmMalloc (uint32_t numBytes)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Number of bytes to be allocated
+ *
+ * <b> Return Value </b>
+ * @n Pointer to the allocated block size
+ */
+
+#define Rm_osalMalloc Osal_rmMalloc
+
+/**
+ * @brief The macro is used by the RM LLD to free a allocated block of
+ * memory
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_rmFree (void *ptr, uint32_t size)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Pointer to the block of memory to be cleaned up.
+ * @n Size of the allocated memory which is being freed.
+ *
+ * <b> Return Value </b>
+ * @n Not applicable.
+ */
+
+#define Rm_osalFree Osal_rmFree
+
+/**
+ * @brief The macro is used by the RM LLD to provide critical sections to
+ * protect global and shared variables from
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void* Osal_rmCsEnter (void)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n None.
+ *
+ * <b> Return Value </b>
+ * @n Handle used to lock critical section.
+ */
+#define Rm_osalCsEnter Osal_rmCsEnter
+
+/**
+ * @brief The macro is used by the RM LLD to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_rmCsExit (void *CsHandle)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Handle for unlocking critical section.
+ *
+ * <b> Return Value </b>
+ * @n Not applicable.
+ */
+#define Rm_osalCsExit Osal_rmCsExit
+
+/**
+ * @brief The macro is used by the RM LLD to provide critical sections to
+ * protect global and shared variables from
+ *
+ * access from multiple threads on single core
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void* Osal_rmMtCsEnter (void)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n None.
+ *
+ * <b> Return Value </b>
+ * @n Handle used to lock critical section.
+ */
+#define Rm_osalMtCsEnter Osal_rmMtCsEnter
+
+/**
+ * @brief The macro is used by the RM LLD to exit a critical section
+ * protected using Osal_rmMtCsEnter() API.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_rmMtCsExit (void *CsHandle)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Handle for unlocking critical section.
+ *
+ * <b> Return Value </b>
+ * @n Not applicable.
+ */
+#define Rm_osalMtCsExit Osal_rmMtCsExit
+
+/**
+ * @brief The macro is used by the RM LLD to log various
+ * messages.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_rmLog( char *fmt, ... )
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n printf-style format string
+ *
+ * <b> Return Value </b>
+ * @n Not applicable.
+ */
+#define Rm_osalLog Osal_rmLog
+
+/**
+ * @brief The macro is used by the RM LLD to indicate that a block
+ * of memory is about to be accessed. If the memory block is cached then
+ * this indicates that the application would need to ensure that the cache
+ * is updated with the data from the actual memory.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_rmBeginMemAccess (void *ptr, uint32_t size)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Address of memory block.
+ * @n Size of memory block.
+ *
+ * <b> Return Value </b>
+ * @n Not applicable.
+ */
+#define Rm_osalBeginMemAccess Osal_rmBeginMemAccess
+
+/**
+ * @brief The macro is used by the RM LLD to indicate that the block of
+ * memory has finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache are updated
+ * immediately to the actual memory.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_rmEndMemAccess (void *ptr, uint32_t size)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Address of memory block.
+ * @n Size of memory block.
+ *
+ * <b> Return Value </b>
+ * @n Not applicable.
+ */
+#define Rm_osalEndMemAccess Osal_rmEndMemAccess
+
+/**
+@}
+*/
+#endif /* __RM_OSAL_H__ */
+
diff --git a/setupenv.bat b/setupenv.bat
index 81d8837e0e0768c8d3b2f00080ca81b6ce0209c3..988da4948d823494e612fe2d9e13270d8ba0da21 100644 (file)
--- a/setupenv.bat
+++ b/setupenv.bat
\r
IF DEFINED PARTNO GOTO partno_defined\r
@REM Configure the Part Number\r
-set PARTNO=c6678\r
+set PARTNO=keystone2\r
:partno_Defined\r
\r
IF DEFINED PDK_INSTALL_PATH GOTO pdk_defined\r
-set PDK_INSTALL_PATH=c:/Program Files/Texas Instruments/pdk_c6678_1_0_0_17/packages\r
+set PDK_INSTALL_PATH=C:\ti\pdk_keystone2_1_00_00_03\packages\r
:pdk_defined\r
\r
@REM ---------------------------------\r
diff --git a/src/Module.xs b/src/Module.xs
--- /dev/null
+++ b/src/Module.xs
@@ -0,0 +1,46 @@
+/******************************************************************************
+ * FILE PURPOSE: RM LLD Source module specification file.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for the RM LLD source directory.
+ *
+ * Copyright (C) 2012, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+var rmlldFile = [
+ "src/rm.c",
+];
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to build all the components of the RM library
+ **************************************************************************/
+function modBuild()
+{
+ /* Build the libraries for all the targets specified. */
+ for (var targets=0; targets < Build.targets.length; targets++)
+ {
+ var libOptions = {
+ incs: lldIncludePath,
+ };
+
+ libUtility.buildLibrary (libOptions, "ti.drv.rm", Build.targets[targets], rmlldFile);
+ }
+
+ /* Add all the .c files to the release package. */
+ var testFiles = libUtility.listAllFiles (".c", "src", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+
+ /* Add all the .h files to the release package. */
+ var testFiles = libUtility.listAllFiles (".h", "src", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+}
diff --git a/src/rm.c b/src/rm.c
--- /dev/null
+++ b/src/rm.c
@@ -0,0 +1,1442 @@
+/**
+ * @file rm.c
+ *
+ * @brief
+ * This is the Resource Manager Low Level Driver file.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+
+/* c99 include */
+#include <stdint.h>
+#include <stdlib.h>
+
+/* RM includes */
+#include <ti/drv/rm/rm.h>
+#include <ti/drv/rm/rm_public_lld.h>
+#include <ti/drv/rm/resource_table_defs.h>
+#include <ti/drv/rm/include/rm_pvt.h>
+
+/* RM OSAL layer */
+#include <rm_osal.h>
+
+/* CSL includes */
+#include <ti/csl/csl_qm_queue.h>
+
+/**********************************************************************
+ ************************** Globals ***********************************
+ **********************************************************************/
+
+/* Place QMSS PDSP permissions array */
+#pragma DATA_SECTION (rmQmssPdspFirmwarePerms, ".rm");
+#pragma DATA_ALIGN (rmQmssPdspFirmwarePerms, 128)
+Rm_Perms rmQmssPdspFirmwarePerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_FIRMWARE_PDSPS, Rm_Perms)];
+
+/* Place QMSS queue permissions array */
+#pragma DATA_SECTION (rmQmssQueuePerms, ".rm");
+#pragma DATA_ALIGN (rmQmssQueuePerms, 128)
+Rm_Perms rmQmssQueuePerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_QUEUES, Rm_Perms)];
+
+/* Place QMSS memory region permissions array */
+#pragma DATA_SECTION (rmQmssMemRegionPerms, ".rm");
+#pragma DATA_ALIGN (rmQmssMemRegionPerms, 128)
+Rm_Perms rmQmssMemRegionPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_MEM_REGIONS, Rm_Perms)];
+
+/* Place QMSS Linking RAM permissions array */
+#pragma DATA_SECTION (rmQmssLinkingRamPerms, ".rm");
+#pragma DATA_ALIGN (rmQmssLinkingRamPerms, 128)
+Rm_qmssLinkingRamPerms rmQmssLinkingRamPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_LINKING_RAM_RANGES, Rm_qmssLinkingRamPerms)];
+
+/* Place QMSS accumulator channel permissions array */
+#pragma DATA_SECTION (rmQmssAccumChPerms, ".rm");
+#pragma DATA_ALIGN (rmQmssAccumChPerms, 128)
+Rm_Perms rmQmssAccumChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_ACCUM_CH, Rm_Perms)];
+
+/* Place QMSS QOS cluster permissions array */
+#pragma DATA_SECTION (rmQmssQosClusterPerms, ".rm");
+#pragma DATA_ALIGN (rmQmssQosClusterPerms, 128)
+Rm_Perms rmQmssQosClusterPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_QOS_CLUSTER, Rm_Perms)];
+
+/* Place QMSS QOS queue permissions array */
+#pragma DATA_SECTION (rmQmssQosQueuePerms, ".rm");
+#pragma DATA_ALIGN (rmQmssQosQueuePerms, 128)
+Rm_Perms rmQmssQosQueuePerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_QMSS_QOS_QUEUES, Rm_Perms)];
+
+/* Place CPPI SRIO TX channel permissions array */
+#pragma DATA_SECTION (rmCppiSrioTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiSrioTxChPerms, 128)
+Rm_Perms rmCppiSrioTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_SRIO_TX_CH, Rm_Perms)];
+
+#ifdef QMSS_MAX_AIF_QUEUE
+/* Place CPPI AIF TX channel permissions array */
+#pragma DATA_SECTION (rmCppiAifTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiAifTxChPerms, 128)
+Rm_Perms rmCppiAifTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_AIF_TX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+/* Place CPPI FFTC A TX channel permissions array */
+#pragma DATA_SECTION (rmCppiFftcATxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcATxChPerms, 128)
+Rm_Perms rmCppiFftcATxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_A_TX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+/* Place CPPI FFTC B TX channel permissions array */
+#pragma DATA_SECTION (rmCppiFftcBTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcBTxChPerms, 128)
+Rm_Perms rmCppiFftcBTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_B_TX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_PASS_QUEUE
+/* Place CPPI PASS TX channel permissions array */
+#pragma DATA_SECTION (rmCppiPassTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiPassTxChPerms, 128)
+Rm_Perms rmCppiPassTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_PASS_TX_CH, Rm_Perms)];
+#endif
+
+/* Place CPPI QMSS TX channel permissions array */
+#pragma DATA_SECTION (rmCppiQmssTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiQmssTxChPerms, 128)
+Rm_Perms rmCppiQmssTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_QMSS_TX_CH, Rm_Perms)];
+
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+/* Place CPPI FFTC C TX channel permissions array */
+#pragma DATA_SECTION (rmCppiFftcCTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcCTxChPerms, 128)
+Rm_Perms rmCppiFftcCTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_C_TX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_BCP_QUEUE
+/* Place CPPI BCP TX channel permissions array */
+#pragma DATA_SECTION (rmCppiBcpTxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiBcpTxChPerms, 128)
+Rm_Perms rmCppiBcpTxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_BCP_TX_CH, Rm_Perms)];
+#endif
+
+/* Place CPPI SRIO RX channel permissions array */
+#pragma DATA_SECTION (rmCppiSrioRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiSrioRxChPerms, 128)
+Rm_Perms rmCppiSrioRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_SRIO_RX_CH, Rm_Perms)];
+
+#ifdef QMSS_MAX_AIF_QUEUE
+/* Place CPPI AIF RX channel permissions array */
+#pragma DATA_SECTION (rmCppiAifRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiAifRxChPerms, 128)
+Rm_Perms rmCppiAifRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_AIF_RX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+/* Place CPPI FFTC A RX channel permissions array */
+#pragma DATA_SECTION (rmCppiFftcARxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcARxChPerms, 128)
+Rm_Perms rmCppiFftcARxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_A_RX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+/* Place CPPI FFTC B RX channel permissions array */
+#pragma DATA_SECTION (rmCppiFftcBRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcBRxChPerms, 128)
+Rm_Perms rmCppiFftcBRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_B_RX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_PASS_QUEUE
+/* Place CPPI PASS RX channel permissions array */
+#pragma DATA_SECTION (rmCppiPassRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiPassRxChPerms, 128)
+Rm_Perms rmCppiPassRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_PASS_RX_CH, Rm_Perms)];
+#endif
+
+/* Place CPPI QMSS RX channel permissions array */
+#pragma DATA_SECTION (rmCppiQmssRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiQmssRxChPerms, 128)
+Rm_Perms rmCppiQmssRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_QMSS_RX_CH, Rm_Perms)];
+
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+/* Place CPPI FFTC C RX channel permissions array */
+#pragma DATA_SECTION (rmCppiFftcCRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcCRxChPerms, 128)
+Rm_Perms rmCppiFftcCRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_C_RX_CH, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_BCP_QUEUE
+/* Place CPPI BCP RX channel permissions array */
+#pragma DATA_SECTION (rmCppiBcpRxChPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiBcpRxChPerms, 128)
+Rm_Perms rmCppiBcpRxChPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_BCP_RX_CH, Rm_Perms)];
+#endif
+
+/* Place CPPI SRIO flow permissions array */
+#pragma DATA_SECTION (rmCppiSrioFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiSrioFlowPerms, 128)
+Rm_Perms rmCppiSrioFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_SRIO_FLOW, Rm_Perms)];
+
+#ifdef QMSS_MAX_AIF_QUEUE
+/* Place CPPI AIF flow permissions array */
+#pragma DATA_SECTION (rmCppiAifFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiAifFlowPerms, 128)
+Rm_Perms rmCppiAifFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_AIF_FLOW, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+/* Place CPPI FFTC A flow permissions array */
+#pragma DATA_SECTION (rmCppiFftcAFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcAFlowPerms, 128)
+Rm_Perms rmCppiFftcAFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_A_FLOW, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+/* Place CPPI FFTC B flow permissions array */
+#pragma DATA_SECTION (rmCppiFftcBFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcBFlowPerms, 128)
+Rm_Perms rmCppiFftcBFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_B_FLOW, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_PASS_QUEUE
+/* Place CPPI PASS flow permissions array */
+#pragma DATA_SECTION (rmCppiPassFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiPassFlowPerms, 128)
+Rm_Perms rmCppiPassFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_PASS_FLOW, Rm_Perms)];
+#endif
+
+/* Place CPPI QMSS flow permissions array */
+#pragma DATA_SECTION (rmCppiQmssFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiQmssFlowPerms, 128)
+Rm_Perms rmCppiQmssFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_QMSS_FLOW, Rm_Perms)];
+
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+/* Place CPPI FFTC C flow permissions array */
+#pragma DATA_SECTION (rmCppiFftcCFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiFftcCFlowPerms, 128)
+Rm_Perms rmCppiFftcCFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_FFTC_C_FLOW, Rm_Perms)];
+#endif
+
+#ifdef QMSS_MAX_BCP_QUEUE
+/* Place CPPI BCP flow permissions array */
+#pragma DATA_SECTION (rmCppiBcpFlowPerms, ".rm");
+#pragma DATA_ALIGN (rmCppiBcpFlowPerms, 128)
+Rm_Perms rmCppiBcpFlowPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_CPPI_BCP_FLOW, Rm_Perms)];
+#endif
+
+/* Place PA lookup table permissions array */
+#pragma DATA_SECTION (rmPaLutPerms, ".rm");
+#pragma DATA_ALIGN (rmPaLutPerms, 128)
+Rm_Perms rmPaLutPerms[RM_ALIGN_PERMISSIONS_ARRAY(RM_PA_LUT, Rm_Perms)];
+
+/* Rm_init/Rm_start synchronization object. Initialized to 0. */
+#pragma DATA_SECTION (rmGSyncObj, ".rm");
+#pragma DATA_ALIGN (rmGSyncObj, 128)
+Rm_Sync_Obj rmGSyncObj =
+{
+ {
+ RM_PERMISSION_TABLE_NOT_VALID,
+ }
+};
+
+/* Create, populate, and place RM global permissions object */
+#pragma DATA_SECTION (rmGPermsObj, ".rm");
+#pragma DATA_ALIGN (rmGPermsObj, 128)
+Rm_GlobalPermissionsObj rmGPermsObj =
+{
+ {
+ /* qmssPdspFirmwarePerms */
+ &rmQmssPdspFirmwarePerms[0],
+ /* Pointer: qmssQueuePerms */
+ &rmQmssQueuePerms[0],
+ /* Pointer: qmssMemRegionPerms */
+ &rmQmssMemRegionPerms[0],
+ /* qmssLinkRamControlPerms */
+ {
+ 0u,
+ 0u,
+ },
+ /* Pointer: qmssLinkRamPerms */
+ &rmQmssLinkingRamPerms[0],
+ /* Pointer: qmssAccumChPerms */
+ &rmQmssAccumChPerms[0],
+ /* qmssQosPdspTimerPerms */
+ {
+ 0u,
+ 0u,
+ },
+ /* Pointer: qmssQosClusterPerms */
+ &rmQmssQosClusterPerms[0],
+ /* Pointer: qmssQosQueuePerms */
+ &rmQmssQosQueuePerms[0],
+ /* Pointer array: cppiTxChPerms - Must be in same order as DMA objects */
+ {
+ { &rmCppiSrioTxChPerms[0],
+#ifdef QMSS_MAX_AIF_QUEUE
+ &rmCppiAifTxChPerms[0],
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ &rmCppiFftcATxChPerms[0],
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ &rmCppiFftcBTxChPerms[0],
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ &rmCppiPassTxChPerms[0],
+#endif
+ &rmCppiQmssTxChPerms[0],
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ &rmCppiFftcCTxChPerms[0],
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ &rmCppiBcpTxChPerms[0]
+#endif
+ }
+ },
+ /* Pointer array: cppiRxChPerms - Must be in same order as DMA objects */
+ {
+ { &rmCppiSrioRxChPerms[0],
+#ifdef QMSS_MAX_AIF_QUEUE
+ &rmCppiAifRxChPerms[0],
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ &rmCppiFftcARxChPerms[0],
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ &rmCppiFftcBRxChPerms[0],
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ &rmCppiPassRxChPerms[0],
+#endif
+ &rmCppiQmssRxChPerms[0],
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ &rmCppiFftcCRxChPerms[0],
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ &rmCppiBcpRxChPerms[0]
+#endif
+ }
+ },
+ /* Pointer array: cppiFlowPerms - Must be in same order as DMA objects */
+ {
+ { &rmCppiSrioFlowPerms[0],
+#ifdef QMSS_MAX_AIF_QUEUE
+ &rmCppiAifFlowPerms[0],
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ &rmCppiFftcAFlowPerms[0],
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ &rmCppiFftcBFlowPerms[0],
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ &rmCppiPassFlowPerms[0],
+#endif
+ &rmCppiQmssFlowPerms[0],
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ &rmCppiFftcCFlowPerms[0],
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ &rmCppiBcpFlowPerms[0]
+#endif
+ }
+ },
+ /* paFirmwarePerms */
+ {
+ 0u,
+ 0u,
+ },
+ /* Pointer: paLutPerms */
+ &rmPaLutPerms[0],
+ }
+};
+
+/** @brief Global Variable (should be local per DSP) containing LLD RM permission checkers */
+Rm_LldPermCallouts rmPermissionCheckers =
+{
+ Rm_initPermissionChecker,
+ Rm_usePermissionChecker,
+};
+
+/** @brief Global Variable which describes the RM LLD Version Information */
+const char rmLldVersionStr[] = RM_LLD_VERSION_STR ":" __DATE__ ":" __TIME__;
+
+/**********************************************************************
+ ********************** Internal Functions *********************************
+ **********************************************************************/
+
+/**
+ * @b Description
+ * @n
+ * Initialize the permission tables. All resources are intialized to deny all initialization
+ * and usage permissions.
+ *
+ */
+void Rm_permissionTableInit(void)
+{
+ uint16_t resourceIndex;
+ Rm_Perms *resArrayPtr;
+ uint16_t dmaNum;
+ uint16_t dmaTxCh[RM_CPPI_MAX_DMAS] = {RM_CPPI_SRIO_TX_CH,
+#ifdef QMSS_MAX_AIF_QUEUE
+ RM_CPPI_AIF_TX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ RM_CPPI_FFTC_A_TX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ RM_CPPI_FFTC_B_TX_CH,
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ RM_CPPI_PASS_TX_CH,
+#endif
+ RM_CPPI_QMSS_TX_CH,
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ RM_CPPI_FFTC_C_TX_CH,
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ RM_CPPI_BCP_TX_CH
+#endif
+ };
+ uint16_t dmaRxCh[RM_CPPI_MAX_DMAS] = {RM_CPPI_SRIO_RX_CH,
+#ifdef QMSS_MAX_AIF_QUEUE
+ RM_CPPI_AIF_RX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ RM_CPPI_FFTC_A_RX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ RM_CPPI_FFTC_B_RX_CH,
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ RM_CPPI_PASS_RX_CH,
+#endif
+ RM_CPPI_QMSS_RX_CH,
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ RM_CPPI_FFTC_C_RX_CH,
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ RM_CPPI_BCP_RX_CH
+#endif
+ };
+ uint16_t dmaFlow[RM_CPPI_MAX_DMAS] = {RM_CPPI_SRIO_FLOW,
+#ifdef QMSS_MAX_AIF_QUEUE
+ RM_CPPI_AIF_FLOW,
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ RM_CPPI_FFTC_A_FLOW,
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ RM_CPPI_FFTC_B_FLOW,
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ RM_CPPI_PASS_FLOW,
+#endif
+ RM_CPPI_QMSS_FLOW,
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ RM_CPPI_FFTC_C_FLOW,
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ RM_CPPI_BCP_FLOW
+#endif
+ };
+
+ /* QMSS Linking RAM Control */
+ rmGPermsObj.obj.qmssLinkRamControlPerms.initPerms = 0;
+ rmGPermsObj.obj.qmssLinkRamControlPerms.usePerms = 0;
+
+ /* QMSS QOS PDSP Timer */
+ rmGPermsObj.obj.qmssQosPdspTimerPerms.initPerms = 0;
+ rmGPermsObj.obj.qmssQosPdspTimerPerms.usePerms = 0;
+
+ /* PA Firmware */
+ rmGPermsObj.obj.paFirmwarePerms.initPerms = 0;
+ rmGPermsObj.obj.paFirmwarePerms.usePerms = 0;
+
+ /* Writeback the values that were initialized in the global object itself */
+ Rm_osalEndMemAccess ((void *) &rmGPermsObj, sizeof (Rm_GlobalPermissionsObj));
+
+ /* QMSS PDSP Firmware */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_FIRMWARE_PDSPS; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssPdspFirmwarePerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.qmssPdspFirmwarePerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the qmssPdspFirmwarePerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssPdspFirmwarePerms, sizeof (Rm_Perms)*RM_QMSS_FIRMWARE_PDSPS);
+
+ /* QMSS queues */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_QUEUES; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssQueuePerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.qmssQueuePerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the qmssQueuePerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssQueuePerms, sizeof (Rm_Perms)*RM_QMSS_QUEUES);
+
+ /* QMSS memory regions */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_MEM_REGIONS; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssMemRegionPerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.qmssMemRegionPerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the qmssMemRegionPerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssMemRegionPerms, sizeof (Rm_Perms)*RM_QMSS_MEM_REGIONS);
+
+ /* QMSS Linking RAM */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_LINKING_RAM_RANGES; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssLinkRamPerms[resourceIndex].startIndex = RM_QMSS_LINKING_RAM_RANGE_INIT;
+ rmGPermsObj.obj.qmssLinkRamPerms[resourceIndex].endIndex = RM_QMSS_LINKING_RAM_RANGE_INIT;
+ rmGPermsObj.obj.qmssLinkRamPerms[resourceIndex].rangePerms.initPerms = 0;
+ rmGPermsObj.obj.qmssLinkRamPerms[resourceIndex].rangePerms.usePerms = 0;
+ }
+ /* Writeback the qmssLinkRamPerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssLinkRamPerms, sizeof (Rm_Perms)*RM_QMSS_LINKING_RAM_RANGES);
+
+ /* QMSS accumulator channels */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_ACCUM_CH; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssAccumChPerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.qmssAccumChPerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the qmssAccumChPerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssAccumChPerms, sizeof (Rm_Perms)*RM_QMSS_ACCUM_CH);
+
+ /* QMSS QOS Clusters */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_QOS_CLUSTER; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssQosClusterPerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.qmssQosClusterPerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the qmssQosClusterPerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssQosClusterPerms, sizeof (Rm_Perms)*RM_QMSS_QOS_CLUSTER);
+
+ /* QMSS QOS Queues */
+ for (resourceIndex = 0; resourceIndex < RM_QMSS_QOS_QUEUES; resourceIndex++)
+ {
+ rmGPermsObj.obj.qmssQosQueuePerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.qmssQosQueuePerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the qmssQosQueuePerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.qmssQosQueuePerms, sizeof (Rm_Perms)*RM_QMSS_QOS_QUEUES);
+
+ /* CPPI DMA transmit channels */
+ for (dmaNum = 0; dmaNum < RM_CPPI_MAX_DMAS; dmaNum++)
+ {
+ resArrayPtr = rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[dmaNum];
+
+ for (resourceIndex = 0; resourceIndex < dmaTxCh[dmaNum]; resourceIndex++)
+ {
+ resArrayPtr[resourceIndex].initPerms = 0;
+ resArrayPtr[resourceIndex].usePerms = 0;
+ }
+
+ /* Writeback each of the transmit channel arrays */
+ Rm_osalEndMemAccess ((void *) resArrayPtr, sizeof (Rm_Perms)*dmaTxCh[dmaNum]);
+ }
+
+ /* CPPI DMA receive channels */
+ for (dmaNum = 0; dmaNum < RM_CPPI_MAX_DMAS; dmaNum++)
+ {
+ resArrayPtr = rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[dmaNum];
+
+ for (resourceIndex = 0; resourceIndex < dmaRxCh[dmaNum]; resourceIndex++)
+ {
+ resArrayPtr[resourceIndex].initPerms = 0;
+ resArrayPtr[resourceIndex].usePerms = 0;
+ }
+
+ /* Writeback each of the receive channel arrays */
+ Rm_osalEndMemAccess ((void *) resArrayPtr, sizeof (Rm_Perms)*dmaRxCh[dmaNum]);
+ }
+
+ /* CPPI DMA flows */
+ for (dmaNum = 0; dmaNum < RM_CPPI_MAX_DMAS; dmaNum++)
+ {
+ resArrayPtr = rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[dmaNum];
+
+ for (resourceIndex = 0; resourceIndex < dmaFlow[dmaNum]; resourceIndex++)
+ {
+ resArrayPtr[resourceIndex].initPerms = 0;
+ resArrayPtr[resourceIndex].usePerms = 0;
+ }
+
+ /* Writeback each of the flow arrays */
+ Rm_osalEndMemAccess ((void *) resArrayPtr, sizeof (Rm_Perms)*dmaFlow[dmaNum]);
+ }
+
+ /* PA Lookup tables */
+ for (resourceIndex = 0; resourceIndex < RM_PA_LUT; resourceIndex++)
+ {
+ rmGPermsObj.obj.paLutPerms[resourceIndex].initPerms = 0;
+ rmGPermsObj.obj.paLutPerms[resourceIndex].usePerms = 0;
+ }
+ /* Writeback the paLutPerms array */
+ Rm_osalEndMemAccess ((void *) rmGPermsObj.obj.paLutPerms, sizeof (Rm_Perms)*RM_PA_LUT);
+
+}
+
+/**
+ * @b Description
+ * @n
+ * Sets a list of entries in a permissions array to the specified permissions
+ *
+ * @param[in] resourceEntry
+ * The resource entry from the application defined resource table containing
+ * a range of resources and the permissions to assign to them.
+ *
+ * @param[in] rmPermsArray
+ * The permissions array for the resource specified in the resourceEntry.
+ *
+ * @param[in] len
+ * Full length of permissions array for writeback after the permissions have been
+ * transferred.
+ */
+void Rm_setTablePermissions (const Rm_Resource *resourceEntry, Rm_Perms *rmPermsArray, uint32_t len)
+{
+ uint32_t index;
+
+ /* Scan through the resource range filling in the specified permission */
+ for (index = resourceEntry->resourceStart; index < resourceEntry->resourceEnd + 1; index++)
+ {
+ rmPermsArray[index].initPerms = resourceEntry->resourceInitFlags;
+ rmPermsArray[index].usePerms = resourceEntry->resourceUseFlags;
+ }
+
+ Rm_osalEndMemAccess ((void *)rmPermsArray, sizeof (Rm_Perms)* len);
+}
+
+/**
+ * @b Description
+ * @n
+ * Takes an application specified resource table as input and transfers all
+ * resource permissions specified within into the internal resource
+ * permission tables. Upon completion of permission transfer a global
+ * synchronization object is written to sync with slave cores.
+ *
+ * @param[in] rmResourceTable
+ * Application defined resource table containing all resources that should
+ * have permissions set for the DSPs
+ *
+ * @retval
+ * Success - RM_OK
+ * @retval
+ * Failure - RM_ERROR_PERMISSION_TABLE_POPULATION_FAILED
+ */
+Rm_Result Rm_populatePermissionTable(const Rm_Resource *rmResourceTable)
+{
+ const Rm_Resource *resourceEntry;
+ uint16_t linkRamIndex;
+
+ /* Verify resource table can be read by verifying magic number is contained
+ * in first entry of the resource table */
+ resourceEntry = rmResourceTable;
+
+ /* Invalidate the resource */
+ Rm_osalBeginMemAccess ((void *) resourceEntry, sizeof (Rm_Resource));
+ if (resourceEntry->resourceId != RM_RESOURCE_MAGIC_NUMBER)
+ {
+ return RM_ERROR_PERMISSION_TABLE_POPULATION_FAILED;
+ }
+
+ /* Magic number is visible start parsing the resource table and transferring
+ * permissions to the internal permissions tables */
+
+ /* Parse resource table until last entry field is encountered */
+ while (resourceEntry->resourceId != RM_RESOURCE_FINAL_ENTRY)
+ {
+ /* Invalidate the resource */
+ Rm_osalBeginMemAccess ((void *) resourceEntry, sizeof (Rm_Resource));
+
+ /* Populate a permission table based on the resourceId */
+ switch (resourceEntry->resourceId)
+ {
+ case RM_RESOURCE_MAGIC_NUMBER:
+ break;
+
+ case RM_RESOURCE_QMSS_FIRMWARE_PDSP:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_FIRMWARE_PDSPS, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.qmssPdspFirmwarePerms, RM_QMSS_FIRMWARE_PDSPS);
+ break;
+
+ case RM_RESOURCE_QMSS_QUEUE:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_QUEUES, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.qmssQueuePerms, RM_QMSS_QUEUES);
+ break;
+
+ case RM_RESOURCE_QMSS_MEMORY_REGION:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_MEM_REGIONS, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.qmssMemRegionPerms, RM_QMSS_MEM_REGIONS);
+ break;
+
+ case RM_RESOURCE_QMSS_LINKING_RAM_CONTROL:
+ rmGPermsObj.obj.qmssLinkRamControlPerms.initPerms = resourceEntry->resourceInitFlags;
+ rmGPermsObj.obj.qmssLinkRamControlPerms.usePerms = resourceEntry->resourceUseFlags;
+ break;
+
+ case RM_RESOURCE_QMSS_LINKING_RAM:
+ /* Expect Linking RAM ranges to be presented in order */
+
+ /* Find next available unused Linking RAM permissions entry */
+ for (linkRamIndex = 0; linkRamIndex < RM_QMSS_LINKING_RAM_RANGES; linkRamIndex++)
+ {
+ if ((rmGPermsObj.obj.qmssLinkRamPerms[linkRamIndex].startIndex == RM_QMSS_LINKING_RAM_RANGE_INIT) &&
+ (rmGPermsObj.obj.qmssLinkRamPerms[linkRamIndex].endIndex == RM_QMSS_LINKING_RAM_RANGE_INIT))
+ {
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_LINKING_RAM_RANGE_INIT,
+ RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ /* Populate the entry with the Linking RAM resource data */
+ rmGPermsObj.obj.qmssLinkRamPerms[linkRamIndex].startIndex = resourceEntry->resourceStart;
+ rmGPermsObj.obj.qmssLinkRamPerms[linkRamIndex].endIndex = resourceEntry->resourceEnd;
+ rmGPermsObj.obj.qmssLinkRamPerms[linkRamIndex].rangePerms.initPerms = resourceEntry->resourceInitFlags;
+ rmGPermsObj.obj.qmssLinkRamPerms[linkRamIndex].rangePerms.usePerms = resourceEntry->resourceUseFlags;
+
+ Rm_osalEndMemAccess ((void *)&rmGPermsObj.obj.qmssLinkRamPerms[0], sizeof (Rm_Perms)* RM_QMSS_LINKING_RAM_RANGES);
+
+ /* Leave search loop */
+ break;
+ }
+ }
+ break;
+
+ case RM_RESOURCE_QMSS_ACCUMULATOR_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_ACCUM_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.qmssAccumChPerms, RM_QMSS_ACCUM_CH);
+ break;
+
+ case RM_RESOURCE_QMSS_QOS_PDSP_TIMER:
+ rmGPermsObj.obj.qmssQosPdspTimerPerms.initPerms = resourceEntry->resourceInitFlags;
+ rmGPermsObj.obj.qmssQosPdspTimerPerms.usePerms = resourceEntry->resourceUseFlags;
+ break;
+
+ case RM_RESOURCE_QMSS_QOS_CLUSTER:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_QOS_CLUSTER, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.qmssQosClusterPerms, RM_QMSS_QOS_CLUSTER);
+ break;
+
+ case RM_RESOURCE_QMSS_QOS_QUEUE:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_QMSS_QOS_QUEUES, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.qmssQosQueuePerms, RM_QMSS_QOS_QUEUES);
+ break;
+
+ case RM_RESOURCE_CPPI_SRIO_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_SRIO_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_SRIO_DMA_ID], RM_CPPI_SRIO_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_SRIO_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_SRIO_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_SRIO_DMA_ID], RM_CPPI_SRIO_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_SRIO_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_SRIO_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_SRIO_DMA_ID], RM_CPPI_SRIO_FLOW);
+ break;
+
+#ifdef QMSS_MAX_AIF_QUEUE
+ case RM_RESOURCE_CPPI_AIF_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_AIF_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_AIF_DMA_ID], RM_CPPI_AIF_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_AIF_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_AIF_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_AIF_DMA_ID], RM_CPPI_AIF_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_AIF_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_AIF_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_AIF_DMA_ID], RM_CPPI_AIF_FLOW);
+ break;
+#endif
+
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ case RM_RESOURCE_CPPI_FFTC_A_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_A_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_FFTC_A_DMA_ID], RM_CPPI_FFTC_A_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_FFTC_A_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_A_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_FFTC_A_DMA_ID], RM_CPPI_FFTC_A_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_FFTC_A_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_A_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_FFTC_A_DMA_ID], RM_CPPI_FFTC_A_FLOW);
+ break;
+#endif
+
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ case RM_RESOURCE_CPPI_FFTC_B_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_B_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_FFTC_B_DMA_ID], RM_CPPI_FFTC_B_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_FFTC_B_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_B_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_FFTC_B_DMA_ID], RM_CPPI_FFTC_B_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_FFTC_B_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_B_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_FFTC_B_DMA_ID], RM_CPPI_FFTC_B_FLOW);
+ break;
+#endif
+
+#ifdef QMSS_MAX_PASS_QUEUE
+ case RM_RESOURCE_CPPI_PASS_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_PASS_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_PASS_DMA_ID], RM_CPPI_PASS_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_PASS_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_PASS_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_PASS_DMA_ID], RM_CPPI_PASS_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_PASS_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_PASS_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_PASS_DMA_ID], RM_CPPI_PASS_FLOW);
+ break;
+#endif
+
+ case RM_RESOURCE_CPPI_QMSS_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_QMSS_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_QMSS_DMA_ID], RM_CPPI_QMSS_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_QMSS_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_QMSS_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_QMSS_DMA_ID], RM_CPPI_QMSS_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_QMSS_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_QMSS_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_QMSS_DMA_ID], RM_CPPI_QMSS_FLOW);
+ break;
+
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ case RM_RESOURCE_CPPI_FFTC_C_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_C_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_FFTC_C_DMA_ID], RM_CPPI_FFTC_C_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_FFTC_C_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_C_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_FFTC_C_DMA_ID], RM_CPPI_FFTC_C_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_FFTC_C_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_FFTC_C_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_FFTC_C_DMA_ID], RM_CPPI_FFTC_C_FLOW);
+ break;
+#endif
+
+#ifdef QMSS_MAX_BCP_QUEUE
+ case RM_RESOURCE_CPPI_BCP_TX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_BCP_TX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[RM_CPPI_BCP_DMA_ID], RM_CPPI_BCP_TX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_BCP_RX_CH:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_BCP_RX_CH, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[RM_CPPI_BCP_DMA_ID], RM_CPPI_BCP_RX_CH);
+ break;
+
+ case RM_RESOURCE_CPPI_BCP_FLOW:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_CPPI_BCP_FLOW, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[RM_CPPI_BCP_DMA_ID], RM_CPPI_BCP_FLOW);
+ break;
+#endif
+
+ case RM_RESOURCE_PA_FIRMWARE:
+ rmGPermsObj.obj.paFirmwarePerms.initPerms = resourceEntry->resourceInitFlags;
+ rmGPermsObj.obj.paFirmwarePerms.usePerms = resourceEntry->resourceUseFlags;
+ break;
+
+ case RM_RESOURCE_PA_LUT_ENTRY:
+ RM_RANGE_CHECK (resourceEntry->resourceStart, resourceEntry->resourceEnd, RM_PA_LUT, RM_ERROR_PERMISSION_TABLE_ENTRY_FAILURE);
+ Rm_setTablePermissions (resourceEntry, rmGPermsObj.obj.paLutPerms, RM_PA_LUT);
+ break;
+
+ default:
+ return RM_ERROR_PERMISSION_TABLE_POPULATION_FAILED;
+
+ }
+
+ resourceEntry++;
+ };
+
+ /* Write synchronization object so that slave cores know permissions table is
+ * populated and valid */
+ rmGSyncObj.obj.globalSyncObj = RM_PERMISSION_TABLE_VALID;
+
+ /* Writeback Sync Object */
+ Rm_osalEndMemAccess ((void *) &rmGSyncObj, sizeof (Rm_Sync_Obj));
+
+ return RM_OK;
+}
+
+/**
+ * @b Description
+ * @n
+ * This function is called on slave DSPs after the master DSP has populated
+ * the internal permission tables. This function invalidates all internal
+ * global permission tables so that no further invalidates are required
+ * when LLDs perform resource permission checks
+ *
+ */
+void Rm_updatePermissionTables(void)
+{
+ uint16_t dmaIndex;
+ const uint16_t dmaTxCh[RM_CPPI_MAX_DMAS] = {RM_CPPI_SRIO_TX_CH,
+#ifdef QMSS_MAX_AIF_QUEUE
+ RM_CPPI_AIF_TX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ RM_CPPI_FFTC_A_TX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ RM_CPPI_FFTC_B_TX_CH,
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ RM_CPPI_PASS_TX_CH,
+#endif
+ RM_CPPI_QMSS_TX_CH,
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ RM_CPPI_FFTC_C_TX_CH,
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ RM_CPPI_BCP_TX_CH
+#endif
+ };
+ const uint16_t dmaRxCh[RM_CPPI_MAX_DMAS] = {RM_CPPI_SRIO_RX_CH,
+#ifdef QMSS_MAX_AIF_QUEUE
+ RM_CPPI_AIF_RX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ RM_CPPI_FFTC_A_RX_CH,
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ RM_CPPI_FFTC_B_RX_CH,
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ RM_CPPI_PASS_RX_CH,
+#endif
+ RM_CPPI_QMSS_RX_CH,
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ RM_CPPI_FFTC_C_RX_CH,
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ RM_CPPI_BCP_RX_CH
+#endif
+ };
+ const uint16_t dmaFlow[RM_CPPI_MAX_DMAS] = {RM_CPPI_SRIO_FLOW,
+#ifdef QMSS_MAX_AIF_QUEUE
+ RM_CPPI_AIF_FLOW,
+#endif
+#ifdef QMSS_MAX_FFTC_A_QUEUE
+ RM_CPPI_FFTC_A_FLOW,
+#endif
+#ifdef QMSS_MAX_FFTC_B_QUEUE
+ RM_CPPI_FFTC_B_FLOW,
+#endif
+#ifdef QMSS_MAX_PASS_QUEUE
+ RM_CPPI_PASS_FLOW,
+#endif
+ RM_CPPI_QMSS_FLOW,
+#ifdef QMSS_MAX_FFTC_C_QUEUE
+ RM_CPPI_FFTC_C_FLOW,
+#endif
+#ifdef QMSS_MAX_BCP_QUEUE
+ RM_CPPI_BCP_FLOW
+#endif
+ };
+
+ /* Invalidate all permission tables so no further invalidates are required
+ * on slave cores */
+
+ /* Global permissions object */
+ Rm_osalBeginMemAccess ((void *) &rmGPermsObj, sizeof (Rm_GlobalPermissionsObj));
+
+ /* QMSS Permission Tables */
+
+ /* QMSS PDSPs */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssPdspFirmwarePerms, sizeof (Rm_Perms) * RM_QMSS_FIRMWARE_PDSPS);
+ /* QMSS Queues */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssQueuePerms, sizeof (Rm_Perms) * RM_QMSS_QUEUES);
+ /* QMSS Memory Regions */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssMemRegionPerms, sizeof (Rm_Perms) * RM_QMSS_MEM_REGIONS);
+ /* QMSS Linking RAM */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssLinkRamPerms, sizeof (Rm_qmssLinkingRamPerms) * RM_QMSS_LINKING_RAM_RANGES);
+ /* QMSS Accumulator Channels */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssAccumChPerms, sizeof (Rm_Perms) * RM_QMSS_ACCUM_CH);
+ /* QMSS QOS Clusters */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssQosClusterPerms, sizeof (Rm_Perms) * RM_QMSS_QOS_CLUSTER);
+ /* QMSS QOS Queues */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.qmssQosQueuePerms, sizeof (Rm_Perms) * RM_QMSS_QOS_QUEUES);
+
+ /* CPPI Permission Tables */
+
+ /* CPPI DMA Transmit Channels */
+ for (dmaIndex = 0; dmaIndex < RM_CPPI_MAX_DMAS; dmaIndex++)
+ {
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[dmaIndex], sizeof (Rm_Perms)*dmaTxCh[dmaIndex]);
+ }
+ /* CPPI DMA Receive Channels */
+ for (dmaIndex = 0; dmaIndex < RM_CPPI_MAX_DMAS; dmaIndex++)
+ {
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[dmaIndex], sizeof (Rm_Perms)*dmaRxCh[dmaIndex]);
+ }
+ /* CPPI DMA Receive Flows */
+ for (dmaIndex = 0; dmaIndex < RM_CPPI_MAX_DMAS; dmaIndex++)
+ {
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[dmaIndex], sizeof (Rm_Perms)*dmaFlow[dmaIndex]);
+ }
+
+ /* PA permission tables */
+
+ /* PA Firmware invalidated as part of global permissions object invalidate */
+ /* PA LUTs */
+ Rm_osalBeginMemAccess ((void *)rmGPermsObj.obj.paLutPerms, sizeof (Rm_Perms) * RM_PA_LUT);
+}
+
+/**
+ * @b Description
+ * @n
+ * This function extracts the initialization permission for a DSP from a resource
+ * permission element.
+ *
+ * @param[in] resourcePermissions
+ * A permissions structure element to extract the per DSP initialization permission
+ *
+ * @retval
+ * Success - RM_INIT_PERMISSION_APPROVED
+ * @retval
+ * Failure - RM_INIT_PERMISSION_DENIED
+ */
+Rm_Result Rm_getInitPermissions (Rm_Perms *resourcePermissions)
+{
+ /* Check the init permissions for the calling DSP */
+ if (!(RM_GET_PERMISSIONS(resourcePermissions->initPerms)))
+ {
+ return RM_INIT_PERMISSION_DENIED;
+ }
+
+ return RM_INIT_PERMISSION_APPROVED;
+}
+
+/**
+ * @b Description
+ * @n
+ * This function extracts the usage permission for a DSP from a resource
+ * permission element.
+ *
+ * @param[in] resourcePermissions
+ * A permissions structure element to extract the per DSP usage permission
+ *
+ * @retval
+ * Success - RM_INIT_PERMISSION_APPROVED
+ * @retval
+ * Failure - RM_INIT_PERMISSION_DENIED
+ */
+Rm_Result Rm_getUsePermissions (Rm_Perms *resourcePermissions)
+{
+ /* Check the use permissions for the calling DSP */
+ if (!(RM_GET_PERMISSIONS(resourcePermissions->usePerms)))
+ {
+ return RM_USE_PERMISSION_DENIED;
+ }
+
+ return RM_USE_PERMISSION_APPROVED;
+}
+
+/**
+ * @b Description
+ * @n
+ * This function searches the list of linking RAM address ranges to find one that has
+ * the requested linking RAM address within it. If found the function returns the permissions
+ * for this range. Otherwise it returns denied.
+ *
+ * @param[in] isInitCheck
+ * True - Permissions check is for initialization
+ * False - Permissions check is for usage
+ *
+ * @param[in] linkRamPermArray
+ * Internal array of linking RAM ranges and their permissions
+ *
+ * @param[in] linkRamResData
+ * Linking RAM addresses to check for initialization or usage permissions
+ *
+ * @retval
+ * Success - RM_INIT_PERMISSION_APPROVED
+ * @retval
+ * Failure - RM_INIT_PERMISSION_DENIED
+ */
+Rm_Result Rm_getLinkRamPermissions (Bool isInitCheck, Rm_qmssLinkingRamPerms *linkRamPermArray, Rm_ResourceInfo *linkRamResData)
+{
+ Rm_Result retVal;
+ uint16_t linkRamIndex;
+
+ /* Initialize the return value based on type of check boolean */
+ if (isInitCheck)
+ {
+ retVal = RM_INIT_PERMISSION_DENIED;
+ }
+ else
+ {
+ retVal = RM_USE_PERMISSION_DENIED;
+ }
+
+ for (linkRamIndex = 0; linkRamIndex < RM_QMSS_LINKING_RAM_RANGES; linkRamIndex++)
+ {
+ if ((linkRamResData->res_info.linkRamData.linkRamStartIndex >= linkRamPermArray[linkRamIndex].startIndex) &&
+ (linkRamResData->res_info.linkRamData.linkRamEndIndex <= linkRamPermArray[linkRamIndex].endIndex))
+ {
+ /* Check the use permissions for the calling DSP */
+ if (isInitCheck)
+ {
+ if (RM_GET_PERMISSIONS(linkRamPermArray[linkRamIndex].rangePerms.initPerms))
+ {
+ retVal = RM_USE_PERMISSION_APPROVED;
+ }
+ }
+ else
+ {
+ if (RM_GET_PERMISSIONS(linkRamPermArray[linkRamIndex].rangePerms.usePerms))
+ {
+ retVal = RM_USE_PERMISSION_APPROVED;
+ }
+ }
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+/**********************************************************************
+ **********APIs visible to other LLDs internally via call table *******************
+ **********************************************************************/
+
+/**
+ * @b Description
+ * @n
+ * This function is used by LLDs to check initialization permissions for a resource
+ *
+ * @param[in] resourceData
+ * Structure containing resource information such as resource type and the
+ * resource value to be checked
+ *
+ * @retval
+ * Success - RM_INIT_PERMISSION_APPROVED
+ * @retval
+ * Failure - RM_INIT_PERMISSION_DENIED
+ */
+Rm_Result Rm_initPermissionChecker (Rm_ResourceInfo *resourceData)
+{
+ switch (resourceData->resourceType)
+ {
+ case Rm_resource_QMSS_FIRMWARE_PDSP:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssPdspFirmwarePerms[resourceData->res_info.pdspNum]));
+
+ case Rm_resource_QMSS_QUEUE:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssQueuePerms[resourceData->res_info.queNum]));
+
+ case Rm_resource_QMSS_MEMORY_REGION:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssMemRegionPerms[resourceData->res_info.memRegion]));
+
+ case Rm_resource_QMSS_LINKING_RAM_CONTROL:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssLinkRamControlPerms));
+
+ case Rm_resource_QMSS_LINKING_RAM:
+ return (Rm_getLinkRamPermissions (TRUE, &rmGPermsObj.obj.qmssLinkRamPerms[0], resourceData));
+
+ case Rm_resource_QMSS_ACCUM_CH:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssAccumChPerms[resourceData->res_info.accumCh]));
+
+ case Rm_resource_QMSS_QOS_TIMER:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssQosPdspTimerPerms));
+
+ case Rm_resource_QMSS_QOS_CLUSTER:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssQosClusterPerms[resourceData->res_info.qosCluster]));
+
+ case Rm_resource_QMSS_QOS_QUEUE:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.qmssQosQueuePerms[resourceData->res_info.qosQueue]));
+
+ case Rm_resource_CPPI_TX_CH:
+ {
+ Rm_Perms *txChPermsArray = rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[resourceData->res_info.cpDmaData.dmaNum];
+ return (Rm_getInitPermissions(&txChPermsArray[resourceData->res_info.cpDmaData.cppiChNumOrFlowId]));
+ }
+
+ case Rm_resource_CPPI_RX_CH:
+ {
+ Rm_Perms *rxChPermsArray = rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[resourceData->res_info.cpDmaData.dmaNum];
+ return (Rm_getInitPermissions(&rxChPermsArray[resourceData->res_info.cpDmaData.cppiChNumOrFlowId]));
+ }
+
+ case Rm_resource_CPPI_RX_FLOW:
+ {
+ Rm_Perms *flowPermsArray = rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[resourceData->res_info.cpDmaData.dmaNum];
+ return (Rm_getInitPermissions(&flowPermsArray[resourceData->res_info.cpDmaData.cppiChNumOrFlowId]));
+ }
+
+ case Rm_resource_PA_FIRMWARE:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.paFirmwarePerms));
+
+ case Rm_resource_PA_LUT:
+ return (Rm_getInitPermissions(&rmGPermsObj.obj.paLutPerms[resourceData->res_info.lutEntry]));
+
+ default:
+ return (RM_INIT_PERMISSION_DENIED);
+ }
+}
+
+/**
+ * @b Description
+ * @n
+ * This function is used by LLDs to check usage permissions for a resource
+ *
+ * @param[in] resourceData
+ * Structure containing resource information such as resource type and the
+ * resource value to be checked
+ *
+ * @retval
+ * Success - RM_INIT_PERMISSION_APPROVED
+ * @retval
+ * Failure - RM_INIT_PERMISSION_DENIED
+ */
+Rm_Result Rm_usePermissionChecker (Rm_ResourceInfo *resourceData)
+{
+ switch (resourceData->resourceType)
+ {
+ case Rm_resource_QMSS_FIRMWARE_PDSP:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssPdspFirmwarePerms[resourceData->res_info.pdspNum]));
+
+ case Rm_resource_QMSS_QUEUE:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssQueuePerms[resourceData->res_info.queNum]));
+
+ case Rm_resource_QMSS_MEMORY_REGION:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssMemRegionPerms[resourceData->res_info.memRegion]));
+
+ case Rm_resource_QMSS_LINKING_RAM_CONTROL:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssLinkRamControlPerms));
+
+ case Rm_resource_QMSS_LINKING_RAM:
+ return (Rm_getLinkRamPermissions(FALSE, &rmGPermsObj.obj.qmssLinkRamPerms[0], resourceData));
+
+ case Rm_resource_QMSS_ACCUM_CH:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssAccumChPerms[resourceData->res_info.accumCh]));
+
+ case Rm_resource_QMSS_QOS_TIMER:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssQosPdspTimerPerms));
+
+ case Rm_resource_QMSS_QOS_CLUSTER:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssQosClusterPerms[resourceData->res_info.qosCluster]));
+
+ case Rm_resource_QMSS_QOS_QUEUE:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.qmssQosQueuePerms[resourceData->res_info.qosQueue]));
+
+ case Rm_resource_CPPI_TX_CH:
+ {
+ Rm_Perms *txChPermsArray = rmGPermsObj.obj.cppiTxChPerms.dmaPermPtrs[resourceData->res_info.cpDmaData.dmaNum];
+ return (Rm_getUsePermissions(&txChPermsArray[resourceData->res_info.cpDmaData.cppiChNumOrFlowId]));
+ }
+
+ case Rm_resource_CPPI_RX_CH:
+ {
+ Rm_Perms *rxChPermsArray = rmGPermsObj.obj.cppiRxChPerms.dmaPermPtrs[resourceData->res_info.cpDmaData.dmaNum];
+ return (Rm_getUsePermissions(&rxChPermsArray[resourceData->res_info.cpDmaData.cppiChNumOrFlowId]));
+ }
+
+ case Rm_resource_CPPI_RX_FLOW:
+ {
+ Rm_Perms *flowPermsArray = rmGPermsObj.obj.cppiFlowPerms.dmaPermPtrs[resourceData->res_info.cpDmaData.dmaNum];
+ return (Rm_getUsePermissions(&flowPermsArray[resourceData->res_info.cpDmaData.cppiChNumOrFlowId]));
+ }
+
+ case Rm_resource_PA_FIRMWARE:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.paFirmwarePerms));
+
+ case Rm_resource_PA_LUT:
+ return (Rm_getUsePermissions(&rmGPermsObj.obj.paLutPerms[resourceData->res_info.lutEntry]));
+
+ default:
+ return (RM_USE_PERMISSION_DENIED);
+ }
+}
+
+/* */
+
+/**********************************************************************
+ *********************** Application visible APIs ***************************
+ **********************************************************************/
+
+/** @addtogroup RM_LLD_FUNCTION
+@{
+*/
+
+/**
+ * @b Description
+ * @n
+ * This function initializes the Resource Manager low level driver
+ * This function is called once in the system to setup the Resource Manager
+ * low level driver by mapping the application defined resource table to internal
+ * permission tables. After mapping is complete a global synchronization object
+ * is written to sync with slave cores
+ *
+ * @param[in] rmResourceTable
+ * Resource table defined by application. Used to populate internal permission
+ * tables.
+ *
+ * @post
+ * RM LLD global permissions are set.
+ *
+ * @retval
+ * Success - RM_OK
+ * @retval
+ * Failure - RM_ERROR_PERMISSION_TABLE_POPULATION_FAILED
+ */
+Rm_Result Rm_init (const Rm_Resource *rmResourceTable)
+{
+ void *key;
+ Rm_Result ret_val = RM_ERROR;
+
+ /* Check permission structure sizes to make sure they're evenly
+ * divisible into a cache line. This generates no object code when
+ * optimizer is on. If failes, assert will occur at compile time */
+ RM_COMPILE_TIME_SIZE_CHECK((RM_MAX_CACHE_ALIGN/sizeof(Rm_Perms)) * sizeof(Rm_Perms) == RM_MAX_CACHE_ALIGN);
+ RM_COMPILE_TIME_SIZE_CHECK((RM_MAX_CACHE_ALIGN/sizeof(Rm_qmssLinkingRamPerms)) * \
+ sizeof(Rm_qmssLinkingRamPerms) == RM_MAX_CACHE_ALIGN);
+
+ /* Begin Critical Section before accessing shared resources. */
+ key = Rm_osalCsEnter ();
+
+ /* Initialize the permissions table */
+ Rm_permissionTableInit();
+
+ if (!rmResourceTable)
+ {
+ /* End Critical Section */
+ Rm_osalCsExit (key);
+ return RM_ERROR_PERMISSION_TABLE_POPULATION_FAILED;
+ }
+
+ ret_val = Rm_populatePermissionTable(rmResourceTable);
+
+ /* End Critical Section */
+ Rm_osalCsExit (key);
+ return ret_val;
+}
+
+/**
+ * @b Description
+ * @n
+ * This function waits for the Resource Manager master to populate the
+ * global permissions table based on a global sync object. Once the
+ * global sync object has been written by the master core this function
+ * will invalidate all permissions tables. Since the permissions table are
+ * static, and will not change through the system up-time, a single
+ * invalidation at the start will suffice.
+ *
+ * This function can be called on all core besides that which called
+ * Rm_init. Calling this function on said cores will act as a blocking
+ * synchronization point.
+ *
+ * @retval
+ * Success - RM_OK
+ * @retval
+ * Failure - RM_FAILURE
+ */
+Rm_Result Rm_start (void)
+{
+ /* Loop until the global sync object signals the permissions table has been
+ * populated and valid */
+ do
+ {
+ /* Invalidate the global sync object */
+ Rm_osalBeginMemAccess ((void *) &rmGSyncObj, sizeof (Rm_Sync_Obj));
+ } while (rmGSyncObj.obj.globalSyncObj != RM_PERMISSION_TABLE_VALID);
+
+ /* Master core finished populating the permission tables. Must invalidate
+ * all tables to see latest permissions */
+ Rm_updatePermissionTables();
+
+ return RM_OK;
+}
+
+/**
+ * @b Description
+ * @n
+ * This function returns an RM handle to the application to provide
+ * to LLDs that want to use the RM.
+ *
+ * @retval
+ * Success - RM Handle. Used an an input parameter for LLD startCfg functions.
+ * @retval
+ * Failure - NULL
+ */
+Rm_Handle Rm_getHandle(void)
+{
+ return ((void *) &rmPermissionCheckers);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to get the version information of the RM LLD.
+ *
+ * @retval
+ * Version Information.
+ */
+uint32_t Rm_getVersion (void)
+{
+ return RM_LLD_VERSION_ID;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to get the version string for the RM LLD.
+ *
+ * @retval
+ * Version String.
+ */
+const char* Rm_getVersionStr (void)
+{
+ return rmLldVersionStr;
+}
+
+/**
+@}
+*/
diff --git a/test/Module.xs b/test/Module.xs
--- /dev/null
+++ b/test/Module.xs
@@ -0,0 +1,48 @@
+/******************************************************************************
+ * FILE PURPOSE: RM LLD unit test files.
+ ******************************************************************************
+ * FILE NAME: module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for RM LLD test files.
+ *
+ * Copyright (C) 2012, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to add all the source files in the test
+ * directory into the package.
+ **************************************************************************/
+function modBuild()
+{
+ /* Add all the .c files to the release package. */
+ var testFiles = libUtility.listAllFiles (".c", "test", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+
+ /* Add all the .h files to the release package. */
+ var testFiles = libUtility.listAllFiles (".h", "test", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+
+ /* Add all the .cmd files to the release package. */
+ var testFiles = libUtility.listAllFiles (".cmd", "test", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+
+ /* Add all the .cfg files to the release package. */
+ var testFiles = libUtility.listAllFiles (".cfg", "test", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+
+ /* Add the .txt to the package */
+ var testFiles = libUtility.listAllFiles (".txt", "test", true);
+ for (var k = 0 ; k < testFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];
+}
diff --git a/test/README.txt b/test/README.txt
--- /dev/null
+++ b/test/README.txt
@@ -0,0 +1,28 @@
+Resource Manager(RM) LLD Unit Test
+----------------------------------
+
+- Please use project create script to create/generate the RM LLD unit
+ test project.
+
+- The name of the RM LLD unit test project is "rm_testproject".
+
+- Import the project to CCS using "Import Existing Project" option and build it.
+
+- Connect the EVM to core 0 and core 1.
+
+- Load the same out file generated in both the cores.
+
+- First run core 0 and wait for the test to complete, then run core 1 and wait
+ for the test to complete.
+
+- A sample output line is provided below:
+
+[C66xx_1] RM test core id: 0, passed for Pa_addMac, val -12
+
+Note that, in above output, the passed string indicate the RM configuration is
+working as expected for the the function (e.g.: Pa_addMac in above case).
+The last number (val = ###) is not relevant in the RM unit test context.
+
+- The resources for this unit test configured such that all resources are
+ granted for core 0 and denied for core 1.
+
diff --git a/test/cppi_test/rm_test_cppi.c b/test/cppi_test/rm_test_cppi.c
--- /dev/null
@@ -0,0 +1,363 @@
+#include <xdc/runtime/Memory.h>
+
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_semAux.h>
+#include <ti/csl/cslr_device.h>
+
+#include "ti/drv/rm/test/rm_test.h"
+#include "ti/drv/cppi/cppi_drv.h"
+
+#define NUM_HOST_DESC 32
+#define SIZE_HOST_DESC 48
+#define NUM_MONOLITHIC_DESC 32
+#define SIZE_MONOLITHIC_DESC 160
+
+#define NUM_DATA_BUFFER 32
+#define SIZE_DATA_BUFFER 64
+
+#define CPPI_HW_SEM 4
+
+/* CPPI device specific configuration */
+extern Cppi_GlobalConfigParams cppiGblCfgParams;
+
+Void rmTestRxChannelOpen (Cppi_Handle cppiHnd, rm_test_expect_e expect)
+{
+ UInt8 isAllocated;
+ Cppi_ChHnd ChHnd;
+ Cppi_RxChInitCfg ChCfg;
+
+ /* Don't specify channel number and let CPPI allocate the next available one */
+ ChCfg.channelNum = CPPI_PARAM_NOT_SPECIFIED;
+ ChCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE;
+
+ /* Open Channel */
+ ChHnd = (Cppi_ChHnd) Cppi_rxChannelOpen (cppiHnd, &ChCfg, &isAllocated);
+ if (ChHnd == NULL)
+ {
+ RM_PRINT_RESULT("Cppi_rxChannelOpen", expect, rm_denied, (uint32_t) ChHnd);
+ }
+ else
+ {
+ RM_PRINT_RESULT("Cppi_rxChannelOpen", expect, rm_granted, (uint32_t) ChHnd);
+ Cppi_channelClose (ChHnd);
+ }
+
+}
+
+Void rmTestTxChannelOpen(Cppi_Handle cppiHnd, rm_test_expect_e expect)
+{
+ UInt8 isAllocated;
+ Cppi_ChHnd ChHnd;
+ Cppi_TxChInitCfg ChCfg;
+
+ /* Don't specify channel number and let CPPI allocate the next available one */
+ ChCfg.channelNum = CPPI_PARAM_NOT_SPECIFIED;
+ ChCfg.priority = 2;
+ ChCfg.filterEPIB = 1;
+ ChCfg.filterPS = 1;
+ ChCfg.aifMonoMode = 1;
+ ChCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE;
+
+ /* Open Channel */
+ ChHnd = (Cppi_ChHnd) Cppi_txChannelOpen (cppiHnd, &ChCfg, &isAllocated);
+ if (ChHnd == NULL)
+ {
+ RM_PRINT_RESULT("Cppi_txChannelOpen", expect, rm_denied, (uint32_t) ChHnd);
+ }
+ else
+ {
+ RM_PRINT_RESULT("Cppi_txChannelOpen", expect, rm_granted, (uint32_t) ChHnd);
+ Cppi_channelClose (ChHnd);
+ }
+
+}
+
+Void rmTestRxFlowConfig (Cppi_Handle cppiHnd, rm_test_expect_e expect)
+{
+ UInt8 isAllocated;
+ Cppi_FlowHnd rxFlowHnd;
+ Cppi_RxFlowCfg rxFlowCfg;
+
+ memset ((Void *) &rxFlowCfg, 0, sizeof (Cppi_RxFlowCfg));
+
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* Request flow number 12 - 0 through 11 are given to ARM */
+ rxFlowCfg.flowIdNum = 12;
+#else /* All other devices without an ARM */
+ /* Request flow number 0 */
+ rxFlowCfg.flowIdNum = 0;
+#endif
+
+ /* Open Rx Flow */
+
+ rxFlowHnd = (Cppi_FlowHnd) Cppi_configureRxFlow (cppiHnd, &rxFlowCfg, &isAllocated);
+ if (rxFlowHnd == NULL) {
+ RM_PRINT_RESULT("Cppi_configureRxFlow", expect, rm_denied, (uint32_t) rxFlowHnd);
+ }
+ else {
+ RM_PRINT_RESULT("Cppi_configureRxFlow", expect, rm_granted, (uint32_t) rxFlowHnd);
+ Cppi_closeRxFlow (rxFlowHnd);
+ }
+}
+
+void rm_test_cppi(Rm_Handle rm_handle, rm_test_expect_e expect)
+{
+ Cppi_CpDmaInitCfg cpdmaCfg;
+ Cppi_Handle cppiHnd;
+ Cppi_StartCfg startCfg;
+ Cppi_Result result;
+
+ System_printf ("~~~~~~~~~~~~~Core %d RM CPPI TEST START~~~~~~~~~~~~~~~~\n", DNUM);
+
+ if (DNUM == 0) {
+ /* Initialize CPPI LLD */
+ result = Cppi_init (&cppiGblCfgParams);
+ if (result != CPPI_SOK)
+ {
+ System_printf ("Error Core %d : Initializing CPPI LLD error code : %d\n", DNUM, result);
+ }
+ }
+
+ memset ((Void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));
+ cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA;
+ cpdmaCfg.writeFifoDepth = 32;
+ cpdmaCfg.timeoutCount = 0x7F;
+ cpdmaCfg.qm0BaseAddress = 0x34020000;
+
+ cppiHnd = (Cppi_Handle) Cppi_open (&cpdmaCfg);
+ if (cppiHnd == NULL)
+ {
+ System_printf ("Error Core %d : Initializing SRIO CPPI CPDMA %d\n", DNUM, cpdmaCfg.dmaNum);
+ return;
+ }
+
+ startCfg.rmHandle = rm_handle;
+
+ Cppi_startCfg(&startCfg);
+
+ rmTestRxChannelOpen(cppiHnd, expect);
+
+ rmTestTxChannelOpen (cppiHnd, expect);
+
+ rmTestRxFlowConfig(cppiHnd, expect);
+
+ System_printf ("~~~~~~~~~~~~~Core %d RM CPPI TEST DONE~~~~~~~~~~~~~~~~\n", DNUM);
+
+}
+
+UInt32 cppiMallocCounter = 0;
+UInt32 cppiFreeCounter = 0;
+extern UInt32 coreKey [MAX_NUM_CORES];
+
+/**
+ * @b Description
+ * @n
+ * The function is used to allocate a memory block of the specified size.
+ *
+ * Note: If the LLD is used by applications on multiple core, the "cppiHeap"
+ * should be in shared memory
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @retval
+ * Allocated block address
+ */
+Ptr Osal_cppiMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+ Ptr dataPtr;
+
+ /* Increment the allocation counter. */
+ cppiMallocCounter++;
+
+ /* Allocate memory. */
+ dataPtr = Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+ return (dataPtr);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to free a memory block of the specified size allocated
+ * using Osal_cppiMalloc() API.
+ *
+ * @param[in] ptr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] size
+ * Size of the memory block to be cleaned up.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_cppiFree (Ptr ptr, UInt32 size)
+{
+ /* Increment the free counter. */
+ cppiFreeCounter++;
+ Memory_free (NULL, ptr, size);
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access CPPI shared
+ * library at the same time.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_cppiCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core CPPI synchronization lock
+ */
+ while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cppiCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab CPPI access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_cppiCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (CPPI_HW_SEM);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is the CPPI OSAL Logging API which logs
+ * the messages on the console.
+ *
+ * @param[in] fmt
+ * Formatted String.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_cppiLog ( String fmt, ... )
+{
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be invalidated
+ *
+ * @param[in] size
+ * Size of the block to be invalidated
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_cppiBeginMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be written back
+ *
+ * @param[in] size
+ * Size of the block to be written back
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_cppiEndMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
diff --git a/test/pa_test/rm_test_pa.c b/test/pa_test/rm_test_pa.c
--- /dev/null
@@ -0,0 +1,353 @@
+#include "ti/drv/rm/test/rm_test.h"
+#include "ti/drv/qmss/qmss_drv.h"
+#include "ti/drv/cppi/cppi_drv.h"
+#include "ti/drv/cppi/cppi_desc.h"
+#include "ti/drv/pa/pa.h"
+/* Firmware images */
+#include "ti/drv/qmss/qmss_firmware.h"
+#include "ti/drv/pa/fw/classify1_bin.c"
+#include "ti/drv/pa/fw/classify2_bin.c"
+#include "ti/drv/pa/fw/pam_bin.c"
+
+#include <ti/csl/cslr_device.h>
+
+#define CONFIG_MAX_L2_HANDLES 10
+#define CONFIG_MAX_L3_HANDLES 20
+
+#define CONFIG_BUFSIZE_PA_INST 256
+#define CONFIG_BUFSIZE_L2_TABLE 1000
+#define CONFIG_BUFSIZE_L3_TABLE 4000
+
+/* PA instance */
+#pragma DATA_ALIGN(paInstBuf, 8)
+Uint8 paInstBuf[CONFIG_BUFSIZE_PA_INST];
+Pa_Handle paInst;
+
+/* Memory used for PA handles */
+#pragma DATA_ALIGN(memL2Ram, 8)
+#pragma DATA_ALIGN(memL3Ram, 8)
+Uint8 memL2Ram[CONFIG_BUFSIZE_L2_TABLE];
+Uint8 memL3Ram[CONFIG_BUFSIZE_L3_TABLE];
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (PASS applications and non-PASS applications)
+ * across different cores to the PA library.
+ */
+#define PA_HW_SEM 5
+
+Void rmTestAddCustomLUT2 (Pa_Handle iHandle, rm_test_expect_e expect)
+{
+ paReturn_t ret_val;
+
+ ret_val = Pa_addCustomLUT2 (iHandle, pa_MAX_CUSTOM_TYPES_LUT2 - 1, NULL, 0, 0,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL);
+ if (ret_val == pa_RESOURCE_USE_DENIED) {
+ RM_PRINT_RESULT("Pa_addCustomLUT2", expect, rm_denied, ret_val);
+ }
+ else {
+ RM_PRINT_RESULT("Pa_addCustomLUT2", expect, rm_granted, ret_val);
+ }
+}
+
+Void rmTestAddSRIO (Pa_Handle iHandle, rm_test_expect_e expect)
+{
+ paReturn_t ret_val;
+
+ ret_val = Pa_addSrio (iHandle, pa_LUT1_INDEX_NOT_SPECIFIED, NULL, 0, 0,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL);
+ if (ret_val == pa_RESOURCE_USE_DENIED) {
+ RM_PRINT_RESULT("Pa_addSrio", expect, rm_denied, ret_val);
+ }
+ else {
+ RM_PRINT_RESULT("Pa_addSrio", expect, rm_granted, ret_val);
+ }
+}
+
+Void rmTestAddMac (Pa_Handle iHandle, rm_test_expect_e expect)
+{
+ paReturn_t ret_val;
+
+ ret_val = Pa_addMac ((Pa_Handle)iHandle,
+ pa_LUT1_INDEX_NOT_SPECIFIED, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL);
+
+ if (ret_val == pa_RESOURCE_USE_DENIED) {
+ RM_PRINT_RESULT("Pa_addMac", expect, rm_denied, ret_val);
+ }
+ else {
+ RM_PRINT_RESULT("Pa_addMac", expect, rm_granted, ret_val);
+ }
+}
+
+Void rmTestAddPort (Pa_Handle iHandle, rm_test_expect_e expect)
+{
+ paReturn_t ret_val;
+
+ ret_val = Pa_addPort ((Pa_Handle)iHandle,
+ pa_LUT2_PORT_SIZE_16, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL);
+
+ if (ret_val == pa_RESOURCE_USE_DENIED) {
+ RM_PRINT_RESULT("Pa_addPort", expect, rm_denied, ret_val);
+ }
+ else {
+ RM_PRINT_RESULT("Pa_addPort", expect, rm_granted, ret_val);
+ }
+}
+
+void rm_test_pa(Rm_Handle rm_handle, rm_test_expect_e expect)
+{
+ paSizeInfo_t paSize;
+ paConfig_t paCfg;
+ int sizes[pa_N_BUFS];
+ int aligns[pa_N_BUFS];
+ void* bases[pa_N_BUFS];
+ paStartCfg_t paStartCfg;
+ paReturn_t ret_val;
+ int i;
+
+ System_printf ("~~~~~~~~~~~~~Core %d RM PA TEST START~~~~~~~~~~~~~~~~\n", DNUM);
+
+ paStartCfg.rmHandle = rm_handle;
+
+ paSize.nMaxL2 = CONFIG_MAX_L2_HANDLES;
+ paSize.nMaxL3 = CONFIG_MAX_L3_HANDLES;
+ paSize.nUsrStats = 0;
+
+ ret_val = Pa_getBufferReq(&paSize, sizes, aligns);
+
+
+ bases[0] = (void *)paInstBuf;
+ bases[1] = (void *)memL2Ram;
+ bases[2] = (void *)memL3Ram;
+ bases[3] = 0;
+
+ paCfg.initTable = TRUE;
+ paCfg.initDefaultRoute = TRUE;
+ paCfg.baseAddr = CSL_PA_SS_CFG_REGS;
+ paCfg.sizeCfg = &paSize;
+
+ ret_val = Pa_create (&paCfg, bases, &paInst);
+
+ Pa_startCfg (paInst, &paStartCfg);
+
+ Pa_resetControl (paInst, pa_STATE_RESET);
+
+ /* PDPSs 0-2 use image c1 */
+ for (i = 0; i < 3; i++)
+ {
+ ret_val = Pa_downloadImage (paInst, i, (void *)c1, c1Size);
+ if (ret_val == pa_RESOURCE_INIT_DENIED) {
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM downloads PA firmware, all cores should be denied */
+ RM_PRINT_RESULT("Pa_downloadImage[0-2]", rm_denied, rm_denied, ret_val);
+#else /* All other devices without an ARM */
+ RM_PRINT_RESULT("Pa_downloadImage[0-2]", expect, rm_denied, ret_val);
+#endif
+ } else {
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM downloads PA firmware, all cores should be denied */
+ RM_PRINT_RESULT("Pa_downloadImage[0-2]", rm_denied, rm_granted, ret_val);
+#else /* All other devices without an ARM */
+ RM_PRINT_RESULT("Pa_downloadImage[0-2]", expect, rm_granted, ret_val);
+#endif
+ }
+ }
+
+ /* PDSP 3 uses image c2 */
+ ret_val = Pa_downloadImage (paInst, 3, (void *)c2, c2Size);
+ if (ret_val == pa_RESOURCE_INIT_DENIED) {
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM downloads PA firmware, all cores should be denied */
+ RM_PRINT_RESULT("Pa_downloadImage[3]", rm_denied, rm_denied, ret_val);
+#else /* All other devices without an ARM */
+ RM_PRINT_RESULT("Pa_downloadImage[3]", expect, rm_denied, ret_val);
+#endif
+ } else {
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM downloads PA firmware, all cores should be denied */
+ RM_PRINT_RESULT("Pa_downloadImage[3]", rm_denied, rm_granted, ret_val);
+#else /* All other devices without an ARM */
+ RM_PRINT_RESULT("Pa_downloadImage[3]", expect, rm_granted, ret_val);
+#endif
+ }
+
+ /* PDSPs 4-5 use image m */
+ for (i = 4; i < 6; i++)
+ {
+ ret_val = Pa_downloadImage (paInst, i, (void *)m, mSize);
+ if (ret_val == pa_RESOURCE_INIT_DENIED) {
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM downloads PA firmware, all cores should be denied */
+ RM_PRINT_RESULT("Pa_downloadImage[4-6]", rm_denied, rm_denied, ret_val);
+#else /* All other devices without an ARM */
+ RM_PRINT_RESULT("Pa_downloadImage[4-6]", expect, rm_denied, ret_val);
+#endif
+ } else {
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM downloads PA firmware, all cores should be denied */
+ RM_PRINT_RESULT("Pa_downloadImage[4-6]", rm_denied, rm_granted, ret_val);
+#else /* All other devices without an ARM */
+ RM_PRINT_RESULT("Pa_downloadImage[4-6]", expect, rm_granted, ret_val);
+#endif
+ }
+ }
+
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* MAC uses LUT1-0 which is always used by ARM. AddMac should be denied for all cores */
+ rmTestAddMac(paInst, rm_denied);
+ /* SRIO uses LUT1-0 which is always used by ARM. AddSrio should be denied for all cores */
+ rmTestAddSRIO (paInst, rm_denied);
+#else /* All other devices without an ARM */
+ rmTestAddMac(paInst, expect);
+
+ rmTestAddSRIO (paInst, expect);
+#endif
+
+ /*rmTestAddIP(paInst, expect);*/
+
+ rmTestAddPort(paInst, expect);
+
+ /*rmTestAddCustomLUT1(paInst, expect);*/
+
+ rmTestAddCustomLUT2(paInst, expect);
+
+ System_printf ("~~~~~~~~~~~~~Core %d RM PA TEST DONE~~~~~~~~~~~~~~~~\n", DNUM);
+}
+
+
+UInt32 paMemProtNestedLevel= 0;
+
+/**
+ * @brief This macro is used to alert the application that the PA is
+ * going to access table memory. The application must ensure
+ * cache coherency and semaphores for multi-core applications
+ *
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_paBeginMemAccess (void* addr, uint32_t sizeWords)
+ @endverbatim
+ *
+ * <b> Parameters </b>
+ * @n The address of the table to be accessed
+ * @n The number of bytes in the table
+ *
+ * @note PA will make nested calls to this function for memory access
+ * protection of different memory tables. The multicore semaphore
+ * should be allocated only for the first call of a nested group
+ * of calls.
+ */
+
+
+void Osal_paBeginMemAccess (Ptr addr, UInt32 size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ SYS_CACHE_INV (addr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+}
+
+/**
+ * @brief This macro is used to alert the application that the PA
+ * has completed access to table memory. This call will always
+ * be made following a call to Osal_paBeginMemAccess and have
+ * the same parameters
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void Osal_paEndMemAccess (void* addr, uint32_t sizeWords)
+ @endverbatim
+ *
+ * <b> Parameters </b>
+ * @n The address of the table to be accessed
+ * @n The number of bytes in the table
+ *
+ * @note PA will make nested calls to this function for memory access
+ * protection of different memory tables. The multicore semaphore
+ * should be freed when all previous memory access has completed,
+ * in other words, when the nested call level reaches 0.
+ */
+
+void Osal_paEndMemAccess (Ptr addr, UInt32 size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ SYS_CACHE_WB (addr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple threads on single core
+ * and
+ * access from multiple cores
+ *
+ * @param[in] key
+ * Key used to lock the critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_paMtCsEnter (uint32_t *key)
+{
+
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core PA synchronization lock
+ */
+ while ((CSL_semAcquireDirect (PA_HW_SEM)) == 0);
+ *key = 0;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to exit a critical section
+ * protected using Osal_salldCsEnter() API.
+ *
+ * @param[in] key
+ * Key used to unlock the critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_paMtCsExit (uint32_t key)
+{
+ /* Release the hardware semaphore */
+ CSL_semReleaseSemaphore (PA_HW_SEM);
+
+}
diff --git a/test/qmss_test/rm_test_qmss.c b/test/qmss_test/rm_test_qmss.c
--- /dev/null
@@ -0,0 +1,408 @@
+#include <xdc/runtime/Memory.h>
+
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_semAux.h>
+#include <ti/csl/cslr_device.h>
+
+#include "ti/drv/qmss/qmss_drv.h"
+#include "ti/drv/cppi/cppi_drv.h"
+#include "ti/drv/rm/test/rm_test.h"
+
+#define NUM_HOST_DESC 32
+#define SIZE_HOST_DESC 64
+#define NUM_MONOLITHIC_DESC 32
+
+/* Accumulator channel to use */
+#define TEST_ACC_CHANNEL_NUM 0u
+
+#define RM_BASE_QUEUE_NUM 0u
+
+#define RM_BASE_LOW_PRIO_QUEUE_NUM 128u
+
+#define QMSS_HW_SEM 3
+
+#pragma DATA_ALIGN (hostDesc, 16)
+UInt8 hostDesc[SIZE_HOST_DESC * NUM_HOST_DESC];
+/* CPDMA configuration */
+Cppi_CpDmaInitCfg cpdmaCfg;
+/* QMSS configuration */
+Qmss_InitCfg qmssInitConfig;
+/* Memory region configuration information */
+Qmss_MemRegInfo hostMemInfo;
+/* Accumulator configuration */
+Qmss_AccCmdCfg cfg = {0};
+
+/* QM descriptor configuration */
+Qmss_DescCfg descCfg = {0};
+
+extern Qmss_GlobalConfigParams qmssGblCfgParams;
+
+UInt32 l2_global_address (UInt32 addr)
+{
+ UInt32 corenum;
+
+ /* Get the core number. */
+ corenum = DNUM;
+
+ /* Compute the global address. */
+ return (addr + (0x10000000 + (corenum * 0x1000000)));
+}
+
+#define QMSS_RET_RM_RANGE(err) ((err <= QMSS_RESOURCE_INIT_DENIED) && (err >= QMSS_FIRMWARE_REVISION_DIFFERENCE))
+
+#define RM_TEST_QMSS_CHECK_PRINT_RESULT(name, expect, ret_val) do { \
+ if (QMSS_RET_RM_RANGE(ret_val)) \
+ RM_PRINT_RESULT(name, expect, rm_denied, ret_val); \
+ else \
+ RM_PRINT_RESULT(name, expect, rm_granted, ret_val); \
+} while(0)
+
+void rm_test_qmss(Rm_Handle rm_handle, rm_test_expect_e expect)
+{
+ Qmss_Result result;
+ //Cppi_Handle cppiHnd;
+ Qmss_StartCfg startCfg;
+ Qmss_QueueHnd qHandle;
+ Qmss_QosQueueCfg queueCfg = {0};
+ Qmss_QosClusterCfg clusterCfg;
+ uint32_t numAllocated;
+
+ System_printf ("~~~~~~~~~~~~~Core %d RM QMSS TEST START~~~~~~~~~~~~~~~~\n", DNUM);
+
+ if (DNUM == 0) {
+ memset ((Void *) &qmssInitConfig, 0, sizeof (Qmss_InitCfg));
+
+ qmssInitConfig.linkingRAM0Base = 0;
+ qmssInitConfig.linkingRAM0Size = 0;
+ qmssInitConfig.linkingRAM1Base = 0;
+ qmssInitConfig.maxDescNum = NUM_MONOLITHIC_DESC + NUM_HOST_DESC;
+
+ qmssGblCfgParams.qmRmHandle = rm_handle;
+
+ /* Initialize Queue Manager SubSystem */
+ result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams);
+#if (defined(_CSL_RL_TCI6638_H_) || defined(_CSL_RL_TCI6636_H_))
+ /* ARM has Linking RAM Control so expect deny always */
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_init", rm_denied, result);
+#else /* All other devices without an ARM */
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_init", expect, result);
+#endif
+ }
+ /* Start Queue Manager SubSystem */
+ startCfg.rmHandle = rm_handle;
+ result = Qmss_startCfg (&startCfg);
+ if (result != QMSS_SOK)
+ {
+ System_printf ("Core %d : Error in Qmss_StartCfg error code : %d\n", DNUM, result);
+ }
+
+ memset ((Void *) &hostDesc, 0, SIZE_HOST_DESC * NUM_HOST_DESC);
+ hostMemInfo.descBase = (UInt32 *) l2_global_address ((UInt32) hostDesc);
+ hostMemInfo.descSize = SIZE_HOST_DESC;
+ hostMemInfo.descNum = NUM_HOST_DESC;
+ hostMemInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
+ hostMemInfo.memRegion = Qmss_MemRegion_MEMORY_REGION_NOT_SPECIFIED;
+ hostMemInfo.startIndex = 0;
+
+ result = Qmss_insertMemoryRegion (&hostMemInfo);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_insertMemoryRegion", expect, result);
+
+ descCfg.memRegion = Qmss_MemRegion_MEMORY_REGION1;
+ qHandle = Qmss_initDescriptor (&descCfg, &numAllocated);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_initDescriptor", expect, qHandle);
+
+ qHandle = Qmss_queueOpen (Qmss_QueueType_LOW_PRIORITY_QUEUE, RM_BASE_LOW_PRIO_QUEUE_NUM, (uint8_t *)&numAllocated);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_queueOpen", expect, qHandle);
+
+ /* Reset qHandle to a valid queue number if the queueOpen returned a resource denied error */
+ if (qHandle < 0)
+ {
+ qHandle = 0;
+ }
+
+ result = Qmss_setQueueThreshold (qHandle, 1, 1);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_setQueueThreshold", expect, result);
+
+ cfg.channel = TEST_ACC_CHANNEL_NUM;
+ result = Qmss_programAccumulator (Qmss_PdspId_PDSP1, &cfg);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_programAccumulator", expect, result);
+
+#if 0
+ result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, TEST_ACC_CHANNEL_NUM);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_disableAccumulator", expect, result);
+#endif
+
+ result = Qmss_configureQosQueue (RM_BASE_QUEUE_NUM, &queueCfg);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_configureQosQueue", expect, result);
+
+ result = Qmss_configureQosCluster (RM_BASE_QUEUE_NUM, &clusterCfg);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_configureQosCluster", expect, result);
+
+ result = Qmss_resetQosQueueStats (RM_BASE_QUEUE_NUM);
+ RM_TEST_QMSS_CHECK_PRINT_RESULT("Qmss_resetQosQueueStats", expect, result);
+
+ System_printf ("~~~~~~~~~~~~~Core %d RM QMSS TEST DONE~~~~~~~~~~~~~~~~\n", DNUM);
+}
+
+
+/**********************************************************************
+ *************************** OSAL Functions **************************
+ **********************************************************************/
+UInt32 qmssMallocCounter = 0;
+UInt32 qmssFreeCounter = 0;
+UInt32 coreKey [MAX_NUM_CORES];
+
+/**
+ * @b Description
+ * @n
+ * The function is used to allocate a memory block of the specified size.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @retval
+ * Allocated block address
+ */
+Ptr Osal_qmssMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+ Ptr dataPtr;
+
+ /* Increment the allocation counter. */
+ qmssMallocCounter++;
+
+ /* Allocate memory. */
+ dataPtr = Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+ return (dataPtr);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to free a memory block of the specified size.
+ *
+ * @param[in] ptr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] size
+ * Size of the memory block to be cleaned up.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_qmssFree (Ptr ptr, UInt32 size)
+{
+ /* Increment the free counter. */
+ qmssFreeCounter++;
+ Memory_free(NULL, ptr, size);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ *
+ * @param[in] key
+ * Key used to lock the critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+Ptr Osal_qmssCsEnter (void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core QMSS synchronization lock
+ */
+ while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to exit a critical section
+ * protected using Osal_qmssCsEnter() API.
+ *
+ * @param[in] key
+ * Key used to unlock the critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_qmssCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (QMSS_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsEnter
+ *
+ * @b brief
+ * @n This API ensures ONLY multi-threaded
+ * synchronization to the QMSS user.
+ *
+ * This is a BLOCKING API.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_qmssMtCsEnter (Void)
+{
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ //coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cpswQmssMtCsEnter ()
+ * API. It resets the multi-threaded lock, enabling another process
+ * on the current core to grab it.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssMtCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ //Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is the QMSS OSAL Logging API which logs
+ * the messages on the console.
+ *
+ * @param[in] fmt
+ * Formatted String.
+ *
+ * @retval
+ * Not Applicable
+ */
+Void Osal_qmssLog ( String fmt, ... )
+{
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be invalidated
+ *
+ * @param[in] size
+ * Size of the block to be invalidated
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_qmssBeginMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ SYS_CACHE_INV (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be written back
+ *
+ * @param[in] size
+ * Size of the block to be written back
+
+ * @retval
+ * Not Applicable
+ */
+void Osal_qmssEndMemAccess (void *blockPtr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ SYS_CACHE_WB (blockPtr, size, CACHE_FENCE_WAIT);
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
+
diff --git a/test/rm_linker.cmd b/test/rm_linker.cmd
--- /dev/null
+++ b/test/rm_linker.cmd
@@ -0,0 +1,7 @@
+SECTIONS
+{
+ .init_array: load >> MSMCSRAM
+ .rm: load >> MSMCSRAM
+ .qmss: load >> MSMCSRAM
+ .cppi: load >> MSMCSRAM
+}
diff --git a/test/rm_osal.c b/test/rm_osal.c
--- /dev/null
+++ b/test/rm_osal.c
@@ -0,0 +1,288 @@
+/**
+ * @file rm_osal.c
+ *
+ * @brief
+ * This is the OS abstraction layer and is used by the the RM LLD.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+#include <xdc/std.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+ /* CSL modules */
+#include <ti/csl/csl_semAux.h>
+/* CSL Cache module includes */
+#include <ti/csl/csl_cacheAux.h>
+/* CSL XMC module includes */
+#include <ti/csl/csl_xmcAux.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+#define RM_HW_SEM 2
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+uint32_t rmMallocCounter = 0;
+uint32_t rmFreeCounter = 0;
+
+/**********************************************************************
+ *************************** OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * @b Description
+ * @n
+ * The function is used to allocate a memory block of the specified size.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @retval
+ * Allocated block address
+ */
+void* Osal_biosMalloc (uint32_t num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ rmMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to free a memory block of the specified size.
+ *
+ * @param[in] ptr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] size
+ * Size of the memory block to be cleaned up.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_biosFree (void *ptr, uint32_t size)
+{
+ /* Increment the free counter. */
+ rmFreeCounter++;
+ Memory_free(NULL, ptr, size);
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to enter a critical section.
+ * Function protects against
+ *
+ * access from multiple cores
+ * and
+ * access from multiple threads on single core
+ *
+ * @retval
+ * Handle used to lock critical section
+ */
+void* Osal_rmCsEnter (void)
+{
+ /* Get the hardware semaphore */
+ while ((CSL_semAcquireDirect (RM_HW_SEM)) == 0);
+
+ /* Create Semaphore for protection against access from multiple threads
+ * Not created here becasue application is not multithreaded
+ * */
+ return NULL;
+
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmCsExit (void *CsHandle)
+{
+ /* Release Semaphore using handle */
+
+ /* Release the hardware semaphore */
+ CSL_semReleaseSemaphore (RM_HW_SEM);
+
+ return;
+}
+/**
+ * @b Description
+ * @n
+ * The function is used to enter a critical section.
+ * Function protects against
+ * access from multiple threads on single core
+ *
+ * @retval
+ * Handle used to lock critical section
+ */
+void* Osal_rmMtCsEnter (void)
+{
+ /* Create Semaphore for protection against access from multiple threads
+ * Not created here becasue application is not multithreaded
+ * */
+ return NULL;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to exit a critical section
+ * protected using Osal_rmCsEnter() API.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmMtCsExit (void *CsHandle)
+{
+ /* Release Semaphore using handle */
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmBeginMemAccess (void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+ /* Cleanup the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+ CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT);
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * @b Description
+ * @n
+ * The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+ *
+ * @retval
+ * Not Applicable
+ */
+void Osal_rmEndMemAccess (void *ptr, uint32_t size)
+{
+ uint32_t key;
+
+ /* Disable Interrupts */
+ key = Hwi_disable();
+
+#ifdef L2_CACHE
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+ CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT);
+
+#else
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+#endif
+
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+ asm (" nop 4");
+
+ /* Reenable Interrupts. */
+ Hwi_restore(key);
+ return;
+}
+
diff --git a/test/rm_osal.h b/test/rm_osal.h
--- /dev/null
+++ b/test/rm_osal.h
@@ -0,0 +1,71 @@
+/**
+ * @file rm_osal.h
+ *
+ * @brief
+ * This is the OS adaptation layer for the RM low level Driver. This file should
+ * be modified by the system integrator to their system/OS implementation
+ * The file is provided as an 'example' template ported for XDC/BIOS.
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2009 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+*/
+#ifndef __RM_OSAL_H__
+#define __RM_OSAL_H__
+
+extern void* Osal_biosMalloc (uint32_t num_bytes);
+extern void Osal_biosFree (void *ptr, uint32_t size);
+extern void* Osal_rmCsEnter (void);
+extern void Osal_rmCsExit (void *CsHandle);
+extern void* Osal_rmMtCsEnter (void);
+extern void Osal_rmMtCsExit (void *CsHandle);
+extern void Osal_rmBeginMemAccess (void *ptr, uint32_t size);
+extern void Osal_rmEndMemAccess (void *ptr, uint32_t size);
+
+/* RM LLD OSAL Memory Allocation API are redefined to TEST application API */
+#define Rm_osalMalloc Osal_biosMalloc
+#define Rm_osalFree Osal_biosFree
+
+/* RM LLD OSAL Critical section and cache coherency APIs are used without redefinition in TEST application API */
+#define Rm_osalCsEnter Osal_rmCsEnter
+#define Rm_osalCsExit Osal_rmCsExit
+#define Rm_osalMtCsEnter Osal_rmMtCsEnter
+#define Rm_osalMtCsExit Osal_rmMtCsExit
+#define Rm_osalBeginMemAccess Osal_rmBeginMemAccess
+#define Rm_osalEndMemAccess Osal_rmEndMemAccess
+
+/* RM LLD OSAL Logging API is mapped directly to an XDC Runtime API */
+#define Rm_osalLog System_printf
+
+#endif /* __RM_OSAL_H__ */
+
diff --git a/test/rm_test.c b/test/rm_test.c
--- /dev/null
+++ b/test/rm_test.c
@@ -0,0 +1,57 @@
+
+#include <c6x.h>
+#include <xdc/std.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/csl/cslr_device.h>
+
+#include "ti/drv/rm/test/rm_test.h"
+
+Void main (Void)
+{
+ Rm_Result ret_val;
+ Rm_Handle rm_handle;
+
+
+ rm_test_expect_e expect;
+
+ System_printf ("*********************************************************\n");
+ System_printf ("******************* RM LLD Testing **********************\n");
+ System_printf ("*********************************************************\n");
+
+ System_printf ("RM Version : 0x%08x\nVersion String: %s\n", Rm_getVersion(), Rm_getVersionStr());
+
+ if (DNUM == 0) {
+ expect = rm_granted;
+ } else {
+ expect = rm_denied;
+ }
+
+ if (DNUM == 0) {
+ ret_val = Rm_init(rmTestResourceTable);
+ if (ret_val < 0) {
+ System_printf ("Rm_init failed error code : %d\n", ret_val);
+ return;
+ }
+ } else {
+ Rm_start();
+ }
+
+ rm_handle = Rm_getHandle();
+ if (!rm_handle) {
+ System_printf ("Rm_getHandle returned NULL\n");
+ return;
+ }
+
+ System_printf ("Testing QMSS\n");
+ rm_test_qmss(rm_handle, expect);
+
+ System_printf ("Testing CPPI\n");
+ rm_test_cppi(rm_handle, expect);
+
+#ifndef _C6657_Atrenta_DSP1_H_ /* C6657 does not have PA */
+ System_printf ("Testing PA\n");
+ rm_test_pa(rm_handle, expect);
+#endif
+
+}
diff --git a/test/rm_test.cfg b/test/rm_test.cfg
--- /dev/null
+++ b/test/rm_test.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012 by Texas Instruments Incorporated.
+ *
+ * All rights reserved. Property of Texas Instruments Incorporated.
+ * Restricted rights to use, duplicate or disclose this code are
+ * granted through contract.
+ *
+ */
+
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+var Log = xdc.useModule('xdc.runtime.Log');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+
+/* Load and use the CSL package */
+var Csl = xdc.loadPackage('ti.csl');
+var Cppi = xdc.loadPackage('ti.drv.cppi');
+var Qmss = xdc.loadPackage('ti.drv.qmss');
+var Pa;
+try {
+ Pa = xdc.loadPackage('ti.drv.pa');
+}
+catch(e) {
+ /* Nothing to be done. PA may not be present for some devices */
+}
+
+var Rm = xdc.loadPackage('ti.drv.rm');
+
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Create a default system heap using ti.bios.HeapMem. */
+var heapMemParams1 = new HeapMem.Params;
+heapMemParams1.size = 12288;
+heapMemParams1.sectionName = "systemHeap";
+Program.global.heap0 = HeapMem.create(heapMemParams1);
+
+/* This is the default memory heap. */
+Memory.defaultHeapInstance = Program.global.heap0;
+
+Program.sectMap["systemHeap"] = Program.platform.stackMemory;
+
+
diff --git a/test/rm_test.h b/test/rm_test.h
--- /dev/null
+++ b/test/rm_test.h
@@ -0,0 +1,72 @@
+/* Standard includes */
+#include <c6x.h>
+#include <string.h>
+
+/* XDC includes */
+#include <xdc/std.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+/* BIOS includes */
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/BIOS.h>
+
+/* CSL Cache module includes */
+#include <ti/csl/csl_cacheAux.h>
+/* CSL XMC module includes */
+#include <ti/csl/csl_xmcAux.h>
+/* CSL Semaphore module includes */
+#include <ti/csl/csl_semAux.h>
+
+/* RM LLD include */
+#include "ti/drv/rm/rm.h"
+
+#ifndef RM_TEST_H
+#define RM_TEST_H
+
+#define MAX_NUM_CORES 8
+
+#undef L2_CACHE
+#ifdef L2_CACHE
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete. */
+#define SYS_CACHE_INV(addr, size, code) CACHE_invL2 (addr, size, code)
+
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete. */
+#define SYS_CACHE_WB(addr, size, code) CACHE_wbL2 (addr, size, code)
+
+#else
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+#define SYS_CACHE_INV(addr, size, code) CACHE_invL1d (addr, size, code)
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled */
+#define SYS_CACHE_WB(addr, size, code) CACHE_wbL1d (addr, size, code)
+
+#endif
+
+extern Rm_Resource rmTestResourceTable[];
+
+typedef enum {
+ rm_granted, /* RM granted the resource */
+ rm_denied /* RM denied the resource */
+} rm_test_expect_e;
+
+#define RM_PRINT_RESULT(name, expect, result, ret_val)\
+do {\
+if (expect == result)\
+ System_printf ("RM test core id: %d, passed for %s, val %d\n", DNUM, name, ret_val);\
+else\
+ System_printf ("RM test core id: %d, failed for %s, val %d\n", DNUM, name, ret_val);\
+} while(0)
+
+void rm_test_cppi(Rm_Handle rm_handle, rm_test_expect_e expect);
+
+void rm_test_qmss(Rm_Handle rm_handle, rm_test_expect_e expect);
+
+#ifndef _C6657_Atrenta_DSP1_H_ /* C6657 does not have PA */
+void rm_test_pa(Rm_Handle rm_handle, rm_test_expect_e expect);
+#endif
+
+#endif /*RM_TEST_H*/
diff --git a/test/rm_test_resource.c b/test/rm_test_resource.c
--- /dev/null
+++ b/test/rm_test_resource.c
@@ -0,0 +1,765 @@
+/*
+ * rm_test_resource.c
+ *
+ * This file contains the resource table for the RM test project on the
+ * TCI6614 device.
+ *
+ * Resources in this file are shared between the DSP and ARM. The file
+ * is created to give the DSP access to all system resources except
+ * the resources specified by 'default' Linux device tree.
+ */
+
+/* Resource table defines */
+#include "ti/drv/rm/test/rm_test.h"
+
+/* CSL Include */
+#include <ti/csl/csl_qm_queue.h>
+
+#define RM_TEST_CORE0_PERMS \
+ (RM_RESOURCE_FLAG_DSP_SHIFT(0, RM_RESOURCE_PERM_ALLOWED))
+
+/** @brief QMSS DPSP default start and end ranges */
+#define QMSS_PDSP_DEFAULT_START_RANGE (0u)
+#define QMSS_PDSP_DEFAULT_END_RANGE (2u)
+/** @brief QMSS queue default start and end ranges */
+#define QMSS_QUEUE_DEFAULT_START_RANGE (0u)
+#define QMSS_QUEUE_DEFAULT_END_RANGE (8192u)
+/** @brief QMSS memory region default start and end ranges */
+#define QMSS_MEM_REGION_DEFAULT_START_RANGE (0u)
+#define QMSS_MEM_REGION_DEFAULT_END_RANGE (19u)
+/** @brief QMSS Linking RAM default start and end ranges */
+#define QMSS_LINK_RAM_DEFAULT_START_RANGE (0x00000000)
+#define QMSS_LINK_RAM_DEFAULT_END_RANGE (0xFFFFFFFF)
+/** @brief QMSS Accumulator channels default start and end ranges */
+#define QMSS_ACCUM_CH_DEFAULT_START_RANGE (0u)
+#define QMSS_ACCUM_CH_DEFAULT_END_RANGE (47u)
+/** @brief QMSS QOS clusters default start and end ranges */
+#define QMSS_QOS_CLUSTER_DEFAULT_START_RANGE (0u)
+#define QMSS_QOS_CLUSTER_DEFAULT_END_RANGE (7u)
+/** @brief QMSS QOS queue default start and end ranges */
+#define QMSS_QOS_QUEUE_DEFAULT_START_RANGE (0u)
+#define QMSS_QOS_QUEUE_DEFAULT_END_RANGE (63u)
+
+/** @brief CPPI SRIO tx channels default start and end ranges */
+#define CPPI_SRIO_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_TX_CH_DEFAULT_END_RANGE (15u)
+/** @brief CPPI SRIO rx channels default start and end ranges */
+#define CPPI_SRIO_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_RX_CH_DEFAULT_END_RANGE (15u)
+/** @brief CPPI SRIO rx flows default start and end ranges */
+#define CPPI_SRIO_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_SRIO_FLOW_DEFAULT_END_RANGE (19u)
+/** @brief CPPI AIF tx channels default start and end ranges */
+#define CPPI_AIF_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_TX_CH_DEFAULT_END_RANGE (128u)
+/** @brief CPPI AIF rx channels default start and end ranges */
+#define CPPI_AIF_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_RX_CH_DEFAULT_END_RANGE (128u)
+/** @brief CPPI AIF rx flows default start and end ranges */
+#define CPPI_AIF_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_AIF_FLOW_DEFAULT_END_RANGE (128u)
+/** @brief CPPI FFTC_A tx channels default start and end ranges */
+#define CPPI_FFTC_A_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_TX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_A rx channels default start and end ranges */
+#define CPPI_FFTC_A_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_RX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_A rx flows default start and end ranges */
+#define CPPI_FFTC_A_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_A_FLOW_DEFAULT_END_RANGE (7u)
+/** @brief CPPI FFTC_B tx channels default start and end ranges */
+#define CPPI_FFTC_B_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_TX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_B rx channels default start and end ranges */
+#define CPPI_FFTC_B_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_RX_CH_DEFAULT_END_RANGE (3u)
+/** @brief CPPI FFTC_B rx flows default start and end ranges */
+#define CPPI_FFTC_B_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_FFTC_B_FLOW_DEFAULT_END_RANGE (7u)
+/** @brief CPPI PASS tx channels default start and end ranges */
+#define CPPI_PASS_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_TX_CH_DEFAULT_END_RANGE (8u)
+/** @brief CPPI PASS rx channels default start and end ranges */
+#define CPPI_PASS_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_RX_CH_DEFAULT_END_RANGE (23u)
+/** @brief CPPI PASS rx flows default start and end ranges */
+#define CPPI_PASS_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_PASS_FLOW_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS tx channels default start and end ranges */
+#define CPPI_QMSS_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_TX_CH_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS rx channels default start and end ranges */
+#define CPPI_QMSS_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_RX_CH_DEFAULT_END_RANGE (31u)
+/** @brief CPPI QMSS rx flows default start and end ranges */
+#define CPPI_QMSS_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_QMSS_FLOW_DEFAULT_END_RANGE (63u)
+/** @brief CPPI BCP tx channels default start and end ranges */
+#define CPPI_BCP_TX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_TX_CH_DEFAULT_END_RANGE (7u)
+/** @brief CPPI BCP rx channels default start and end ranges */
+#define CPPI_BCP_RX_CH_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_RX_CH_DEFAULT_END_RANGE (7u)
+/** @brief CPPI BCP rx flows default start and end ranges */
+#define CPPI_BCP_FLOW_DEFAULT_START_RANGE (0u)
+#define CPPI_BCP_FLOW_DEFAULT_END_RANGE (63u)
+
+/** @brief PA LUT entry default start and end ranges */
+#define PA_LUT_ENTRY_DEFAULT_START_RANGE (0u)
+#define PA_LUT_ENTRY_DEFAULT_END_RANGE (4u)
+
+/** @brief ARM Linux General Purpose Queue range (Derived from the device tree) */
+#define ARM_LINUX_GENERAL_PURPOSE_QUEUE_BASE 4000
+#define ARM_LINUX_GENERAL_PURPOSE_NUM_QUEUES 64
+
+#define ARM_LINUX_INFRASTRUCTURE_NUM_QUEUES 12
+#define ARM_LINUX_CPPI_QMSS_TX_CH_NUM 12
+#define ARM_LINUX_CPPI_QMSS_RX_CH_NUM 12
+#define ARM_LINUX_CPPI_QMSS_FLOW 12
+
+/** @brief ARM Linux UDMA driver Low priority accumulator queue and channel range
+ * ARM UDMA driver uses:
+ * 0-127 low priority accumulator queues
+ * 32-35 low priority accumulator channels
+ * 728-735 high priority accumulator queues
+ * 672 SRIO queue for RapidIO
+ * 24-31 high priority accumulator channels
+ */
+#define ARM_LINUX_LOW_PRIO_ACCUM_QUEUES_NUM 128
+#define ARM_LINUX_LOW_PRIO_ACCUM_CH_BASE 32
+#define ARM_LINUX_LOW_PRIO_ACCUM_CH_NUM 4
+#define ARM_LINUX_HIGH_PRIO_ACCUM_QUEUES_BASE 728
+#define ARM_LINUX_HIGH_PRIO_ACCUM_CH_BASE 24
+
+/** @brief ARM Linux General Purpose Queue range (Derived from the device tree) */
+#define ARM_LINUX_MEMORY_REGION_BASE 12
+#define ARM_LINUX_MEMORY_REGION_NUMBER 3
+
+/** @brief ARM Linux SRIO Queues for RapidIO (Derived from the device tree) */
+#define ARM_LINUX_RAPIDIO_QUEUE_NUM 1
+
+/** @brief RM LLD test application resource table permissions when ARM is running.
+ * Must be cache line aligned. Select pragma format based on language */
+#ifdef __cplusplus
+#pragma DATA_ALIGN (128)
+#else
+#pragma DATA_ALIGN (rmTestResourceTable, 128)
+#endif
+Rm_Resource rmTestResourceTable[] =
+{
+ /* Magic Number structure to verify RM can read the resource table */
+ {
+ /** DSP QMSS Firmware access */
+ RM_RESOURCE_MAGIC_NUMBER,
+ /** No start range */
+ 0u,
+ /** No end range */
+ 0u,
+ /** No init permissions */
+ 0u,
+ /** No use permissions */
+ 0u,
+ },
+
+ /* QMSS Resource Definitions */
+
+ /******************************************************************************
+ * DSP has all access to the linking RAM indexes.
+ ******************************************************************************/
+ {
+ /** DSP QMSS Linking RAM access */
+ RM_RESOURCE_QMSS_LINKING_RAM,
+ /** Linking RAM start range*/
+ QMSS_LINK_RAM_DEFAULT_START_RANGE,
+ /** Linking RAM end range */
+ QMSS_LINK_RAM_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /*******************************************************************************
+ * The Queues are divided as follows:-
+ * - ARM gets low priority accumulator queues 0-127
+ * - AIF, FFTC-A, FFTC-B and BCP queues are completely owned by the DSP and
+ * this should never be changed.
+ * - PASS Queues are actually shared and both ARM & DSP will be using these
+ * queues.
+ * - All INTC (Direct Interrupt Queues) are owned by the DSP.
+ * - All Accumulator Queues are owned by the DSP.
+ * - All Starvation Queues are owned by the DSP.
+ * - SRIO queue 672 is ARM's.
+ * - High priority accumulator queues 728-735 are ARM, the rest are DSP
+ * - Account for the Linux General Purpose Queue usage and give all other
+ * general purpose queues to the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS queue access: Low priority queues 128-511 are owned by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_LOW_PRIORITY_QUEUE_BASE + ARM_LINUX_LOW_PRIO_ACCUM_QUEUES_NUM,
+ /** Queue end range */
+ QMSS_LOW_PRIORITY_QUEUE_BASE + QMSS_MAX_LOW_PRIORITY_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: AIF Queues are owned by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_AIF_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_AIF_QUEUE_BASE + QMSS_MAX_AIF_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: PASS Queues are actually shared between the DSP and ARM */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_PASS_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_PASS_QUEUE_BASE + QMSS_MAX_PASS_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: All the Direct Interrupt Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_INTC_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_INTC_QUEUE_BASE + QMSS_MAX_INTC_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: SRIO Queues 673 - 687 are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_SRIO_QUEUE_BASE + ARM_LINUX_RAPIDIO_QUEUE_NUM,
+ /** Queue end range */
+ QMSS_SRIO_QUEUE_BASE + QMSS_MAX_SRIO_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: FFTC-A Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_FFTC_A_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_FFTC_A_QUEUE_BASE + QMSS_MAX_FFTC_A_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: FFTC-B Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_FFTC_B_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_FFTC_B_QUEUE_BASE + QMSS_MAX_FFTC_B_QUEUE -1 ,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: BCP Queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_BCP_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_BCP_QUEUE_BASE + QMSS_MAX_BCP_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: The first 24 queues are used by the DSP. The remaining are
+ * used by ARM Linux*/
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_HIGH_PRIORITY_QUEUE_BASE,
+ /** Queue end range */
+ ARM_LINUX_HIGH_PRIO_ACCUM_QUEUES_BASE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: All the starvation queues are used by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_STARVATION_COUNTER_QUEUE_BASE,
+ /** Queue end range */
+ QMSS_STARVATION_COUNTER_QUEUE_BASE + QMSS_MAX_STARVATION_COUNTER_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: Infrastructure Queues reserved by the DSP. */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_INFRASTRUCTURE_QUEUE_BASE + ARM_LINUX_INFRASTRUCTURE_NUM_QUEUES,
+ /** Queue end range */
+ QMSS_INFRASTRUCTURE_QUEUE_BASE + QMSS_MAX_INFRASTRUCTURE_QUEUE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: General Purpose Queues reserved by the DSP */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ QMSS_GENERAL_PURPOSE_QUEUE_BASE,
+ /** Queue end range */
+ ARM_LINUX_GENERAL_PURPOSE_QUEUE_BASE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS queue access: General Purpose Queues reserved by the DSP */
+ RM_RESOURCE_QMSS_QUEUE,
+ /** Queue start range*/
+ ARM_LINUX_GENERAL_PURPOSE_QUEUE_BASE + ARM_LINUX_GENERAL_PURPOSE_NUM_QUEUES,
+ /** Queue end range */
+ QMSS_QUEUE_DEFAULT_END_RANGE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * ARM has access to a certain number of memory regions while all other memory
+ * regions are assigned to the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS Memory Region */
+ RM_RESOURCE_QMSS_MEMORY_REGION,
+ /** Memory Region start range*/
+ QMSS_MEM_REGION_DEFAULT_START_RANGE,
+ /** Memory Region end range */
+ ARM_LINUX_MEMORY_REGION_BASE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS Memory Region */
+ RM_RESOURCE_QMSS_MEMORY_REGION,
+ /** Memory Region start range*/
+ ARM_LINUX_MEMORY_REGION_BASE + ARM_LINUX_MEMORY_REGION_NUMBER,
+ /** Memory Region end range */
+ QMSS_MEM_REGION_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * The accumulator channels are divided between the DSP and ARM Linux.
+ * - channels 0-23 are DSPs
+ * - channels 24-35 are ARM Linux
+ * - channels 36-47 are DSPs
+ ******************************************************************************/
+ {
+ /** DSP QMSS high priority accumulator channels 0-19 */
+ RM_RESOURCE_QMSS_ACCUMULATOR_CH,
+ /** Accumulator channel start range 0 */
+ QMSS_ACCUM_CH_DEFAULT_START_RANGE,
+ /** Accumulator channel end range 23 */
+ ARM_LINUX_HIGH_PRIO_ACCUM_CH_BASE - 1,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS low priority accumulator channels 36-47 */
+ RM_RESOURCE_QMSS_ACCUMULATOR_CH,
+ /** Accumulator channel start range 36 */
+ ARM_LINUX_LOW_PRIO_ACCUM_CH_BASE + ARM_LINUX_LOW_PRIO_ACCUM_CH_NUM,
+ /** Accumulator channel end range 47 */
+ QMSS_ACCUM_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * QOS PDSP Timers are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS QOS PDSP Timer */
+ RM_RESOURCE_QMSS_QOS_PDSP_TIMER,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * The QOS Queues & Clusters are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP QMSS QOS clusters */
+ RM_RESOURCE_QMSS_QOS_CLUSTER,
+ /** QOS cluster start range*/
+ QMSS_QOS_CLUSTER_DEFAULT_START_RANGE,
+ /** QOS cluster end range */
+ QMSS_QOS_CLUSTER_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP QMSS QOS queues */
+ RM_RESOURCE_QMSS_QOS_QUEUE,
+ /** QOS queues start range*/
+ QMSS_QOS_QUEUE_DEFAULT_START_RANGE,
+ /** QOS queues end range */
+ QMSS_QOS_QUEUE_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /* CPPI Resource Definitions */
+
+ /******************************************************************************
+ * All SRIO resources are currently owned by the DSP.
+ ******************************************************************************/
+
+ {
+ /** DSP CPPI SRIO tx channels */
+ RM_RESOURCE_CPPI_SRIO_TX_CH,
+ /** CPPI SRIO tx channel start range*/
+ CPPI_SRIO_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI SRIO tx channel end range */
+ CPPI_SRIO_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI SRIO rx channels */
+ RM_RESOURCE_CPPI_SRIO_RX_CH,
+ /** CPPI SRIO rx channel start range*/
+ CPPI_SRIO_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI SRIO rx channel end range */
+ CPPI_SRIO_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI SRIO rx flows */
+ RM_RESOURCE_CPPI_SRIO_FLOW,
+ /** CPPI SRIO rx flow start range*/
+ CPPI_SRIO_FLOW_DEFAULT_START_RANGE,
+ /** CPPI SRIO rx flow end range */
+ CPPI_SRIO_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * All AIF2 resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI AIF tx channels */
+ RM_RESOURCE_CPPI_AIF_TX_CH,
+ /** CPPI AIF tx channel start range*/
+ CPPI_AIF_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI AIF tx channel end range */
+ CPPI_AIF_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI AIF rx channels */
+ RM_RESOURCE_CPPI_AIF_RX_CH,
+ /** CPPI AIF rx channel start range*/
+ CPPI_AIF_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI AIF rx channel end range */
+ CPPI_AIF_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI AIF rx flows */
+ RM_RESOURCE_CPPI_AIF_FLOW,
+ /** CPPI AIF rx flow start range*/
+ CPPI_AIF_FLOW_DEFAULT_START_RANGE,
+ /** CPPI AIF rx flow end range */
+ CPPI_AIF_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * All FFTC-A resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI FFTC_A tx channels */
+ RM_RESOURCE_CPPI_FFTC_A_TX_CH,
+ /** CPPI FFTC_A tx channel start range*/
+ CPPI_FFTC_A_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A tx channel end range */
+ CPPI_FFTC_A_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A rx channels */
+ RM_RESOURCE_CPPI_FFTC_A_RX_CH,
+ /** CPPI FFTC_A rx channel start range*/
+ CPPI_FFTC_A_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A rx channel end range */
+ CPPI_FFTC_A_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_A rx flows */
+ RM_RESOURCE_CPPI_FFTC_A_FLOW,
+ /** CPPI FFTC_A rx flow start range*/
+ CPPI_FFTC_A_FLOW_DEFAULT_START_RANGE,
+ /** CPPI FFTC_A rx flow end range */
+ CPPI_FFTC_A_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * All FFTC-B resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI FFTC_B tx channels */
+ RM_RESOURCE_CPPI_FFTC_B_TX_CH,
+ /** CPPI FFTC_B tx channel start range*/
+ CPPI_FFTC_B_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B tx channel end range */
+ CPPI_FFTC_B_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B rx channels */
+ RM_RESOURCE_CPPI_FFTC_B_RX_CH,
+ /** CPPI FFTC_B rx channel start range*/
+ CPPI_FFTC_B_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B rx channel end range */
+ CPPI_FFTC_B_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI FFTC_B rx flows */
+ RM_RESOURCE_CPPI_FFTC_B_FLOW,
+ /** CPPI FFTC_B rx flow start range*/
+ CPPI_FFTC_B_FLOW_DEFAULT_START_RANGE,
+ /** CPPI FFTC_B rx flow end range */
+ CPPI_FFTC_B_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ /******************************************************************************
+ * All PASS Tx and Rx channels are allocated to the ARM.
+ * PASS Flow 30 and 31 is allocated to ARM
+ ******************************************************************************/
+ {
+ /** DSP CPPI PASS rx flows */
+ RM_RESOURCE_CPPI_PASS_FLOW,
+ /** CPPI PASS rx flow start range*/
+ CPPI_PASS_FLOW_DEFAULT_START_RANGE,
+ /** CPPI PASS rx flow end range */
+ CPPI_PASS_FLOW_DEFAULT_END_RANGE - 2,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /*******************************************************************************
+ * The CPPI Transmit and Receive Channels are divided as follows:-
+ * - CPPI Tx Channel 0 is given to ARM
+ * - CPPI Rx Channel 0 is given to ARM
+ * - CPPI Transmit Flow 0 is given to ARM (Used by Virtual Eth Driver)
+ * - All other CPPI Tx & Rx Channels and flows are for the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI QMSS tx channels */
+ RM_RESOURCE_CPPI_QMSS_TX_CH,
+ /** CPPI QMSS tx channel start range*/
+ CPPI_QMSS_TX_CH_DEFAULT_START_RANGE + ARM_LINUX_CPPI_QMSS_TX_CH_NUM,
+ /** CPPI QMSS tx channel end range */
+ CPPI_QMSS_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS rx channels */
+ RM_RESOURCE_CPPI_QMSS_RX_CH,
+ /** CPPI QMSS rx channel start range*/
+ CPPI_QMSS_RX_CH_DEFAULT_START_RANGE + ARM_LINUX_CPPI_QMSS_RX_CH_NUM,
+ /** CPPI QMSS rx channel end range */
+ CPPI_QMSS_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI QMSS rx flows */
+ RM_RESOURCE_CPPI_QMSS_FLOW,
+ /** CPPI QMSS rx flow start range*/
+ CPPI_QMSS_FLOW_DEFAULT_START_RANGE + ARM_LINUX_CPPI_QMSS_FLOW,
+ /** CPPI QMSS rx flow end range */
+ CPPI_QMSS_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /******************************************************************************
+ * All BCP resources are owned by the DSP.
+ ******************************************************************************/
+ {
+ /** DSP CPPI BCP tx channels */
+ RM_RESOURCE_CPPI_BCP_TX_CH,
+ /** CPPI BCP tx channel start range*/
+ CPPI_BCP_TX_CH_DEFAULT_START_RANGE,
+ /** CPPI BCP tx channel end range */
+ CPPI_BCP_TX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI BCP rx channels */
+ RM_RESOURCE_CPPI_BCP_RX_CH,
+ /** CPPI BCP rx channel start range*/
+ CPPI_BCP_RX_CH_DEFAULT_START_RANGE,
+ /** CPPI BCP rx channel end range */
+ CPPI_BCP_RX_CH_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+ {
+ /** DSP CPPI BCP rx flows */
+ RM_RESOURCE_CPPI_BCP_FLOW,
+ /** CPPI BCP rx flow start range*/
+ CPPI_BCP_FLOW_DEFAULT_START_RANGE,
+ /** CPPI BCP rx flow end range */
+ CPPI_BCP_FLOW_DEFAULT_END_RANGE,
+ /** Full permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /* PA Resource Definitions */
+
+ /*******************************************************************************
+ * PA LUT Rules: LUT1-0 is owned by the ARM all else by the DSP.
+ ******************************************************************************/
+
+ {
+ /** DSP PA Look-up entry tables */
+ RM_RESOURCE_PA_LUT_ENTRY,
+ /** PA Look-up entry start range*/
+ PA_LUT_ENTRY_DEFAULT_START_RANGE + 1,
+ /** PA Look-up entry end range */
+ PA_LUT_ENTRY_DEFAULT_END_RANGE,
+ /** Full init permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ /** Full use permissions for DSP CORE0 */
+ RM_TEST_CORE0_PERMS,
+ },
+
+ /* Final entry structure for RM to find the last entry of resource table */
+
+ {
+ /** Final entry */
+ RM_RESOURCE_FINAL_ENTRY,
+ /** No start range*/
+ 0u,
+ /** No end range */
+ 0u,
+ /** No init permissions */
+ 0u,
+ /** No use permissions */
+ 0u,
+ },
+
+ /* Extra entries added to avoid a cache invalidate wiping out data placed after array
+ * Seven extra entries covers an extra cache line */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 1 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 2 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 3 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 4 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 5 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u}, /* extra entry: 6 */
+ {RM_RESOURCE_FINAL_ENTRY, 0u, 0u, 0u, 0u} /* extra entry: 7 */
+};
diff --git a/test/rm_testproject.txt b/test/rm_testproject.txt
--- /dev/null
+++ b/test/rm_testproject.txt
@@ -0,0 +1,16 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/README.txt"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_test.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_test.h"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_osal.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_osal.h"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_test_resource.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/cppi_test/rm_test_cppi.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/qmss_test/rm_test_qmss.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/pa_test/rm_test_pa.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/qmss_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_linker.cmd"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/rm/test/rm_test.cfg"
+-ccs.setCompilerOptions "-mv6600 -g --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/rm -I${PDK_INSTALL_PATH}/ti/drv/cppi -I${PDK_INSTALL_PATH}/ti/drv/qmss"
+-rtsc.enableRtsc
+