index a59ca876f1c3f2eb5300384802bf5a2e148876c2..46189698d4274c439cd66bc3b42b931ebb8deca4 100644 (file)
#include "testconn.h"
#include "salldsim/salldcfg.h"
#include "ti/osal/osal.h"
+#if defined (NSS_LITE2)
+#include "ti/csl/arch/csl_arch.h"
+#include <inttypes.h>
+#endif
/*
* Declare protocol and connection related handles
#define SAU_TXPKT_TO_HOST 1
+/* Internal local functions for throughput measurement */
+#if defined (BUILD_MCU)
+static void sau_cycle_cnt_init(void)
+{
+ uint32_t val;
+ CSL_armR5PmuCfg(0, 0, 1);
+ /* Clear the overflow */
+ val = CSL_armR5PmuReadCntrOverflowStatus();
+ val &= 0x80000007;
+ CSL_armR5PmuClearCntrOverflowStatus(val);
+ CSL_armR5PmuCfgCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM, CSL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT);
+ CSL_armR5PmuEnableAllCntrs(0);
+ CSL_armR5PmuResetCycleCnt();
+ /* Set PMCR C-bit */
+ CSL_armR5PmuResetCntrs();
+ CSL_armR5PmuEnableAllCntrs(1);
+}
+static uint64_t sau_read_cycle_cnt(void)
+{
+ uint32_t val;
+ uint64_t cnt;
+ val = CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM);
+ cnt = (uint64_t) val;
+ return (cnt);
+}
+#elif defined (BUILD_MPU)
+static void sau_cycle_cnt_init(void)
+{
+ CSL_initGTC();
+}
+static uint64_t sau_read_cycle_cnt(void)
+{
+ uint64_t cnt;
+ cnt = CSL_getGTCcount();
+ return (cnt);
+}
+#else
+static void sau_cycle_cnt_init(void)
+{
+ /* stub function */
+}
+static uint64_t sau_read_cycle_cnt(void)
+{
+ /* stub function */
+}
+
+#endif
+
+
/*******************************************************************************
* Function: Create a Data Mode channel
*******************************************************************************
@@ -991,6 +1044,7 @@ void sauCheckDesc(CSL_UdmapCppi5HMPD *hd, uint32_t connIndex, uint32_t pktNum, u
lineNum, connIndex, pktNum, pktlen, bufflen);
System_flush();
}
+
}
/*******************************************************************************
memcpy(authTag, (void *) psDataAddr, infoLen);
}
-#if defined(SOC_AM64X)
+#if defined (DMA_TYPE_LCDMA)
#else
sauCheckDesc(hd, connIndex, pktNum, __LINE__);
#endif
System_flush();
salld_sim_halt();
}
-
+#if defined (DMA_TYPE_LCDMA)
+#else
sauCheckDesc(hd, connIndex+1, pktNum, __LINE__);
+#endif
salld_sim_print("Conn %d: Receive Data Mode Pkt %d from SA\n", connIndex+1, pktNum);
/* Extract PS Info if exists */
psDataAddr = CSL_udmapCppi5GetPsDataAddr((void*) hd, 0, 1);
uint32_t descType;
#else
Int encFirstTime, decFirstTime;
- uint64_t encGtcCumSumVal = 0, decGtcCumSumVal = 0;
- uint64_t gtcTxStart, gtcTxEnd;
- uint64_t gtcRxStart, gtcRxEnd;
+ volatile uint64_t encGtcCumSumVal = 0, decGtcCumSumVal = 0;
+ volatile uint64_t gtcTxStart, gtcTxEnd;
+ volatile uint64_t gtcRxStart, gtcRxEnd, overhead;
#endif
uint16_t pktNum, nPkts, payloadLen;
uint32_t infoLen, numPktsRx, pLen;
@@ -1260,15 +1316,36 @@ void sauConnTputDmPktTest(tFramework_t *tf, saTest_t *pat, uint16_t numPkts)
Int pIdx;
Int pktLen[SAU_TPUT_NUM_PKTSIZES] = { 64, 512, 1024, 2048 };
uint32_t psFlags;
-/* Temporary arrangement until Board Lib for AM64X sets up the correct R5F Freq */
-#if defined (SOC_AM64X)
-#if defined (BUILD_MCU)
- Osal_HwAttrs hwAttrs;
- hwAttrs.cpuFreqKHz = 800000;
- Osal_setHwAttrs(OSAL_HWATTR_SET_CPU_FREQ, &hwAttrs);
-#endif
+
+ /* Initialize the cycle counter */
+ sau_cycle_cnt_init();
+ gtcTxStart = sau_read_cycle_cnt();
+ gtcTxEnd = sau_read_cycle_cnt();
+ overhead = gtcTxEnd - gtcTxStart;
+ gtcTxStart = sau_read_cycle_cnt();
+ /* 32 cycle NOP instructions, which can be used to compute the overhead */
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+ asm (" NOP "); asm (" NOP "); asm (" NOP "); asm (" NOP ");
+
+ gtcTxEnd = sau_read_cycle_cnt();
+ /* Total cycle should be 32 cycles + overhead */
+ encGtcCumSumVal = gtcTxEnd - gtcTxStart - overhead;
+
+#if defined(BUILD_MCU)
+ SALog("Captured cycle is = 0x%" PRIx64 " \n", encGtcCumSumVal);
+ SALog("overhead cycle is = 0x%" PRIx64 " \n", overhead);
+#else
+ SALog("Captured cycle is = 0x%" PRIx64 " \n", encGtcCumSumVal);
+ SALog("overhead cycle is = 0x%" PRIx64 " \n", overhead);
#endif
+
#if SAU_TPUT_TEST_DESC_DUMP
gSauDescDumpEncIndex = gSauDescDumpDecIndex = 0;
#endif
memcpy((void *)&gSauDescEncDumpMem[gSauDescDumpEncIndex++], (void *) hd[i], sizeof(CSL_UdmapCppi5HMPD));
#endif
pLen = CSL_udmapCppi5GetPktLen((void *) hd[i]);
+
+ /* Benchmarking Ring Push API */
+ if (i == 0)
+ {
+ gtcTxStart = sau_read_cycle_cnt();
+ }
RingPush(tFramework.gTxRingHandle, pLen, (physptr_t) hd[i]);
+ if (i == 0)
+ {
+ gtcTxEnd = sau_read_cycle_cnt();
+ gSauTputData[pIdx][connIndex].ringPushCycles = gtcTxEnd - gtcTxStart - overhead;
+ }
}
/*Make sure there is no packet in the Rx ring before enable of TX DMA */
} while (gRxPktCntInRing);
/* Now start the profile */
- gtcTxStart = TimerP_getTimeInUsecs();
+ gtcTxStart = sau_read_cycle_cnt();
/* The packets should loop back into queue TF_RING_RXQ after the
* udma is enabled
*/
@@ -1367,11 +1455,11 @@ void sauConnTputDmPktTest(tFramework_t *tf, saTest_t *pat, uint16_t numPkts)
#if SAU_TPUT_TEST_DESC_DUMP
#else
/* Stop the profile */
- gtcTxEnd = TimerP_getTimeInUsecs();
+ gtcTxEnd = sau_read_cycle_cnt();
/* Book keep */
sauBookKeepTx();
- encGtcCumSumVal = gtcTxEnd - gtcTxStart;
+ encGtcCumSumVal = gtcTxEnd - gtcTxStart - overhead;
/* Check */
if (numPktsRx > maxBatch)
FW_CPPI_DESC_T *pAppDesc;
pAppDesc = (FW_CPPI_DESC_T *) NULL;
hd[i] = (CSL_UdmapCppi5HMPD *)(NULL);
+ /* Benchmarking Ring Push API */
+ if (i == 0)
+ {
+ gtcTxStart = sau_read_cycle_cnt();
+ }
RingPop(tFramework.gRxRingHandle, &pAppDesc);
+ if (i == 0)
+ {
+ gtcTxEnd = sau_read_cycle_cnt();
+ gSauTputData[pIdx][connIndex].ringPopCycles = gtcTxEnd - gtcTxStart - overhead;
+ }
+
if (pAppDesc != (FW_CPPI_DESC_T *) NULL)
{
hd[i] = &pAppDesc->hostDesc;
}
}
- gSauTputData[pIdx][connIndex].cycles = encGtcCumSumVal;
- /* GTC runs at 200 MHz */
- gSauTputData[pIdx][connIndex].MegaBps = (8000UL * payloadLen * maxBatch)/encGtcCumSumVal;
+ gSauTputData[pIdx][connIndex].cycles = (uint32_t)encGtcCumSumVal;
/* Collect the first batch encryption cycles */
if (encFirstTime == TRUE)
tFramework.txComplRingNum);
#endif
pLen = CSL_udmapCppi5GetPktLen((void *) hd[i]);
+
+ /* Benchmarking Ring Push API */
+ if (i == 0)
+ {
+ gtcTxStart = sau_read_cycle_cnt();
+ }
RingPush(tFramework.gTxRingHandle, pLen, (physptr_t) hd[i]);
+
+ if (i == 0)
+ {
+ gtcTxEnd = sau_read_cycle_cnt();
+ gSauTputData[pIdx][connIndex+1].ringPushCycles = gtcTxEnd - gtcTxStart - overhead;
+ }
}
/* Make sre there are no Rx Pkts before enable of TX DMA */
@@ -1469,16 +1578,15 @@ void sauConnTputDmPktTest(tFramework_t *tf, saTest_t *pat, uint16_t numPkts)
* udma is unpaused
*/
- /* Now start the profile */
- gtcRxStart = TimerP_getTimeInUsecs();
-
- salld_test_controlTxDma(SA2UL_UDMAP_TX_UNPAUSE);
-
#if SAU_TPUT_TEST_DESC_DUMP
#else
numPktsRx = 0;
#endif
+ /* Now start the profile */
+ gtcRxStart = sau_read_cycle_cnt();
+ salld_test_controlTxDma(SA2UL_UDMAP_TX_UNPAUSE);
+
#if defined(SOC_AM64X)
while (numPktsRx < maxBatch)
{
#if SAU_TPUT_TEST_DESC_DUMP
#else
/* Stop the profile */
- gtcRxEnd = TimerP_getTimeInUsecs();
- decGtcCumSumVal = gtcRxEnd - gtcRxStart;
+ gtcRxEnd = sau_read_cycle_cnt();
+ decGtcCumSumVal = gtcRxEnd - gtcRxStart - overhead;
/* Pause the Tx UDMAP channel to prevent sa2ul to consume further packets */
salld_test_controlTxDma(SA2UL_UDMAP_TX_PAUSE);
FW_CPPI_DESC_T *pAppDesc;
pAppDesc = (FW_CPPI_DESC_T *) NULL;
hd[i] = (CSL_UdmapCppi5HMPD *)(NULL);
+ /* Benchmarking Ring Pop API */
+ if (i == 0)
+ {
+ gtcTxStart = sau_read_cycle_cnt();
+ }
RingPop(tFramework.gRxRingHandle, &pAppDesc);
+ if (i == 0)
+ {
+ gtcTxEnd = sau_read_cycle_cnt();
+ gSauTputData[pIdx][connIndex+1].ringPopCycles = gtcTxEnd - gtcTxStart - overhead;
+ }
+
if (pAppDesc != (FW_CPPI_DESC_T *) NULL)
{
hd[i] = &pAppDesc->hostDesc;
}
}
- gSauTputData[pIdx][connIndex].cycles = decGtcCumSumVal;
+ gSauTputData[pIdx][connIndex+1].cycles = (uint32_t)decGtcCumSumVal;
- /* GTC runs at 200 MHz */
- gSauTputData[pIdx][connIndex+1].MegaBps = (8000UL * payloadLen * maxBatch)/decGtcCumSumVal;
#endif /* SAU_TPUT_TEST_DESC_DUMP */
/* Book keep */