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raw | patch | inline | side by side (parent: 5b1fba0)
raw | patch | inline | side by side (parent: 5b1fba0)
author | Aravind Batni <aravindbr@ti.com> | |
Tue, 1 Mar 2016 23:56:50 +0000 (18:56 -0500) | ||
committer | Aravind Batni <aravindbr@ti.com> | |
Tue, 1 Mar 2016 23:56:50 +0000 (18:56 -0500) |
.gitignore | patch | blob | history | |
src/salldcom.c | patch | blob | history | |
src/salldloc.h | patch | blob | history |
diff --git a/.gitignore b/.gitignore
index 30f8073bc15d8d6a2cd6548ffb708d93cba96bb5..1b8db60be1f78c1326f40d6b4b155c96ac7a5a1c 100644 (file)
--- a/.gitignore
+++ b/.gitignore
test/*/*/c66/bios/src
example/*/*/armv7/bios/src/
example/*/*/c66/bios/src/
-
+makefile
diff --git a/src/salldcom.c b/src/salldcom.c
index 05f5be0eef71fdce220471849b31fb58a1887e67..5f6efd9841df7e32c15db3ec3d459c80d658054c 100755 (executable)
--- a/src/salldcom.c
+++ b/src/salldcom.c
@@ -1134,8 +1134,9 @@ static void sa_ipsec_stats_add(Sa_IpsecSysStats_t *sum, Sa_IpsecSysStats_t *src
*****************************************************************************/
static void sa_trigger_halt_on_err(salldObj_t *inst, int numPdsps)
{
- int i, flag;
- uint32_t reg27;
+ int i;
+ uint32_t flag;
+ uint32_t reg27, mask = 0x00008000;
CSL_Cp_aceRegs* pSaRegs = (CSL_Cp_aceRegs*)salldLObj.baseAddr;
flag = SALLD_FW_CTRL_LEVEL1_DEBUG_MASK;
/* Halt the PDSP */
pSaRegs->PDSP_CONTROL_STATUS[i].PDSP_CONTROL = 1;
+ /* Wait for halt - bit 15 to clear */
+ while (pSaRegs->PDSP_CONTROL_STATUS[i].PDSP_CONTROL & mask);
+
/* Read 32 bit value of register 27 */
reg27 = pSaRegs->PDSP_DEBUG[i].PDSP_IGP[27];
+ /* Clear the two debug flag bits (bit-15, bit-14) before setting */
+ reg27 &= (uint32_t) 0xFFFF3FFF;
+
/* Or the flag */
reg27 |= flag;
/* Non zero value indicates to enable the debug info in PDSPs */
if (res) {
/* wait for a micro second to make sure firmware init sequence is complete */
- for (i = 0; i < 125; i++)
+ for (i = 0; i < 1000; i++)
asm (" nop ");
sa_trigger_halt_on_err(inst, numPdsps);
diff --git a/src/salldloc.h b/src/salldloc.h
index ee8d0f35f06f4d9827771080e6af99f3bfcae3a7..9a2cd8408d3e5317064bc3b05fb2b09eeb42885e 100755 (executable)
--- a/src/salldloc.h
+++ b/src/salldloc.h
typedef struct salldL1DbgInfo_s {
uint32_t ctrl_status[SA_DBG_COLLECT_NUM_STATUS + 1]; /* pdsp control and status */
uint32_t dbgregs[SA_DBG_COLLECT_DBGREGS_SIZE >> 2]; /* PDSP debug register dump */
- uint8_t cmdLblTmpBuf[SA_DBG_COLLECT_CMDLBL_TBUF_SIZE]; /* Last command label/temp buf dump */
- uint8_t intBuf[SA_DBG_COLLECT_INT_BUF_SIZE]; /* two Internal Buffer content dump */
+ uint32_t cmdLblTmpBuf[SA_DBG_COLLECT_CMDLBL_TBUF_SIZE >> 2]; /* Last command label/temp buf dump */
+ uint32_t intBuf[SA_DBG_COLLECT_INT_BUF_SIZE >> 2]; /* two Internal Buffer content dump */
} salldL1DbgInfo_t;
/******************************************************************************
******************************************************************************/
typedef struct salldCoreDumpInfo_s {
- uint32_t phpVer[3]; /* PHP versions */
+ uint32_t phpVer[3]; /* PHP versions for all PDSPs */
uint16_t numPdsps; /* Number of Valid PDSPs */
uint16_t debug_level; /* Debug Level set */
Sa_SysStats_t sysStats; /* System stats dump */
uint32_t mmr[SA_DBG_COLLECT_MMR_SIZE >> 2]; /* mmr registers */
- salldL1DbgInfo_t dbgLevel1[3]; /* Level 1 debug information */
- salldL2DbgInfo_t dbgLevel2[16]; /* Level 2 debug information */
+ salldL1DbgInfo_t dbgLevel1[3]; /* Level 1 debug information for all PDSPs */
+ salldL2DbgInfo_t dbgLevel2[16]; /* Level 2 debug information capturing
+ 16 packets information for Air Cipher PDSP */
} salldCoreDumpInfo_t;