summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: ee16f6e)
raw | patch | inline | side by side (parent: ee16f6e)
test: Update R5 linker placement for rm_pm_hal sections REL.CORESDK.07.00.04.12 REL.CORESDK.07.00.04.13 REL.CORESDK.07.00.04.14 REL.CORESDK.07.01.00.18 REL.CORESDK.07.01.00.19 REL.CORESDK.07.01.00.20 REL.CORESDK.07.01.00.21 REL.CORESDK.07.01.00.22 REL.CORESDK.07.01.00.23 REL.CORESDK.07.01.00.24 REL.CORESDK.07.01.00.25
author | Stephen Molfetta <sjmolfetta@ti.com> | |
Tue, 29 Sep 2020 16:32:22 +0000 (11:32 -0500) | ||
committer | Stephen Molfetta <sjmolfetta@ti.com> | |
Tue, 29 Sep 2020 16:32:22 +0000 (11:32 -0500) |
Update R5 linker files to place sections related to rm_pm_hal
integration
Signed-off-by: Stephen Molfetta <sjmolfetta@ti.com>
integration
Signed-off-by: Stephen Molfetta <sjmolfetta@ti.com>
test/SaUnitTest/j721e/linker_r5.lds | patch | blob | history | |
test/SaUnitTest/j721e/linker_r5_sysbios.lds | patch | blob | history |
index a454d692be472886f9598fdda9d78ee26a1c270a..69ef88552fe7c69aa34a0785792aa07bd2ee801e 100755 (executable)
.boardcfg_data : {} palign(128) > MSMC3
.sysmem : {} > DDR0
.data_buffer : {} palign(128) > DDR0
+ .boardcfg_data : {} palign(8) > DDR0
+ .const* : {} palign(4) > DDR0
+ .bss* : {} align(4) > DDR0
.saSrcBuffers : {} palign(128) > OCMRAM
.saDstBuffers : {} palign(128) > OCMRAM
.scBufs : {} palign(128) > OCMRAM
diff --git a/test/SaUnitTest/j721e/linker_r5_sysbios.lds b/test/SaUnitTest/j721e/linker_r5_sysbios.lds
index 35de3dd7010974d6607c914408a1f3b8f3edce34..4ef79888ca489a6d76de91e41800bf59c7f5a22c 100644 (file)
.sysmem : {} align(8) > DDR0
.stack : {} align(4) > DDR0
.data_buffer: {} palign(128) > DDR0
+ .boardcfg_data : {} palign(8) > DDR0
+ .const* : {} palign(4) > DDR0
+ .bss* : {} align(4) > DDR0
.saSrcBuffers: {} palign(128) > DDR0
.saDstBuffers: {} palign(128) > DDR0
.scBufs : {} palign(128) > DDR0