PRSDK-4706: Adds support for MCU1_1 split mode on lockstep enabled

[keystone-rtos/sbl.git] / soc / k3 / sbl_slave_core_boot.c

diff --git a/soc/k3/sbl_slave_core_boot.c b/soc/k3/sbl_slave_core_boot.c
index f156269499e96ae533465daa44fc8273e8220abd..1ff0513b439c20865233c9780f51179bc322151a 100644 (file)
--- a/soc/k3/sbl_slave_core_boot.c
+++ b/soc/k3/sbl_slave_core_boot.c
@@ -442,7 +442,7 @@ void SBL_SetupCoreMem(uint32_t core_id)
                 SblErrLoop(__FILE__, __LINE__);
             }
             /* SBL running on MCU0, don't fool around with its power */
-            if ((core_id != MCU1_CPU0_ID) && (core_id != MCU1_CPU1_ID))
+            if (core_id != MCU1_CPU0_ID)
             {
                 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
@@ -455,7 +455,7 @@ void SBL_SetupCoreMem(uint32_t core_id)
                 SblErrLoop(__FILE__, __LINE__);
             }
             /* SBL running on MCU0, don't fool around with its power & TCMs */
-            if ((core_id != MCU1_CPU0_ID) && (core_id != MCU1_CPU1_ID))
+            if (core_id != MCU1_CPU0_ID)
             {
                 SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                 Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
@@ -591,10 +591,6 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
 
             if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
             {
-                SBL_log(SBL_LOG_MAX, "Clearing core_id %d  ATCM @ 0x%x ", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
-                memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
-                SBL_log(SBL_LOG_MAX, "& BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
-                memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
                 /* Skip copy if R5 app entry point is already 0 */
                 if (pAppEntry->CpuEntryPoint[core_id])
                 {
@@ -633,20 +629,21 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
                 SblErrLoop(__FILE__, __LINE__);
             }
 
-            /* Power down cores */
+            /* Power down core running SBL */
             Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
-            Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
 
-            /* Both cores halted at this point. Now un-halt them */
-            Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+            /* Both cores halted at this point. Now un-halt them as needed */
             Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU0, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
-            Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+            if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
+            {
+                Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+            }
 
             /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
             status = Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
             status = Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
 
-            /* Power up cores */
+            /* Power up cores as needed */
             Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
             if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
             {
@@ -686,8 +683,6 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
                     SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
                     memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
                 }
-                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
-                Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                 SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
                 status =  Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                 if (status != CSL_PASS)