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raw | patch | inline | side by side (parent: 59fed82)
raw | patch | inline | side by side (parent: 59fed82)
author | Madan Srinivas <uda0756974local@uda0756974> | |
Wed, 5 Dec 2018 16:18:01 +0000 (11:18 -0500) | ||
committer | Madan Srinivas <a0756974@ti.com> | |
Wed, 5 Dec 2018 16:26:04 +0000 (11:26 -0500) |
Signed-off-by: Madan Srinivas<madans@ti.com>
15 files changed:
board/k3/sbl_main.c | patch | blob | history | |
board/k3/sbl_main.h | [new file with mode: 0644] | patch | blob |
example/k3MulticoreApp/sbl_amp_multicore.c | patch | blob | history | |
example/k3MulticoreApp/sbl_amp_multicore_sections.h | patch | blob | history | |
soc/k3/sbl_err_trap.h | [new file with mode: 0644] | patch | blob |
soc/k3/sbl_log.h | [new file with mode: 0644] | patch | blob |
soc/k3/sbl_misc.asm | [new file with mode: 0644] | patch | blob |
soc/k3/sbl_slave_core_boot.c | patch | blob | history | |
soc/k3/sbl_slave_core_boot.h | patch | blob | history | |
soc/k3/sbl_typecast.h | [new file with mode: 0644] | patch | blob |
soc/sbl_soc.h | patch | blob | history | |
src/rprc/sbl_rprc.c | patch | blob | history | |
src/rprc/sbl_rprc.h | [new file with mode: 0644] | patch | blob |
src/rprc/sbl_rprc_parse.h | patch | blob | history | |
tools/flashWriter/qspi/src/sbl_qspi_writer.c | patch | blob | history |
diff --git a/board/k3/sbl_main.c b/board/k3/sbl_main.c
index 80bf8340f79e36f61d4dc424ecf3d27bdf668a5c..441dc580fff3d6e83895a75afe4b74a8d09c1725 100644 (file)
--- a/board/k3/sbl_main.c
+++ b/board/k3/sbl_main.c
*/
/* TI RTOS header files */
-#include <string.h>
-#include <ti/csl/cslr_device.h>
-#include <ti/board/board.h>
-#include <ti/drv/uart/UART.h>
-#include <ti/drv/uart/src/UART_osal.h>
-#include <ti/drv/uart/UART_stdio.h>
-#include <ti/csl/tistdtypes.h>
-#include <ti/csl/csl_a15.h>
-#include <ti/csl/arch/csl_arch.h>
-#include <ti/csl/src/ip/rat/V0/csl_rat.h>
-
-#include "sbl_slave_core_boot.h"
-#include "sbl_sci_client.h"
-#include "sbl_ver.h"
-#include "sbl_soc.h"
+#include "sbl_main.h"
/**********************************************************************
************************** Macros ************************************
/**********************************************************************
************************** Internal functions ************************
**********************************************************************/
-static void asm_AtcmEn(void)
-{
- asm volatile (" MRC p15, #0, r0, c9, c1, #1");
- asm volatile (" ORR r0, r0, #0x1");
- asm volatile (" MCR p15, #0, r0, c9, c1, #1");
-}
-
static void SBL_EnableATCM(void)
{
- uint8_t remap_mem[64];
+ uint32_t remap_mem[16];
+ uint32_t *temp_vecs_start, *atcm_vec_base;
+ uint32_t num_elements = sizeof(remap_mem)/sizeof(uint32_t);
+ uint32_t *temp_vecs_end = &remap_mem[num_elements - 1];
/* Save SBL Vectors */
- memcpy((void *)remap_mem, (void *)CSL_MCU_ATCM_BASE, sizeof(remap_mem));
- CSL_armR5CacheWbInv((const void *)CSL_MCU_ATCM_BASE, sizeof(remap_mem));
+ for (temp_vecs_start = remap_mem, atcm_vec_base = NULL; temp_vecs_start <= temp_vecs_end; *temp_vecs_start++ = *atcm_vec_base++) {};
+ CSL_armR5CacheWbInv((const void *)atcm_vec_base, (int32_t)sizeof(remap_mem));
- asm_AtcmEn();
+ _sblAtcmEn();
/* Restore SBL Vectors */
- memcpy((void *)CSL_MCU_ATCM_BASE, (void *)remap_mem, sizeof(remap_mem));
+ for (temp_vecs_start = remap_mem, atcm_vec_base = NULL; temp_vecs_start <= temp_vecs_end; *atcm_vec_base++ = *temp_vecs_start++) {};
}
/**********************************************************************
************************** Global Variables **************************
**********************************************************************/
-static sblEntryPoint_t am65xx_evmEntry;
+sblEntryPoint_t am65xx_evmEntry;
int main()
{
SBL_EnableATCM();
/* Board Init UART for logging. */
- Board_init(BOARD_INIT_UART_STDIO);
+ Board_init(BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG);
/* Load SYSFW. */
SBL_SciClientInit();
/* Image Copy */
SBL_ImageCopy(&am65xx_evmEntry);
- for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
+ for (core_id = MPU1_CPU0_ID; core_id <= MCU1_CPU1_ID; core_id ++)
{
/* Try booting all cores other than the one running the SBL */
if ((am65xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR) && (core_id != MCU1_CPU0_ID))
diff --git a/board/k3/sbl_main.h b/board/k3/sbl_main.h
--- /dev/null
+++ b/board/k3/sbl_main.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <string.h>
+#include <ti/csl/cslr_device.h>
+#include <ti/board/board.h>
+#include <ti/drv/uart/UART.h>
+#include <ti/drv/uart/src/UART_osal.h>
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/csl/tistdtypes.h>
+#include <ti/csl/csl_a15.h>
+#include <ti/csl/arch/csl_arch.h>
+#include <ti/csl/src/ip/rat/V0/csl_rat.h>
+
+#include "sbl_slave_core_boot.h"
+#include "sbl_sci_client.h"
+#include "sbl_ver.h"
+#include "sbl_soc.h"
+#include "sbl_log.h"
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Enables ATCM @0x0 at runtime. This is typically called by SBL.
+ *
+ *
+ * \param None
+ *
+ * \return None
+ *
+ */
+void _sblAtcmEn (void);
diff --git a/example/k3MulticoreApp/sbl_amp_multicore.c b/example/k3MulticoreApp/sbl_amp_multicore.c
index 0c95c925d6cd807eb3b187481159ce0f6765147c..09aa8b7123a2423c292f9bb7270fca035c790405 100644 (file)
volatile int *sblTestPokeMemStartAddr = (volatile int *)POKE_MEM_ADDR_MCU1_0;
volatile int *sblTestPokeMemEndAddr = (volatile int *)POKE_MEM_ADDR_MPU2_0;
int sblTestMsmcSectionSize = 0x800;
+ volatile int boot_delay = BOOT_DELAY;
+
+ while (boot_delay--);
// if we have run before, someone
// reset the system, dont print message
diff --git a/example/k3MulticoreApp/sbl_amp_multicore_sections.h b/example/k3MulticoreApp/sbl_amp_multicore_sections.h
index 2b30f986cf76b2d1986f44680c29af9c61e86ca7..40b9850c2386cf2601dd32cc91b2bbfdb1c6755a 100644 (file)
#ifdef BUILD_MCU1_0
#define CORE_NAME "MCU1_0"
+ #define BOOT_DELAY (0x80000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU1_0)
#pragma SET_CODE_SECTION(".sbl_mcu_1_0_resetvector")
#endif
#ifdef BUILD_MCU1_1
#define CORE_NAME "MCU1_1"
+ #define BOOT_DELAY (0xA0000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU1_1)
#pragma SET_CODE_SECTION(".sbl_mcu_1_1_resetvector")
#endif
#ifdef BUILD_MPU1_0
#define CORE_NAME "MPU1_0"
+ #define BOOT_DELAY (0x1)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MPU1_0)
int sblTestmain(void) __attribute__((section(".sbl_mpu_1_0_resetvector")));
static void sblTestResetMcu(void) __attribute__((section(".sbl_mpu_1_0_resetvector")));
#ifdef BUILD_MPU1_1
#define CORE_NAME "MPU1_1"
+ #define BOOT_DELAY (0x20000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MPU1_1)
int sblTestmain(void) __attribute__((section(".sbl_mpu_1_1_resetvector")));
#endif
#ifdef BUILD_MPU2_0
#define CORE_NAME "MPU2_0"
+ #define BOOT_DELAY (0x40000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MPU2_0)
int sblTestmain(void) __attribute__((section(".sbl_mpu_2_0_resetvector")));
#endif
#ifdef BUILD_MPU2_1
#define CORE_NAME "MPU2_1"
+ #define BOOT_DELAY (0x60000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MPU2_1)
int sblTestmain(void) __attribute__((section(".sbl_mpu_2_1_resetvector")));
#endif
diff --git a/soc/k3/sbl_err_trap.h b/soc/k3/sbl_err_trap.h
--- /dev/null
+++ b/soc/k3/sbl_err_trap.h
@@ -0,0 +1,52 @@
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#ifndef SBL_ERR_TRAP_H\r
+#define SBL_ERR_TRAP_H_\r
+\r
+/* ========================================================================== */\r
+/* Include Files */\r
+/* ========================================================================== */\r
+#include "sbl_typecast.h"\r
+\r
+/* ========================================================================== */\r
+/* Macros & Typedefs */\r
+/* ========================================================================== */\r
+\r
+/* ========================================================================== */\r
+/* Function Declarations */\r
+/* ========================================================================== */\r
+void SblErrLoop (const char *fileName, int32_t lineNo);\r
+\r
+#endif /* SBL_ERR_TRAP */\r
+\r
diff --git a/soc/k3/sbl_log.h b/soc/k3/sbl_log.h
--- /dev/null
+++ b/soc/k3/sbl_log.h
@@ -0,0 +1,52 @@
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#ifndef SBL_LOG_H\r
+#define SBL_LOG_H_\r
+/* ========================================================================== */\r
+/* Include Files */\r
+/* ========================================================================== */\r
+#include <stdint.h>\r
+\r
+/* ========================================================================== */\r
+/* Macros & Typedefs */\r
+/* ========================================================================== */\r
+#define SBL_LOG_NONE (0U)\r
+#define SBL_LOG_ERR (1U)\r
+#define SBL_LOG_MIN (2U)\r
+#define SBL_LOG_MAX (3U)\r
+\r
+#define SBL_log(dbg_level, ...) if ((int32_t)(dbg_level) <= SBL_LOG_LEVEL) { UART_printf(__VA_ARGS__); }\r
+\r
+\r
+#endif\r
diff --git a/soc/k3/sbl_misc.asm b/soc/k3/sbl_misc.asm
--- /dev/null
+++ b/soc/k3/sbl_misc.asm
@@ -0,0 +1,87 @@
+;******************************************************************************
+;* *
+;* Copyright (c) 2018-2019 Texas Instruments Incorporated *
+;* http://www.ti.com/ *
+;* *
+;* Redistribution and use in source and binary forms, with or without *
+;* modification, are permitted provided that the following conditions *
+;* are met: *
+;* *
+;* Redistributions of source code must retain the above copyright *
+;* notice, this list of conditions and the following disclaimer. *
+;* *
+;* Redistributions in binary form must reproduce the above copyright *
+;* notice, this list of conditions and the following disclaimer in *
+;* the documentation and/or other materials provided with the *
+;* distribution. *
+;* *
+;* Neither the name of Texas Instruments Incorporated nor the names *
+;* of its contributors may be used to endorse or promote products *
+;* derived from this software without specific prior written *
+;* permission. *
+;* *
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS *
+;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *
+;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR *
+;* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *
+;* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
+;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *
+;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, *
+;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *
+;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
+;* *
+;******************************************************************************
+ .arm
+
+;****************************************************************************
+; SBL Error Loop
+;****************************************************************************
+ .sect ".text"
+ .global SblErrLoop
+SblErrLoop:
+ .asmfunc
+ B SblErrLoop
+ .endasmfunc
+
+;****************************************************************************
+; SBL Read ATCM Region Register
+;****************************************************************************
+ .sect ".text"
+ .global _sblAtcmEn
+_sblAtcmEn:
+ .asmfunc
+ MRC p15, #0, r0, c9, c1, #1
+ ORR r0, r0, #0x1
+ MCR p15, #0, r0, c9, c1, #1
+ BX lr
+ .endasmfunc
+
+;****************************************************************************
+; Supress Klockworks Ptr Errors
+;****************************************************************************
+ .sect ".text"
+ .global uint32_to_void_ptr
+ .global uint32_to_const_void_ptr
+ .global uint32_to_uint32_ptr
+ .global uint32_ptr_to_void_ptr
+ .global const_uint8_ptr_to_void_ptr
+ .global uint32_to_int32
+ .global uint64_to_uint32
+ .global uint64_to_int32
+
+uint32_to_int32:
+uint32_to_void_ptr:
+uint32_to_const_void_ptr:
+uint32_to_uint32_ptr:
+uint32_ptr_to_void_ptr:
+const_uint8_ptr_to_void_ptr:
+uint64_to_uint32:
+uint64_to_int32:
+
+ .asmfunc
+
+ BX lr
+ .endasmfunc
+
index 553ff17f22ced8b0327130aa5fb09a9a1f2fb65a..771cd0fe2dc2448bb4aad701abbbae72a5838778 100644 (file)
#include <ti/drv/uart/UART_stdio.h>
#include "sbl_soc.h"
+#include "sbl_log.h"
+#include "sbl_err_trap.h"
#include "sbl_sci_client.h"
#include "sbl_slave_core_boot.h"
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", SCICLIENT_PROCID_R5_CL0_C0);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
proc_set_config_req.processor_id = SCICLIENT_PROCID_R5_CL0_C0;
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x... \n", SCICLIENT_PROCID_R5_CL0_C0);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
}
@@ -204,7 +206,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", map_proc_id[core_id]);
@@ -212,7 +214,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
proc_set_config_req.processor_id = map_proc_id[core_id];
@@ -234,7 +236,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
if ((proc_set_config_req.processor_id == SCICLIENT_PROCID_R5_CL0_C0) &&
@@ -266,7 +268,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", map_proc_id[core_id]);
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
/* Branch to start of ATCM */
@@ -290,7 +292,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootWaitProcessorState...FAILED \n");
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
/* Powering up again */
@@ -302,7 +304,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", map_proc_id[core_id]);
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
/* Execute a WFI */
@@ -316,7 +318,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", map_proc_id[core_id]);
- for(;;);
+ SblErrLoop(__FILE__, __LINE__);
}
}
index e3e41472c1356890af2ab75e47f8bdc9f22f5317..caa717c23413817f4bc6d3c98af7e247117bfa9d 100644 (file)
MPU1_CPU1_ID,
MPU2_CPU0_ID,
MPU2_CPU1_ID,
- MCU1_CPU0_ID,
- MCU1_CPU1_ID,
+ MCU1_CPU0_ID, /* add additional MPU/MCU cores before this */
+ MCU1_CPU1_ID, /* only SMP core ID should be after this */
MPU1_SMP_ID,
MPU2_SMP_ID,
MPU_SMP_ID,
diff --git a/soc/k3/sbl_typecast.h b/soc/k3/sbl_typecast.h
--- /dev/null
+++ b/soc/k3/sbl_typecast.h
@@ -0,0 +1,52 @@
+/*\r
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#ifndef SBL_TYPECAST_H\r
+#define SBL_TYPECAST_H\r
+\r
+/* ========================================================================== */\r
+/* Function Declarations */\r
+/* ========================================================================== */\r
+#include <stdint.h>\r
+\r
+int32_t uint32_to_int32(uint32_t value);\r
+void *uint32_to_void_ptr(uint32_t value);\r
+const void *uint32_to_const_void_ptr(uint32_t value);\r
+uint32_t *uint32_to_uint32_ptr(uint32_t value);\r
+uint32_t uint64_to_uint32(uint64_t value);\r
+int32_t uint64_to_int32(uint64_t value);\r
+void *uint32_ptr_to_void_ptr(uint32_t *ptr);\r
+void *const_uint8_ptr_to_void_ptr(const uint8_t *ptr);\r
+\r
+\r
+#endif /* SBL_TYPECAST_H */\r
diff --git a/soc/sbl_soc.h b/soc/sbl_soc.h
index 3fecbb7a1860024e7ca441add414dfe7dec17afb..008ffb74865f9e2ea78957dc2fc3455b84c6f882 100644 (file)
--- a/soc/sbl_soc.h
+++ b/soc/sbl_soc.h
/* ========================================================================== */\r
/* Macros & Typedefs */\r
/* ========================================================================== */\r
-#define SBL_LOG_NONE 0\r
-#define SBL_LOG_ERR 1\r
-#define SBL_LOG_MIN 2\r
-#define SBL_LOG_MAX 3\r
\r
-#define SBL_log(dbg_level, ...) if (dbg_level <= SBL_LOG_LEVEL) UART_printf(__VA_ARGS__)\r
-\r
-#define SBL_INVALID_ENTRY_ADDR ((uint32_t)0xFFFFFFFF)\r
+#define SBL_INVALID_ENTRY_ADDR ((uint32_t)0xFFFFFFFFU)\r
\r
/**\r
* @brief - SBL_socInit() - function to do initialize settings based on soc\r
* -1 = Error occurred\r
*\r
*/\r
-int32_t SBL_socInit();\r
-\r
-#if defined(BOOT_OSPI)\r
-/**\r
- * @brief - SBL_ospiInit() - function to do initialize QSPI\r
- *\r
-\r
- * @param\r
- * handle = pointer to return QSPI handle\r
- *\r
-\r
- * @return - int32t\r
- * 0 = Init completed successfully\r
- * -1 = Error occurred\r
-\r
- *\r
- */\r
-int32_t SBL_ospiInit(void *handle);\r
-\r
-/**\r
- * @brief - SBL_ospiFlashRead() - function to do flash QSPI\r
- *\r
- * @param\r
- * handle = pointer to QSPI handle\r
- * dst = byte pointer to destination\r
- * length = size of source to copy\r
- * offset = QSPI offset to flash into\r
- *\r
- * @return - int32t\r
- * 0 = Init completed successfully\r
- * <0 = Negative value indicate error occurred\r
- *\r
- */\r
-int32_t SBL_ospiFlashRead(void *handle, uint8_t *dst, uint32_t length,\r
- uint32_t offset);\r
-\r
-/**\r
-\r
- * @brief - SBL_ospiClose() - function to do close QSPI handle\r
-\r
- *\r
- * @param\r
-\r
- * handle = pointer to QSPI handle\r
- *\r
-\r
- * @return - int32t\r
- * 0 = Init completed successfully\r
-\r
- * -1 = Error occurred\r
- *\r
-\r
- */\r
-int32_t SBL_ospiClose(void *handle);\r
-\r
-#endif /* end of BOOT_OSPI definitions */\r
+int32_t SBL_socInit(void);\r
\r
#if defined(BOOT_QSPI)\r
/**\r
diff --git a/src/rprc/sbl_rprc.c b/src/rprc/sbl_rprc.c
index f9589dc1f1b3556f2a125dcd3be7072614941150..b6e28098a007785c9dba9b05e0e998ebec6f7573 100644 (file)
--- a/src/rprc/sbl_rprc.c
+++ b/src/rprc/sbl_rprc.c
*
*/
-#include "sbl_rprc_parse.h"
-
/* TI-RTOS Header files */
-#include <ti/drv/uart/UART_stdio.h>
-#include <ti/csl/cslr_device.h>
-#include <ti/csl/arch/csl_arch.h>
-#include <soc/sbl_soc.h>
-#include <stdio.h>
+#include "sbl_rprc_parse.h"
+#include "sbl_rprc.h"
-#if defined(SOC_AM65XX)
-#include <ti/board/board.h>
-#include <ti/drv/pm/include/pm_types.h>
-#include <ti/drv/pm/include/pmlib_clkrate.h>
-#endif
/* ========================================================================== */
-/* Structures and Enums */
+/* Global Variables */
/* ========================================================================== */
-
-typedef struct rprcFileHeader {
- uint32_t magic;
- uint32_t entry;
- uint32_t rsvd_addr;
- uint32_t SectionCount;
- uint32_t version;
-} rprcFileHeader_t;
-
-typedef struct rprcSectionHeader {
- uint32_t addr;
- uint32_t rsvd_addr;
- uint32_t size;
- uint32_t rsvdCrc;
- uint32_t rsvd;
-} rprcSectionHeader_t;
-
-typedef struct meta_header_start
-{
- uint32_t magic_str;
- uint32_t num_files;
- uint32_t dev_id;
- uint32_t rsvd;
-}meta_header_start_t;
-
-typedef struct meta_header_core
-{
- uint32_t core_id;
- uint32_t image_offset;
-}meta_header_core_t;
-
-typedef struct meta_header_end
-{
- uint32_t rsvd;
- uint32_t magic_string_end;
-}meta_header_end_t;
-
-/* Magic numbers for gforge and sourceforge */
-#define MAGIC_NUM_GF (0xA1ACED00)
-#define MAGIC_NUM_SF (0x55424CBB)
-
-/* Magic number and tokens for RPRC format */
-#define RPRC_MAGIC_NUMBER 0x43525052
-#define RPRC_RESOURCE 0
-#define RPRC_BOOTADDR 5
-
-#define MAX_INPUT_FILES 10
-#define META_HDR_MAGIC_STR 0x5254534D /* MSTR in ascii */
-#define META_HDR_MAGIC_END 0x444E454D /* MEND in ascii */
-
-#if !defined(OMAPL137_BUILD)
-#define SOC_OCMC_RAM1_SIZE ((uint32_t) 0x80000) /*OCMC1 512KB*/
-#define SOC_OCMC_RAM2_SIZE ((uint32_t) 0x100000) /*OCMC2 1MB */
-#define SOC_OCMC_RAM3_SIZE ((uint32_t) 0x100000) /*OCMC3 1MB */
-
-#define MPU_IPU1_ROM (CSL_IPU_IPU1_TARGET_REGS)
-
-#define MPU_IPU1_RAM (CSL_IPU_IPU1_TARGET_REGS + \
- (uint32_t) 0x20000)
-
-#define MPU_IPU2_ROM (CSL_IPU_IPU1_ROM_REGS)
-
-#define MPU_IPU2_RAM (CSL_IPU_IPU1_ROM_REGS + \
- (uint32_t) 0x20000)
-
-#define MPU_DSP1_L2_RAM (0x40800000)
-#define MPU_DSP1_L1P_CACHE (0x40E00000)
-#define MPU_DSP1_L1D_CACHE (0x40F00000)
-#define MPU_DSP2_L2_RAM (0x41000000)
-#define MPU_DSP2_L1P_CACHE (0x41600000)
-#define MPU_DSP2_L1D_CACHE (0x41700000)
-
-#if !defined(SOC_AM574x)
-#define SOC_DSP_L2_BASE (0x800000)
-#define SOC_DSP_L1P_BASE (0xe00000)
-#define SOC_DSP_L1D_BASE (0xf00000)
-#endif
-#endif
-
-/* Function Pointer used while reading data from the storage. */
int32_t (*fp_readData)(void *dstAddr, void *srcAddr,
uint32_t length);
/* Function Pointer used while reading data from the storage. */
void (*fp_seek)(void *srcAddr, uint32_t location);
-/**
- * \brief SBL_RprcImageParse function parse the RPRC executable image.
- * Copies individual section into destination location
- *
- * \param[in] srcAddr - Pointer RPRC image
- * \param[out] entryPoint - CPU entry point address
- * \param[in] CoreId - CPU ID to identify the CPU core
- *
- *
- * \return uint32_t: Status (success or failure)
- */
-static int32_t SBL_RprcImageParse(void *srcAddr, uint32_t *entryPoint,
- int32_t CoreId);
-
-/**
- * \brief SBL_BootCore function stores the CPU entry location into
- * global pointer.
- *
- * \param[in] entry - CPU Entry location
- * \param[in] entryPoint - CPU ID
- *
- * \return none
- */
-void SBL_BootCore(uint32_t entry, uint32_t CoreID, sblEntryPoint_t *pAppEntry);
-
-int32_t GetDeviceId(void);
-
-/**
- * \brief QSPIBootRprc function parses the multi-core app image
- * stored in the QSPI serial flash.
- * It Parses the AppImage & copies the section into CPU
- * internal memory & external memory.
- * CPUs entry loctions are stored into entry point
- * global pointers.
- *
- *
- * \param none
- *
- *
- * \return error status.If error has occured it returns a non zero
- * value.
- * If no error has occured then return status will be
- * zero.
- */
-
/******************************************************************************
-** SBL Multicore RPRC parse functions
+ *** SBL Multicore RPRC parse functions ***
*******************************************************************************/
int32_t SBL_MulticoreImageParse(void *srcAddr,
}
/* Read all the Core offset addresses */
- for (i = 0; i < mHdrStr.num_files; i++)
+ for (i = (0U); i < mHdrStr.num_files; i++)
{
fp_readData(&mHdrCore[i], srcAddr, sizeof (meta_header_core_t));
}
/* Add Base Offset address for All core Image start offset */
- for (i = 0; i < mHdrStr.num_files; i++)
+ for (i = (0U); i < mHdrStr.num_files; i++)
{
mHdrCore[i].image_offset += ImageOffset;
}
/* Now Parse Individual RPRC files */
- for (i = 0; i < mHdrStr.num_files; i++)
+ for (i = (0U); i < mHdrStr.num_files; i++)
{
if (mHdrCore[i].core_id != (0xFFFFFFFFU))
{
fp_seek(srcAddr, mHdrCore[i].image_offset);
if (SBL_RprcImageParse(srcAddr, &entryPoint,
- mHdrCore[i].core_id) != E_PASS)
+ (int32_t)(mHdrCore[i].core_id)) != E_PASS)
{
/* Error occurred parsing the RPRC file continue to
* parsing next
}
}
-#if defined(K2G_BUILD) || defined(K2E_BUILD) || defined(K2H_BUILD) || defined(K2K_BUILD) || defined(K2L_BUILD) || (AM571x_BUILD) || (AM572x_BUILD) || defined(AM574x_BUILD)
+#if defined(K2G_BUILD) || defined(K2E_BUILD) || defined(K2H_BUILD) || defined(K2K_BUILD) || defined(K2L_BUILD) || defined(AM571x_BUILD) || defined(AM572x_BUILD) || defined(AM574x_BUILD)
static int32_t SBL_RprcImageParse(void *srcAddr,
uint32_t *entryPoint,
int32_t CoreId)
case DSP0_ID:
section.addr |= 0x10000000; /* CorePac0 L2 SRAM */
break;
-
+#if defined(K2H_BUILD) || defined(K2K_BUILD) || defined(K2L_BUILD)
case DSP1_ID:
section.addr |= 0x11000000; /* CorePac1 L2 SRAM */
break;
case DSP3_ID:
section.addr |= 0x13000000; /* CorePac3 L2 SRAM */
break;
-
+#endif
+#if defined(K2H_BUILD) || defined(K2K_BUILD)
case DSP4_ID:
section.addr |= 0x14000000; /* CorePac4 L2 SRAM */
break;
case DSP7_ID:
section.addr |= 0x17000000; /* CorePac7 L2 SRAM */
break;
+#endif
+ default:
+ /* Wrong CPU ID */
+ break;
}
}
else
{
rprcFileHeader_t header;
rprcSectionHeader_t section;
- int32_t i;
+ uint32_t i;
int32_t retVal = E_PASS;
/*read application image header*/
{
rprcFileHeader_t header;
rprcSectionHeader_t section;
- int32_t i;
+ uint32_t i;
int32_t retVal = E_PASS;
/*read application image header*/
*entryPoint = header.entry;
/*read entrypoint and copy sections to memory*/
- for (i = 0; i < header.SectionCount; i++)
+ for (i = (0U); i < header.SectionCount; i++)
{
fp_readData(§ion, srcAddr, sizeof (rprcSectionHeader_t));
/* Get offset into ATCM */
SBL_log(SBL_LOG_MAX, "Translating MCU1 local ATCM addr 0x%x to ", section.addr);
section.addr = section.addr - CSL_MCU_ATCM_BASE;
- section.addr = CSL_MCU_ARMSS0_CORE1_ATCM_BASE + section.addr;
+ section.addr = (uint32_t)(CSL_MCU_ARMSS0_CORE1_ATCM_BASE) + section.addr;
SBL_log(SBL_LOG_MAX, "SoC MCU1 ATCM addr 0x%x\n", section.addr);
}
else if ((section.addr >= CSL_MCU_BTCM_BASE) &&
/* Get offset into BTCM */
SBL_log(SBL_LOG_MAX, "Translating MCU1 local BTCM addr 0x%x to ", section.addr);
section.addr = section.addr - CSL_MCU_BTCM_BASE;
- section.addr = CSL_MCU_ARMSS0_CORE1_BTCM_BASE + section.addr;
+ section.addr = (uint32_t)(CSL_MCU_ARMSS0_CORE1_BTCM_BASE) + section.addr;
SBL_log(SBL_LOG_MAX, "SoC MCU1 BTCM addr 0x%x\n", section.addr);
}
else
}
SBL_log(SBL_LOG_MAX, "Copying 0x%x bytes to 0x%x\n", section.size, section.addr);
- fp_readData((void *) section.addr, srcAddr, section.size);
+ fp_readData((void *)(section.addr), srcAddr, section.size);
#ifdef BUILD_MCU
- CSL_armR5CacheWbInv((const void *)section.addr, section.size);
+ CSL_armR5CacheWbInv((const void *)(section.addr), (int32_t)(section.size));
#endif
}
}
* \return Return the device id
*
**/
-int32_t GetDeviceId(void)
+uint32_t GetDeviceId(void)
{
- int32_t deviceId = 55;
+ uint32_t deviceId = 55U;
return (deviceId);
}
diff --git a/src/rprc/sbl_rprc.h b/src/rprc/sbl_rprc.h
--- /dev/null
+++ b/src/rprc/sbl_rprc.h
@@ -0,0 +1,185 @@
+/**
+ * \file sbl_rprc.h
+ *
+ * \brief This file contains function prototypes of RPRC image parse functions.
+ *
+ */
+
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef SBL_RPRC_H_
+#define SBL_RPRC_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/csl/cslr_device.h>
+#include <ti/csl/arch/csl_arch.h>
+#include <soc/sbl_soc.h>
+#include <stdio.h>
+
+#if defined(SOC_AM65XX)
+#include "sbl_log.h"
+#include <ti/board/board.h>
+#include <ti/drv/pm/include/pm_types.h>
+#include <ti/drv/pm/include/pmlib_clkrate.h>
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+/* Magic numbers for gforge and sourceforge */
+#define MAGIC_NUM_GF (0xA1ACED00)
+#define MAGIC_NUM_SF (0x55424CBB)
+
+/* Magic number and tokens for RPRC format */
+#define RPRC_MAGIC_NUMBER 0x43525052
+#define RPRC_RESOURCE 0
+#define RPRC_BOOTADDR 5
+
+#define MAX_INPUT_FILES 10
+#define META_HDR_MAGIC_STR 0x5254534D /* MSTR in ascii */
+#define META_HDR_MAGIC_END 0x444E454D /* MEND in ascii */
+
+#if !defined(OMAPL137_BUILD)
+#define SOC_OCMC_RAM1_SIZE ((uint32_t) 0x80000) /*OCMC1 512KB*/
+#define SOC_OCMC_RAM2_SIZE ((uint32_t) 0x100000) /*OCMC2 1MB */
+#define SOC_OCMC_RAM3_SIZE ((uint32_t) 0x100000) /*OCMC3 1MB */
+
+#define MPU_IPU1_ROM (CSL_IPU_IPU1_TARGET_REGS)
+
+#define MPU_IPU1_RAM (CSL_IPU_IPU1_TARGET_REGS + \
+ (uint32_t) 0x20000)
+
+#define MPU_IPU2_ROM (CSL_IPU_IPU1_ROM_REGS)
+
+#define MPU_IPU2_RAM (CSL_IPU_IPU1_ROM_REGS + \
+ (uint32_t) 0x20000)
+
+#define MPU_DSP1_L2_RAM (0x40800000)
+#define MPU_DSP1_L1P_CACHE (0x40E00000)
+#define MPU_DSP1_L1D_CACHE (0x40F00000)
+#define MPU_DSP2_L2_RAM (0x41000000)
+#define MPU_DSP2_L1P_CACHE (0x41600000)
+#define MPU_DSP2_L1D_CACHE (0x41700000)
+
+#if !defined(SOC_AM574x)
+#define SOC_DSP_L2_BASE (0x800000)
+#define SOC_DSP_L1P_BASE (0xe00000)
+#define SOC_DSP_L1D_BASE (0xf00000)
+#endif
+#endif
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+typedef struct rprcFileHeader {
+ uint32_t magic;
+ uint32_t entry;
+ uint32_t rsvd_addr;
+ uint32_t SectionCount;
+ uint32_t version;
+} rprcFileHeader_t;
+
+typedef struct rprcSectionHeader {
+ uint32_t addr;
+ uint32_t rsvd_addr;
+ uint32_t size;
+ uint32_t rsvdCrc;
+ uint32_t rsvd;
+} rprcSectionHeader_t;
+
+typedef struct meta_header_start
+{
+ uint32_t magic_str;
+ uint32_t num_files;
+ uint32_t dev_id;
+ uint32_t rsvd;
+}meta_header_start_t;
+
+typedef struct meta_header_core
+{
+ uint32_t core_id;
+ uint32_t image_offset;
+}meta_header_core_t;
+
+typedef struct meta_header_end
+{
+ uint32_t rsvd;
+ uint32_t magic_string_end;
+}meta_header_end_t;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+/**
+ * \brief SBL_RprcImageParse function parse the RPRC executable image.
+ * Copies individual section into destination location
+ *
+ * \param[in] srcAddr - Pointer RPRC image
+ * \param[out] entryPoint - CPU entry point address
+ * \param[in] CoreId - CPU ID to identify the CPU core
+ *
+ *
+ * \return uint32_t: Status (success or failure)
+ */
+static int32_t SBL_RprcImageParse(void *srcAddr, uint32_t *entryPoint,
+ int32_t CoreId);
+
+/**
+ * \brief SBL_BootCore function stores the CPU entry location into
+ * global pointer.
+ *
+ * \param[in] entry - CPU Entry location
+ * \param[in] entryPoint - CPU ID
+ *
+ * \return none
+ */
+void SBL_BootCore(uint32_t entry, uint32_t CoreID, sblEntryPoint_t *pAppEntry);
+
+uint32_t GetDeviceId(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*SBL_RPRC_PARSE_H_*/
+
index e19eb2a02ef936fbf3c542b844a7d18811c3676d..c932c2c0bbe4b5a45f236c03d154a5bd805798c7 100644 (file)
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
-
-
#ifndef E_PASS
#define E_PASS ((int32_t)(0))
#endif
/* Function Pointer used while reading data from the storage. */
extern void (*fp_seek)(void *srcAddr, uint32_t location);
-
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
*/
int32_t SBL_MulticoreImageParse(void *srcAddr,
uint32_t ImageOffset,
- sblEntryPoint_t *pEntry);
+ sblEntryPoint_t *pAppEntry);
#ifdef __cplusplus
}
diff --git a/tools/flashWriter/qspi/src/sbl_qspi_writer.c b/tools/flashWriter/qspi/src/sbl_qspi_writer.c
index 9e0db095b5e83b4793ce97217bfeac02403622ed..6f7a0b6e627958ba369103c4107871e08a5e3c45 100644 (file)
/* File name which need to be copied from mmcsd to QSPI */
char fileName[9U];
/* Offset address where the flash image is to be written */
- int offsetAddr = 0U;
+ uint32_t offsetAddr = 0U;
/* DDR address where image has to be copied from mmcsd card.
* The image is then copied from this address to QSPI flash
*/
{
while(0U != f_gets(gTmpBuf, sizeof(gTmpBuf), &fileObject))
{
- if ( -1 != sscanf(gTmpBuf,"%s %x", fileName, &offsetAddr))
+ if ( -1 != sscanf(gTmpBuf,"%8s %x", fileName, &offsetAddr))
{
status = S_PASS;
}