summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: c55fba4)
raw | patch | inline | side by side (parent: c55fba4)
author | Madan Srinivas <madans@ti.com> | |
Mon, 13 Aug 2018 16:19:05 +0000 (12:19 -0400) | ||
committer | Madan Srinivas <madans@ti.com> | |
Mon, 13 Aug 2018 16:19:05 +0000 (12:19 -0400) |
In SYFW2018.07a, some of the dev ids for the MCU clocks were changed.
This causes the SBL build to break.
Signed-off-by: Madan Srinivas <madans@ti.com>
This causes the SBL build to break.
Signed-off-by: Madan Srinivas <madans@ti.com>
soc/am65xx/sbl_slave_core_boot.c | patch | blob | history |
index 673e75b20125aa91bb4668c6aeffe62acdcc2ca2..87401f2993be5644770b69c93bcd4b87150b0873 100644 (file)
@@ -129,8 +129,8 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
TISCI_DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK,
TISCI_DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK,
TISCI_DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK,
- TISCI_DEV_MCU_ARMSS0_BUS_CPU0_CLK,
- TISCI_DEV_MCU_ARMSS0_BUS_CPU1_CLK
+ TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,
+ TISCI_DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK
};
const int32_t map_cpu_freq_hz[] =