Change of macros to make SBL Hyperflash porting between SOCs easy

- SBL_HYPERFLASH_BASE_ADDRESS and SBL_HYPERFLASH_CTLR_BASE_ADDRESS defined in
  sbl_soc_cfg.c

diff --git a/soc/k3/sbl_soc_cfg.h b/soc/k3/sbl_soc_cfg.h
index 8e602fb7176b24871e4aa87707852bff822cd4de..105ca83be0a9f518d464861a280d55fe9edd82bd 100755 (executable)
--- a/soc/k3/sbl_soc_cfg.h
+++ b/soc/k3/sbl_soc_cfg.h
@@ -366,6 +366,9 @@ extern sblRatCfgInfo_t* sblRatCfgList;
 #define SBL_CLK_ID_DSP2_C7X         (0xBAD00000)
 #define SBL_DSP2_C7X_FREQ_HZ        (0xBAD00000)
 
+#define SBL_HYPERFLASH_BASE_ADDRESS      (CSL_MCU_FSS0_DAT_REG1_BASE)
+#define SBL_HYPERFLASH_CTLR_BASE_ADDRESS (CSL_FSS0_HPB_CTRL_BASE)
+
 #endif
 
 /* ========================================================================== */

diff --git a/src/hyperflash/sbl_hyperflash.c b/src/hyperflash/sbl_hyperflash.c
index c28203a69654b5f790dd7a39713f16a8448ab55a..918d3e10c27c01ca887476b8810e8595318d8cab 100644 (file)
--- a/src/hyperflash/sbl_hyperflash.c
+++ b/src/hyperflash/sbl_hyperflash.c
@@ -49,6 +49,7 @@
 #include "sbl_rprc_parse.h"
 #include "sbl_err_trap.h"
 #include "sbl_sci_client.h"
+#include "sbl_soc_cfg.h"
 
 /* TI-RTOS Header files */
 #include <ti/drv/gpio/soc/GPIO_soc.h>
@@ -75,9 +76,9 @@
 #define HYPERFLASH_OFFSET_SI              (0xC0000U)
 #define HYPERFLASH_OFFSET_SYSFW           (0x40000U)
 
-uint32_t gBaseAddress = CSL_MCU_FSS0_DAT_REG1_BASE;
+uint32_t gBaseAddress = SBL_HYPERFLASH_BASE_ADDRESS;
 
-CSL_hyperbus_coreRegs *hpbCoreRegs = (CSL_hyperbus_coreRegs *) (CSL_FSS0_HPB_CTRL_BASE);
+CSL_hyperbus_coreRegs *hpbCoreRegs = (CSL_hyperbus_coreRegs *) (SBL_HYPERFLASH_CTLR_BASE_ADDRESS);
 
 int8_t Hyperflash_mdllLocked(void);
 static void SBL_HYPERFLASH_seek(void *srcAddr, uint32_t location);