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raw | patch | inline | side by side (parent: f2f101e)
author | Madan Srinivas <a0756974@ti.com> | |
Mon, 20 May 2019 15:43:44 +0000 (11:43 -0400) | ||
committer | Madan Srinivas <a0756974@ti.com> | |
Tue, 21 May 2019 18:49:06 +0000 (14:49 -0400) |
To switch MCU cluster 0 from lockstep to split mode, the SBL needs to
halt and unhalt the MCU 0 cores, when the SYSFW is waiting for WFI.
To do this, the Sciclient_procBootSetSequenceCtrl must be able to
send a message to SYSFW and return successfully without waiting for
the status. This patch adds this support to the API.
Signed-off-by: Madan Srinivas<madans@ti.com>
halt and unhalt the MCU 0 cores, when the SYSFW is waiting for WFI.
To do this, the Sciclient_procBootSetSequenceCtrl must be able to
send a message to SYSFW and return successfully without waiting for
the status. This patch adds this support to the API.
Signed-off-by: Madan Srinivas<madans@ti.com>
include/sciclient_procboot.h | patch | blob | history | |
src/sciclient_dummy.c | patch | blob | history | |
src/sciclient_procboot.c | patch | blob | history |
index 012de101b63ef925db07074cb2f98a4284499630..e1f897a69ec8681a8f2362ec98b50aa718604d0a 100755 (executable)
* \param control_flags_1_clear Optional Processor specific Control Flags to clear.
* Setting a bit here implies required bit has to be
* cleared to 0.
+ * \param reqFlag Can be TISCI_MSG_FLAG_AOR/TISCI_MSG_FLAG_AOP ORRed
+ * with additional flag that can be set to alter the
+ * device state.
* \param timeout Gives a sense of how long to wait for the operation.
* Refer \ref Sciclient_ServiceOperationTimeout.
* \return CSL_PASS on success, else failure
int32_t Sciclient_procBootSetSequenceCtrl(uint8_t processorId,
uint32_t control_flags_1_set,
uint32_t control_flags_1_clear,
+ uint32_t reqFlag,
uint32_t timeout);
/**
diff --git a/src/sciclient_dummy.c b/src/sciclient_dummy.c
index 03954aae53a0c6d2c058e9d20b8b2dfb2170495d..656f51be9d54ea55a0dfa2740a6971a87f56108a 100644 (file)
--- a/src/sciclient_dummy.c
+++ b/src/sciclient_dummy.c
int32_t Sciclient_procBootSetSequenceCtrl(uint8_t processorId,
uint32_t control_flags_1_set,
uint32_t control_flags_1_clear,
+ uint32_t reqFlag,
uint32_t timeout)
{
int32_t retVal = CSL_PASS;
index 473524c25947e874c9db02b1740ad6586963c510..057cb9b12a0d6f64caaf127cc386c1347e360578 100755 (executable)
--- a/src/sciclient_procboot.c
+++ b/src/sciclient_procboot.c
int32_t Sciclient_procBootSetSequenceCtrl(uint8_t processorId,
uint32_t control_flags_1_set,
uint32_t control_flags_1_clear,
+ uint32_t reqFlag,
uint32_t timeout)
{
int32_t retVal = CSL_PASS;
struct tisci_msg_proc_set_control_resp response;
Sciclient_ReqPrm_t reqParam ;
reqParam.messageType = (uint16_t) TISCI_MSG_PROC_SET_CONTROL;
- reqParam.flags = (uint32_t) TISCI_MSG_FLAG_AOP;
+ reqParam.flags = (uint32_t) reqFlag;
reqParam.pReqPayload = (const uint8_t *) &request;
reqParam.reqPayloadSize = (uint32_t) sizeof (request);
reqParam.timeout = (uint32_t) timeout;
respParam.pRespPayload = (uint8_t *) &response;
respParam.respPayloadSize = (uint32_t) sizeof (response);
- retVal = Sciclient_service(&reqParam, &respParam);
+ if (((reqFlag & TISCI_MSG_FLAG_AOP) != TISCI_MSG_FLAG_AOP)&&
+ (reqFlag != 0))
+ {
+ retVal = CSL_EFAIL;
+ }
+ if(retVal == CSL_PASS)
+ {
+ retVal = Sciclient_service(&reqParam, &respParam);
+ }
if((retVal != CSL_PASS) ||
- ((respParam.flags & TISCI_MSG_FLAG_ACK) != TISCI_MSG_FLAG_ACK))
+ ((reqFlag != 0) &&
+ ((respParam.flags & TISCI_MSG_FLAG_ACK) != TISCI_MSG_FLAG_ACK)))
{
retVal = CSL_EFAIL;
}