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raw | patch | inline | side by side (parent: 030e9cc)
raw | patch | inline | side by side (parent: 030e9cc)
author | Piyali Goswami <piyali_g@ti.com> | |
Fri, 17 May 2019 14:14:45 +0000 (19:44 +0530) | ||
committer | Piyali Goswami <piyali_g@ti.com> | |
Fri, 17 May 2019 17:15:05 +0000 (22:45 +0530) |
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
index 7f832b0ad9b8a8b22cd50b4f9cf2acf2de38d861..0e7950cdcbccc8d974a564d7dd870cb9c2d62bb9 100755 (executable)
#if defined (__aarch64__)
#include <ti/sysbios/family/arm/v8a/Mmu.h>
#endif
+#if defined (__C7100__)
+#include <ti/sysbios/family/c7x/Mmu.h>
+#endif
#endif
#include <stdio.h>
"\n-----------------------------------------------------------------------------------------------------------\r\n");
}
-uint8_t App_sciclientGetChar()
-{
- uint8_t retVal = 0U;
- retVal = UART_getc();
- return retVal;
-}
-
uint32_t App_sciclientGetNum()
{
uint32_t number=0U, numberOfBytes=0U;
goto mmu_exit;
}
+ retVal = Mmu_map(0x78000000, 0x78000000, 0x8000000, &attrs); /* msmc */
+ if(retVal == FALSE)
+ {
+ goto mmu_exit;
+ }
+
attrs.attrIndx = Mmu_AttrIndx_MAIR7;
retVal = Mmu_map(0x80000000, 0x80000000, 0x20000000, &attrs); /* ddr */
goto mmu_exit;
}
- retVal = Mmu_map(0x70000000, 0x70000000, 0x10000000, &attrs); /* msmc */
+ retVal = Mmu_map(0x70000000, 0x70000000, 0x5800000, &attrs); /* msmc */
if(retVal == FALSE)
{
goto mmu_exit;
index 4735bd153a72683fb01cff36828d416fba929359..294da102874eed948c86a896b0e30a29d7c48588 100755 (executable)
#define PRINT_RESULTS ('g')
#define PARSER_QUIT ('q')
/* @} */
-
+#if defined (__C7100__)
+#define App_sciclientPrintf printf
+#define App_sciclientGetChar getchar
+#else
#define App_sciclientPrintf UART_printf
+#define App_sciclientGetChar UART_getc
+#endif
/* ========================================================================== */
/* Structures and Enums */
*/
int32_t App_sciclientTestMain(App_sciclientTestParams_t *testParams);
-void App_sciclientPrintf(const char *pcString, ...);
-
-uint8_t App_sciclientGetChar();
-
uint32_t App_sciclientGetNum();
void App_sciclientConsoleInit();
index 254c9f72a63e66c837deb78b0fae6ccf8c889afc..5897d8c36cb3d63acb113cff11b5187c9e7f3753 100755 (executable)
INCLUDE_EXTERNAL_INTERFACES = pdk sciclient osal_tirtos board uart bios xdc\r
\r
# List all the components required by the application\r
-COMP_LIST_COMMON = sciclient csl osal_tirtos board uart bios xdc\r
+COMP_LIST_COMMON = sciclient csl osal_tirtos board uart bios xdc i2c\r
ifeq ($(ARCH),c66x)\r
COMP_LIST_COMMON += csl_intc\r
else\r
diff --git a/examples/sciclient_unit_testapp/sciclient_ut_main.c b/examples/sciclient_unit_testapp/sciclient_ut_main.c
index f8b6bac523308db92011a18e63247acad554f560..78cb141a96079f0005537663513b79ae510d9dc1 100755 (executable)
/* ========================================================================== */\r
\r
static volatile int32_t gTestStatus;\r
+static uint8_t gAppTskStackMain[16*1024] __attribute__((aligned(8192)));;\r
+/* IMPORTANT NOTE: For C7x, \r
+ * - stack size and stack ptr MUST be 8KB aligned \r
+ * - AND min stack size MUST be 16KB \r
+ * - AND stack assigned for task context is "size - 8KB"\r
+ * - 8KB chunk for the stack area is used for interrupt handling in this task context\r
+ */\r
\r
/* ========================================================================== */\r
/* Function Definitions */\r
Task_Params taskParams;\r
Error_Block eb;\r
uint32_t retVal = CSL_PASS;\r
+ #if defined (__C7100__)\r
+ int *CLEC = (int *)0x7ce01000;\r
+ *CLEC = 0x403c000e;\r
+ #endif\r
\r
Task_Params_init(&taskParams);\r
taskParams.priority = 14;\r
+ taskParams.stack = gAppTskStackMain;\r
+ taskParams.stackSize = sizeof (gAppTskStackMain);\r
\r
Error_init(&eb);\r
App_sciclientConsoleInit();\r
index a5dfe88ef6bb70d22993bfc99113c2f3722ab922..9537121b7fae47a88c521576ef7c493a27112a08 100755 (executable)
#define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1536U)
/* @} */
+#define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
+#define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)
+
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
index c8d841d623d31ecab1d21b8c920e3549b2a14adf..511920eb6e49971f73dba292c985d6e22a19e857 100755 (executable)
/** Thread ID of the notification thread(read) available for the CPU */
TISCI_SEC_PROXY_C7X_0_READ_NOTIFY_THREAD_ID,
/** Notification Interrupt Number. */
- CSLR_COMPUTE_CLUSTER0_GIC_SPI_NAVSS0_INTR_PEND_191
+ SCICLIENT_C7X_SECURE_INTERRUPT_NUM
},
{
/** Context **/
/** Thread ID of the notification thread(read) available for the CPU */
TISCI_SEC_PROXY_C7X_1_READ_NOTIFY_THREAD_ID,
/** Notification Interrupt Number. */
- CSLR_COMPUTE_CLUSTER0_GIC_SPI_NAVSS0_INTR_PEND_189
+ SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM
},
{
/** Context **/
diff --git a/src/sciclient.c b/src/sciclient.c
index bb774c56d357a5c4d365f8cd63ac36d25b06dc9e..ad5b4951774cecf43ff42e97e7ae069d5c082fba 100755 (executable)
--- a/src/sciclient.c
+++ b/src/sciclient.c
#include <ti/drv/sciclient/src/sciclient_priv.h>
#include <ti/csl/soc.h>
#include <string.h> /*For memcpy*/
+#include <ti/csl/csl_clec.h>
/* ========================================================================== */
/* Macros & Typedefs */
intrPrms.corepacConfig.corepacEventNum = 0U;
intrPrms.corepacConfig.intVecNum = gSciclientMap[contextId].respIntrNum;
#endif
+ #if defined (__C7100__)
+ {
+ CSL_CLEC_EVTRegs * regs = (CSL_CLEC_EVTRegs *) CSL_COMPUTE_CLUSTER0_CLEC_BASE;
+ CSL_ClecEventConfig evtCfg;
+ evtCfg.secureClaimEnable = 0;
+ evtCfg.evtSendEnable = 1;
+ evtCfg.rtMap = 0x3C;
+ evtCfg.extEvtNum = 0x0;
+ evtCfg.c7xEvtNum = SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM;
+ /* Clec interrupt number 1024 is connected to GIC interrupt number 32 in J721E.
+ * Due to this for CLEC programming one needs to add an offset of 992 (1024 - 32)
+ * to the event number which is shared between GIC and CLEC.
+ */
+ CSL_clecConfigEvent(regs, CSLR_COMPUTE_CLUSTER0_GIC_SPI_NAVSS0_INTR_PEND_189 + 992, &evtCfg);
+ intrPrms.corepacConfig.priority = 1U;
+ }
+ #endif
/* Clear Interrupt */
Osal_ClearInterrupt(intrPrms.corepacConfig.corepacEventNum, intrPrms.corepacConfig.intVecNum);
/* Register interrupts */
intrPrms.corepacConfig.corepacEventNum = 0U;
intrPrms.corepacConfig.intVecNum = gSciclientMap[contextId].respIntrNum;
#endif
+ #if defined (__C7100__)
+ {
+ CSL_CLEC_EVTRegs * regs = (CSL_CLEC_EVTRegs *) CSL_COMPUTE_CLUSTER0_CLEC_BASE;
+ CSL_ClecEventConfig evtCfg;
+ evtCfg.secureClaimEnable = 0;
+ evtCfg.evtSendEnable = 1;
+ evtCfg.rtMap = 0x3C;
+ evtCfg.extEvtNum = 0x0;
+ evtCfg.c7xEvtNum = SCICLIENT_C7X_SECURE_INTERRUPT_NUM;
+ /* Clec interrupt number 1024 is connected to GIC interrupt number 32 in J721E.
+ * Due to this for CLEC programming one needs to add an offset of 992 (1024 - 32)
+ * to the event number which is shared between GIC and CLEC.
+ */
+ CSL_clecConfigEvent(regs, CSLR_COMPUTE_CLUSTER0_GIC_SPI_NAVSS0_INTR_PEND_191 + 992, &evtCfg);
+ intrPrms.corepacConfig.priority = 1U;
+ }
+ #endif
/* Clear Interrupt */
Osal_ClearInterrupt(intrPrms.corepacConfig.corepacEventNum, intrPrms.corepacConfig.intVecNum);
/* Register interrupts */