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raw | patch | inline | side by side (parent: ccf7389)
raw | patch | inline | side by side (parent: ccf7389)
| author | Prasad Konnur <prasadkonnur@ti.com> | |
| Wed, 18 Sep 2019 13:12:51 +0000 (18:42 +0530) | ||
| committer | Sivaraj R <sivaraj@ti.com> | |
| Thu, 19 Sep 2019 06:49:33 +0000 (01:49 -0500) |
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
| soc/V1/sciclient_defaultBoardcfg.c | patch | blob | history | |
| soc/V1/sciclient_fmwMsgParams.h | patch | blob | history | |
| src/sciclient.c | patch | blob | history |
index 55299f51d90b3580d6c348823e4fe6daee0ca632..1c738edb0f635768d7b7106a0a637705cb4216b3 100755 (executable)
.control = {
.subhdr = {
.magic = TISCI_BOARDCFG_CONTROL_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_control),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_control),
},
-
+
/* Enable/disable support for System Firmware main isolation.
* If disabled, main isolation SCI message will be rejected with NAK.
*/
.secproxy = {
.subhdr = {
.magic = TISCI_BOARDCFG_SECPROXY_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_secproxy),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_secproxy),
},
/* Memory allocation for messages scaling factor. In current design,
* only value of “1” is supported. For future design, a value of “2”
.msmc = {
.subhdr = {
.magic = TISCI_BOARDCFG_MSMC_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_msmc),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_msmc),
},
/* If the whole memory is X MB the value you write to this field is n.
* The value of n sets the cache size as n * X/32. The value of n should
.debug_cfg = {
.subhdr = {
.magic = TISCI_BOARDCFG_DBG_CFG_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_dbg_cfg),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_dbg_cfg),
},
/* This enables the trace for DMSC logging. Should be used only for
* debug.
.host_cfg = {
.subhdr = {
.magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_rm_host_cfg),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
},
.host_cfg_entries = {
[0] = {
* invalid/errors. These are encoded in a bitfield because
* there is one set of allowed order-IDs for every host ID.
*/
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
/* Allowed bus priority configuration for host ID. The host
* ID gets assigned a list of bus priorities which are
* allowed. As bus priority is a 3-bit field, there are 8
[1] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[2] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[3] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[4] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[5] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[6] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[7] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[8] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[9] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[10] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[11] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[12] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[13] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[14] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[15] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[16] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[17] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[18] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[19] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[20] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[21] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[22] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[23] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
[24] = {
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
- .allowed_orderid = 0xAAAAAAAA,
+ .allowed_orderid = 0xAAAAAAAAU,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
}
.resasg = {
.subhdr = {
.magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_rm_resasg),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
},
.resasg_entries_size = TISCI_BOARDCFG_RM_RESASG_ENTRIES * sizeof(struct tisci_boardcfg_rm_resasg_entry),
},
.processor_acl_list = {
.subhdr = {
.magic = TISCI_BOARDCFG_PROC_ACL_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_proc_acl),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_proc_acl),
},
.proc_acl_entries = {0},
},
.host_hierarchy = {
.subhdr = {
.magic = TISCI_BOARDCFG_HOST_HIERARCHY_MAGIC_NUM,
- .size = sizeof(struct tisci_boardcfg_host_hierarchy),
+ .size = (uint16_t) sizeof(struct tisci_boardcfg_host_hierarchy),
},
.host_hierarchy_entries = {0},
},
};
#endif
+
index 0477f0d86516460c5b73dc7efcaea74f23425dec..eb0a7e699dce2152aae934e507b54a53fe433b49 100755 (executable)
* @{
* Power Management Module Device IDs
*/
-#define TISCI_DEV_MCU_ADC0 (0)
-#define TISCI_DEV_MCU_ADC1 (1)
-#define TISCI_DEV_ATL0 (2)
-#define TISCI_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0 (3)
-#define TISCI_DEV_A72SS0 (4)
-#define TISCI_DEV_COMPUTE_CLUSTER0_CFG_WRAP (5)
-#define TISCI_DEV_COMPUTE_CLUSTER0_CLEC (6)
-#define TISCI_DEV_COMPUTE_CLUSTER0_CORE_CORE (7)
-#define TISCI_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW (8)
-#define TISCI_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP (9)
-#define TISCI_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0 (10)
-#define TISCI_DEV_COMPUTE_CLUSTER0_DIVP_TFT0 (11)
-#define TISCI_DEV_COMPUTE_CLUSTER0_DMSC_WRAP (12)
-#define TISCI_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN (13)
-#define TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS (14)
-#define TISCI_DEV_C71SS0 (15)
-#define TISCI_DEV_C71SS0_MMA (16)
-#define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_WRAP (17)
-#define TISCI_DEV_MCU_CPSW0 (18)
-#define TISCI_DEV_CPSW0 (19)
-#define TISCI_DEV_CPT2_AGGR0 (20)
-#define TISCI_DEV_CPT2_AGGR1 (21)
-#define TISCI_DEV_DMSC_WKUP_0 (22)
-#define TISCI_DEV_CPT2_AGGR2 (23)
-#define TISCI_DEV_MCU_CPT2_AGGR0 (24)
-#define TISCI_DEV_CSI_PSILSS0 (25)
-#define TISCI_DEV_CSI_RX_IF0 (26)
-#define TISCI_DEV_CSI_RX_IF1 (27)
-#define TISCI_DEV_CSI_TX_IF0 (28)
-#define TISCI_DEV_STM0 (29)
-#define TISCI_DEV_DCC0 (30)
-#define TISCI_DEV_DCC1 (31)
-#define TISCI_DEV_DCC2 (32)
-#define TISCI_DEV_DCC3 (33)
-#define TISCI_DEV_DCC4 (34)
-#define TISCI_DEV_MCU_TIMER0 (35)
-#define TISCI_DEV_DCC5 (36)
-#define TISCI_DEV_DCC6 (37)
-#define TISCI_DEV_DCC7 (38)
-#define TISCI_DEV_DCC8 (39)
-#define TISCI_DEV_DCC9 (40)
-#define TISCI_DEV_DCC10 (41)
-#define TISCI_DEV_DCC11 (42)
-#define TISCI_DEV_DCC12 (43)
-#define TISCI_DEV_MCU_DCC0 (44)
-#define TISCI_DEV_MCU_DCC1 (45)
-#define TISCI_DEV_MCU_DCC2 (46)
-#define TISCI_DEV_DDR0 (47)
-#define TISCI_DEV_DMPAC_TOP_MAIN_0 (48)
-#define TISCI_DEV_TIMER0 (49)
-#define TISCI_DEV_TIMER1 (50)
-#define TISCI_DEV_TIMER2 (51)
-#define TISCI_DEV_TIMER3 (52)
-#define TISCI_DEV_TIMER4 (53)
-#define TISCI_DEV_TIMER5 (54)
-#define TISCI_DEV_TIMER6 (55)
-#define TISCI_DEV_TIMER7 (57)
-#define TISCI_DEV_TIMER8 (58)
-#define TISCI_DEV_TIMER9 (59)
-#define TISCI_DEV_TIMER10 (60)
-#define TISCI_DEV_GTC0 (61)
-#define TISCI_DEV_TIMER11 (62)
-#define TISCI_DEV_TIMER12 (63)
-#define TISCI_DEV_TIMER13 (64)
-#define TISCI_DEV_TIMER14 (65)
-#define TISCI_DEV_TIMER15 (66)
-#define TISCI_DEV_TIMER16 (67)
-#define TISCI_DEV_TIMER17 (68)
-#define TISCI_DEV_TIMER18 (69)
-#define TISCI_DEV_TIMER19 (70)
-#define TISCI_DEV_MCU_TIMER1 (71)
-#define TISCI_DEV_MCU_TIMER2 (72)
-#define TISCI_DEV_MCU_TIMER3 (73)
-#define TISCI_DEV_MCU_TIMER4 (74)
-#define TISCI_DEV_MCU_TIMER5 (75)
-#define TISCI_DEV_MCU_TIMER6 (76)
-#define TISCI_DEV_MCU_TIMER7 (77)
-#define TISCI_DEV_MCU_TIMER8 (78)
-#define TISCI_DEV_MCU_TIMER9 (79)
-#define TISCI_DEV_ECAP0 (80)
-#define TISCI_DEV_ECAP1 (81)
-#define TISCI_DEV_ECAP2 (82)
-#define TISCI_DEV_EHRPWM0 (83)
-#define TISCI_DEV_EHRPWM1 (84)
-#define TISCI_DEV_EHRPWM2 (85)
-#define TISCI_DEV_EHRPWM3 (86)
-#define TISCI_DEV_EHRPWM4 (87)
-#define TISCI_DEV_EHRPWM5 (88)
-#define TISCI_DEV_ELM0 (89)
-#define TISCI_DEV_EMIF_DATA_0_VD (90)
-#define TISCI_DEV_MMCSD0 (91)
-#define TISCI_DEV_MMCSD1 (92)
-#define TISCI_DEV_MMCSD2 (93)
-#define TISCI_DEV_EQEP0 (94)
-#define TISCI_DEV_EQEP1 (95)
-#define TISCI_DEV_EQEP2 (96)
-#define TISCI_DEV_ESM0 (97)
-#define TISCI_DEV_MCU_ESM0 (98)
-#define TISCI_DEV_WKUP_ESM0 (99)
-#define TISCI_DEV_FSS_MCU_0 (100)
-#define TISCI_DEV_MCU_FSS0_FSAS_0 (101)
-#define TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0 (102)
-#define TISCI_DEV_MCU_FSS0_OSPI_0 (103)
-#define TISCI_DEV_MCU_FSS0_OSPI_1 (104)
-#define TISCI_DEV_GPIO0 (105)
-#define TISCI_DEV_GPIO1 (106)
-#define TISCI_DEV_GPIO2 (107)
-#define TISCI_DEV_GPIO3 (108)
-#define TISCI_DEV_GPIO4 (109)
-#define TISCI_DEV_GPIO5 (110)
-#define TISCI_DEV_GPIO6 (111)
-#define TISCI_DEV_GPIO7 (112)
-#define TISCI_DEV_WKUP_GPIO0 (113)
-#define TISCI_DEV_WKUP_GPIO1 (114)
-#define TISCI_DEV_GPMC0 (115)
-#define TISCI_DEV_I3C0 (116)
-#define TISCI_DEV_MCU_I3C0 (117)
-#define TISCI_DEV_MCU_I3C1 (118)
-#define TISCI_DEV_PRU_ICSSG0 (119)
-#define TISCI_DEV_PRU_ICSSG1 (120)
-#define TISCI_DEV_C66SS0_INTROUTER0 (121)
-#define TISCI_DEV_C66SS1_INTROUTER0 (122)
-#define TISCI_DEV_CMPEVENT_INTRTR0 (123)
-#define TISCI_DEV_J7_LASCAR_GPU_WRAP_MAIN_0 (124)
-#define TISCI_DEV_GPU0_GPU_0 (125)
-#define TISCI_DEV_GPU0_GPUCORE_0 (126)
-#define TISCI_DEV_LED0 (127)
-#define TISCI_DEV_MAIN2MCU_LVL_INTRTR0 (128)
-#define TISCI_DEV_MAIN2MCU_PLS_INTRTR0 (130)
-#define TISCI_DEV_GPIOMUX_INTRTR0 (131)
-#define TISCI_DEV_WKUP_PORZ_SYNC0 (132)
-#define TISCI_DEV_PSC0 (133)
-#define TISCI_DEV_R5FSS0_INTROUTER0 (134)
-#define TISCI_DEV_R5FSS1_INTROUTER0 (135)
-#define TISCI_DEV_TIMESYNC_INTRTR0 (136)
-#define TISCI_DEV_WKUP_GPIOMUX_INTRTR0 (137)
-#define TISCI_DEV_WKUP_PSC0 (138)
-#define TISCI_DEV_AASRC0 (139)
-#define TISCI_DEV_K3_C66_COREPAC_MAIN_0 (140)
-#define TISCI_DEV_K3_C66_COREPAC_MAIN_1 (141)
-#define TISCI_DEV_C66SS0_CORE0 (142)
-#define TISCI_DEV_C66SS1_CORE0 (143)
-#define TISCI_DEV_DECODER0 (144)
-#define TISCI_DEV_WKUP_DDPA0 (145)
-#define TISCI_DEV_UART0 (146)
-#define TISCI_DEV_DPHY_RX0 (147)
-#define TISCI_DEV_DPHY_RX1 (148)
-#define TISCI_DEV_MCU_UART0 (149)
-#define TISCI_DEV_DSS_DSI0 (150)
-#define TISCI_DEV_DSS_EDP0 (151)
-#define TISCI_DEV_DSS0 (152)
-#define TISCI_DEV_ENCODER0 (153)
-#define TISCI_DEV_WKUP_VTM0 (154)
-#define TISCI_DEV_MAIN2WKUPMCU_VD (155)
-#define TISCI_DEV_MCAN0 (156)
-#define TISCI_DEV_BOARD0 (157)
-#define TISCI_DEV_MCAN1 (158)
-#define TISCI_DEV_MCAN2 (160)
-#define TISCI_DEV_MCAN3 (161)
-#define TISCI_DEV_MCAN4 (162)
-#define TISCI_DEV_MCAN5 (163)
-#define TISCI_DEV_MCAN6 (164)
-#define TISCI_DEV_MCAN7 (165)
-#define TISCI_DEV_MCAN8 (166)
-#define TISCI_DEV_MCAN9 (167)
-#define TISCI_DEV_MCAN10 (168)
-#define TISCI_DEV_MCAN11 (169)
-#define TISCI_DEV_MCAN12 (170)
-#define TISCI_DEV_MCAN13 (171)
-#define TISCI_DEV_MCU_MCAN0 (172)
-#define TISCI_DEV_MCU_MCAN1 (173)
-#define TISCI_DEV_MCASP0 (174)
-#define TISCI_DEV_MCASP1 (175)
-#define TISCI_DEV_MCASP2 (176)
-#define TISCI_DEV_MCASP3 (177)
-#define TISCI_DEV_MCASP4 (178)
-#define TISCI_DEV_MCASP5 (179)
-#define TISCI_DEV_MCASP6 (180)
-#define TISCI_DEV_MCASP7 (181)
-#define TISCI_DEV_MCASP8 (182)
-#define TISCI_DEV_MCASP9 (183)
-#define TISCI_DEV_MCASP10 (184)
-#define TISCI_DEV_MCASP11 (185)
-#define TISCI_DEV_MLB0 (186)
-#define TISCI_DEV_I2C0 (187)
-#define TISCI_DEV_I2C1 (188)
-#define TISCI_DEV_I2C2 (189)
-#define TISCI_DEV_I2C3 (190)
-#define TISCI_DEV_I2C4 (191)
-#define TISCI_DEV_I2C5 (192)
-#define TISCI_DEV_I2C6 (193)
-#define TISCI_DEV_MCU_I2C0 (194)
-#define TISCI_DEV_MCU_I2C1 (195)
-#define TISCI_DEV_WKUP_I2C0 (197)
-#define TISCI_DEV_NAVSS0 (199)
-#define TISCI_DEV_NAVSS0_CPTS_0 (201)
-#define TISCI_DEV_A72SS0_CORE0 (202)
-#define TISCI_DEV_A72SS0_CORE1 (203)
-#define TISCI_DEV_NAVSS0_DTI_0 (206)
-#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_0 (207)
-#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_1 (208)
-#define TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0 (209)
-#define TISCI_DEV_NAVSS0_PROXY_0 (210)
-#define TISCI_DEV_NAVSS0_RINGACC0 (211)
-#define TISCI_DEV_NAVSS0_UDMAP0 (212)
-#define TISCI_DEV_NAVSS0_INTR_ROUTER_0 (213)
-#define TISCI_DEV_NAVSS0_MAILBOX_0 (214)
-#define TISCI_DEV_NAVSS0_MAILBOX_1 (215)
-#define TISCI_DEV_NAVSS0_MAILBOX_2 (216)
-#define TISCI_DEV_NAVSS0_MAILBOX_3 (217)
-#define TISCI_DEV_NAVSS0_MAILBOX_4 (218)
-#define TISCI_DEV_NAVSS0_MAILBOX_5 (219)
-#define TISCI_DEV_NAVSS0_MAILBOX_6 (220)
-#define TISCI_DEV_NAVSS0_MAILBOX_7 (221)
-#define TISCI_DEV_NAVSS0_MAILBOX_8 (222)
-#define TISCI_DEV_NAVSS0_MAILBOX_9 (223)
-#define TISCI_DEV_NAVSS0_MAILBOX_10 (224)
-#define TISCI_DEV_NAVSS0_MAILBOX_11 (225)
-#define TISCI_DEV_NAVSS0_SPINLOCK_0 (226)
-#define TISCI_DEV_NAVSS0_MCRC_0 (227)
-#define TISCI_DEV_NAVSS0_TBU_0 (228)
-#define TISCI_DEV_NAVSS0_TCU_0 (229)
-#define TISCI_DEV_NAVSS0_TIMERMGR_0 (230)
-#define TISCI_DEV_NAVSS0_TIMERMGR_1 (231)
-#define TISCI_DEV_MCU_NAVSS0 (232)
-#define TISCI_DEV_MCU_NAVSS0_INTAGGR_0 (233)
-#define TISCI_DEV_MCU_NAVSS0_PROXY_0 (234)
-#define TISCI_DEV_MCU_NAVSS0_RINGACC0 (235)
-#define TISCI_DEV_MCU_NAVSS0_UDMAP0 (236)
-#define TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0 (237)
-#define TISCI_DEV_MCU_NAVSS0_MCRC_0 (238)
-#define TISCI_DEV_PCIE0 (239)
-#define TISCI_DEV_PCIE1 (240)
-#define TISCI_DEV_PCIE2 (241)
-#define TISCI_DEV_PCIE3 (242)
-#define TISCI_DEV_PULSAR_SL_MAIN_0 (243)
-#define TISCI_DEV_PULSAR_SL_MAIN_1 (244)
-#define TISCI_DEV_R5FSS0_CORE0 (245)
-#define TISCI_DEV_R5FSS0_CORE1 (246)
-#define TISCI_DEV_R5FSS1_CORE0 (247)
-#define TISCI_DEV_R5FSS1_CORE1 (248)
-#define TISCI_DEV_PULSAR_SL_MCU_0 (249)
-#define TISCI_DEV_MCU_R5FSS0_CORE0 (250)
-#define TISCI_DEV_MCU_R5FSS0_CORE1 (251)
-#define TISCI_DEV_RTI0 (252)
-#define TISCI_DEV_RTI1 (253)
-#define TISCI_DEV_RTI24 (254)
-#define TISCI_DEV_RTI25 (255)
-#define TISCI_DEV_RTI16 (256)
-#define TISCI_DEV_RTI15 (257)
-#define TISCI_DEV_RTI28 (258)
-#define TISCI_DEV_RTI29 (259)
-#define TISCI_DEV_RTI30 (260)
-#define TISCI_DEV_RTI31 (261)
-#define TISCI_DEV_MCU_RTI0 (262)
-#define TISCI_DEV_MCU_RTI1 (263)
-#define TISCI_DEV_SA2_UL0 (264)
-#define TISCI_DEV_MCU_SA2_UL0 (265)
-#define TISCI_DEV_MCSPI0 (266)
-#define TISCI_DEV_MCSPI1 (267)
-#define TISCI_DEV_MCSPI2 (268)
-#define TISCI_DEV_MCSPI3 (269)
-#define TISCI_DEV_MCSPI4 (270)
-#define TISCI_DEV_MCSPI5 (271)
-#define TISCI_DEV_MCSPI6 (272)
-#define TISCI_DEV_MCSPI7 (273)
-#define TISCI_DEV_MCU_MCSPI0 (274)
-#define TISCI_DEV_MCU_MCSPI1 (275)
-#define TISCI_DEV_MCU_MCSPI2 (276)
-#define TISCI_DEV_UFS0 (277)
-#define TISCI_DEV_UART1 (278)
-#define TISCI_DEV_UART2 (279)
-#define TISCI_DEV_UART3 (280)
-#define TISCI_DEV_UART4 (281)
-#define TISCI_DEV_UART5 (282)
-#define TISCI_DEV_UART6 (283)
-#define TISCI_DEV_UART7 (284)
-#define TISCI_DEV_UART8 (285)
-#define TISCI_DEV_UART9 (286)
-#define TISCI_DEV_WKUP_UART0 (287)
-#define TISCI_DEV_USB0 (288)
-#define TISCI_DEV_USB1 (289)
-#define TISCI_DEV_VPAC_TOP_MAIN_0 (290)
-#define TISCI_DEV_VPFE0 (291)
-#define TISCI_DEV_SERDES_16G0 (292)
-#define TISCI_DEV_SERDES_16G1 (293)
-#define TISCI_DEV_SERDES_16G2 (294)
-#define TISCI_DEV_SERDES_16G3 (295)
-#define TISCI_DEV_DPHY_TX0 (296)
-#define TISCI_DEV_SERDES_10G0 (297)
-#define TISCI_DEV_WKUPMCU2MAIN_VD (298)
-#define TISCI_DEV_NAVSS0_MODSS (299)
-#define TISCI_DEV_NAVSS0_UDMASS (300)
-#define TISCI_DEV_NAVSS0_VIRTSS (301)
-#define TISCI_DEV_MCU_NAVSS0_MODSS (302)
-#define TISCI_DEV_MCU_NAVSS0_UDMASS (303)
-#define TISCI_DEV_DEBUGSS_WRAP0 (304)
-#define TISCI_DEV_DMPAC0_SDE_0 (305)
-#define TISCI_DEV_MAX (306)
+#define TISCI_DEV_MCU_ADC0 (0U)
+#define TISCI_DEV_MCU_ADC1 (1U)
+#define TISCI_DEV_ATL0 (2U)
+#define TISCI_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0 (3U)
+#define TISCI_DEV_A72SS0 (4U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_CFG_WRAP (5U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_CLEC (6U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_CORE_CORE (7U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW (8U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP (9U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0 (10U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_DIVP_TFT0 (11U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_DMSC_WRAP (12U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN (13U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS (14U)
+#define TISCI_DEV_C71SS0 (15U)
+#define TISCI_DEV_C71SS0_MMA (16U)
+#define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_WRAP (17U)
+#define TISCI_DEV_MCU_CPSW0 (18U)
+#define TISCI_DEV_CPSW0 (19U)
+#define TISCI_DEV_CPT2_AGGR0 (20U)
+#define TISCI_DEV_CPT2_AGGR1 (21U)
+#define TISCI_DEV_DMSC_WKUP_0 (22U)
+#define TISCI_DEV_CPT2_AGGR2 (23U)
+#define TISCI_DEV_MCU_CPT2_AGGR0 (24U)
+#define TISCI_DEV_CSI_PSILSS0 (25U)
+#define TISCI_DEV_CSI_RX_IF0 (26U)
+#define TISCI_DEV_CSI_RX_IF1 (27U)
+#define TISCI_DEV_CSI_TX_IF0 (28U)
+#define TISCI_DEV_STM0 (29U)
+#define TISCI_DEV_DCC0 (30U)
+#define TISCI_DEV_DCC1 (31U)
+#define TISCI_DEV_DCC2 (32U)
+#define TISCI_DEV_DCC3 (33U)
+#define TISCI_DEV_DCC4 (34U)
+#define TISCI_DEV_MCU_TIMER0 (35U)
+#define TISCI_DEV_DCC5 (36U)
+#define TISCI_DEV_DCC6 (37U)
+#define TISCI_DEV_DCC7 (38U)
+#define TISCI_DEV_DCC8 (39U)
+#define TISCI_DEV_DCC9 (40U)
+#define TISCI_DEV_DCC10 (41U)
+#define TISCI_DEV_DCC11 (42U)
+#define TISCI_DEV_DCC12 (43U)
+#define TISCI_DEV_MCU_DCC0 (44U)
+#define TISCI_DEV_MCU_DCC1 (45U)
+#define TISCI_DEV_MCU_DCC2 (46U)
+#define TISCI_DEV_DDR0 (47U)
+#define TISCI_DEV_DMPAC_TOP_MAIN_0 (48U)
+#define TISCI_DEV_TIMER0 (49U)
+#define TISCI_DEV_TIMER1 (50U)
+#define TISCI_DEV_TIMER2 (51U)
+#define TISCI_DEV_TIMER3 (52U)
+#define TISCI_DEV_TIMER4 (53U)
+#define TISCI_DEV_TIMER5 (54U)
+#define TISCI_DEV_TIMER6 (55U)
+#define TISCI_DEV_TIMER7 (57U)
+#define TISCI_DEV_TIMER8 (58U)
+#define TISCI_DEV_TIMER9 (59U)
+#define TISCI_DEV_TIMER10 (60U)
+#define TISCI_DEV_GTC0 (61U)
+#define TISCI_DEV_TIMER11 (62U)
+#define TISCI_DEV_TIMER12 (63U)
+#define TISCI_DEV_TIMER13 (64U)
+#define TISCI_DEV_TIMER14 (65U)
+#define TISCI_DEV_TIMER15 (66U)
+#define TISCI_DEV_TIMER16 (67U)
+#define TISCI_DEV_TIMER17 (68U)
+#define TISCI_DEV_TIMER18 (69U)
+#define TISCI_DEV_TIMER19 (70U)
+#define TISCI_DEV_MCU_TIMER1 (71U)
+#define TISCI_DEV_MCU_TIMER2 (72U)
+#define TISCI_DEV_MCU_TIMER3 (73U)
+#define TISCI_DEV_MCU_TIMER4 (74U)
+#define TISCI_DEV_MCU_TIMER5 (75U)
+#define TISCI_DEV_MCU_TIMER6 (76U)
+#define TISCI_DEV_MCU_TIMER7 (77U)
+#define TISCI_DEV_MCU_TIMER8 (78U)
+#define TISCI_DEV_MCU_TIMER9 (79U)
+#define TISCI_DEV_ECAP0 (80U)
+#define TISCI_DEV_ECAP1 (81U)
+#define TISCI_DEV_ECAP2 (82U)
+#define TISCI_DEV_EHRPWM0 (83U)
+#define TISCI_DEV_EHRPWM1 (84U)
+#define TISCI_DEV_EHRPWM2 (85U)
+#define TISCI_DEV_EHRPWM3 (86U)
+#define TISCI_DEV_EHRPWM4 (87U)
+#define TISCI_DEV_EHRPWM5 (88U)
+#define TISCI_DEV_ELM0 (89U)
+#define TISCI_DEV_EMIF_DATA_0_VD (90U)
+#define TISCI_DEV_MMCSD0 (91U)
+#define TISCI_DEV_MMCSD1 (92U)
+#define TISCI_DEV_MMCSD2 (93U)
+#define TISCI_DEV_EQEP0 (94U)
+#define TISCI_DEV_EQEP1 (95U)
+#define TISCI_DEV_EQEP2 (96U)
+#define TISCI_DEV_ESM0 (97U)
+#define TISCI_DEV_MCU_ESM0 (98U)
+#define TISCI_DEV_WKUP_ESM0 (99U)
+#define TISCI_DEV_FSS_MCU_0 (100U)
+#define TISCI_DEV_MCU_FSS0_FSAS_0 (101U)
+#define TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0 (102U)
+#define TISCI_DEV_MCU_FSS0_OSPI_0 (103U)
+#define TISCI_DEV_MCU_FSS0_OSPI_1 (104U)
+#define TISCI_DEV_GPIO0 (105U)
+#define TISCI_DEV_GPIO1 (106U)
+#define TISCI_DEV_GPIO2 (107U)
+#define TISCI_DEV_GPIO3 (108U)
+#define TISCI_DEV_GPIO4 (109U)
+#define TISCI_DEV_GPIO5 (110U)
+#define TISCI_DEV_GPIO6 (111U)
+#define TISCI_DEV_GPIO7 (112U)
+#define TISCI_DEV_WKUP_GPIO0 (113U)
+#define TISCI_DEV_WKUP_GPIO1 (114U)
+#define TISCI_DEV_GPMC0 (115U)
+#define TISCI_DEV_I3C0 (116U)
+#define TISCI_DEV_MCU_I3C0 (117U)
+#define TISCI_DEV_MCU_I3C1 (118U)
+#define TISCI_DEV_PRU_ICSSG0 (119U)
+#define TISCI_DEV_PRU_ICSSG1 (120U)
+#define TISCI_DEV_C66SS0_INTROUTER0 (121U)
+#define TISCI_DEV_C66SS1_INTROUTER0 (122U)
+#define TISCI_DEV_CMPEVENT_INTRTR0 (123U)
+#define TISCI_DEV_J7_LASCAR_GPU_WRAP_MAIN_0 (124U)
+#define TISCI_DEV_GPU0_GPU_0 (125U)
+#define TISCI_DEV_GPU0_GPUCORE_0 (126U)
+#define TISCI_DEV_LED0 (127U)
+#define TISCI_DEV_MAIN2MCU_LVL_INTRTR0 (128U)
+#define TISCI_DEV_MAIN2MCU_PLS_INTRTR0 (130U)
+#define TISCI_DEV_GPIOMUX_INTRTR0 (131U)
+#define TISCI_DEV_WKUP_PORZ_SYNC0 (132U)
+#define TISCI_DEV_PSC0 (133U)
+#define TISCI_DEV_R5FSS0_INTROUTER0 (134U)
+#define TISCI_DEV_R5FSS1_INTROUTER0 (135U)
+#define TISCI_DEV_TIMESYNC_INTRTR0 (136U)
+#define TISCI_DEV_WKUP_GPIOMUX_INTRTR0 (137U)
+#define TISCI_DEV_WKUP_PSC0 (138U)
+#define TISCI_DEV_AASRC0 (139U)
+#define TISCI_DEV_K3_C66_COREPAC_MAIN_0 (140U)
+#define TISCI_DEV_K3_C66_COREPAC_MAIN_1 (141U)
+#define TISCI_DEV_C66SS0_CORE0 (142U)
+#define TISCI_DEV_C66SS1_CORE0 (143U)
+#define TISCI_DEV_DECODER0 (144U)
+#define TISCI_DEV_WKUP_DDPA0 (145U)
+#define TISCI_DEV_UART0 (146U)
+#define TISCI_DEV_DPHY_RX0 (147U)
+#define TISCI_DEV_DPHY_RX1 (148U)
+#define TISCI_DEV_MCU_UART0 (149U)
+#define TISCI_DEV_DSS_DSI0 (150U)
+#define TISCI_DEV_DSS_EDP0 (151U)
+#define TISCI_DEV_DSS0 (152U)
+#define TISCI_DEV_ENCODER0 (153U)
+#define TISCI_DEV_WKUP_VTM0 (154U)
+#define TISCI_DEV_MAIN2WKUPMCU_VD (155U)
+#define TISCI_DEV_MCAN0 (156U)
+#define TISCI_DEV_BOARD0 (157U)
+#define TISCI_DEV_MCAN1 (158U)
+#define TISCI_DEV_MCAN2 (160U)
+#define TISCI_DEV_MCAN3 (161U)
+#define TISCI_DEV_MCAN4 (162U)
+#define TISCI_DEV_MCAN5 (163U)
+#define TISCI_DEV_MCAN6 (164U)
+#define TISCI_DEV_MCAN7 (165U)
+#define TISCI_DEV_MCAN8 (166U)
+#define TISCI_DEV_MCAN9 (167U)
+#define TISCI_DEV_MCAN10 (168U)
+#define TISCI_DEV_MCAN11 (169U)
+#define TISCI_DEV_MCAN12 (170U)
+#define TISCI_DEV_MCAN13 (171U)
+#define TISCI_DEV_MCU_MCAN0 (172U)
+#define TISCI_DEV_MCU_MCAN1 (173U)
+#define TISCI_DEV_MCASP0 (174U)
+#define TISCI_DEV_MCASP1 (175U)
+#define TISCI_DEV_MCASP2 (176U)
+#define TISCI_DEV_MCASP3 (177U)
+#define TISCI_DEV_MCASP4 (178U)
+#define TISCI_DEV_MCASP5 (179U)
+#define TISCI_DEV_MCASP6 (180U)
+#define TISCI_DEV_MCASP7 (181U)
+#define TISCI_DEV_MCASP8 (182U)
+#define TISCI_DEV_MCASP9 (183U)
+#define TISCI_DEV_MCASP10 (184U)
+#define TISCI_DEV_MCASP11 (185U)
+#define TISCI_DEV_MLB0 (186U)
+#define TISCI_DEV_I2C0 (187U)
+#define TISCI_DEV_I2C1 (188U)
+#define TISCI_DEV_I2C2 (189U)
+#define TISCI_DEV_I2C3 (190U)
+#define TISCI_DEV_I2C4 (191U)
+#define TISCI_DEV_I2C5 (192U)
+#define TISCI_DEV_I2C6 (193U)
+#define TISCI_DEV_MCU_I2C0 (194U)
+#define TISCI_DEV_MCU_I2C1 (195U)
+#define TISCI_DEV_WKUP_I2C0 (197U)
+#define TISCI_DEV_NAVSS0 (199U)
+#define TISCI_DEV_NAVSS0_CPTS_0 (201U)
+#define TISCI_DEV_A72SS0_CORE0 (202U)
+#define TISCI_DEV_A72SS0_CORE1 (203U)
+#define TISCI_DEV_NAVSS0_DTI_0 (206U)
+#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_0 (207U)
+#define TISCI_DEV_NAVSS0_MODSS_INTAGGR_1 (208U)
+#define TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0 (209U)
+#define TISCI_DEV_NAVSS0_PROXY_0 (210U)
+#define TISCI_DEV_NAVSS0_RINGACC0 (211U)
+#define TISCI_DEV_NAVSS0_UDMAP0 (212U)
+#define TISCI_DEV_NAVSS0_INTR_ROUTER_0 (213U)
+#define TISCI_DEV_NAVSS0_MAILBOX_0 (214U)
+#define TISCI_DEV_NAVSS0_MAILBOX_1 (215U)
+#define TISCI_DEV_NAVSS0_MAILBOX_2 (216U)
+#define TISCI_DEV_NAVSS0_MAILBOX_3 (217U)
+#define TISCI_DEV_NAVSS0_MAILBOX_4 (218U)
+#define TISCI_DEV_NAVSS0_MAILBOX_5 (219U)
+#define TISCI_DEV_NAVSS0_MAILBOX_6 (220U)
+#define TISCI_DEV_NAVSS0_MAILBOX_7 (221U)
+#define TISCI_DEV_NAVSS0_MAILBOX_8 (222U)
+#define TISCI_DEV_NAVSS0_MAILBOX_9 (223U)
+#define TISCI_DEV_NAVSS0_MAILBOX_10 (224U)
+#define TISCI_DEV_NAVSS0_MAILBOX_11 (225U)
+#define TISCI_DEV_NAVSS0_SPINLOCK_0 (226U)
+#define TISCI_DEV_NAVSS0_MCRC_0 (227U)
+#define TISCI_DEV_NAVSS0_TBU_0 (228U)
+#define TISCI_DEV_NAVSS0_TCU_0 (229U)
+#define TISCI_DEV_NAVSS0_TIMERMGR_0 (230U)
+#define TISCI_DEV_NAVSS0_TIMERMGR_1 (231U)
+#define TISCI_DEV_MCU_NAVSS0 (232U)
+#define TISCI_DEV_MCU_NAVSS0_INTAGGR_0 (233U)
+#define TISCI_DEV_MCU_NAVSS0_PROXY_0 (234U)
+#define TISCI_DEV_MCU_NAVSS0_RINGACC0 (235U)
+#define TISCI_DEV_MCU_NAVSS0_UDMAP0 (236U)
+#define TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0 (237U)
+#define TISCI_DEV_MCU_NAVSS0_MCRC_0 (238U)
+#define TISCI_DEV_PCIE0 (239U)
+#define TISCI_DEV_PCIE1 (240U)
+#define TISCI_DEV_PCIE2 (241U)
+#define TISCI_DEV_PCIE3 (242U)
+#define TISCI_DEV_PULSAR_SL_MAIN_0 (243U)
+#define TISCI_DEV_PULSAR_SL_MAIN_1 (244U)
+#define TISCI_DEV_R5FSS0_CORE0 (245U)
+#define TISCI_DEV_R5FSS0_CORE1 (246U)
+#define TISCI_DEV_R5FSS1_CORE0 (247U)
+#define TISCI_DEV_R5FSS1_CORE1 (248U)
+#define TISCI_DEV_PULSAR_SL_MCU_0 (249U)
+#define TISCI_DEV_MCU_R5FSS0_CORE0 (250U)
+#define TISCI_DEV_MCU_R5FSS0_CORE1 (251U)
+#define TISCI_DEV_RTI0 (252U)
+#define TISCI_DEV_RTI1 (253U)
+#define TISCI_DEV_RTI24 (254U)
+#define TISCI_DEV_RTI25 (255U)
+#define TISCI_DEV_RTI16 (256U)
+#define TISCI_DEV_RTI15 (257U)
+#define TISCI_DEV_RTI28 (258U)
+#define TISCI_DEV_RTI29 (259U)
+#define TISCI_DEV_RTI30 (260U)
+#define TISCI_DEV_RTI31 (261U)
+#define TISCI_DEV_MCU_RTI0 (262U)
+#define TISCI_DEV_MCU_RTI1 (263U)
+#define TISCI_DEV_SA2_UL0 (264U)
+#define TISCI_DEV_MCU_SA2_UL0 (265U)
+#define TISCI_DEV_MCSPI0 (266U)
+#define TISCI_DEV_MCSPI1 (267U)
+#define TISCI_DEV_MCSPI2 (268U)
+#define TISCI_DEV_MCSPI3 (269U)
+#define TISCI_DEV_MCSPI4 (270U)
+#define TISCI_DEV_MCSPI5 (271U)
+#define TISCI_DEV_MCSPI6 (272U)
+#define TISCI_DEV_MCSPI7 (273U)
+#define TISCI_DEV_MCU_MCSPI0 (274U)
+#define TISCI_DEV_MCU_MCSPI1 (275U)
+#define TISCI_DEV_MCU_MCSPI2 (276U)
+#define TISCI_DEV_UFS0 (277U)
+#define TISCI_DEV_UART1 (278U)
+#define TISCI_DEV_UART2 (279U)
+#define TISCI_DEV_UART3 (280U)
+#define TISCI_DEV_UART4 (281U)
+#define TISCI_DEV_UART5 (282U)
+#define TISCI_DEV_UART6 (283U)
+#define TISCI_DEV_UART7 (284U)
+#define TISCI_DEV_UART8 (285U)
+#define TISCI_DEV_UART9 (286U)
+#define TISCI_DEV_WKUP_UART0 (287U)
+#define TISCI_DEV_USB0 (288U)
+#define TISCI_DEV_USB1 (289U)
+#define TISCI_DEV_VPAC_TOP_MAIN_0 (290U)
+#define TISCI_DEV_VPFE0 (291U)
+#define TISCI_DEV_SERDES_16G0 (292U)
+#define TISCI_DEV_SERDES_16G1 (293U)
+#define TISCI_DEV_SERDES_16G2 (294U)
+#define TISCI_DEV_SERDES_16G3 (295U)
+#define TISCI_DEV_DPHY_TX0 (296U)
+#define TISCI_DEV_SERDES_10G0 (297U)
+#define TISCI_DEV_WKUPMCU2MAIN_VD (298U)
+#define TISCI_DEV_NAVSS0_MODSS (299U)
+#define TISCI_DEV_NAVSS0_UDMASS (300U)
+#define TISCI_DEV_NAVSS0_VIRTSS (301U)
+#define TISCI_DEV_MCU_NAVSS0_MODSS (302U)
+#define TISCI_DEV_MCU_NAVSS0_UDMASS (303U)
+#define TISCI_DEV_DEBUGSS_WRAP0 (304U)
+#define TISCI_DEV_DMPAC0_SDE_0 (305U)
+#define TISCI_DEV_MAX (306U)
/* @} */
/**
diff --git a/src/sciclient.c b/src/sciclient.c
index 7f88ea40fb59b3b0bec6919bfc36ad5d4e7581a9..0e2e67086529966e7bcee5eb48ebbb72ed5a5614 100755 (executable)
--- a/src/sciclient.c
+++ b/src/sciclient.c
}
}
- if (gSciclientHandle.opModeFlag == SCICLIENT_SERVICE_OPERATION_MODE_INTERRUPT)
+ if ((status == CSL_PASS) &&
+ (gSciclientHandle.opModeFlag == SCICLIENT_SERVICE_OPERATION_MODE_INTERRUPT))
{
#if defined (_TMS320C6X)
Osal_ClearInterrupt(gSciclientMap[contextId].respIntrNum, OSAL_REGINT_INTVEC_EVENT_COMBINER);
if (gSciclientHandle.respIntr[0] != NULL)
{
contextId = Sciclient_getCurrentContext(TISCI_MSG_VERSION);
- (void) Osal_DeleteInterrupt(gSciclientHandle.respIntr[0], (int32_t) gSciclientMap[contextId].respIntrNum);
+ if(contextId < SCICLIENT_CONTEXT_MAX_NUM)
+ {
+ (void) Osal_DeleteInterrupt(gSciclientHandle.respIntr[0], (int32_t) gSciclientMap[contextId].respIntrNum);
+ }
}
if (gSciclientHandle.respIntr[1] != NULL)
{
contextId = Sciclient_getCurrentContext(TISCI_MSG_BOARD_CONFIG);
- (void) Osal_DeleteInterrupt(gSciclientHandle.respIntr[1], (int32_t) gSciclientMap[contextId].respIntrNum);
+ if(contextId < SCICLIENT_CONTEXT_MAX_NUM)
+ {
+ (void) Osal_DeleteInterrupt(gSciclientHandle.respIntr[1], (int32_t) gSciclientMap[contextId].respIntrNum);
+ }
}
}
}