1 /**
2 * @file serdes_diag.h
3 *
4 * @brief
5 * Header file for functional layer of DIAGNOSTIC SERDES DIAG.
6 *
7 * It contains the various enumerations, structure definitions and function
8 * declarations
9 *
10 * \par
11 * ============================================================================
12 * @n (C) Copyright 2015, Texas Instruments, Inc.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
44 /** ============================================================================
45 *
46 * @defgroup SERDES_DIAG SERDES DIAG
47 * @ingroup SERDES_DIAG_API
48 *
49 * @section Introduction
50 *
51 * @subsection xxx Overview
52 * A bi-directional BER Test (TX and RX enabled at both ends) can be run across the various TX
53 * filter coefficients (CM, C1 and C2) by using the Serdes_Diag_SweepCMC1C2 API in combination with
54 * synchronizing the TX and RX using DSS. The Serdes Diag package contains serdes_dss.js which
55 * controls the TX/RX synchronization using DSS.
56 *
57 * @subsection References
58 *
59 * ============================================================================
60 */
61 #ifndef _DIAG_SERDES_H_
62 #define _DIAG_SERDES_H_
64 #include <stdio.h>
65 #include <stdint.h>
66 #include <string.h>
67 #include <ti/csl/soc.h>
68 #include <ti/csl/csl.h>
69 #include <ti/csl/csl_serdes.h>
70 #include <ti/csl/csl_tsc.h>
72 #define SERDES_DIAG_MAX_COEFF_RANGE 512
73 #define SERDES_DIAG_MAX_LANES 4
74 #define SERDES_DIAG_MAX_DLY 128
75 #define SERDES_DIAG_MAX_ARRAY 256
76 #define SERDES_DIAG_AVERAGE_DELAY 100
78 #define SERDES_DIAG_CMU_MAP(base_addr, offset) (base_addr + offset)
79 #define SERDES_DIAG_LANE_MAP(base_addr, lane_num, offset) ((base_addr) + 0x200*(lane_num + 1) + offset)
80 #define SERDES_DIAG_COMLANE_MAP(base_addr, offset) (base_addr + 0xa00 + offset)
82 typedef struct SERDES_DIAG_CMC1C2
83 {
84 uint32_t cm[SERDES_DIAG_MAX_COEFF_RANGE];
85 uint32_t c1[SERDES_DIAG_MAX_COEFF_RANGE];
86 uint32_t c2[SERDES_DIAG_MAX_COEFF_RANGE];
87 uint64_t run_time[SERDES_DIAG_MAX_COEFF_RANGE];
89 uint32_t berlane0[SERDES_DIAG_MAX_COEFF_RANGE];
90 uint32_t berlane1[SERDES_DIAG_MAX_COEFF_RANGE];
91 uint32_t berlane2[SERDES_DIAG_MAX_COEFF_RANGE];
92 uint32_t berlane3[SERDES_DIAG_MAX_COEFF_RANGE];
94 uint32_t bist_valid0[SERDES_DIAG_MAX_COEFF_RANGE];
95 uint32_t bist_valid1[SERDES_DIAG_MAX_COEFF_RANGE];
96 uint32_t bist_valid2[SERDES_DIAG_MAX_COEFF_RANGE];
97 uint32_t bist_valid3[SERDES_DIAG_MAX_COEFF_RANGE];
99 uint32_t att0[SERDES_DIAG_MAX_COEFF_RANGE];
100 uint32_t att1[SERDES_DIAG_MAX_COEFF_RANGE];
101 uint32_t att2[SERDES_DIAG_MAX_COEFF_RANGE];
102 uint32_t att3[SERDES_DIAG_MAX_COEFF_RANGE];
104 uint32_t boost0[SERDES_DIAG_MAX_COEFF_RANGE];
105 uint32_t boost1[SERDES_DIAG_MAX_COEFF_RANGE];
106 uint32_t boost2[SERDES_DIAG_MAX_COEFF_RANGE];
107 uint32_t boost3[SERDES_DIAG_MAX_COEFF_RANGE];
109 uint32_t pma0[SERDES_DIAG_MAX_COEFF_RANGE];
110 uint32_t pma1[SERDES_DIAG_MAX_COEFF_RANGE];
111 uint32_t pma2[SERDES_DIAG_MAX_COEFF_RANGE];
112 uint32_t pma3[SERDES_DIAG_MAX_COEFF_RANGE];
114 uint32_t cdr0[SERDES_DIAG_MAX_COEFF_RANGE];
115 uint32_t cdr1[SERDES_DIAG_MAX_COEFF_RANGE];
116 uint32_t cdr2[SERDES_DIAG_MAX_COEFF_RANGE];
117 uint32_t cdr3[SERDES_DIAG_MAX_COEFF_RANGE];
119 int32_t dfe1_0[SERDES_DIAG_MAX_COEFF_RANGE];
120 int32_t dfe2_0[SERDES_DIAG_MAX_COEFF_RANGE];
121 int32_t dfe3_0[SERDES_DIAG_MAX_COEFF_RANGE];
122 int32_t dfe4_0[SERDES_DIAG_MAX_COEFF_RANGE];
123 int32_t dfe5_0[SERDES_DIAG_MAX_COEFF_RANGE];
125 int32_t dfe1_1[SERDES_DIAG_MAX_COEFF_RANGE];
126 int32_t dfe2_1[SERDES_DIAG_MAX_COEFF_RANGE];
127 int32_t dfe3_1[SERDES_DIAG_MAX_COEFF_RANGE];
128 int32_t dfe4_1[SERDES_DIAG_MAX_COEFF_RANGE];
129 int32_t dfe5_1[SERDES_DIAG_MAX_COEFF_RANGE];
131 int32_t dfe1_2[SERDES_DIAG_MAX_COEFF_RANGE];
132 int32_t dfe2_2[SERDES_DIAG_MAX_COEFF_RANGE];
133 int32_t dfe3_2[SERDES_DIAG_MAX_COEFF_RANGE];
134 int32_t dfe4_2[SERDES_DIAG_MAX_COEFF_RANGE];
135 int32_t dfe5_2[SERDES_DIAG_MAX_COEFF_RANGE];
137 int32_t dfe1_3[SERDES_DIAG_MAX_COEFF_RANGE];
138 int32_t dfe2_3[SERDES_DIAG_MAX_COEFF_RANGE];
139 int32_t dfe3_3[SERDES_DIAG_MAX_COEFF_RANGE];
140 int32_t dfe4_3[SERDES_DIAG_MAX_COEFF_RANGE];
141 int32_t dfe5_3[SERDES_DIAG_MAX_COEFF_RANGE];
143 int32_t cdfe1_0[SERDES_DIAG_MAX_COEFF_RANGE];
144 int32_t cdfe2_0[SERDES_DIAG_MAX_COEFF_RANGE];
145 int32_t cdfe3_0[SERDES_DIAG_MAX_COEFF_RANGE];
146 int32_t cdfe4_0[SERDES_DIAG_MAX_COEFF_RANGE];
147 int32_t cdfe5_0[SERDES_DIAG_MAX_COEFF_RANGE];
149 int32_t cdfe1_1[SERDES_DIAG_MAX_COEFF_RANGE];
150 int32_t cdfe2_1[SERDES_DIAG_MAX_COEFF_RANGE];
151 int32_t cdfe3_1[SERDES_DIAG_MAX_COEFF_RANGE];
152 int32_t cdfe4_1[SERDES_DIAG_MAX_COEFF_RANGE];
153 int32_t cdfe5_1[SERDES_DIAG_MAX_COEFF_RANGE];
155 int32_t cdfe1_2[SERDES_DIAG_MAX_COEFF_RANGE];
156 int32_t cdfe2_2[SERDES_DIAG_MAX_COEFF_RANGE];
157 int32_t cdfe3_2[SERDES_DIAG_MAX_COEFF_RANGE];
158 int32_t cdfe4_2[SERDES_DIAG_MAX_COEFF_RANGE];
159 int32_t cdfe5_2[SERDES_DIAG_MAX_COEFF_RANGE];
161 int32_t cdfe1_3[SERDES_DIAG_MAX_COEFF_RANGE];
162 int32_t cdfe2_3[SERDES_DIAG_MAX_COEFF_RANGE];
163 int32_t cdfe3_3[SERDES_DIAG_MAX_COEFF_RANGE];
164 int32_t cdfe4_3[SERDES_DIAG_MAX_COEFF_RANGE];
165 int32_t cdfe5_3[SERDES_DIAG_MAX_COEFF_RANGE];
167 uint32_t dlevp0[SERDES_DIAG_MAX_COEFF_RANGE];
168 uint32_t dlevp1[SERDES_DIAG_MAX_COEFF_RANGE];
169 uint32_t dlevp2[SERDES_DIAG_MAX_COEFF_RANGE];
170 uint32_t dlevp3[SERDES_DIAG_MAX_COEFF_RANGE];
172 uint32_t dlevn0[SERDES_DIAG_MAX_COEFF_RANGE];
173 uint32_t dlevn1[SERDES_DIAG_MAX_COEFF_RANGE];
174 uint32_t dlevn2[SERDES_DIAG_MAX_COEFF_RANGE];
175 uint32_t dlevn3[SERDES_DIAG_MAX_COEFF_RANGE];
177 uint32_t dlevavg0[SERDES_DIAG_MAX_COEFF_RANGE];
178 uint32_t dlevavg1[SERDES_DIAG_MAX_COEFF_RANGE];
179 uint32_t dlevavg2[SERDES_DIAG_MAX_COEFF_RANGE];
180 uint32_t dlevavg3[SERDES_DIAG_MAX_COEFF_RANGE];
182 int32_t dll_c0[SERDES_DIAG_MAX_COEFF_RANGE];
183 int32_t dll_c1[SERDES_DIAG_MAX_COEFF_RANGE];
184 int32_t dll_c2[SERDES_DIAG_MAX_COEFF_RANGE];
185 int32_t dll_c3[SERDES_DIAG_MAX_COEFF_RANGE];
187 int32_t dll_f0[SERDES_DIAG_MAX_COEFF_RANGE];
188 int32_t dll_f1[SERDES_DIAG_MAX_COEFF_RANGE];
189 int32_t dll_f2[SERDES_DIAG_MAX_COEFF_RANGE];
190 int32_t dll_f3[SERDES_DIAG_MAX_COEFF_RANGE];
192 int32_t delay0[SERDES_DIAG_MAX_COEFF_RANGE];
193 int32_t delay1[SERDES_DIAG_MAX_COEFF_RANGE];
194 int32_t delay2[SERDES_DIAG_MAX_COEFF_RANGE];
195 int32_t delay3[SERDES_DIAG_MAX_COEFF_RANGE];
197 int32_t swing[SERDES_DIAG_MAX_COEFF_RANGE];
198 int32_t deemph[SERDES_DIAG_MAX_COEFF_RANGE];
199 } SERDES_DIAG_CMC1C2_T;
201 typedef struct SERDES_DIAG_BER_VAL
202 {
203 uint32_t val[SERDES_DIAG_MAX_LANES];
204 uint32_t bist_valid[SERDES_DIAG_MAX_LANES];
205 uint64_t run_time[SERDES_DIAG_MAX_LANES];
206 uint32_t att[SERDES_DIAG_MAX_LANES];
207 uint32_t boost[SERDES_DIAG_MAX_LANES];
208 uint32_t pma[SERDES_DIAG_MAX_LANES];
209 uint32_t cdr[SERDES_DIAG_MAX_LANES];
210 int32_t dfe1[SERDES_DIAG_MAX_LANES];
211 int32_t dfe2[SERDES_DIAG_MAX_LANES];
212 int32_t dfe3[SERDES_DIAG_MAX_LANES];
213 int32_t dfe4[SERDES_DIAG_MAX_LANES];
214 int32_t dfe5[SERDES_DIAG_MAX_LANES];
215 int32_t cdfe1[SERDES_DIAG_MAX_LANES];
216 int32_t cdfe2[SERDES_DIAG_MAX_LANES];
217 int32_t cdfe3[SERDES_DIAG_MAX_LANES];
218 int32_t cdfe4[SERDES_DIAG_MAX_LANES];
219 int32_t cdfe5[SERDES_DIAG_MAX_LANES];
220 int32_t dlevp[SERDES_DIAG_MAX_LANES];
221 int32_t dlevn[SERDES_DIAG_MAX_LANES];
222 int32_t dlevavg[SERDES_DIAG_MAX_LANES];
223 int32_t dll_c[SERDES_DIAG_MAX_LANES];
224 int32_t dll_f[SERDES_DIAG_MAX_LANES];
225 int32_t delay[SERDES_DIAG_MAX_LANES];
226 } SERDES_DIAG_BER_VAL_T;
228 typedef struct SERDES_DIAG_BOOST_ATT
229 {
230 uint32_t att[SERDES_DIAG_MAX_COEFF_RANGE];
231 uint32_t boost[SERDES_DIAG_MAX_COEFF_RANGE];
232 uint32_t ber[SERDES_DIAG_MAX_COEFF_RANGE];
233 } SERDES_DIAG_BOOST_ATT_T;
236 typedef struct SERDES_DIAG_TX_COEFF
237 {
238 uint32_t tx_att_start;
239 uint32_t tx_att_end;
240 uint32_t tx_vreg_start;
241 uint32_t tx_vreg_end;
242 uint32_t cm_coeff_start;
243 uint32_t cm_coeff_end;
244 uint32_t c1_coeff_start;
245 uint32_t c1_coeff_end;
246 uint32_t c2_coeff_start;
247 uint32_t c2_coeff_end;
248 uint32_t tx_swing_start;
249 uint32_t tx_swing_end;
250 uint32_t tx_deemph_start;
251 uint32_t tx_deemph_end;
252 }SERDES_DIAG_TX_COEFF_T;
254 typedef struct SERDES_DIAG_EYE_OUTPUT
255 {
257 uint32_t eye_width;
259 uint32_t eye_height;
260 }SERDES_DIAG_EYE_OUTPUT_T;
262 typedef enum
263 {
264 SERDES_DIAG_PCIE_GEN1 = 1,
266 SERDES_DIAG_PCIE_GEN2 = 2
267 } SERDES_DIAG_PCIE_TYPE;
269 typedef enum
270 {
272 SERDES_DIAG_SETUP_OK = 0,
275 SERDES_DIAG_SETUP_TIME_OUT = 1,
278 SERDES_DIAG_INVALID_BUS_WIDTH = 2,
281 SERDES_DIAG_INVALID_PHY_TYPE = 3
282 } SERDES_DIAG_STAT;
284 typedef enum
285 {
287 SERDES_PRBS_7 = 0,
290 SERDES_PRBS_15 = 1,
293 SERDES_PRBS_23 = 2,
296 SERDES_PRBS_31 = 3,
299 SERDES_PRBS_UDP = 4,
302 SERDES_PRBS_FEP_LPBK = 5
303 } SERDES_DIAG_PRBS_PATTERN;
305 typedef enum
306 {
308 SERDES_DIAG_BIST_TX_CLK_DISABLED = 0,
311 SERDES_DIAG_BIST_TX_CLK_ENABLED = 1
312 } SERDES_DIAG_BIST_TX_CLK;
314 typedef enum
315 {
317 SERDES_DIAG_BIST_RX_CLK_DISABLED = 0,
320 SERDES_DIAG_BIST_RX_CLK_ENABLED = 1
321 } SERDES_DIAG_BIST_RX_CLK;
323 typedef enum
324 {
326 SERDES_DIAG_LOOPBACK = 0,
329 SERDES_DIAG_NON_LOOPBACK = 1,
332 SERDES_DIAG_FEP_LOOPBACK = 2
333 } SERDES_DIAG_LOOPBACK_TYPE;
335 typedef struct SERDES_DIAG_BER_INIT
336 {
338 uint32_t base_addr;
340 uint32_t num_lanes;
342 uint64_t bertesttime;
344 SERDES_DIAG_PRBS_PATTERN prbs_pattern;
346 uint64_t timeoutloops;
348 csl_serdes_phy_type phy_type;
350 SERDES_DIAG_PCIE_TYPE pcie_gen_type;
352 SERDES_DIAG_BIST_TX_CLK bist_tx_clk_en;
354 SERDES_DIAG_BIST_RX_CLK bist_rx_clk_en;
356 SERDES_DIAG_LOOPBACK_TYPE loopback_type;
358 uint32_t polarity[SERDES_DIAG_MAX_LANES];
360 CSL_SERDES_LANE_CTRL_RATE lane_ctrl_rate[SERDES_DIAG_MAX_LANES];
362 CSL_SERDES_TX_COEFF_T tx_coeff;
364 uint8_t lane_mask;
365 } SERDES_DIAG_BER_INIT_T;
367 typedef struct SERDES_DIAG_EYE_INIT
368 {
370 uint32_t base_addr;
372 int32_t lane_num;
374 int32_t num_lanes;
376 int32_t phase_num;
378 uint64_t gatetime;
380 int32_t v_offset;
382 int32_t t_offset;
384 int32_t calibrate_eye;
386 csl_serdes_phy_type phy_type;
388 SERDES_DIAG_PCIE_TYPE pcie_gen_type;
390 int32_t lane_mask;
392 CSL_SERDES_LINK_RATE link_rate;
393 } SERDES_DIAG_EYE_INIT_T;
396 extern volatile uint32_t serdes_diag_dss_lock_key;
397 extern volatile uint32_t serdes_diag_dss_unlock_key;
400 extern volatile uint32_t serdes_diag_dss_stall_key0;
402 extern volatile uint32_t serdes_diag_dss_stall_key1;
404 extern volatile uint32_t serdes_diag_dss_stall_key2;
406 extern volatile uint32_t serdes_diag_dss_stall_flag_set;
407 extern volatile uint32_t serdes_diag_dss_stall_flag_clear;
410 extern volatile uint32_t serdes_diag_dss_stall_flag0;
412 extern volatile uint32_t serdes_diag_dss_stall_flag1;
414 extern volatile uint32_t serdes_diag_dss_stall_flag2;
416 extern volatile uint32_t serdes_diag_dss_test_complete_flag_set;
418 extern volatile uint32_t serdes_diag_dss_test_complete_flag;
420 extern volatile uint16_t serdes_diag_eye_scan_errors_array[SERDES_DIAG_MAX_ARRAY]
421 [SERDES_DIAG_MAX_DLY];
423 extern void Serdes_Diag_cycleDelay (uint64_t count);
424 extern void Serdes_Diag_Write_32_Mask(uint32_t base_addr,
425 uint32_t mask_value,
426 uint32_t set_value);
431 static inline SERDES_DIAG_STAT Serdes_Diag_UDPTest(const SERDES_DIAG_BER_INIT_T *ber_params_init)
432 {
433 uint32_t lane_num;
436 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
437 {
438 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
439 {
440 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),5,5,0);
441 }
442 }
447 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
448 {
449 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
450 {
451 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),22,22,ber_params_init->bist_tx_clk_en);
452 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),23,23,ber_params_init->bist_rx_clk_en);
453 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),18,18,0);
457 if (ber_params_init->phy_type == SERDES_PCIe)
458 {
460 if(ber_params_init->pcie_gen_type == SERDES_DIAG_PCIE_GEN1)
461 {
462 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
463 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,0);
464 }
466 else if(ber_params_init->pcie_gen_type == SERDES_DIAG_PCIE_GEN2)
467 {
468 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
469 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
470 }
472 else
473 {
474 return SERDES_DIAG_INVALID_BUS_WIDTH;
475 }
476 }
479 else if(ber_params_init->phy_type == SERDES_SGMII)
480 {
481 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
482 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,0);
483 }
486 else if(ber_params_init->phy_type == SERDES_10GE)
487 {
488 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
489 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
490 }
493 else
494 {
495 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
496 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
497 }
498 }
499 }
502 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
503 {
504 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
505 {
506 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),7,7,0);
507 }
508 }
511 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
512 {
513 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
514 {
515 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),27,27,0);
516 }
517 }
521 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
522 {
523 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
524 {
525 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),21,19,ber_params_init->prbs_pattern);
526 }
527 }
532 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(ber_params_init->base_addr, 0x14)),25,24,0);
536 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
537 {
538 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
539 {
540 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),31,24,(uint32_t)0x83);
541 }
542 }
544 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
545 {
546 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
547 {
548 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 1,0,0x2);
549 }
550 }
554 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
555 {
556 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
557 {
558 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 17,8,0x17c);
559 }
560 }
571 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
572 {
573 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
574 {
575 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x38)) = 0xAAAAAAAA;
576 }
577 }
579 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
580 {
581 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
582 {
583 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x3c)), 7,0,170);
584 }
585 }
587 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
588 {
589 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
590 {
591 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x40)) = 0;
592 }
593 }
595 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
596 {
597 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
598 {
599 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x44)), 27,0,0);
600 }
601 }
603 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
604 {
605 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
606 {
607 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 4,2,0);
608 }
609 }
611 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
612 {
613 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
614 {
615 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),30,28,0);
616 }
617 }
620 Serdes_Diag_cycleDelay(50);
623 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
624 {
625 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
626 {
627 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 5,5,1);
628 }
629 }
634 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
635 {
636 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
637 {
638 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)), 7,6,2);
639 }
640 }
642 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
643 {
644 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
645 {
646 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)),22,20,0);
647 }
648 }
651 Serdes_Diag_cycleDelay(50);
654 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
655 {
656 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
657 {
658 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 7,7,1);
659 }
660 }
663 Serdes_Diag_cycleDelay(10000);
664 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
665 {
666 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
667 {
669 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)),2,1,0);
670 }
671 }
672 Serdes_Diag_cycleDelay(10000);
674 return SERDES_DIAG_SETUP_OK;
675 }
679 static inline void Serdes_Diag_SetFEPLoopback(const SERDES_DIAG_BER_INIT_T *ber_params_init)
680 {
682 uint32_t lane_num;
683 CSL_SERDES_DLEV_OUT_T pDLEVOut;
684 CSL_SERDES_TAP_OFFSETS_T pTapOffsets;
686 memset(&pDLEVOut, 0, sizeof(pDLEVOut));
687 memset(&pTapOffsets, 0, sizeof(pTapOffsets));
690 if(ber_params_init->phy_type == SERDES_10GE)
691 {
692 CSL_Serdes_PHYB_Init_Config(ber_params_init->base_addr,
693 SERDES_DIAG_MAX_LANES,
694 ber_params_init->phy_type,
695 ber_params_init->lane_mask,
696 &pTapOffsets);
697 }
700 if(ber_params_init->phy_type != SERDES_PCIe)
701 {
702 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
703 {
704 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
705 {
706 CSL_SerdesClearTXIdle(ber_params_init->base_addr, lane_num, ber_params_init->phy_type);
707 }
708 }
709 }
712 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
713 {
714 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
715 {
716 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + 0x200*(lane_num+1) + 0x00),7,6,0);
717 }
718 }
721 Serdes_Diag_cycleDelay(2000);
725 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
726 {
727 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
728 {
729 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + 0x200*(lane_num+1) + 0x00),22,20,5);
730 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + 0x200*(lane_num+1) + 0x00),23,23,1);
731 }
732 }
734 if(ber_params_init->phy_type == SERDES_10GE)
735 {
736 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + 0x200 + 0x98),14,14, 1);
737 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + 0x200 + 0x98),14,14, 0);
738 }
741 CSL_SerdesWaitForRXValid(ber_params_init->base_addr, SERDES_DIAG_MAX_LANES, ber_params_init->lane_mask, ber_params_init->phy_type);
744 if(ber_params_init->phy_type != SERDES_10GE)
745 {
746 CSL_SerdesRXAttConfig_PhyA(ber_params_init->base_addr,
747 SERDES_DIAG_MAX_LANES,
748 ber_params_init->phy_type,
749 ber_params_init->lane_mask);
751 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
752 {
753 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
754 {
755 CSL_SerdesRXBoostConfig_PhyA(ber_params_init->base_addr, lane_num,
756 ber_params_init->phy_type,
757 ber_params_init->lane_mask);
758 }
759 }
760 }
762 else
763 {
764 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
765 {
766 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
767 {
768 CSL_SerdesRXAttBoostConfig_PhyB(ber_params_init->base_addr, lane_num,
769 ber_params_init->phy_type,
770 ber_params_init->lane_mask);
771 }
772 }
773 }
776 if(ber_params_init->phy_type == SERDES_10GE)
777 {
778 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
779 {
780 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
781 {
782 CSL_Serdes_RX_Calibration_PHYB(ber_params_init->base_addr,lane_num, ber_params_init->phy_type,
783 &pTapOffsets,&pDLEVOut);
784 }
785 }
786 }
788 }
792 static inline SERDES_DIAG_STAT Serdes_Diag_PRBS_Check(const SERDES_DIAG_BER_INIT_T *ber_params_init, uint32_t *lane_status)
793 {
795 uint32_t lane_num, temp, bist_valid[SERDES_DIAG_MAX_LANES] = {0,0,0,0};
796 uint64_t start_time;
798 *lane_status = 0;
801 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
802 {
803 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
804 {
805 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x4)), 4,4,0x0);
806 }
807 }
809 Serdes_Diag_cycleDelay(1000000);
812 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
813 {
814 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
815 {
816 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x4)), 3,3,0x1);
817 }
818 }
820 start_time = CSL_tscRead();
822 do
823 {
824 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
825 {
826 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
827 {
828 bist_valid[lane_num]= (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xC) & 0x0400) >> 10;
830 if (((*(volatile uint32_t *)(ber_params_init->base_addr + 0x1fc0 + 0x34))&(1<<lane_num)) == 0)
831 {
832 bist_valid[lane_num] = 0;
833 }
834 }
836 }
838 for(lane_num=0,temp=1;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
839 {
840 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
841 {
842 temp &= bist_valid[lane_num];
843 *lane_status |= (bist_valid[lane_num] << lane_num);
844 }
845 }
847 if ((CSL_tscRead() - start_time) > ber_params_init->timeoutloops) {
848 break;
849 }
851 } while (!temp);
853 return SERDES_DIAG_SETUP_OK;
854 }
859 static inline SERDES_DIAG_STAT Serdes_Diag_BERTest_TX(const SERDES_DIAG_BER_INIT_T *ber_params_init)
860 {
861 uint32_t lane_num;
864 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
865 {
866 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
867 {
868 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),5,5,0);
869 }
870 }
876 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
877 {
878 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
879 {
880 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),
881 22,22,ber_params_init->bist_tx_clk_en);
882 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),
883 23,23,ber_params_init->bist_rx_clk_en);
885 if(ber_params_init->prbs_pattern == SERDES_PRBS_UDP)
886 {
887 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),18,18,0);
888 }
889 else
890 {
891 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)), 18,18,1);
892 }
897 if (ber_params_init->phy_type == SERDES_PCIe)
898 {
900 if(ber_params_init->pcie_gen_type == SERDES_DIAG_PCIE_GEN1)
901 {
902 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
903 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,0);
904 }
906 else if(ber_params_init->pcie_gen_type == SERDES_DIAG_PCIE_GEN2)
907 {
908 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
909 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
912 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x50)),31,30,0);
915 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x0C)),25,25,1);
916 }
918 else
919 {
920 return SERDES_DIAG_INVALID_BUS_WIDTH;
921 }
922 }
925 else if(ber_params_init->phy_type == SERDES_SGMII)
926 {
927 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
928 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,0);
929 }
932 else if(ber_params_init->phy_type == SERDES_10GE)
933 {
934 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
935 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
936 }
939 else
940 {
941 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
942 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
943 }
944 }
945 }
948 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
949 {
950 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
951 {
952 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),7,7,0);
953 }
954 }
957 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
958 {
959 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
960 {
961 if(ber_params_init->phy_type != SERDES_PCIe)
962 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),27,27,0);
963 }
964 }
968 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
969 {
970 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
971 {
972 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),21,19,ber_params_init->prbs_pattern);
973 }
974 }
979 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(ber_params_init->base_addr, 0x14)),25,24,0);
983 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
984 {
985 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
986 {
987 if(ber_params_init->phy_type != SERDES_PCIe)
988 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),31,24,(uint32_t)0x83);
989 }
990 }
992 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
993 {
994 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
995 {
996 if(ber_params_init->phy_type != SERDES_PCIe)
997 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 1,0,0x2);
998 }
999 }
1003 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1004 {
1005 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1006 {
1007 if(ber_params_init->phy_type != SERDES_PCIe)
1008 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 17,8,0x17c);
1009 }
1010 }
1021 if(ber_params_init->prbs_pattern == SERDES_PRBS_UDP)
1022 {
1023 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1024 {
1025 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1026 {
1027 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr +0x200*(lane_num+1)+0x30),18,18, 0);
1028 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x38)) = 0xAAAAAAAA;
1029 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr +0x200*(lane_num+1)+0x3C),7,0, 0xAA);
1030 }
1031 }
1032 }
1033 else
1034 {
1035 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1036 {
1037 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1038 {
1039 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x38)) = 0;
1040 }
1041 }
1043 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1044 {
1045 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1046 {
1047 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x3c)) = 0;
1048 }
1049 }
1050 }
1052 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1053 {
1054 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1055 {
1056 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x40)) = 0;
1057 }
1058 }
1060 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1061 {
1062 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1063 {
1064 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x44)), 27,0,0);
1065 }
1066 }
1068 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1069 {
1070 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1071 {
1072 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 4,2,0);
1073 }
1074 }
1076 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1077 {
1078 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1079 {
1080 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),30,28,0);
1081 }
1082 }
1085 Serdes_Diag_cycleDelay(50);
1088 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1089 {
1090 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1091 {
1092 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 5,5,1);
1093 }
1094 }
1097 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1098 {
1099 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1100 {
1101 if(ber_params_init->phy_type != SERDES_PCIe)
1102 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)), 23,23,0);
1103 }
1104 }
1109 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1110 {
1111 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1112 {
1113 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)), 7,6,2);
1114 }
1115 }
1117 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1118 {
1119 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1120 {
1121 if(ber_params_init->phy_type != SERDES_PCIe)
1122 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)),22,20,0);
1123 }
1124 }
1127 Serdes_Diag_cycleDelay(50);
1130 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1131 {
1132 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1133 {
1134 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 7,7,1);
1135 }
1136 }
1139 Serdes_Diag_cycleDelay(10000);
1140 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1141 {
1142 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1143 {
1145 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)),2,1,0);
1146 }
1147 }
1148 Serdes_Diag_cycleDelay(10000);
1152 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1153 {
1154 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1155 {
1156 if(ber_params_init->phy_type != SERDES_PCIe)
1157 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)), 6,3,((0)|(1<<1)|(2<<((ber_params_init->phy_type==SERDES_10GE)?3:2))));
1158 }
1159 }
1161 Serdes_Diag_cycleDelay(300000);
1163 return SERDES_DIAG_SETUP_OK;
1164 }
1169 static inline SERDES_DIAG_STAT Serdes_Diag_BERTest(const SERDES_DIAG_BER_INIT_T *ber_params_init,
1170 SERDES_DIAG_BER_VAL_T *pBERval,
1171 CSL_SERDES_TAP_OFFSETS_T *pTapOffsets)
1172 {
1173 uint32_t lane_num,temp,any_lane_valid, stat;
1174 uint64_t llWaitTillTime;
1175 uint64_t llCurTscVal;
1176 uint32_t bist_chk_sync;
1177 CSL_SERDES_DLEV_OUT_T pDLEVOut;
1179 volatile uint32_t iDone;
1181 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1182 {
1183 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1184 {
1185 pBERval->bist_valid[lane_num] = 0;
1186 }
1187 }
1190 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1191 {
1192 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1193 {
1194 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),5,5,0);
1195 }
1196 }
1202 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1203 {
1204 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1205 {
1206 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),22,22,ber_params_init->bist_tx_clk_en);
1207 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),23,23,ber_params_init->bist_rx_clk_en);
1208 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),18,18,1);
1212 if (ber_params_init->phy_type == SERDES_PCIe)
1213 {
1215 if(ber_params_init->pcie_gen_type == SERDES_DIAG_PCIE_GEN1)
1216 {
1217 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
1218 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,0);
1219 }
1221 else if(ber_params_init->pcie_gen_type == SERDES_DIAG_PCIE_GEN2)
1222 {
1223 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
1224 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
1227 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x50)),29,28,0);
1230 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x50)),31,30,0);
1233 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x0C)),25,25,1);
1234 }
1235 else
1236 {
1238 return SERDES_DIAG_INVALID_BUS_WIDTH;
1239 }
1240 }
1243 else if(ber_params_init->phy_type == SERDES_SGMII)
1244 {
1245 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
1246 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,0);
1247 }
1250 else if(ber_params_init->phy_type == SERDES_10GE)
1251 {
1252 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,1);
1253 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
1254 }
1257 else
1258 {
1259 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),16,16,0);
1260 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),6,6,1);
1261 }
1262 }
1263 }
1266 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1267 {
1268 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1269 {
1270 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),7,7,0);
1271 }
1272 }
1275 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1276 {
1277 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1278 {
1279 if(ber_params_init->phy_type != SERDES_PCIe)
1280 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),27,27,0);
1281 }
1282 }
1286 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1287 {
1288 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1289 {
1290 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),21,19,ber_params_init->prbs_pattern);
1291 }
1292 }
1297 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(ber_params_init->base_addr, 0x14)),25,24,0);
1301 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1302 {
1303 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1304 {
1305 if(ber_params_init->phy_type != SERDES_PCIe)
1306 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x30)),31,24,(uint32_t)0x83);
1307 }
1308 }
1310 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1311 {
1312 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1313 {
1314 if(ber_params_init->phy_type != SERDES_PCIe)
1315 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 1,0,0x2);
1316 }
1317 }
1321 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1322 {
1323 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1324 {
1325 if(ber_params_init->phy_type != SERDES_PCIe)
1326 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 17,8,0x17c);
1327 }
1328 }
1338 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1339 {
1340 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1341 {
1342 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x38)) = 0;
1343 }
1344 }
1346 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1347 {
1348 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1349 {
1350 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x3c)) = 0;
1351 }
1352 }
1354 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1355 {
1356 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1357 {
1358 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x40)) = 0;
1359 }
1360 }
1362 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1363 {
1364 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1365 {
1366 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x44)), 27,0,0);
1367 }
1368 }
1370 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1371 {
1372 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1373 {
1374 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 4,2,0);
1375 }
1376 }
1378 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1379 {
1380 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1381 {
1382 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)),30,28,0);
1383 }
1384 }
1387 Serdes_Diag_cycleDelay(50);
1390 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1391 {
1392 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1393 {
1394 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 5,5,1);
1395 }
1396 }
1401 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1402 {
1403 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1404 {
1405 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)), 7,6,2);
1406 }
1407 }
1409 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1410 {
1411 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1412 {
1413 if(ber_params_init->phy_type != SERDES_PCIe)
1414 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)),22,20,0);
1415 }
1416 }
1419 Serdes_Diag_cycleDelay(50);
1421 if(ber_params_init->loopback_type == SERDES_DIAG_NON_LOOPBACK)
1422 {
1423 serdes_diag_dss_stall_flag2 = serdes_diag_dss_stall_flag_set;
1425 while(serdes_diag_dss_stall_key2 != serdes_diag_dss_unlock_key)
1426 {}
1428 serdes_diag_dss_stall_key2 = serdes_diag_dss_lock_key;
1430 serdes_diag_dss_stall_flag2 = serdes_diag_dss_stall_flag_clear;
1431 }
1434 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1435 {
1436 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1437 {
1438 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 7,7,1);
1439 }
1440 }
1443 Serdes_Diag_cycleDelay(10000);
1444 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1445 {
1446 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1447 {
1449 if(ber_params_init->phy_type != SERDES_PCIe)
1450 CSL_Serdes_Force_Signal_Detect_Enable(ber_params_init->base_addr, lane_num);
1451 }
1452 }
1453 Serdes_Diag_cycleDelay(10000);
1457 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1458 {
1459 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1460 {
1461 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)), 6,3,((0)|(1<<1)|(2<<((ber_params_init->phy_type==SERDES_10GE)?3:2))));
1462 }
1463 }
1465 Serdes_Diag_cycleDelay(300000);
1467 llWaitTillTime = ber_params_init->timeoutloops;
1468 llWaitTillTime = CSL_tscRead() + ber_params_init->timeoutloops;
1470 if(ber_params_init->phy_type != SERDES_PCIe)
1471 {
1472 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1473 {
1474 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1475 {
1476 stat = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x2) & 0x020)>>5;
1478 while ((stat != 1) && (llWaitTillTime != 0))
1479 {
1480 stat = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x2) & 0x020)>>5;
1482 if(CSL_tscRead() > llWaitTillTime)
1483 {
1484 break;
1485 }
1486 }
1487 }
1488 }
1489 }
1490 else
1491 {
1492 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1493 {
1494 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1495 {
1496 stat = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x2) & 0x008)>>3;
1498 while ((stat != 1) && (llWaitTillTime != 0))
1499 {
1500 stat = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x2) & 0x008)>>3;
1502 if(CSL_tscRead() > llWaitTillTime)
1503 {
1504 break;
1505 }
1506 }
1507 }
1508 }
1509 }
1512 if(ber_params_init->phy_type != SERDES_10GE)
1513 {
1514 if(ber_params_init->phy_type != SERDES_PCIe)
1515 {
1516 CSL_SerdesRXAttConfig_PhyA(ber_params_init->base_addr,
1517 ber_params_init->num_lanes,
1518 ber_params_init->phy_type,
1519 ber_params_init->lane_mask);
1521 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1522 {
1523 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1524 {
1525 CSL_SerdesRXBoostConfig_PhyA(ber_params_init->base_addr, lane_num,
1526 ber_params_init->phy_type,
1527 ber_params_init->lane_mask);
1528 }
1529 }
1530 }
1531 }
1532 else
1533 {
1534 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1535 {
1536 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1537 {
1538 CSL_SerdesRXAttBoostConfig_PhyB(ber_params_init->base_addr, lane_num,
1539 ber_params_init->phy_type,
1540 ber_params_init->lane_mask);
1541 }
1542 }
1543 }
1545 if(ber_params_init->phy_type == SERDES_10GE)
1546 {
1547 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1548 {
1549 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1550 {
1551 CSL_Serdes_RX_Calibration_PHYB(ber_params_init->base_addr,lane_num, ber_params_init->phy_type, pTapOffsets, &pDLEVOut);
1552 }
1553 }
1554 }
1557 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1558 {
1559 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1560 {
1561 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)), 3,3,1);
1562 }
1563 }
1565 if(ber_params_init->loopback_type == SERDES_DIAG_NON_LOOPBACK)
1566 {
1567 serdes_diag_dss_stall_flag0 = serdes_diag_dss_stall_flag_set;
1569 while(serdes_diag_dss_stall_key0 != serdes_diag_dss_unlock_key)
1570 {}
1572 serdes_diag_dss_stall_key0 = serdes_diag_dss_lock_key;
1574 serdes_diag_dss_stall_flag0 = serdes_diag_dss_stall_flag_clear;
1575 }
1580 Serdes_Diag_cycleDelay(1000000);
1582 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1583 {
1584 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1585 {
1586 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)), 4,4,0);
1587 }
1588 }
1592 llWaitTillTime = CSL_tscRead() + ber_params_init->timeoutloops;
1594 do
1595 {
1596 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1597 {
1598 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1599 {
1600 pBERval->bist_valid[lane_num]= (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xC) & 0x0400) >> 10;
1602 if(ber_params_init->phy_type != SERDES_PCIe)
1603 {
1604 if (((*(volatile uint32_t *)(ber_params_init->base_addr + 0x1fc0 + 0x34))&(1<<lane_num)) == 0)
1605 {
1606 pBERval->bist_valid[lane_num] = 0;
1607 }
1608 }
1609 }
1611 }
1613 for(lane_num=0,temp=1;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1614 {
1615 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1616 {
1617 temp &= pBERval->bist_valid[lane_num];
1618 }
1619 }
1621 llCurTscVal = CSL_tscRead();
1623 } while ((!temp) && (llWaitTillTime>llCurTscVal));
1626 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1627 {
1628 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1629 {
1630 any_lane_valid |= pBERval->bist_valid[lane_num];
1631 }
1632 }
1635 pBERval->run_time[0] = CSL_tscRead();
1636 if (any_lane_valid)
1637 {
1638 Serdes_Diag_cycleDelay(ber_params_init->bertesttime);
1639 }
1641 llCurTscVal = CSL_tscRead();
1643 pBERval->run_time[0] = llCurTscVal - pBERval->run_time[0];
1646 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1647 {
1648 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1649 {
1650 pBERval->pma[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x5) & 0x0ffc) >> 2;
1651 pBERval->cdr[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x6) & 0x07f8) >> 3;
1652 }
1653 }
1656 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1657 {
1658 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1659 {
1660 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x04)), 3,3,0);
1661 }
1662 }
1664 if(ber_params_init->loopback_type == SERDES_DIAG_NON_LOOPBACK)
1665 {
1666 serdes_diag_dss_stall_flag1 = serdes_diag_dss_stall_flag_set;
1668 while(serdes_diag_dss_stall_key1 != serdes_diag_dss_unlock_key)
1669 {}
1671 serdes_diag_dss_stall_key1 = serdes_diag_dss_lock_key;
1673 serdes_diag_dss_stall_flag1 = serdes_diag_dss_stall_flag_clear;
1674 }
1676 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1677 {
1678 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1679 {
1680 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x34)), 7,7,0);
1681 }
1682 }
1685 Serdes_Diag_cycleDelay(50);
1687 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1688 {
1689 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1690 {
1691 bist_chk_sync=(CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xc)) & 0x0400;
1693 while(bist_chk_sync != 0x0000)
1694 {
1695 bist_chk_sync=(CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xc)) & 0x0400;
1696 }
1697 }
1698 }
1701 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1702 {
1703 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1704 {
1705 if(ber_params_init->phy_type == SERDES_10GE)
1706 {
1707 if(pBERval->bist_valid[lane_num])
1708 {
1709 pBERval->val[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xc) & 0x3ff) << 6;
1710 pBERval->val[lane_num] |= (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xd) & 0x0fc0) >> 6;
1711 }
1712 else
1713 {
1714 pBERval->val[lane_num] = 0x1ffff;
1715 }
1717 pBERval->att[lane_num] = CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x10);
1718 pBERval->boost[lane_num] = CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x10);
1719 pBERval->att[lane_num] = (pBERval->att[lane_num] >> 4) & 0x0f;
1720 pBERval->boost[lane_num] = (pBERval->boost[lane_num] >> 8) & 0x0f;
1722 pBERval->dfe1[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x16) & 0x00fe) >> 1;
1724 pBERval->dfe2[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x16) & 0x1) << 5;
1725 pBERval->dfe2[lane_num] |= (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x17) & 0x0f80) >> 7;
1727 pBERval->dfe3[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x17) & 0x07e) >> 1;
1729 pBERval->dfe4[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x17) & 0x01) << 5;
1730 pBERval->dfe4[lane_num] |= (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x18) & 0x0f80) >> 7;
1732 pBERval->dfe5[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x18) & 0x7e) >> 1;
1734 pBERval->dfe1[lane_num] = pBERval->dfe1[lane_num] - 64;
1735 pBERval->dfe2[lane_num] = pBERval->dfe2[lane_num] - 32;
1736 pBERval->dfe3[lane_num] = pBERval->dfe3[lane_num] - 32;
1737 pBERval->dfe4[lane_num] = pBERval->dfe4[lane_num] - 32;
1738 pBERval->dfe5[lane_num] = pBERval->dfe5[lane_num] - 32;
1741 pBERval->cdfe1[lane_num] = pDLEVOut.tap_values[lane_num][0];
1742 pBERval->cdfe2[lane_num] = pDLEVOut.tap_values[lane_num][1];
1743 pBERval->cdfe3[lane_num] = pDLEVOut.tap_values[lane_num][2];
1744 pBERval->cdfe4[lane_num] = pDLEVOut.tap_values[lane_num][3];
1745 pBERval->cdfe5[lane_num] = pDLEVOut.tap_values[lane_num][4];
1747 pBERval->dlevp[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x44) & 0xff0) >> 4;
1749 pBERval->dlevn[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x45) & 0x0ff);
1751 pBERval->dlevavg[lane_num] = (pBERval->dlevn[lane_num] - pBERval->dlevp[lane_num])/2;
1752 pBERval->delay[lane_num] = pDLEVOut.delay[lane_num];
1753 }
1754 else
1755 {
1756 if(pBERval->bist_valid[lane_num])
1757 {
1758 pBERval->val[lane_num] = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xc) & 0x3ff) << 6;
1759 pBERval->val[lane_num] |= (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0xd) & 0x0fc0) >> 6;
1760 }
1761 else
1762 {
1763 pBERval->val[lane_num] = 0x1ffff;
1764 }
1766 pBERval->att[lane_num] = CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x11);
1767 pBERval->boost[lane_num] = CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x11);
1768 pBERval->att[lane_num] = (pBERval->att[lane_num] >> 4) & 0x0f;
1769 pBERval->boost[lane_num] = (pBERval->boost[lane_num] >> 8) & 0x0f;
1770 }
1771 }
1772 }
1776 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1777 {
1778 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1779 {
1780 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)), 7,7,0);
1781 }
1782 }
1784 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1785 {
1786 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1787 {
1788 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(ber_params_init->base_addr, lane_num, 0x00)),22,20,0);
1789 }
1790 }
1792 return SERDES_DIAG_SETUP_OK;
1793 }
1798 static inline void Serdes_Diag_SweepCMC1C2(const SERDES_DIAG_BER_INIT_T *ber_params_init,
1799 SERDES_DIAG_CMC1C2_T *pDiagCMC1C2,
1800 CSL_SERDES_TAP_OFFSETS_T *pTapOffsets,
1801 const SERDES_DIAG_TX_COEFF_T *diag_tx_coeff)
1802 {
1803 uint32_t cm, c1, c2, lane_num, count = 0;
1804 CSL_SERDES_RESULT diag_stat;
1805 SERDES_DIAG_BER_VAL_T pBERval;
1807 memset(&pBERval, 0, sizeof(pBERval));
1809 for (cm = diag_tx_coeff->cm_coeff_start; cm <= diag_tx_coeff->cm_coeff_end; cm++)
1810 {
1811 for (c1 = diag_tx_coeff->c1_coeff_start; c1 <= diag_tx_coeff->c1_coeff_end; c1++)
1812 {
1813 for (c2 = diag_tx_coeff->c2_coeff_start; c2 <= diag_tx_coeff->c2_coeff_end; c2++)
1814 {
1815 CSL_Serdes_Assert_Reset(ber_params_init->base_addr, ber_params_init->phy_type, ber_params_init->lane_mask);
1817 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1818 {
1819 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1820 {
1821 CSL_SERDES_CONFIG_CM_C1_C2(ber_params_init->base_addr, lane_num, cm, c1, c2, ber_params_init->phy_type);
1822 }
1823 }
1825 CSL_Serdes_Force_Signal_Detect_Low(ber_params_init->base_addr, SERDES_DIAG_MAX_LANES, ber_params_init->lane_mask);
1827 diag_stat = CSL_Serdes_Deassert_Reset(ber_params_init->base_addr, ber_params_init->phy_type, 1, SERDES_DIAG_MAX_LANES, ber_params_init->lane_mask);
1830 if (ber_params_init->phy_type == SERDES_10GE)
1831 {
1832 CSL_SerdesWriteAverageOffsets(ber_params_init->base_addr,
1833 SERDES_DIAG_MAX_LANES,
1834 ber_params_init->lane_mask,
1835 ber_params_init->phy_type, pTapOffsets);
1836 }
1838 if(ber_params_init->phy_type != SERDES_10GE)
1839 {
1840 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1841 {
1842 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1843 {
1844 CSL_Serdes_PHYA_Init_Config(ber_params_init->base_addr, lane_num);
1845 }
1846 }
1847 }
1850 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1851 {
1852 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1853 {
1854 CSL_SerdesClearTXIdle(ber_params_init->base_addr, lane_num, ber_params_init->phy_type);
1855 }
1856 }
1858 pDiagCMC1C2->cm[count] = cm;
1859 pDiagCMC1C2->c1[count] = c1;
1860 pDiagCMC1C2->c2[count] = c2;
1862 if(diag_stat == SERDES_DIAG_SETUP_OK)
1863 {
1865 Serdes_Diag_BERTest(ber_params_init, &pBERval,pTapOffsets);
1867 pDiagCMC1C2->run_time[count] = pBERval.run_time[0];
1869 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
1870 {
1871 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
1872 {
1873 switch(lane_num)
1874 {
1875 case 0:
1877 pDiagCMC1C2->berlane0[count] = pBERval.val[lane_num];
1878 pDiagCMC1C2->bist_valid0[count] = pBERval.bist_valid[lane_num];
1879 pDiagCMC1C2->att0[count] = pBERval.att[lane_num];
1880 pDiagCMC1C2->boost0[count] = pBERval.boost[lane_num];
1882 pDiagCMC1C2->dfe1_0[count] = pBERval.dfe1[lane_num];
1883 pDiagCMC1C2->dfe2_0[count] = pBERval.dfe2[lane_num];
1884 pDiagCMC1C2->dfe3_0[count] = pBERval.dfe3[lane_num];
1885 pDiagCMC1C2->dfe4_0[count] = pBERval.dfe4[lane_num];
1886 pDiagCMC1C2->dfe5_0[count] = pBERval.dfe5[lane_num];
1888 pDiagCMC1C2->cdfe1_0[count] = pBERval.cdfe1[lane_num];
1889 pDiagCMC1C2->cdfe2_0[count] = pBERval.cdfe2[lane_num];
1890 pDiagCMC1C2->cdfe3_0[count] = pBERval.cdfe3[lane_num];
1891 pDiagCMC1C2->cdfe4_0[count] = pBERval.cdfe4[lane_num];
1892 pDiagCMC1C2->cdfe5_0[count] = pBERval.cdfe5[lane_num];
1894 pDiagCMC1C2->cdr0[count] = pBERval.cdr[lane_num];
1895 pDiagCMC1C2->pma0[count] = pBERval.pma[lane_num];
1897 pDiagCMC1C2->dlevp0[count] = pBERval.dlevp[lane_num];
1898 pDiagCMC1C2->dlevn0[count] = pBERval.dlevn[lane_num];
1899 pDiagCMC1C2->dlevavg0[count] = pBERval.dlevavg[lane_num];
1900 pDiagCMC1C2->delay0[count] = pBERval.delay[lane_num];
1901 break;
1903 case 1:
1905 pDiagCMC1C2->berlane1[count] = pBERval.val[lane_num];
1906 pDiagCMC1C2->bist_valid1[count] = pBERval.bist_valid[lane_num];
1907 pDiagCMC1C2->att1[count] = pBERval.att[lane_num];
1908 pDiagCMC1C2->boost1[count] = pBERval.boost[lane_num];
1910 pDiagCMC1C2->dfe1_1[count] = pBERval.dfe1[lane_num];
1911 pDiagCMC1C2->dfe2_1[count] = pBERval.dfe2[lane_num];
1912 pDiagCMC1C2->dfe3_1[count] = pBERval.dfe3[lane_num];
1913 pDiagCMC1C2->dfe4_1[count] = pBERval.dfe4[lane_num];
1914 pDiagCMC1C2->dfe5_1[count] = pBERval.dfe5[lane_num];
1916 pDiagCMC1C2->cdfe1_1[count] = pBERval.cdfe1[lane_num];
1917 pDiagCMC1C2->cdfe2_1[count] = pBERval.cdfe2[lane_num];
1918 pDiagCMC1C2->cdfe3_1[count] = pBERval.cdfe3[lane_num];
1919 pDiagCMC1C2->cdfe4_1[count] = pBERval.cdfe4[lane_num];
1920 pDiagCMC1C2->cdfe5_1[count] = pBERval.cdfe5[lane_num];
1922 pDiagCMC1C2->cdr1[count] = pBERval.cdr[lane_num];
1923 pDiagCMC1C2->pma1[count] = pBERval.pma[lane_num];
1925 pDiagCMC1C2->dlevp1[count] = pBERval.dlevp[lane_num];
1926 pDiagCMC1C2->dlevn1[count] = pBERval.dlevn[lane_num];
1927 pDiagCMC1C2->dlevavg1[count] = pBERval.dlevavg[lane_num];
1928 pDiagCMC1C2->delay1[count] = pBERval.delay[lane_num];
1929 break;
1931 case 2:
1933 pDiagCMC1C2->berlane2[count] = pBERval.val[lane_num];
1934 pDiagCMC1C2->bist_valid2[count] = pBERval.bist_valid[lane_num];
1935 pDiagCMC1C2->att2[count] = pBERval.att[lane_num];
1936 pDiagCMC1C2->boost2[count] = pBERval.boost[lane_num];
1938 pDiagCMC1C2->dfe1_2[count] = pBERval.dfe1[lane_num];
1939 pDiagCMC1C2->dfe2_2[count] = pBERval.dfe2[lane_num];
1940 pDiagCMC1C2->dfe3_2[count] = pBERval.dfe3[lane_num];
1941 pDiagCMC1C2->dfe4_2[count] = pBERval.dfe4[lane_num];
1942 pDiagCMC1C2->dfe5_2[count] = pBERval.dfe5[lane_num];
1944 pDiagCMC1C2->cdfe1_2[count] = pBERval.cdfe1[lane_num];
1945 pDiagCMC1C2->cdfe2_2[count] = pBERval.cdfe2[lane_num];
1946 pDiagCMC1C2->cdfe3_2[count] = pBERval.cdfe3[lane_num];
1947 pDiagCMC1C2->cdfe4_2[count] = pBERval.cdfe4[lane_num];
1948 pDiagCMC1C2->cdfe5_2[count] = pBERval.cdfe5[lane_num];
1950 pDiagCMC1C2->cdr2[count] = pBERval.cdr[lane_num];
1951 pDiagCMC1C2->pma2[count] = pBERval.pma[lane_num];
1953 pDiagCMC1C2->dlevp2[count] = pBERval.dlevp[lane_num];
1954 pDiagCMC1C2->dlevn2[count] = pBERval.dlevn[lane_num];
1955 pDiagCMC1C2->dlevavg2[count] = pBERval.dlevavg[lane_num];
1956 pDiagCMC1C2->delay2[count] = pBERval.delay[lane_num];
1957 break;
1959 case 3:
1961 pDiagCMC1C2->berlane3[count] = pBERval.val[lane_num];
1962 pDiagCMC1C2->bist_valid3[count] = pBERval.bist_valid[lane_num];
1963 pDiagCMC1C2->att3[count] = pBERval.att[lane_num];
1964 pDiagCMC1C2->boost3[count] = pBERval.boost[lane_num];
1966 pDiagCMC1C2->dfe1_3[count] = pBERval.dfe1[lane_num];
1967 pDiagCMC1C2->dfe2_3[count] = pBERval.dfe2[lane_num];
1968 pDiagCMC1C2->dfe3_3[count] = pBERval.dfe3[lane_num];
1969 pDiagCMC1C2->dfe4_3[count] = pBERval.dfe4[lane_num];
1970 pDiagCMC1C2->dfe5_3[count] = pBERval.dfe5[lane_num];
1972 pDiagCMC1C2->cdfe1_3[count] = pBERval.cdfe1[lane_num];
1973 pDiagCMC1C2->cdfe2_3[count] = pBERval.cdfe2[lane_num];
1974 pDiagCMC1C2->cdfe3_3[count] = pBERval.cdfe3[lane_num];
1975 pDiagCMC1C2->cdfe4_3[count] = pBERval.cdfe4[lane_num];
1976 pDiagCMC1C2->cdfe5_3[count] = pBERval.cdfe5[lane_num];
1978 pDiagCMC1C2->cdr3[count] = pBERval.cdr[lane_num];
1979 pDiagCMC1C2->pma3[count] = pBERval.pma[lane_num];
1981 pDiagCMC1C2->dlevp3[count] = pBERval.dlevp[lane_num];
1982 pDiagCMC1C2->dlevn3[count] = pBERval.dlevn[lane_num];
1983 pDiagCMC1C2->dlevavg3[count] = pBERval.dlevavg[lane_num];
1984 pDiagCMC1C2->delay3[count] = pBERval.delay[lane_num];
1985 break;
1986 }
1987 }
1988 }
1989 }
1990 else
1991 {
1992 pDiagCMC1C2->run_time[count] = 0xdeadbeef;
1993 pDiagCMC1C2->berlane0[count] = 0xdeadbeef;
1994 pDiagCMC1C2->berlane1[count] = 0xdeadbeef;
1995 pDiagCMC1C2->berlane2[count] = 0xdeadbeef;
1996 pDiagCMC1C2->berlane3[count] = 0xdeadbeef;
1997 }
1999 count++;
2000 }
2001 }
2002 }
2003 }
2007 static inline void Serdes_Diag_SweepPCIE(const SERDES_DIAG_BER_INIT_T *ber_params_init,
2008 SERDES_DIAG_CMC1C2_T *pDiagCMC1C2,
2009 CSL_SERDES_TAP_OFFSETS_T *pTapOffsets,
2010 const SERDES_DIAG_TX_COEFF_T *diag_tx_coeff)
2011 {
2012 uint32_t swing, deemph, lane_num, tbus_data, count = 0;
2013 CSL_SERDES_RESULT diag_stat = SERDES_DIAG_SETUP_OK;
2014 SERDES_DIAG_BER_VAL_T pBERval;
2016 memset(&pBERval, 0, sizeof(pBERval));
2018 for (swing = diag_tx_coeff->tx_swing_start; swing <= diag_tx_coeff->tx_swing_end; swing++)
2019 {
2020 for (deemph = diag_tx_coeff->tx_deemph_start; deemph <= diag_tx_coeff->tx_deemph_end; deemph++)
2021 {
2023 for(lane_num = 0; lane_num < ber_params_init->num_lanes; lane_num++)
2024 {
2026 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),27,27, swing);
2029 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),28,28, deemph);
2030 }
2033 for(lane_num = 0; lane_num < ber_params_init->num_lanes; lane_num++)
2034 {
2035 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
2036 {
2038 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),19,19, 0x1);
2040 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),29,29, 0x1);
2042 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),15,15, 0x1);
2045 tbus_data = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x2) & 0x10) >> 4;
2047 while ( (tbus_data & 0x001 ) == 0x001)
2048 {
2049 tbus_data = (CSL_SerdesReadSelectedTbus(ber_params_init->base_addr, lane_num+1, 0x2) & 0x10) >> 4;
2050 }
2053 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),19,19, 0x1);
2054 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),16,16, 0x1);
2056 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),19,19, 0x1);
2057 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),16,16, 0x1);
2059 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),19,19, 0x1);
2060 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),16,16, 0x1);
2063 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),19,19, 0x0);
2064 CSL_FINSR(*(volatile uint32_t *)(ber_params_init->base_addr + (lane_num * 0x200) + 0x200 + 0x028),16,16, 0x1);
2065 }
2067 }
2069 pDiagCMC1C2->swing[count] = swing;
2070 pDiagCMC1C2->deemph[count] = deemph;
2072 if(diag_stat == SERDES_DIAG_SETUP_OK)
2073 {
2075 Serdes_Diag_BERTest(ber_params_init, &pBERval,pTapOffsets);
2077 pDiagCMC1C2->run_time[count] = pBERval.run_time[0];
2079 for(lane_num=0;lane_num<SERDES_DIAG_MAX_LANES;lane_num++)
2080 {
2081 if ((ber_params_init->lane_mask & (1<<lane_num))!=0)
2082 {
2083 switch(lane_num)
2084 {
2085 case 0:
2087 pDiagCMC1C2->berlane0[count] = pBERval.val[lane_num];
2088 pDiagCMC1C2->bist_valid0[count] = pBERval.bist_valid[lane_num];
2089 pDiagCMC1C2->att0[count] = pBERval.att[lane_num];
2090 pDiagCMC1C2->boost0[count] = pBERval.boost[lane_num];
2092 pDiagCMC1C2->dfe1_0[count] = pBERval.dfe1[lane_num];
2093 pDiagCMC1C2->dfe2_0[count] = pBERval.dfe2[lane_num];
2094 pDiagCMC1C2->dfe3_0[count] = pBERval.dfe3[lane_num];
2095 pDiagCMC1C2->dfe4_0[count] = pBERval.dfe4[lane_num];
2096 pDiagCMC1C2->dfe5_0[count] = pBERval.dfe5[lane_num];
2098 pDiagCMC1C2->cdfe1_0[count] = pBERval.cdfe1[lane_num];
2099 pDiagCMC1C2->cdfe2_0[count] = pBERval.cdfe2[lane_num];
2100 pDiagCMC1C2->cdfe3_0[count] = pBERval.cdfe3[lane_num];
2101 pDiagCMC1C2->cdfe4_0[count] = pBERval.cdfe4[lane_num];
2102 pDiagCMC1C2->cdfe5_0[count] = pBERval.cdfe5[lane_num];
2104 pDiagCMC1C2->cdr0[count] = pBERval.cdr[lane_num];
2105 pDiagCMC1C2->pma0[count] = pBERval.pma[lane_num];
2107 pDiagCMC1C2->dlevp0[count] = pBERval.dlevp[lane_num];
2108 pDiagCMC1C2->dlevn0[count] = pBERval.dlevn[lane_num];
2109 pDiagCMC1C2->dlevavg0[count] = pBERval.dlevavg[lane_num];
2110 pDiagCMC1C2->delay0[count] = pBERval.delay[lane_num];
2111 break;
2113 case 1:
2115 pDiagCMC1C2->berlane1[count] = pBERval.val[lane_num];
2116 pDiagCMC1C2->bist_valid1[count] = pBERval.bist_valid[lane_num];
2117 pDiagCMC1C2->att1[count] = pBERval.att[lane_num];
2118 pDiagCMC1C2->boost1[count] = pBERval.boost[lane_num];
2120 pDiagCMC1C2->dfe1_1[count] = pBERval.dfe1[lane_num];
2121 pDiagCMC1C2->dfe2_1[count] = pBERval.dfe2[lane_num];
2122 pDiagCMC1C2->dfe3_1[count] = pBERval.dfe3[lane_num];
2123 pDiagCMC1C2->dfe4_1[count] = pBERval.dfe4[lane_num];
2124 pDiagCMC1C2->dfe5_1[count] = pBERval.dfe5[lane_num];
2126 pDiagCMC1C2->cdfe1_1[count] = pBERval.cdfe1[lane_num];
2127 pDiagCMC1C2->cdfe2_1[count] = pBERval.cdfe2[lane_num];
2128 pDiagCMC1C2->cdfe3_1[count] = pBERval.cdfe3[lane_num];
2129 pDiagCMC1C2->cdfe4_1[count] = pBERval.cdfe4[lane_num];
2130 pDiagCMC1C2->cdfe5_1[count] = pBERval.cdfe5[lane_num];
2132 pDiagCMC1C2->cdr1[count] = pBERval.cdr[lane_num];
2133 pDiagCMC1C2->pma1[count] = pBERval.pma[lane_num];
2135 pDiagCMC1C2->dlevp1[count] = pBERval.dlevp[lane_num];
2136 pDiagCMC1C2->dlevn1[count] = pBERval.dlevn[lane_num];
2137 pDiagCMC1C2->dlevavg1[count] = pBERval.dlevavg[lane_num];
2138 pDiagCMC1C2->delay1[count] = pBERval.delay[lane_num];
2139 break;
2141 case 2:
2143 pDiagCMC1C2->berlane2[count] = pBERval.val[lane_num];
2144 pDiagCMC1C2->bist_valid2[count] = pBERval.bist_valid[lane_num];
2145 pDiagCMC1C2->att2[count] = pBERval.att[lane_num];
2146 pDiagCMC1C2->boost2[count] = pBERval.boost[lane_num];
2148 pDiagCMC1C2->dfe1_2[count] = pBERval.dfe1[lane_num];
2149 pDiagCMC1C2->dfe2_2[count] = pBERval.dfe2[lane_num];
2150 pDiagCMC1C2->dfe3_2[count] = pBERval.dfe3[lane_num];
2151 pDiagCMC1C2->dfe4_2[count] = pBERval.dfe4[lane_num];
2152 pDiagCMC1C2->dfe5_2[count] = pBERval.dfe5[lane_num];
2154 pDiagCMC1C2->cdfe1_2[count] = pBERval.cdfe1[lane_num];
2155 pDiagCMC1C2->cdfe2_2[count] = pBERval.cdfe2[lane_num];
2156 pDiagCMC1C2->cdfe3_2[count] = pBERval.cdfe3[lane_num];
2157 pDiagCMC1C2->cdfe4_2[count] = pBERval.cdfe4[lane_num];
2158 pDiagCMC1C2->cdfe5_2[count] = pBERval.cdfe5[lane_num];
2160 pDiagCMC1C2->cdr2[count] = pBERval.cdr[lane_num];
2161 pDiagCMC1C2->pma2[count] = pBERval.pma[lane_num];
2163 pDiagCMC1C2->dlevp2[count] = pBERval.dlevp[lane_num];
2164 pDiagCMC1C2->dlevn2[count] = pBERval.dlevn[lane_num];
2165 pDiagCMC1C2->dlevavg2[count] = pBERval.dlevavg[lane_num];
2166 pDiagCMC1C2->delay2[count] = pBERval.delay[lane_num];
2167 break;
2169 case 3:
2171 pDiagCMC1C2->berlane3[count] = pBERval.val[lane_num];
2172 pDiagCMC1C2->bist_valid3[count] = pBERval.bist_valid[lane_num];
2173 pDiagCMC1C2->att3[count] = pBERval.att[lane_num];
2174 pDiagCMC1C2->boost3[count] = pBERval.boost[lane_num];
2176 pDiagCMC1C2->dfe1_3[count] = pBERval.dfe1[lane_num];
2177 pDiagCMC1C2->dfe2_3[count] = pBERval.dfe2[lane_num];
2178 pDiagCMC1C2->dfe3_3[count] = pBERval.dfe3[lane_num];
2179 pDiagCMC1C2->dfe4_3[count] = pBERval.dfe4[lane_num];
2180 pDiagCMC1C2->dfe5_3[count] = pBERval.dfe5[lane_num];
2182 pDiagCMC1C2->cdfe1_3[count] = pBERval.cdfe1[lane_num];
2183 pDiagCMC1C2->cdfe2_3[count] = pBERval.cdfe2[lane_num];
2184 pDiagCMC1C2->cdfe3_3[count] = pBERval.cdfe3[lane_num];
2185 pDiagCMC1C2->cdfe4_3[count] = pBERval.cdfe4[lane_num];
2186 pDiagCMC1C2->cdfe5_3[count] = pBERval.cdfe5[lane_num];
2188 pDiagCMC1C2->cdr3[count] = pBERval.cdr[lane_num];
2189 pDiagCMC1C2->pma3[count] = pBERval.pma[lane_num];
2191 pDiagCMC1C2->dlevp3[count] = pBERval.dlevp[lane_num];
2192 pDiagCMC1C2->dlevn3[count] = pBERval.dlevn[lane_num];
2193 pDiagCMC1C2->dlevavg3[count] = pBERval.dlevavg[lane_num];
2194 pDiagCMC1C2->delay3[count] = pBERval.delay[lane_num];
2195 break;
2196 }
2197 }
2198 }
2199 }
2200 else
2201 {
2202 pDiagCMC1C2->run_time[count] = 0xdeadbeef;
2203 pDiagCMC1C2->berlane0[count] = 0xdeadbeef;
2204 pDiagCMC1C2->berlane1[count] = 0xdeadbeef;
2205 pDiagCMC1C2->berlane2[count] = 0xdeadbeef;
2206 pDiagCMC1C2->berlane3[count] = 0xdeadbeef;
2207 }
2209 count++;
2210 }
2211 }
2212 }
2216 static inline void Serdes_Diag_EyeMonitor(char *fullfilename,
2217 SERDES_DIAG_EYE_INIT_T eye_init_params,
2218 SERDES_DIAG_EYE_OUTPUT_T *pEyeOutput)
2219 {
2220 uint32_t comp_offset;
2221 uint32_t tbus_data;
2222 uint32_t eye_scan_errors;
2223 uint32_t array, delay, error_free = 0, max_error_free = 0, current_bin, previous_bin = 0;
2224 uint32_t count90=0, count=0, countmax=0, endvalue, inphase=0;
2225 uint32_t pcm_outs, pcm90, phase_min, phase_max;
2226 FILE *file;
2227 int iPhyA,iNotFourLaner;
2229 iNotFourLaner=(*(volatile uint32_t *)(eye_init_params.base_addr + 0x1fc0)>>16)&0x0ffff;
2230 iPhyA = (iNotFourLaner != 0x4eba);
2232 memset(&serdes_diag_eye_scan_errors_array, 0, sizeof(serdes_diag_eye_scan_errors_array));
2234 if (eye_init_params.v_offset==0)
2235 {
2236 eye_init_params.v_offset++;
2237 }
2238 if (eye_init_params.t_offset==0)
2239 {
2240 eye_init_params.t_offset++;
2241 }
2243 file = fopen(fullfilename,"w");
2245 if (eye_init_params.calibrate_eye == 1)
2246 {
2248 if(eye_init_params.phase_num == 1)
2249 {
2253 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2254 0xFF00FFFF, 0x00500000);
2255 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2256 0xFFFFFF00, 0x00000010);
2258 }
2259 else
2260 {
2264 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2265 0xFF00FFFF, 0x00900000);
2266 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2267 0xFFFFFF00, 0x00000008);
2268 }
2271 for (array = 0; array < SERDES_DIAG_MAX_DLY; array++)
2272 {
2274 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2275 0x00FFFFFF, array << 24);
2277 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2278 0xFFFFFFFC, array >> 8);
2280 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2281 0xFFFFFFFB, 0x00000004);
2283 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2284 0xFFFFFFFB, 0x00000000);
2286 count90 = 0;
2288 for (delay = 0; delay < SERDES_DIAG_AVERAGE_DELAY; delay++)
2289 {
2290 pcm_outs = CSL_SerdesReadSelectedTbus(eye_init_params.base_addr,
2291 eye_init_params.lane_num+1,0x1D) & 0x0F;
2292 if (((pcm_outs & 0x4) >> 2) == 1)
2293 {
2294 count90++;
2295 }
2297 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30), 0xFFFFFFFB, 0x00000004);
2299 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30), 0xFFFFFFFB, 0x00000000);
2300 }
2302 if (count90 >= 50)
2303 {
2304 pcm90 = 1;
2305 }
2306 else
2307 {
2308 pcm90 = 0;
2309 }
2312 if (pcm90 == 1)
2313 {
2314 inphase = 1;
2315 endvalue = array;
2316 }
2317 else
2318 {
2319 inphase = 0;
2320 }
2322 if (inphase == 1)
2323 {
2324 count++;
2325 }
2326 else
2327 {
2328 if (count > countmax)
2329 {
2330 countmax = count;
2331 phase_max = endvalue;
2332 phase_min = phase_max-count+1;
2333 }
2334 count=0;
2335 }
2336 }
2337 }
2338 else
2339 {
2340 phase_min = 0;
2341 phase_max = (SERDES_DIAG_MAX_DLY - 1);
2342 }
2345 if(eye_init_params.phase_num == 1)
2346 {
2351 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2352 0xFF00FFFF, 0x00700000);
2353 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2354 0xFFFFFF00, 0x00000051);
2356 }
2357 else
2358 {
2363 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2364 0xFF00FFFF, 0x00B00000);
2365 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x30),
2366 0xFFFFFF00, 0x00000089);
2367 }
2372 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2373 0xFFFFFF00, 0x00000007);
2378 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x0098), 0x00FFFFFF, 0x01000000);
2379 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x009c), 0xFFFFFF00, 0x00000080);
2380 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00b8), 0xFFFF00FF, 0x00004000);
2385 if(eye_init_params.phase_num == 1)
2386 {
2388 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00b8), 0x0000FFFF, 0xFFEF0000);
2390 }
2391 else
2392 {
2393 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00b8), 0x0000FFFF, 0xFFF70000);
2394 }
2396 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00bc), 0xFFF00000, 0x000FFFFF);
2399 tbus_data = CSL_SerdesReadSelectedTbus(eye_init_params.base_addr,
2400 eye_init_params.lane_num+1,0x02);
2401 while ((tbus_data & 0x020 )!= 0x020)
2402 {
2403 tbus_data = CSL_SerdesReadTbusVal(eye_init_params.base_addr);
2404 }
2406 Serdes_Diag_cycleDelay(eye_init_params.gatetime);
2408 if(eye_init_params.phase_num == 1)
2409 {
2411 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x008c),
2412 0xFF1FFFFF, 0x00000000 | (2<<21));
2413 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00bc),
2414 0xFFBFFFFF, 0x00400000);
2415 comp_offset = (CSL_SerdesReadSelectedTbus(eye_init_params.base_addr,
2416 eye_init_params.lane_num+1,(iPhyA)?0x12:0x11)>>4)&0x0ff;
2417 }
2418 else
2419 {
2421 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x008c), 0xFF1FFFFF, 0x00000000 | (4<<21));
2422 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00bc), 0xFFBFFFFF, 0x00400000);
2423 comp_offset = (CSL_SerdesReadSelectedTbus(eye_init_params.base_addr,eye_init_params.lane_num+1,(iPhyA)?0x12:0x11)>>4)&0x0ff;
2424 }
2427 for (array = 0; array < SERDES_DIAG_MAX_ARRAY; array=array+eye_init_params.v_offset)
2428 {
2430 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x009c), 0xFFFFFF00, array);
2432 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2433 0xFFFFFBFF, 0x00000400);
2435 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2436 0xFFFFFBFF, 0x00000000);
2439 for (delay = 0; delay < SERDES_DIAG_MAX_DLY; delay=delay+eye_init_params.t_offset)
2440 {
2441 serdes_diag_eye_scan_errors_array[array][delay]=1;
2442 }
2444 for (delay = phase_min; delay <= phase_max; delay=delay+eye_init_params.t_offset)
2445 {
2447 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2448 0x00FFFFFF, (delay & 0x0ff) << 24);
2449 Serdes_Diag_cycleDelay(5000);
2451 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00b8),
2452 0xFFFF00FF, 0x0000C000);
2455 Serdes_Diag_cycleDelay(500000);
2457 eye_scan_errors = (CSL_SerdesReadSelectedTbus(eye_init_params.base_addr,
2458 eye_init_params.lane_num+1,(iPhyA)?0x1A:0x19) << 4);
2459 eye_scan_errors |= ((CSL_SerdesReadSelectedTbus(eye_init_params.base_addr,
2460 eye_init_params.lane_num+1,(iPhyA)?0x1B:0x1A) & 0x0F00) >> 8);
2462 serdes_diag_eye_scan_errors_array[array][delay] = eye_scan_errors;
2465 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00b8),
2466 0xFFFF00FF, 0x00004000);
2467 }
2468 }
2471 for(array = 0; array < SERDES_DIAG_MAX_ARRAY; array=array+eye_init_params.v_offset)
2472 {
2473 for (delay = 0; delay < SERDES_DIAG_MAX_DLY; delay=delay+eye_init_params.t_offset)
2474 {
2475 fprintf(file,"%d ", serdes_diag_eye_scan_errors_array[array][delay]);
2476 }
2477 fprintf(file,"\n");
2478 }
2481 max_error_free = 0;
2483 for (array = 0; array < SERDES_DIAG_MAX_ARRAY; array=array+eye_init_params.v_offset)
2484 {
2485 error_free=current_bin=previous_bin=0;
2486 for (delay = 0; delay < SERDES_DIAG_MAX_DLY; delay=delay+eye_init_params.t_offset)
2487 {
2488 current_bin = serdes_diag_eye_scan_errors_array[array][delay];
2489 if (current_bin == 0)
2490 {
2491 if (previous_bin == current_bin)
2492 {
2493 error_free++;
2494 previous_bin = current_bin;
2495 if (error_free > max_error_free)
2496 {
2497 max_error_free = error_free;
2498 }
2499 }
2500 else
2501 {
2502 error_free++;
2503 previous_bin = current_bin;
2504 }
2505 }
2506 else
2507 {
2508 error_free = 0;
2509 previous_bin = current_bin;
2510 }
2511 }
2512 }
2514 pEyeOutput->eye_width = max_error_free*eye_init_params.t_offset*2;
2517 max_error_free = 0;
2518 for (delay = 0; delay < SERDES_DIAG_MAX_DLY; delay=delay+eye_init_params.t_offset)
2519 {
2520 error_free=current_bin=previous_bin=0;
2521 for (array = 0; array < SERDES_DIAG_MAX_ARRAY; array=array+eye_init_params.v_offset)
2522 {
2523 current_bin = serdes_diag_eye_scan_errors_array[array][delay];
2524 if (current_bin == 0)
2525 {
2526 if (previous_bin == current_bin)
2527 {
2528 error_free++;
2529 previous_bin = current_bin;
2530 if (error_free > max_error_free)
2531 {
2532 max_error_free = error_free;
2533 }
2534 }
2535 else
2536 {
2537 error_free++;
2538 previous_bin = current_bin;
2539 }
2540 }
2541 else
2542 {
2543 error_free = 0;
2544 previous_bin = current_bin;
2545 }
2546 }
2547 }
2549 pEyeOutput->eye_height = max_error_free*eye_init_params.v_offset*2;
2552 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x009c),
2553 0xFFFFFF00, comp_offset);
2555 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2556 0xFFFFFBFF, 0x00000400);
2558 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2559 0xFFFFFBFF, 0x00000000);
2563 Serdes_Diag_Write_32_Mask(eye_init_params.base_addr+
2564 0x200*(eye_init_params.lane_num+1)+0x0030, 0xFFFFFF00, 0x00000000);
2566 Serdes_Diag_Write_32_Mask(eye_init_params.base_addr+
2567 0x200*(eye_init_params.lane_num+1)+0x002C, 0xFFFFFF00, 0x00000003);
2569 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x0098),
2570 0xFEFFFFFF, 0x00000000);
2572 Serdes_Diag_Write_32_Mask(SERDES_DIAG_COMLANE_MAP(eye_init_params.base_addr, 0x00b8),
2573 0xFFFF3FFF, 0x00000000);
2575 Serdes_Diag_Write_32_Mask(SERDES_DIAG_LANE_MAP(eye_init_params.base_addr, eye_init_params.lane_num, 0x2c),
2576 0xFF3FFFFF, 0x00300000);
2578 fclose(file);
2579 }
2584 static inline void Serdes_Diag_Att_Boost_Calibration(const CSL_SERDES_LANE_ENABLE_PARAMS_T *serdes_lane_enable_params,
2585 CSL_SERDES_RX_COEFF_T *pRxCoeff)
2586 {
2587 uint32_t repeat_index, lane_num;
2588 int32_t att = 0, num_att = 0, boost = 0, num_boost = 0;
2589 int32_t att_array[CSL_SERDES_ATT_BOOST_NUM_REPEAT][CSL_SERDES_MAX_LANES];
2590 int32_t boost_array[CSL_SERDES_ATT_BOOST_NUM_REPEAT][CSL_SERDES_MAX_LANES];
2591 int32_t final_att[CSL_SERDES_MAX_LANES];
2592 int32_t final_boost[CSL_SERDES_MAX_LANES];
2595 for(repeat_index=0; repeat_index<CSL_SERDES_ATT_BOOST_NUM_REPEAT; repeat_index++)
2596 {
2597 for(lane_num=0; lane_num<CSL_SERDES_MAX_LANES; lane_num++)
2598 {
2599 if ((serdes_lane_enable_params->lane_mask & (1<<lane_num))!=0)
2600 {
2602 CSL_SerdesWaitForRXValid(serdes_lane_enable_params->base_addr,
2603 CSL_SERDES_MAX_LANES,
2604 serdes_lane_enable_params->lane_mask,
2605 serdes_lane_enable_params->phy_type);
2607 CSL_SerdesRXAttBoostConfig(serdes_lane_enable_params->base_addr, lane_num,
2608 serdes_lane_enable_params->num_lanes,
2609 serdes_lane_enable_params->phy_type,
2610 serdes_lane_enable_params->lane_mask);
2613 att = boost = CSL_SerdesReadSelectedTbus(serdes_lane_enable_params->base_addr,
2614 lane_num + 1,
2615 (serdes_lane_enable_params->phy_type==SERDES_10GE)?0x10:0x11);
2616 att = (att >> 4) & 0x0f;
2617 boost = (boost >> 8) & 0x0f;
2618 att_array[repeat_index][lane_num] = att;
2619 boost_array[repeat_index][lane_num] = boost;
2620 }
2621 }
2624 CSL_Serdes_Force_Signal_Detect_Low(serdes_lane_enable_params->base_addr,
2625 CSL_SERDES_MAX_LANES,
2626 serdes_lane_enable_params->lane_mask);
2628 CSL_Serdes_CycleDelay(10000);
2631 for(lane_num=0; lane_num<CSL_SERDES_MAX_LANES; lane_num++)
2632 {
2633 if ((serdes_lane_enable_params->lane_mask & (1<<lane_num))!=0)
2634 {
2635 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x200*(lane_num+1) + 0x04),2,1, 0x0);
2636 }
2637 }
2638 }
2641 for(lane_num=0; lane_num<CSL_SERDES_MAX_LANES; lane_num++)
2642 {
2643 if ((serdes_lane_enable_params->lane_mask & (1<<lane_num))!=0)
2644 {
2645 att = boost = num_att = num_boost = 0;
2647 for(repeat_index=0; repeat_index<CSL_SERDES_ATT_BOOST_NUM_REPEAT; repeat_index++)
2648 {
2649 if((att_array[repeat_index][lane_num]>0) &&
2650 (att_array[repeat_index][lane_num]<CSL_SERDES_ATT_BOOST_REPEAT_MEAN))
2651 {
2652 att += att_array[repeat_index][lane_num];
2653 num_att++;
2654 }
2656 if((boost_array[repeat_index][lane_num]>0) &&
2657 (boost_array[repeat_index][lane_num]<CSL_SERDES_ATT_BOOST_REPEAT_MEAN))
2658 {
2659 boost += boost_array[repeat_index][lane_num];
2660 num_boost++;
2661 }
2662 }
2664 final_att[lane_num] = (((float)att)/num_att)+0.5;
2665 final_boost[lane_num] = (((float)boost)/num_boost)+0.5;
2666 }
2667 }
2671 for(lane_num=0; lane_num<CSL_SERDES_MAX_LANES; lane_num++)
2672 {
2673 if ((serdes_lane_enable_params->lane_mask & (1<<lane_num))!=0)
2674 {
2676 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x1fc0 + 0x20 + (lane_num*0x04)),15,15, 0x1);
2677 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x1fc0 + 0x20 + (lane_num*0x04)),14,13, 0x0);
2680 if (serdes_lane_enable_params->phy_type != SERDES_PCIe)
2681 {
2682 if (serdes_lane_enable_params->lane_ctrl_rate[lane_num] == CSL_SERDES_LANE_FULL_RATE)
2683 {
2684 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x84),10,10, 0x0);
2685 }
2686 else if (serdes_lane_enable_params->lane_ctrl_rate[lane_num] == CSL_SERDES_LANE_HALF_RATE)
2687 {
2688 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x84),9,9, 0x0);
2689 }
2690 else if (serdes_lane_enable_params->lane_ctrl_rate[lane_num] == CSL_SERDES_LANE_QUARTER_RATE)
2691 {
2692 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x84),8,8, 0x0);
2693 }
2694 }
2696 if (att!=-1)
2697 {
2699 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x84),0,0, 0x0);
2700 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x8c),24,24, 0x0);
2701 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x200*(lane_num+1) + 0x8c),11,8, final_att[lane_num]);
2702 }
2704 if (boost!=-1)
2705 {
2706 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x84),1,1, 0x0);
2707 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0xa00 + 0x8c),25,25, 0x0);
2708 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x200*(lane_num+1) + 0x8c),15,12, final_boost[lane_num]);
2709 }
2712 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x1fc0 + 0x20 + (lane_num*0x04)),15,15, 0x1);
2713 CSL_FINSR(*(volatile uint32_t *)(serdes_lane_enable_params->base_addr + 0x1fc0 + 0x20 + (lane_num*0x04)),14,13, 0x3);
2715 CSL_Serdes_CycleDelay(100000);
2717 att = boost = CSL_SerdesReadSelectedTbus(serdes_lane_enable_params->base_addr,
2718 lane_num + 1,
2719 (serdes_lane_enable_params->phy_type==SERDES_10GE)?0x10:0x11);
2721 pRxCoeff->rx_att[lane_num] = (att >> 4) & 0x0f;
2722 pRxCoeff->rx_boost[lane_num] = (boost >> 8) & 0x0f;
2723 }
2724 }
2725 }
2727 #endif