ospi: PRSDK-5265: fix issue in INDAC mode with interrupt enabled

Fix the wrong OSPI interrupt number used for A53 core.

Signed-off-by: Hao Zhang <hzhang@ti.com>

diff --git a/soc/am65xx/SPI_soc.c b/soc/am65xx/SPI_soc.c
index e94cfeb93f7547964c53b9af51624823c1b82f34..f7585b565c0eb6fcb65e3ae839832ff4014bcc37 100644 (file)
--- a/soc/am65xx/SPI_soc.c
+++ b/soc/am65xx/SPI_soc.c
@@ -345,7 +345,11 @@ OSPI_v0_HwAttrs ospiInitCfg[CSL_OSPI_PER_CNT + 1U] =
         CSL_MCU_FSS0_DAT_REG1_BASE,
 #endif
         OSPI_MODULE_CLOCK,                 /* Input frequency */
+#if defined (__aarch64__)
+        CSL_GIC0_INTR_MCU_FSS0_BUS_OSPI0_LVL_INTR,
+#else
         CSL_MCU0_INTR_FSS0_OSPI0_LVL_INTR, /* OSPI int number for ARM GIC INTC */
+#endif
         0,                                 /* Event ID not used for ARM INTC */
         OSPI_OPER_MODE_CFG,                /* operMode */
         CSL_OSPI_CS0,                      /* chipSelect */
@@ -375,7 +379,11 @@ OSPI_v0_HwAttrs ospiInitCfg[CSL_OSPI_PER_CNT + 1U] =
         CSL_MCU_FSS0_DAT_REG1_BASE + 0x08000000,
 #endif
         OSPI_MODULE_CLOCK,
+#if defined (__aarch64__)
+        CSL_GIC0_INTR_MCU_FSS0_BUS_OSPI1_LVL_INTR,
+#else
         CSL_MCU0_INTR_FSS0_OSPI1_LVL_INTR,
+#endif
         0,
         OSPI_OPER_MODE_CFG,
         CSL_OSPI_CS0,

diff --git a/test/ospi_flash/src/main_ospi_flash_test.c b/test/ospi_flash/src/main_ospi_flash_test.c
index b14f98f9a67b6ee484b6e27273521b7b198a4431..e4882944508efbf7b108bdd929661e0a5f90842f 100644 (file)
--- a/test/ospi_flash/src/main_ospi_flash_test.c
+++ b/test/ospi_flash/src/main_ospi_flash_test.c
@@ -667,8 +667,9 @@ void OSPI_initConfig(OSPI_Tests *test)
     }
     else
     {
-        /* Indirect access controller mode always uses polling, interrupt is not supported */
+        /* Enable interrupt in INDAC mode */
         ospi_cfg.intrEnable = true;
+
         /* Disable PHY in INDAC mode */
         ospi_cfg.phyEnable = false;
     }