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raw | patch | inline | side by side (parent: f62c41b)
raw | patch | inline | side by side (parent: f62c41b)
author | Sinthu Raja M <x0257345@ti.com> | |
Thu, 2 May 2019 12:09:23 +0000 (17:39 +0530) | ||
committer | Sinthu Raja M <x0257345@ti.com> | |
Thu, 2 May 2019 12:09:23 +0000 (17:39 +0530) |
ISSUE:
Delay happens to set the RX interrupt flag in the controller. Due to
this delay, the data is transmitted before the data is been read.
Fix:
In ISR while loop do RX interrupt handling first and then the TX
interrupt handling and then the error handling.
Increment write count index to trigger a dummy transfer only for
interrupt mode so that the receive interrupt will get triggered for the
last byte of data.
Delay happens to set the RX interrupt flag in the controller. Due to
this delay, the data is transmitted before the data is been read.
Fix:
In ISR while loop do RX interrupt handling first and then the TX
interrupt handling and then the error handling.
Increment write count index to trigger a dummy transfer only for
interrupt mode so that the receive interrupt will get triggered for the
last byte of data.
src/v0/SPI_v0.c | patch | blob | history |
diff --git a/src/v0/SPI_v0.c b/src/v0/SPI_v0.c
index b45e597ce6bf9f9550153fd1eee04ee5f3cd563a..66b2431fe4ebd715f6aacbf53d65099e4f0e3320 100644 (file)
--- a/src/v0/SPI_v0.c
+++ b/src/v0/SPI_v0.c
object->writeBufIdx = (uint8_t*)transaction->txBuf;
object->writeCountIdx = transaction->count;
+ /* Increment the writeCountIdx by one to send a dummy transfer to
+ * trigger a receive interrupt to handle delay between TX and RX
+ * interrupt trigger.
+ */
+ if(object->operMode != SPI_OPER_MODE_POLLING)
+ {
+ object->writeCountIdx += 1;
+ }
+
object->readBufIdx = (uint8_t*)transaction->rxBuf;
object->readCountIdx = transaction->count;
/* Loop till all the pending interrupts are serviced */
while (((intCode & SPI_INT_MASK) != 0) && (loop == true))
{
+ /* RX FIFO is full, empty the FIFO to receive more data if necessary */
+ if (intCode & SPI_INT_RX_FULL) {
+ if (object->readCountIdx)
+ {
+ /* Read from the SPIBUF */
+ if (object->readBufIdx)
+ {
+ object->readBufIdx = (uint8_t *) SPI_receiveData_v0(hwAttrs->baseAddr,
+ object->frameSize,
+ object->readBufIdx);
+ }
+
+ object->readCountIdx--;
+ if (object->readCountIdx == 0)
+ {
+ SPIIntDisable(hwAttrs->baseAddr, SPI_INT_RX_FULL);
+ }
+ }
+
+ SPIIntStatusClear(hwAttrs->baseAddr, SPI_INT_RX_FULL);
+
+ intCode = intCode & ~SPI_INT_RX_FULL;
+ }
+
/*
* Refill the TX FIFO if an TX-empty interrupt has occurred & there is more
* data to transmit.
intCode = intCode & ~SPI_INT_TX_EMPTY;
}
- /* RX FIFO is full, empty the FIFO to receive more data if necessary */
- if (intCode & SPI_INT_RX_FULL) {
- if (object->readCountIdx)
- {
- /* Read from the SPIBUF */
- if (object->readBufIdx)
- {
- object->readBufIdx = (uint8_t *) SPI_receiveData_v0(hwAttrs->baseAddr,
- object->frameSize,
- object->readBufIdx);
- }
-
- object->readCountIdx--;
- if (object->readCountIdx == 0)
- {
- SPIIntDisable(hwAttrs->baseAddr, SPI_INT_RX_FULL);
- }
- }
-
- SPIIntStatusClear(hwAttrs->baseAddr, SPI_INT_RX_FULL);
-
- intCode = intCode & ~SPI_INT_RX_FULL;
- }
-
/* RX overrun, read SPIBUF twice to get to the overrun buffer */
if (intCode & SPI_INT_RX_OVERRUN)
{