ospi: PRSDK-5265: fix issue of OSPI INDAC mode with interrupt enabled

Signed-off-by: Hao Zhang <hzhang@ti.com>

diff --git a/src/v0/OSPI_v0.c b/src/v0/OSPI_v0.c
index 1b441f3b4e6399683c191f0164d0776d7714cfa7..e4ac4f06f16aab7d2a85ea4775bba1381313aaf5 100644 (file)
--- a/src/v0/OSPI_v0.c
+++ b/src/v0/OSPI_v0.c
@@ -214,23 +214,17 @@ static void OSPI_hwiFxn_v0(uintptr_t arg)
         {
             if(object->readCountIdx)
             {
-                if (intrStatus & CSL_OSPI_INTR_MASK_IND_XFER_LVL_BREACH)
+                while ((sramLevel = CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 1U)) != 0)
                 {
-                    sramLevel = CSL_OSPI_SRAM_WARERMARK_RD_LVL;
-                }
-                else
-                {
-                    sramLevel = CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 1U);
-                }
-
-                rdBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
-                rdBytes = rdBytes > object->readCountIdx ? object->readCountIdx : rdBytes;
+                    rdBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
+                    rdBytes = rdBytes > object->readCountIdx ? object->readCountIdx : rdBytes;
 
-                /* Read data from FIFO */
-                CSL_ospiReadFifoData(hwAttrs->dataAddr, object->readBufIdx, rdBytes);
+                    /* Read data from FIFO */
+                    CSL_ospiReadFifoData(hwAttrs->dataAddr, object->readBufIdx, rdBytes);
 
-                object->readBufIdx += rdBytes;
-                object->readCountIdx -= rdBytes;
+                    object->readBufIdx += rdBytes;
+                    object->readCountIdx -= rdBytes;
+                }
 
                 if ((object->readCountIdx > 0) &&
                     (object->readCountIdx < (CSL_OSPI_SRAM_WARERMARK_RD_LVL * CSL_OSPI_FIFO_WIDTH)))
@@ -282,6 +276,7 @@ static void OSPI_hwiFxn_v0(uintptr_t arg)
             {
                 sramLevel = CSL_OSPI_SRAM_PARTITION_WR - \
                             CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 0U);
+
                 wrBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
                 wrBytes = wrBytes > object->writeCountIdx ? object->writeCountIdx : wrBytes;
 
@@ -293,6 +288,7 @@ static void OSPI_hwiFxn_v0(uintptr_t arg)
 
                 sramLevel = CSL_OSPI_SRAM_PARTITION_WR - \
                             CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 0U);
+
                 if ((object->writeCountIdx > 0) &&
                     (object->writeCountIdx <= (sramLevel * CSL_OSPI_FIFO_WIDTH)))
                 {
@@ -303,7 +299,7 @@ static void OSPI_hwiFxn_v0(uintptr_t arg)
                 }
             }
 
-            if(intrStatus & CSL_OSPI_INTR_MASK_IND_OP_DONE)
+            if (intrStatus & CSL_OSPI_INTR_MASK_IND_OP_DONE)
             {
                 /* Clear indirect write operation complete status */
                 CSL_ospiClrIndWriteComplete((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));

diff --git a/test/ospi_flash/src/main_ospi_flash_test.c b/test/ospi_flash/src/main_ospi_flash_test.c
index d11980012f6d28024d7ea04923eac25ef50b28bc..459659a0b46ee8e94e9eb9659ca7de3fdd520f97 100644 (file)
--- a/test/ospi_flash/src/main_ospi_flash_test.c
+++ b/test/ospi_flash/src/main_ospi_flash_test.c
@@ -602,7 +602,7 @@ void OSPI_initConfig(OSPI_Tests *test)
     else
     {
         /* Indirect access controller mode always uses polling, interrupt is not supported */
-        ospi_cfg.intrEnable = false;
+        ospi_cfg.intrEnable = true;
         /* Disable PHY in INDAC mode */
         ospi_cfg.phyEnable = false;
     }