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raw | patch | inline | side by side (parent: eeab171)
raw | patch | inline | side by side (parent: eeab171)
| author | Martin Qian <mackuntu@gmail.com> | |
| Sun, 22 Jul 2012 17:59:21 +0000 (13:59 -0400) | ||
| committer | Martin Qian <mackuntu@gmail.com> | |
| Sun, 22 Jul 2012 17:59:21 +0000 (13:59 -0400) |
15 files changed:
diff --git a/config.bld b/config.bld
index b4694484552b34fc451bc67fc6bcb7392067ca66..3e9b8fe5990eca8fd77e58807841308b90350263 100644 (file)
--- a/config.bld
+++ b/config.bld
/* List all the build targets here. */\r
Build.targets = [ C66LE, C66BE ];\r
\r
-var devices = ["tci6634/c66"];\r
+var devices = ["tci6634/c66","tci6608t/c66"];\r
diff --git a/device/tci6608t/src/device_srio_loopback.c b/device/tci6608t/src/device_srio_loopback.c
--- /dev/null
@@ -0,0 +1,376 @@
+/**\r
+ * @file device_srio_loopback.c\r
+ *\r
+ * @brief \r
+ * The 6616 SRIO Device specific code. The SRIO driver calls out\r
+ * this code to initialize the SRIO IP block. The file is provided as \r
+ * a sample configuration and should be modified by customers for \r
+ * their own platforms and configurations.\r
+ *\r
+ * \par\r
+ * NOTE:\r
+ * (C) Copyright 2011 Texas Instruments, Inc.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \par\r
+ */\r
+\r
+/* SRIO Driver Includes. */\r
+#include <ti/drv/srio/srio_types.h>\r
+#include <ti/drv/srio/include/listlib.h>\r
+#include <ti/drv/srio/srio_drv.h>\r
+\r
+/* CSL SRIO Functional Layer */\r
+#include <ti/csl/csl_srio.h>\r
+#include <ti/csl/csl_srioAux.h>\r
+#include <ti/csl/csl_srioAuxPhyLayer.h>\r
+\r
+/* CSL BootCfg Module */\r
+#include <ti/csl/csl_bootcfg.h>\r
+#include <ti/csl/csl_bootcfgAux.h>\r
+\r
+/* CSL Chip Functional Layer */\r
+#include <ti/csl/csl_chip.h>\r
+\r
+/* CSL PSC Module */\r
+#include <ti/csl/csl_pscAux.h>\r
+\r
+/* QMSS Include */\r
+#include <ti/drv/qmss/qmss_drv.h>\r
+\r
+/**********************************************************************\r
+ ************************* LOCAL Definitions **************************\r
+ **********************************************************************/\r
+\r
+/* These are the GARBAGE queues which are used by the TXU to dump the \r
+ * descriptor if there is an error instead of recycling the descriptor\r
+ * to the free queue. */\r
+#define GARBAGE_LEN_QUEUE 905\r
+#define GARBAGE_TOUT_QUEUE 906\r
+#define GARBAGE_RETRY_QUEUE 907\r
+#define GARBAGE_TRANS_ERR_QUEUE 908\r
+#define GARBAGE_PROG_QUEUE 909\r
+#define GARBAGE_SSIZE_QUEUE 910\r
+\r
+/* SRIO Device Information\r
+ * - 16 bit Device Identifier.\r
+ * - 8 bit Device Identifier.\r
+ * - Vendor Identifier. \r
+ * - Device Revision. */\r
+#define DEVICE_VENDOR_ID 0x30\r
+#define DEVICE_REVISION 0x0\r
+\r
+/* SRIO Assembly Information\r
+ * - Assembly Identifier\r
+ * - Assembly Vendor Identifier. \r
+ * - Assembly Device Revision. \r
+ * - Assembly Extension Features */\r
+#define DEVICE_ASSEMBLY_ID 0x0\r
+#define DEVICE_ASSEMBLY_VENDOR_ID 0x30\r
+#define DEVICE_ASSEMBLY_REVISION 0x0\r
+#define DEVICE_ASSEMBLY_INFO 0x0100\r
+\r
+/**********************************************************************\r
+ ************************* Extern Definitions *************************\r
+ **********************************************************************/\r
+\r
+extern const uint32_t DEVICE_ID1_16BIT;\r
+extern const uint32_t DEVICE_ID1_8BIT;\r
+extern const uint32_t DEVICE_ID2_16BIT;\r
+extern const uint32_t DEVICE_ID2_8BIT;\r
+extern const uint32_t DEVICE_ID3_16BIT;\r
+extern const uint32_t DEVICE_ID3_8BIT_ID;\r
+extern const uint32_t DEVICE_ID4_16BIT;\r
+extern const uint32_t DEVICE_ID4_8BIT_ID;\r
+\r
+/**********************************************************************\r
+ *********************** DEVICE SRIO FUNCTIONS ***********************\r
+ **********************************************************************/\r
+\r
+/** @addtogroup SRIO_DEVICE_API\r
+ @{ */\r
+\r
+/**\r
+ * @b Description\r
+ * @n \r
+ * The function provides the initialization sequence for the SRIO IP\r
+ * block. This can be modified by customers for their application and\r
+ * configuration.\r
+ *\r
+ * @retval\r
+ * Success - 0\r
+ * @retval\r
+ * Error - <0\r
+ */\r
+#pragma CODE_SECTION(SrioDevice_init, ".text:SrioDevice_init");\r
+int32_t SrioDevice_init (void)\r
+{\r
+ CSL_SrioHandle hSrio;\r
+ int32_t i;\r
+ SRIO_PE_FEATURES peFeatures;\r
+ SRIO_OP_CAR opCar;\r
+ Qmss_QueueHnd queueHnd;\r
+ uint8_t isAllocated;\r
+ uint32_t gargbageQueue[] = { GARBAGE_LEN_QUEUE, GARBAGE_TOUT_QUEUE,\r
+ GARBAGE_RETRY_QUEUE,GARBAGE_TRANS_ERR_QUEUE,\r
+ GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE };\r
+\r
+ /* Get the CSL SRIO Handle. */\r
+ hSrio = CSL_SRIO_Open (0);\r
+ if (hSrio == NULL)\r
+ return -1;\r
+ \r
+ /* Code to disable SRIO reset isolation */\r
+ if (CSL_PSC_isModuleResetIsolationEnabled(CSL_PSC_LPSC_SRIO))\r
+ CSL_PSC_disableModuleResetIsolation(CSL_PSC_LPSC_SRIO);\r
+\r
+ /* Disable the SRIO Global block */\r
+ CSL_SRIO_GlobalDisable (hSrio);\r
+ \r
+ /* Disable each of the individual SRIO blocks. */\r
+ for(i = 0; i <= 9; i++)\r
+ CSL_SRIO_DisableBlock(hSrio, i);\r
+\r
+ /* Set boot complete to be 0; we are not done with the initialization. */ \r
+ CSL_SRIO_SetBootComplete(hSrio, 0);\r
+\r
+ /* Now enable the SRIO block and all the individual blocks also. */\r
+ CSL_SRIO_GlobalEnable (hSrio);\r
+ for(i = 0; i <= 9; i++)\r
+ CSL_SRIO_EnableBlock(hSrio,i);\r
+\r
+ /* Configure SRIO ports to operate in loopback mode. */\r
+ CSL_SRIO_SetLoopbackMode(hSrio, 0);\r
+ CSL_SRIO_SetLoopbackMode(hSrio, 1);\r
+ CSL_SRIO_SetLoopbackMode(hSrio, 2);\r
+ CSL_SRIO_SetLoopbackMode(hSrio, 3);\r
+\r
+ /* Enable Automatic Priority Promotion of response packets. */\r
+ CSL_SRIO_EnableAutomaticPriorityPromotion(hSrio);\r
+\r
+ /* Set the SRIO Prescalar select to operate in the range of 44.7 to 89.5 */\r
+ CSL_SRIO_SetPrescalarSelect (hSrio, 0);\r
+\r
+ /* Unlock the Boot Configuration Kicker */\r
+ CSL_BootCfgUnlockKicker ();\r
+\r
+ /* Clear the LSU pending interrupts. */\r
+ CSL_SRIO_ClearLSUPendingInterrupt (hSrio, 0xFFFFFFFF, 0xFFFFFFFF);\r
+\r
+ /* Set the Device Information */\r
+ CSL_SRIO_SetDeviceInfo (hSrio, DEVICE_ID1_16BIT, DEVICE_VENDOR_ID, DEVICE_REVISION);\r
+\r
+ /* Set the Assembly Information */\r
+ CSL_SRIO_SetAssemblyInfo(hSrio, DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID, \r
+ DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);\r
+\r
+ /* TODO: Configure the processing element features\r
+ * The SRIO RL file is missing the Re-transmit Suppression Support (Bit6) field definition */\r
+ peFeatures.isBridge = 0;\r
+ peFeatures.isEndpoint = 0;\r
+ peFeatures.isProcessor = 1;\r
+ peFeatures.isSwitch = 0;\r
+ peFeatures.isMultiport = 0;\r
+ peFeatures.isFlowArbiterationSupported = 0;\r
+ peFeatures.isMulticastSupported = 0;\r
+ peFeatures.isExtendedRouteConfigSupported = 0;\r
+ peFeatures.isStandardRouteConfigSupported = 1;\r
+ peFeatures.isFlowControlSupported = 1;\r
+ peFeatures.isCRFSupported = 0;\r
+ peFeatures.isCTLSSupported = 1;\r
+ peFeatures.isExtendedFeaturePtrValid = 1;\r
+ peFeatures.numAddressBitSupported = 1;\r
+ CSL_SRIO_SetProcessingElementFeatures (hSrio, &peFeatures);\r
+\r
+ /* Configure the source operation CAR */\r
+ memset ((void *) &opCar, 0, sizeof (opCar));\r
+ opCar.portWriteOperationSupport = 1;\r
+ opCar.atomicClearSupport = 1;\r
+ opCar.atomicSetSupport = 1;\r
+ opCar.atomicDecSupport = 1;\r
+ opCar.atomicIncSupport = 1;\r
+ opCar.atomicTestSwapSupport = 1;\r
+ opCar.doorbellSupport = 1;\r
+ opCar.dataMessageSupport = 1;\r
+ opCar.writeResponseSupport = 1;\r
+ opCar.streamWriteSupport = 1;\r
+ opCar.writeSupport = 1;\r
+ opCar.readSupport = 1;\r
+ opCar.dataStreamingSupport = 1;\r
+ CSL_SRIO_SetSourceOperationCAR (hSrio, &opCar);\r
+\r
+ /* Configure the destination operation CAR */\r
+ memset ((void *) &opCar, 0, sizeof (opCar));\r
+ opCar.portWriteOperationSupport = 1;\r
+ opCar.doorbellSupport = 1;\r
+ opCar.dataMessageSupport = 1;\r
+ opCar.writeResponseSupport = 1;\r
+ opCar.streamWriteSupport = 1;\r
+ opCar.writeSupport = 1;\r
+ opCar.readSupport = 1;\r
+ CSL_SRIO_SetDestOperationCAR (hSrio, &opCar);\r
+\r
+ /* Set the 16 bit and 8 bit identifier for the SRIO Device. */\r
+ CSL_SRIO_SetDeviceIDCSR (hSrio, DEVICE_ID1_8BIT, DEVICE_ID1_16BIT);\r
+\r
+ /* Enable TLM Base Routing Information for Maintainance Requests & ensure that\r
+ * the BRR's can be used by all the ports. */\r
+ CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 1, 1, 1, 0);\r
+ CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 2, 1, 1, 0);\r
+ CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 3, 1, 1, 0);\r
+ CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 1, 0, 1, 1, 0);\r
+\r
+ /* Configure the Base Routing Register to ensure that all packets matching the \r
+ * Device Identifier & the Secondary Device Id are admitted. */\r
+ CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 1, DEVICE_ID2_16BIT, 0xFFFF);\r
+ CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 2, DEVICE_ID3_16BIT, 0xFFFF);\r
+ CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 3, DEVICE_ID4_16BIT, 0xFFFF);\r
+ CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 1, 0, DEVICE_ID2_8BIT, 0xFF);\r
+\r
+ /* We need to open the Garbage collection queues in the QMSS. This is done to ensure that \r
+ * these queues are not opened by another system entity. */\r
+ for (i = 0; i < 6; i++)\r
+ {\r
+ /* Open the Garabage queues */\r
+ queueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, gargbageQueue[i], &isAllocated);\r
+ if (queueHnd < 0)\r
+ return -1;\r
+\r
+ /* Make sure the queue has not been opened already; we dont the queues to be shared by some other\r
+ * entity in the system. */\r
+ if (isAllocated > 1)\r
+ return -1;\r
+ }\r
+\r
+ /* Set the Transmit Garbage Collection Information. */\r
+ CSL_SRIO_SetTxGarbageCollectionInfo (hSrio, GARBAGE_LEN_QUEUE, GARBAGE_TOUT_QUEUE, \r
+ GARBAGE_RETRY_QUEUE, GARBAGE_TRANS_ERR_QUEUE, \r
+ GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE);\r
+\r
+ /* Set the Host Device Identifier. */\r
+ CSL_SRIO_SetHostDeviceID (hSrio, DEVICE_ID1_16BIT);\r
+\r
+ /* Configure the component tag CSR */\r
+ CSL_SRIO_SetCompTagCSR (hSrio, 0x00000000);\r
+\r
+ /* Configure the PLM for all the ports. */\r
+ for (i = 0; i < 4; i++)\r
+ {\r
+ /* Set the PLM Port Silence Timer. */ \r
+ CSL_SRIO_SetPLMPortSilenceTimer (hSrio, i, 0x2);\r
+\r
+ /* TODO: We need to ensure that the Port 0 is configured to support both\r
+ * the 2x and 4x modes. The Port Width field is read only. So here we simply\r
+ * ensure that the Input and Output ports are enabled. */\r
+ CSL_SRIO_EnableInputPort (hSrio, i);\r
+ CSL_SRIO_EnableOutputPort (hSrio, i);\r
+\r
+ /* Set the PLM Port Discovery Timer. */\r
+ CSL_SRIO_SetPLMPortDiscoveryTimer (hSrio, i, 0x2);\r
+\r
+ /* Reset the Port Write Reception capture. */\r
+ CSL_SRIO_SetPortWriteReceptionCapture(hSrio, i, 0x0);\r
+ }\r
+\r
+ /* Set the Port link timeout CSR */\r
+ CSL_SRIO_SetPortLinkTimeoutCSR (hSrio, 0x000FFF);\r
+\r
+ /* Set the Port General CSR: Only executing as Master Enable */\r
+ CSL_SRIO_SetPortGeneralCSR (hSrio, 0, 1, 0);\r
+\r
+ /* Clear the sticky register bits. */\r
+ CSL_SRIO_SetLLMResetControl (hSrio, 1);\r
+\r
+ /* Set the device id to be 0 for the Maintenance Port-Write operation \r
+ * to report errors to a system host. */\r
+ CSL_SRIO_SetPortWriteDeviceId (hSrio, 0x0, 0x0, 0x0);\r
+\r
+ /* Set the Data Streaming MTU */\r
+ CSL_SRIO_SetDataStreamingMTU (hSrio, 64);\r
+\r
+ /* Configure the path mode for the ports. */\r
+ for(i = 0; i < 4; i++)\r
+ CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);\r
+\r
+ /* Set the LLM Port IP Prescalar. */\r
+ CSL_SRIO_SetLLMPortIPPrescalar (hSrio, 0x21);\r
+\r
+ /* Enable the peripheral. */\r
+ CSL_SRIO_EnablePeripheral(hSrio);\r
+\r
+ /* Configuration has been completed. */\r
+ CSL_SRIO_SetBootComplete(hSrio, 1);\r
+\r
+#ifndef SIMULATOR_SUPPORT\r
+ /* This code checks if the ports are operational or not. The functionality is not supported \r
+ * on the simulator. */ \r
+ for(i = 0; i < 4; i++)\r
+ while (CSL_SRIO_IsPortOk (hSrio, i) != TRUE);\r
+#endif\r
+\r
+ /* Set all the queues 0 to operate at the same priority level and to send packets onto Port 0 */\r
+ for (i =0 ; i < 16; i++)\r
+ CSL_SRIO_SetTxQueueSchedInfo(hSrio, i, 0, 0);\r
+\r
+ /* Set the Doorbell route to determine which routing table is to be used \r
+ * This configuration implies that the Interrupt Routing Table is configured as \r
+ * follows:-\r
+ * Interrupt Destination 0 - INTDST 16 \r
+ * Interrupt Destination 1 - INTDST 17 \r
+ * Interrupt Destination 2 - INTDST 18\r
+ * Interrupt Destination 3 - INTDST 19 \r
+ */\r
+ CSL_SRIO_SetDoorbellRoute(hSrio, 0);\r
+\r
+ /* Route the Doorbell interrupts. \r
+ * Doorbell Register 0 - All 16 Doorbits are routed to Interrupt Destination 0. \r
+ * Doorbell Register 1 - All 16 Doorbits are routed to Interrupt Destination 1. \r
+ * Doorbell Register 2 - All 16 Doorbits are routed to Interrupt Destination 2. \r
+ * Doorbell Register 3 - All 16 Doorbits are routed to Interrupt Destination 3. */\r
+ for (i = 0; i < 16; i++)\r
+ {\r
+ CSL_SRIO_RouteDoorbellInterrupts(hSrio, 0, i, 0);\r
+ CSL_SRIO_RouteDoorbellInterrupts(hSrio, 1, i, 1);\r
+ CSL_SRIO_RouteDoorbellInterrupts(hSrio, 2, i, 2);\r
+ CSL_SRIO_RouteDoorbellInterrupts(hSrio, 3, i, 3);\r
+ }\r
+\r
+ /* Initialization has been completed. */\r
+ return 0;\r
+}\r
+\r
+/**\r
+@}\r
+*/\r
+\r
+\r
+\r
+\r
+\r
index 5075a2dfc312ef619ba1c9806beadc6c9e606764..970e7496a56a746c4e5053ee6d88cce200ef8a49 100644 (file)
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diff --git a/example/SRIOLoopbackDioIsr/simtci6634/c66/bios/loopbackDioIsr.cfg b/example/SRIOLoopbackDioIsr/simtci6634/c66/bios/loopbackDioIsr.cfg
index d1a2db608c17ce8f0a68c3996db8b27cbb83b1ac..5fdc4d5d7e2026eab3e0f7f357015ca08de26e49 100644 (file)
Startup = xdc.useModule('xdc.runtime.Startup');\r
Startup.firstFxns.$add('&myStartupFxn');\r
\r
-MultiProc.setConfig(null, ["CORE0", "CORE1"]);\r
+MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3"]);\r
\r
/* Synchronize all processors (this will be done in Ipc_start) */\r
Ipc.procSync = Ipc.ProcSync_ALL;\r
diff --git a/example/SRIOLoopbackDioIsr/src/loopbackDioIsr.c b/example/SRIOLoopbackDioIsr/src/loopbackDioIsr.c
index 620fe7a90e2f942749c9f6f431c35b20021aa4d1..93b1050543a34411fc009079820cf390ba97866a 100644 (file)
*\r
* \par\r
* NOTE:\r
- * (C) Copyright 2010-2012 Texas Instruments, Inc.\r
+ * (C) Copyright 2011 Texas Instruments, Inc.\r
* \r
* Redistribution and use in source and binary forms, with or without \r
* modification, are permitted provided that the following conditions \r
#define SRIO_DIO_LSU_ISR_NUM_TRANSFERS 3\r
\r
/* ISR timeout value (in cycles) used in this example */\r
-#define SRIO_DIO_LSU_ISR_TIMEOUT 100000\r
+#define SRIO_DIO_LSU_ISR_TIMEOUT 50000\r
\r
\r
/**********************************************************************\r
\r
/* Shared Memory Variable to ensure synchronizing SRIO initialization\r
* with all the other cores. */\r
-/* Created an array to pad the cache line with SRIO_MAX_CACHE_ALIGN size */\r
#pragma DATA_ALIGN (isSRIOInitialized, 128)\r
#pragma DATA_SECTION (isSRIOInitialized, ".srioSharedMem");\r
-volatile Uint32 isSRIOInitialized[(SRIO_MAX_CACHE_ALIGN / sizeof(Uint32))] = { 0 };\r
+volatile Uint32 isSRIOInitialized = 0;\r
\r
+Srio_DrvHandle hAppManagedSrioDrv;\r
Srio_DrvHandle hDrvManagedSrioDrv;\r
\r
CSL_SrioHandle hSrioCSL;\r
/* OSAL Data Buffer Memory Initialization. */\r
extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize);\r
\r
-/* Enable Time Stamp Counter */\r
-extern void CSL_tscEnable(void);\r
-\r
/**********************************************************************\r
************************ SRIO EXAMPLE FUNCTIONS **********************\r
**********************************************************************/\r
@@ -336,12 +333,11 @@ static Int32 dioSocketsWithISR (Srio_DrvHandle hSrioDrv, uint8_t dio_ftype, uint
{\r
Srio_SockBindAddrInfo bindInfo;\r
Srio_SockAddrInfo to;\r
- uint16_t sockIdx, i;\r
+ uint16_t sockIdx, i, compCode;\r
uint16_t counter, srcDstBufIdx = 0;\r
int32_t eventId, startTime;\r
UInt8 **srcDataBufPtr = NULL, **dstDataBufPtr = NULL;\r
- uint8_t compCode;\r
-\r
+ \r
System_printf ("*************************************************************\n");\r
System_printf ("******* DIO Socket Example with Interrupts (Core %d) ********\n", coreNum);\r
System_printf ("*************************************************************\n");\r
@@ -369,16 +365,16 @@ static Int32 dioSocketsWithISR (Srio_DrvHandle hSrioDrv, uint8_t dio_ftype, uint
CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 2, 0);\r
\r
/* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */\r
- CpIntc_dispatchPlug(CSL_CIC0_SRIO_INTDST0, (CpIntc_FuncPtr)myDioTxCompletionIsr, (UArg)hSrioDrv, TRUE);\r
+ CpIntc_dispatchPlug(CSL_INTC0_INTDST0, (CpIntc_FuncPtr)myDioTxCompletionIsr, (UArg)hSrioDrv, TRUE);\r
\r
/* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */\r
- CpIntc_mapSysIntToHostInt(0, CSL_CIC0_SRIO_INTDST0, 8);\r
+ CpIntc_mapSysIntToHostInt(0, CSL_INTC0_INTDST0, 8);\r
\r
/* Enable the Host Interrupt. */\r
CpIntc_enableHostInt(0, 8);\r
\r
/* Enable the System Interrupt */\r
- CpIntc_enableSysInt(0, CSL_CIC0_SRIO_INTDST0);\r
+ CpIntc_enableSysInt(0, CSL_INTC0_INTDST0);\r
\r
/* Get the event id associated with the host interrupt. */\r
eventId = CpIntc_getEventId(8);\r
@@ -475,7 +471,7 @@ static Int32 dioSocketsWithISR (Srio_DrvHandle hSrioDrv, uint8_t dio_ftype, uint
/* Populate the DIO Address Information where the data is to be sent. */\r
to.dio.rapidIOMSB = 0x0;\r
to.dio.rapidIOLSB = (uint32_t)&dstDataBufPtr[srcDstBufIdx][0];\r
- to.dio.dstID = DEVICE_ID2_16BIT;\r
+ to.dio.dstID = DEVICE_ID4_16BIT;\r
to.dio.ttype = dio_ttype;\r
to.dio.ftype = dio_ftype;\r
\r
@@ -550,6 +546,9 @@ static Int32 dioSocketsWithISR (Srio_DrvHandle hSrioDrv, uint8_t dio_ftype, uint
System_printf ("Debug(Core %d): Transfer Completion without Errors - %d\n", coreNum, srioDioLsuGoodTransfers);\r
System_printf ("Debug(Core %d): Transfer Completion with Errors - %d\n", coreNum, srioDioLsuBadTransfers); \r
\r
+ /* Debug Message: Data was validated */\r
+ System_printf ("Debug(Core %d): DIO Transfer Data Validated for all iterations\n", coreNum);\r
+\r
/* Cleanup the source & destination buffers. */\r
for (srcDstBufIdx = 0; srcDstBufIdx < (SRIO_DIO_LSU_ISR_NUM_SOCKETS * SRIO_DIO_LSU_ISR_NUM_TRANSFERS); srcDstBufIdx++)\r
{\r
@@ -563,15 +562,6 @@ static Int32 dioSocketsWithISR (Srio_DrvHandle hSrioDrv, uint8_t dio_ftype, uint
Srio_sockClose_DIO (srioSocket[sockIdx]);\r
}\r
\r
- if (srioDioLsuBadTransfers > 0)\r
- {\r
- System_printf ("Debug(Core %d): DIO Transfer Data NOT completed successfully !!! \n", coreNum);\r
- return -1;\r
- }\r
-\r
- /* Debug Message: Data was validated */\r
- System_printf ("Debug(Core %d): DIO Transfer Data Validated for all iterations\n", coreNum);\r
-\r
/* Debug Message: Example completed */\r
if ((dio_ftype == Srio_Ftype_WRITE) && (dio_ttype == Srio_Ttype_Write_NWRITE_R))\r
{\r
return 0;\r
}\r
\r
+/**\r
+ * @b Description\r
+ * @n \r
+ * Application Raw Receive Cleanup API.\r
+ *\r
+ * @retval\r
+ * Not Applicable.\r
+ */\r
+static void myAppRawRxFree(Srio_DrvBuffer hDrvBuffer)\r
+{\r
+ Qmss_QueueHnd returnQueueHnd;\r
+\r
+ /* Get the return queue. */\r
+ returnQueueHnd = Qmss_getQueueHandle(Cppi_getReturnQueue(Cppi_DescType_HOST, (Cppi_Desc*)hDrvBuffer));\r
+\r
+ /* Push the descriptor into the return queue. */\r
+ Qmss_queuePushDescSize (returnQueueHnd, (Ptr)hDrvBuffer, sizeof(Cppi_HostDesc));\r
+}\r
+\r
/**\r
* @b Description\r
* @n \r
*/\r
static Void dioExampleTask(UArg arg0, UArg arg1)\r
{\r
+ Qmss_QueueHnd myRxFreeQueueHnd;\r
+ Qmss_QueueHnd myRxCompletionQueueHnd;\r
+ Qmss_QueueHnd tmpQueueHnd;\r
+ UInt32 numAllocated;\r
UInt8 isAllocated;\r
+ Cppi_DescCfg descCfg;\r
+ UInt16 index;\r
+ Cppi_HostDesc* ptrHostDesc;\r
+ UInt8* ptrRxData;\r
+ UInt32 numRxBuffers;\r
+ Srio_DrvConfig appCfg;\r
Srio_DrvConfig drvCfg;\r
+ Qmss_Queue queueInfo;\r
\r
+ /* Initialize the SRIO Driver Configuration. */\r
+ memset ((Void *)&appCfg, 0, sizeof(Srio_DrvConfig));\r
+ \r
/* Initialize the SRIO Driver Configuration. */\r
memset ((Void *)&drvCfg, 0, sizeof(Srio_DrvConfig));\r
\r
return;\r
}\r
\r
+ /********************************************************************************\r
+ * The SRIO Driver Instance is going to be created with the following properties:\r
+ * - Application Managed\r
+ * - Receive Completion Queue is Application specified; which implies that there\r
+ * is no interrupt support. Applications will hence need to poll the queue to\r
+ * check if there is data available or not.\r
+ * - The Receive Free Descriptor Queues along with the Size thresholds are \r
+ * managed and created by the application.\r
+ ********************************************************************************/\r
+ \r
+ /* Create the application receive free queue. */\r
+ myRxFreeQueueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, QMSS_PARAM_NOT_SPECIFIED, \r
+ &isAllocated);\r
+ if (myRxFreeQueueHnd < 0)\r
+ {\r
+ System_printf ("Error: Unable to create application receive queues.\n");\r
+ return;\r
+ }\r
+\r
+ /* Create the application receive completion queue. */\r
+ myRxCompletionQueueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, QMSS_PARAM_NOT_SPECIFIED, \r
+ &isAllocated);\r
+ if (myRxCompletionQueueHnd < 0)\r
+ {\r
+ System_printf ("Error: Unable to create the application receive completion queue.\n");\r
+ return;\r
+ }\r
+\r
+ /* Debug Message: */\r
+ System_printf ("Debug(Core %d): AppConfig RxFreeQueue: 0x%x RxCompletionQueue: 0x%x\n", coreNum, \r
+ myRxFreeQueueHnd, myRxCompletionQueueHnd);\r
+\r
+ /* We are going to be using 4 receive buffers in this example. */\r
+ numRxBuffers = 4;\r
+\r
+ /* Application created queue which stores all the receive buffers. */\r
+ descCfg.memRegion = Qmss_MemRegion_MEMORY_REGION0;\r
+ descCfg.descNum = numRxBuffers;\r
+ descCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;\r
+ descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;\r
+ descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;\r
+ descCfg.descType = Cppi_DescType_HOST;\r
+ descCfg.returnQueue = Qmss_getQueueNumber(myRxFreeQueueHnd);\r
+ descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;\r
+ descCfg.returnPushPolicy = Qmss_Location_HEAD;\r
+ descCfg.cfg.host.returnPolicy = Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET;\r
+ descCfg.cfg.host.psLocation = Cppi_PSLoc_PS_IN_DESC;\r
+ tmpQueueHnd = Cppi_initDescriptor (&descCfg, &numAllocated);\r
+ if (tmpQueueHnd < 0)\r
+ {\r
+ System_printf ("Error: Unable to create application receive queues.\n");\r
+ return;\r
+ }\r
+\r
+ /* Initialize the application receive buffers. */\r
+ for (index = 0; index < descCfg.descNum; index++)\r
+ {\r
+ /* Pop off a descriptor */\r
+ ptrHostDesc = (Cppi_HostDesc *)Qmss_queuePop(tmpQueueHnd);\r
+ if (ptrHostDesc == NULL)\r
+ return;\r
+ \r
+ /* Allocate the receive buffer where the data will be received into by the SRIO CPDMA. */\r
+ ptrRxData = (UInt8*)Osal_srioDataBufferMalloc(SRIO_MAX_MTU);\r
+ if (ptrRxData == NULL)\r
+ return;\r
+\r
+ /* Set the DATA and ORIGNAL DATA in the buffer descriptor. */\r
+ Cppi_setData (Cppi_DescType_HOST, (Cppi_Desc*)ptrHostDesc, (UInt8*)ptrRxData, SRIO_MAX_MTU);\r
+ Cppi_setOriginalBufInfo (Cppi_DescType_HOST, (Cppi_Desc*)ptrHostDesc, (UInt8*)ptrRxData, SRIO_MAX_MTU);\r
+\r
+ /* Add the packet descriptor to the Application Receive Free Queue. */\r
+ Qmss_queuePushDescSize (myRxFreeQueueHnd, (UInt32*)ptrHostDesc, SIZE_HOST_DESC);\r
+ }\r
+\r
+ /* Close the temporary queue. */\r
+ Qmss_queueClose (tmpQueueHnd);\r
+\r
+ /* Setup the SRIO Driver Configuration: This is application managed configuration */\r
+ appCfg.bAppManagedConfig = TRUE;\r
+\r
+ /* Get the queue information about the receive completion queue. */\r
+ queueInfo = Qmss_getQueueNumber(myRxCompletionQueueHnd);\r
+\r
+ /* The application managed configuration is capable of reception. */\r
+ appCfg.u.appManagedCfg.bIsRxFlowCfgValid = 1;\r
+\r
+ /* Configure the Receive Flow */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.flowIdNum = -1;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_dest_qnum = queueInfo.qNum;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_dest_qmgr = queueInfo.qMgr;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_sop_offset = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_ps_location = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_desc_type = 0x1; /* Host Descriptor. */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_error_handling = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_psinfo_present = 0x1; /* PS Information */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_einfo_present = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_dest_tag_lo = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_dest_tag_hi = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_src_tag_lo = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_src_tag_hi = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_dest_tag_lo_sel = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_dest_tag_hi_sel = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_src_tag_lo_sel = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_src_tag_hi_sel = 0x0;\r
+\r
+ /* Disable Receive size thresholds. */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_size_thresh0_en = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_size_thresh1_en = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_size_thresh2_en = 0x0;\r
+\r
+ /* Use the Application Receive Free Queue for picking all descriptors. */\r
+ queueInfo = Qmss_getQueueNumber(myRxFreeQueueHnd);\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq1_qnum = queueInfo.qNum;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq1_qmgr = queueInfo.qMgr;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq2_qnum = 0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq2_qmgr = 0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq3_qnum = 0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq3_qmgr = 0;\r
+\r
+ /* Use the Receive Queue for picking the SOP packet also. */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz0_qnum = queueInfo.qNum;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz0_qmgr = queueInfo.qMgr;\r
+\r
+ /* There are no size thresholds configured. */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_size_thresh0 = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_size_thresh1 = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_size_thresh2 = 0x0;\r
+\r
+ /* The other threshold queues do not need to be configured */\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz1_qnum = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz1_qmgr = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz2_qnum = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz2_qmgr = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz3_qnum = 0x0;\r
+ appCfg.u.appManagedCfg.rxFlowCfg.rx_fdq0_sz3_qmgr = 0x0;\r
+\r
+ /* Polling Mode: So dont program the accumulator. */\r
+ appCfg.u.appManagedCfg.bIsAccumlatorCfgValid = 0;\r
+\r
+ /* Populate the rest of the configuration. */\r
+ appCfg.u.appManagedCfg.rawRxFreeDrvBuffer = myAppRawRxFree;\r
+ \r
+ /* Start the application Managed SRIO Driver. */\r
+ hAppManagedSrioDrv = Srio_start(&appCfg);\r
+ if (hAppManagedSrioDrv == NULL)\r
+ {\r
+ System_printf ("Error(Core %d): Application Managed SRIO Driver failed to start\n", coreNum);\r
+ return;\r
+ }\r
+\r
/********************************************************************************\r
* The SRIO Driver Instance is going to be created with the following properties:\r
* - Driver Managed\r
EventCombiner_dispatchPlug (48, (EventCombiner_FuncPtr)Srio_rxCompletionIsr, (UArg)hDrvManagedSrioDrv, TRUE);\r
EventCombiner_enableEvent(48);\r
\r
- /* Enable Time Stamp Counter */\r
- CSL_tscEnable();\r
-\r
/* Run the loopback data transfers on the system initialization core. */\r
if (coreNum == CORE_SYS_INIT)\r
{\r
+#ifndef SIMULATOR_SUPPORT\r
+ /* DIO is NOT supported on the simulator */\r
+ \r
/* DIO Write Operation */\r
if (dioSocketsWithISR (hDrvManagedSrioDrv, Srio_Ftype_WRITE, Srio_Ttype_Write_NWRITE_R) < 0)\r
{\r
System_printf ("Error: Loopback DIO ISR example for Read operation failed\n");\r
Task_exit();\r
}\r
+#endif\r
}\r
\r
/* Print out the Malloc & Free Counter */\r
* - For the Driver Managed Driver Instance \r
* There will be 'numRxBuffers' + 'numTxBuffers' + 1 (Driver Instance)\r
* Take these into account while checking for memory leaks. */\r
- if (free_counter +\r
+ if ((numRxBuffers + 1) + free_counter + \r
(drvCfg.u.drvManagedCfg.rxCfg.numRxBuffers + drvCfg.u.drvManagedCfg.txCfg.numTxBuffers + 1) != malloc_counter)\r
{\r
System_printf ("Error: Memory Leak Detected\n");\r
System_printf ("Executing the SRIO DIO example on the DEVICE\n");\r
#endif\r
\r
+#ifdef TEST_MULTICORE\r
+ /* Initialize the heap in shared memory. Using IPC module to do that */ \r
+ Ipc_start();\r
+#endif\r
+\r
/* Initialize the system only if the core was configured to do so. */\r
if (coreNum == CORE_SYS_INIT)\r
{\r
\r
/* Write to the SHARED memory location at this point in time. The other cores cannot execute\r
* till the SRIO Driver is up and running. */\r
- isSRIOInitialized[0] = 1;\r
+ isSRIOInitialized = 1;\r
\r
/* The SRIO IP block has been initialized. We need to writeback the cache here because it will\r
* ensure that the rest of the cores which are waiting for SRIO to be initialized would now be\r
* woken up. */\r
- CACHE_wbL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);\r
+ CACHE_wbL1d ((void *) &isSRIOInitialized, 128, CACHE_WAIT);\r
}\r
else\r
{\r
\r
/* All other cores loop around forever till the SRIO is up and running. \r
* We need to invalidate the cache so that we always read this from the memory. */\r
- while (isSRIOInitialized[0] == 0)\r
- CACHE_invL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);\r
+ while (isSRIOInitialized == 0)\r
+ CACHE_invL1d ((void *) &isSRIOInitialized, 128, CACHE_WAIT);\r
\r
/* Start the QMSS. */\r
if (Qmss_start() != QMSS_SOK)\r
diff --git a/example/SRIOMulticoreLoopback/simtci6634/c66/bios/SRIO_MulticoreLpbkSimtci6634C66BiosExampleProject.txt b/example/SRIOMulticoreLoopback/simtci6634/c66/bios/SRIO_MulticoreLpbkSimtci6634C66BiosExampleProject.txt
index eb93f39c629a14eafda4f3002ea72a6eff4fdcc8..2c2e65833c86d9a230093bbcd98c86bb49dd1131 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/tci6634/src/qmss_device.c" \r
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/srio/example/SRIOMulticoreLoopback/simtci6634/c66/bios/multicoreLoopback.cmd" \r
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/srio/example/SRIOMulticoreLoopback/simtci6634/c66/bios/multicoreLoopback.cfg" \r
--ccs.setCompilerOptions "-mv6600 -g --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/srio/example/SRIOMulticoreLoopback/src -I${PDK_INSTALL_PATH}/ti/drv/srio/example/SRIOMulticoreLoopback/simtci6634/c66/bios" -rtsc.enableRtsc \r
+-ccs.setCompilerOptions "-mv6600 -g --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/srio/example/SRIOMulticoreLoopback/src" -rtsc.enableRtsc \r
diff --git a/example/SRIOMulticoreLoopback/src/multicoreLoopback.c b/example/SRIOMulticoreLoopback/src/multicoreLoopback.c
index 38ea4f776f429ddba817cde6d3c199c51cee5b8a..07ae683a022d441e9206c87a7b9793d7c947daa5 100644 (file)
*\r
* \par\r
* NOTE:\r
- * (C) Copyright 2009-2012 Texas Instruments, Inc.\r
+ * (C) Copyright 2009 Texas Instruments, Inc.\r
* \r
* Redistribution and use in source and binary forms, with or without \r
* modification, are permitted provided that the following conditions \r
#include <ti/csl/csl_pscAux.h>\r
#include <ti/csl/csl_semAux.h>\r
\r
-/* Device specific include */\r
-#include "srioPlatCfg.h"\r
-\r
/**********************************************************************\r
************************** LOCAL Definitions *************************\r
**********************************************************************/\r
#define CORE_SYS_INIT 1\r
\r
/* Number of cores for which the test is being executed. */\r
-#define NUM_CORES srio_EXAMPLE_NUM_CORES\r
+#define NUM_CORES 4\r
\r
/* SRIO Application Hardware Semaphore. */\r
#define SRIO_APP_HW_SEM 5\r
* application. */\r
UInt32 coreNum = 0xFFFF;\r
\r
-/* Shared Memory Variable to ensure synchronizing SRIO initialization\r
- * with all the other cores. */\r
-/* Created an array to pad the cache line with SRIO_MAX_CACHE_ALIGN size */\r
#pragma DATA_ALIGN (isSRIOInitialized, 128)\r
#pragma DATA_SECTION (isSRIOInitialized, ".srioSharedMem");\r
-volatile Uint32 isSRIOInitialized[(SRIO_MAX_CACHE_ALIGN / sizeof(Uint32))] = { 0 };\r
+volatile Uint32 isSRIOInitialized = 0;\r
\r
-/* Created an array to pad the cache line with SRIO_MAX_CACHE_ALIGN size */\r
#pragma DATA_ALIGN (isSRIOSocketsCreated, 128)\r
#pragma DATA_SECTION (isSRIOSocketsCreated, ".srioSharedMem");\r
-volatile Uint32 isSRIOSocketsCreated[(SRIO_MAX_CACHE_ALIGN / sizeof(Uint32))] = { 0 };\r
+volatile Uint32 isSRIOSocketsCreated = 0;\r
\r
/* Memory used for the accumulator list. */\r
#pragma DATA_ALIGN (gHiPriAccumList, 16)\r
const uint32_t DEVICE_ID1_8BIT = 0xAB;\r
const uint32_t DEVICE_ID2_16BIT = 0x4560;\r
const uint32_t DEVICE_ID2_8BIT = 0xCD;\r
-#if (NUM_CORES > 2)\r
const uint32_t DEVICE_ID3_16BIT = 0x1234;\r
const uint32_t DEVICE_ID3_8BIT = 0x12;\r
const uint32_t DEVICE_ID4_16BIT = 0x5678;\r
const uint32_t DEVICE_ID4_8BIT = 0x56;\r
-#endif\r
\r
/**********************************************************************\r
************************* Extern Definitions *************************\r
/* Initialize the core Device IDs: Each core has a seperate device ID. */\r
coreDeviceID[0] = DEVICE_ID1_16BIT;\r
coreDeviceID[1] = DEVICE_ID2_16BIT;\r
-#if (NUM_CORES > 2)\r
coreDeviceID[2] = DEVICE_ID3_16BIT;\r
coreDeviceID[3] = DEVICE_ID4_16BIT;\r
-#endif\r
\r
/* Initialize the core bindings; we use the same mailbox & letter identifiers. */\r
bindInfo.type11.tt = TRUE;\r
\r
/* Get a transmit buffer from the SRIO Driver. */\r
hDrvBuffer = Srio_allocTransmitBuffer(hSrioDrv, &txData, &allocatedLen);\r
- if ((hDrvBuffer == NULL) || (txData == NULL))\r
+ if (hDrvBuffer == NULL)\r
{\r
System_printf ("Error: Producer Memory Allocation failed.\n");\r
return -1;\r
while ((CSL_semAcquireDirect (SRIO_APP_HW_SEM)) == 0);\r
\r
/* Invalidate the cache and make sure you get the latest from the memory. */\r
- CACHE_invL1d ((void *) &isSRIOSocketsCreated[0], 128, CACHE_WAIT);\r
+ CACHE_invL1d ((void *) &isSRIOSocketsCreated, 128, CACHE_WAIT);\r
\r
/* The core has created the sockets:*/\r
- isSRIOSocketsCreated[0]++;\r
+ isSRIOSocketsCreated++;\r
\r
/* The SRIO Socket has been created. Writeback the contents to the cache. */\r
- CACHE_wbL1d ((void *) &isSRIOSocketsCreated[0], 128, CACHE_WAIT);\r
+ CACHE_wbL1d ((void *) &isSRIOSocketsCreated, 128, CACHE_WAIT);\r
\r
/* Release the hardware semaphore. */\r
CSL_semReleaseSemaphore (SRIO_APP_HW_SEM);\r
* cores have created and bound their SRIO sockets. This is a simple counter running\r
* in shared memory which allows us to SYNC up the socket creation. Wait till all the\r
* cores have created the sockets */\r
- while (isSRIOSocketsCreated[0] != NUM_CORES)\r
- CACHE_invL1d ((void *) &isSRIOSocketsCreated[0], 128, CACHE_WAIT);\r
+ while (isSRIOSocketsCreated != NUM_CORES)\r
+ CACHE_invL1d ((void *) &isSRIOSocketsCreated, 128, CACHE_WAIT);\r
\r
System_printf ("------------------------------------------------------\n");\r
\r
/* Starting Core: This is a special case because unlike the other cores; this initiates\r
* the whole test cycle by sending the first packet. */\r
sendToCore = coreNum + 1;\r
- if (sendToCore == NUM_CORES)\r
- sendToCore = 0;\r
recvFromCore = coreNum - 1;\r
if (recvFromCore < 0)\r
recvFromCore = NUM_CORES-1;\r
\r
/* Write to the SHARED memory location at this point in time. The other cores cannot execute\r
* till the SRIO Driver is up and running. */\r
- isSRIOInitialized[0] = 1;\r
+ isSRIOInitialized = 1;\r
\r
/* The SRIO IP block has been initialized. We need to writeback the cache here because it will\r
* ensure that the rest of the cores which are waiting for SRIO to be initialized would now be\r
* woken up. */\r
- CACHE_wbL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);\r
+ CACHE_wbL1d ((void *) &isSRIOInitialized, 128, CACHE_WAIT);\r
}\r
else\r
{\r
\r
/* All other cores loop around forever till the SRIO is up and running. \r
* We need to invalidate the cache so that we always read this from the memory. */\r
- while (isSRIOInitialized[0] == 0)\r
- CACHE_invL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);\r
+ while (isSRIOInitialized == 0)\r
+ CACHE_invL1d ((void *) &isSRIOInitialized, 128, CACHE_WAIT);\r
\r
/* Start the QMSS. */\r
if (Qmss_start() != QMSS_SOK)\r
diff --git a/package.xdc b/package.xdc
index 78a1877e5e72f320dfad1b4f43a948746e044696..6368d70f896511189c3c639229339744ac13c1c0 100644 (file)
--- a/package.xdc
+++ b/package.xdc
requires ti.drv.cppi;\r
requires ti.drv.qmss;\r
\r
-package ti.drv.srio[02, 00, 00, 02] {\r
+package ti.drv.srio[02, 00, 00, 01] {\r
module Settings;\r
}\r
\r
diff --git a/src/srio_drv.c b/src/srio_drv.c
index d45770237864ee848dd76d7421c08bba251f1a4b..013b0dc159e9d8f1deae7993ff25963d95ea48c3 100644 (file)
--- a/src/srio_drv.c
+++ b/src/srio_drv.c
*\r
* \par\r
* NOTE:\r
- * (C) Copyright 2009-2012 Texas Instruments, Inc.\r
+ * (C) Copyright 2009 Texas Instruments, Inc.\r
* \r
* Redistribution and use in source and binary forms, with or without \r
* modification, are permitted provided that the following conditions \r
\r
/**\r
* @brief Receive Ping Completion Accumulator List address. \r
- * SRIO driver expects accumulator list will be allocated from local memory \r
- * (un-cached memory) for performance reasons. Using local memory reduces \r
- * the overhead of cache invalidates on every Srio_rxCompletionIsr() call.\r
*/\r
uint32_t rxPingAddress;\r
\r
/**\r
* @brief Receive Pong Completion Accumulator List address. \r
- * SRIO driver expects accumulator list will be allocated from local memory \r
- * (un-cached memory) for performance reasons. Using local memory reduces \r
- * the overhead of cache invalidates on every Srio_rxCompletionIsr() call.\r
*/\r
uint32_t rxPongAddress;\r
\r
@@ -546,11 +540,8 @@ void Srio_processReceivedBD(Srio_DriverInst* ptr_srioDrvInst, Cppi_Desc* ptrDesc
ptr_localAddr11Info = (Srio_Type11AddrInfo *)&ptrSocket->addrInfo;\r
\r
/* YES; match the properties with the local binding. */\r
- if ((ptr_localAddr11Info->id != dstID) || \r
- ((ptr_localAddr11Info->letter != SRIO_TYPE11_HW_ASSIGNED_LETTER_VALUE) && \r
- (ptr_localAddr11Info->letter != letter)) || \r
- ((ptr_localAddr11Info->mbox != SRIO_TYPE11_RX_ACCEPT_ALL_MBOX_VALUE) && \r
- (ptr_localAddr11Info->mbox != mbox)))\r
+ if ((ptr_localAddr11Info->id != dstID) || ((ptr_localAddr11Info->letter != SRIO_TYPE11_HW_ASSIGNED_LETTER_VALUE) && \r
+ (ptr_localAddr11Info->letter != letter)) || (ptr_localAddr11Info->mbox != mbox))\r
{\r
/* No Match has been found; move to the next socket. */\r
criticalSectionInfo = Srio_osalEnterSingleCoreCriticalSection(ptr_srioDrvInst);\r
Cppi_CpDmaInitCfg srioCPDMACfg;\r
uint16_t idx;\r
\r
- /* Check assumption that Srio_DriverMCB is padded to multiple of SRIO_MAX_CACHE_ALIGN */\r
- SRIO_COMPILE_TIME_SIZE_CHECK ((sizeof(Srio_DriverMCB) % SRIO_MAX_CACHE_ALIGN));\r
-\r
/* Invalidate the Cache Contents. */\r
Srio_osalBeginMemAccess(&gSRIODriverMCB, sizeof(gSRIODriverMCB));\r
\r
for (idx = 0; idx < NUM_DIO_SOCKETS; idx++) \r
gSRIODriverMCB.lsuStatus[idx] = 0;\r
\r
- /* Enable all the SRIO Receive Channels */ \r
+#ifdef SIMULATOR_SUPPORT\r
+ /* We need to enable all the SRIO Receive and Transmit Channels in the SRIO Simulator. */ \r
{\r
- uint16_t index;\r
+ uint16_t index = 1;\r
Cppi_RxChInitCfg rxCfg;\r
+ Cppi_TxChInitCfg txCfg;\r
Cppi_ChHnd chHnd;\r
uint8_t isAllocated;\r
-\r
+ \r
+ /* We have already initialized 1 channel; here we do the remaining... */\r
for (index = 0; index < 16; index++)\r
{\r
/* Open the SRIO Receive Channel */\r
Srio_osalLog ("Error: Enabling SRIO Rx Channel %d failed\n", index);\r
return -1;\r
}\r
+\r
+ /* Open the SRIO Transmit Channel */\r
+ txCfg.channelNum = CPPI_PARAM_NOT_SPECIFIED;\r
+ txCfg.priority = 0;\r
+ txCfg.txEnable = Cppi_ChState_CHANNEL_DISABLE;\r
+ txCfg.filterEPIB = 0;\r
+ txCfg.filterPS = 0;\r
+ txCfg.aifMonoMode = 0;\r
+ chHnd = Cppi_txChannelOpen (gSRIODriverMCB.cppiHnd, &txCfg, &isAllocated);\r
+ if (chHnd == NULL)\r
+ {\r
+ Srio_osalLog ("Error: Opening SRIO Tx channel %d failed\n", txCfg.channelNum);\r
+ return -1;\r
+ }\r
+\r
+ /* Enable the channel. */\r
+ if (Cppi_channelEnable (chHnd) < 0)\r
+ {\r
+ Srio_osalLog ("Error: Enabling SRIO Tx Channel %d failed\n", index);\r
+ return -1;\r
+ }\r
}\r
- }\r
+ } \r
+#endif\r
\r
/* Once the SRIO has been initialized we need to writeback the contents of the \r
* SRIO Master Control Block back into the cache. */\r
/* Initialize the PING & PONG Completion Address. */\r
ptr_srioDrvInst->rxPingAddress = ptr_srioDrvInst->cfg.u.drvManagedCfg.rxCfg.accCfg.listAddress;\r
ptr_srioDrvInst->rxPongAddress = ptr_srioDrvInst->rxPingAddress + \r
- ptr_srioDrvInst->cfg.u.drvManagedCfg.rxCfg.accCfg.maxPageEntries * \r
- (sizeof(uint32_t) * (1 << ptr_srioDrvInst->cfg.u.drvManagedCfg.rxCfg.accCfg.listEntrySize));\r
+ ptr_srioDrvInst->cfg.u.drvManagedCfg.rxCfg.accCfg.maxPageEntries*4;\r
\r
/* Accumulator has been programmed */\r
ptr_srioDrvInst->isAccumulatorProgrammed = 1;\r
if (result != QMSS_ACC_SOK)\r
{\r
Srio_osalLog ("Error: Program Accumulator for Rx Queue failed 0x%x\n", result);\r
- return -1;\r
+ return -1;\r
}\r
\r
/* Remember the accumulator channel which is being programmed. */\r
/* Initialize the PING & PONG Completion Address. */\r
ptr_srioDrvInst->rxPingAddress = ptr_srioDrvInst->cfg.u.appManagedCfg.accCfg.listAddress;\r
ptr_srioDrvInst->rxPongAddress = ptr_srioDrvInst->rxPingAddress + \r
- ptr_srioDrvInst->cfg.u.appManagedCfg.accCfg.maxPageEntries * \r
- (sizeof(uint32_t) * (1 << ptr_srioDrvInst->cfg.u.appManagedCfg.accCfg.listEntrySize));\r
+ ptr_srioDrvInst->cfg.u.appManagedCfg.accCfg.maxPageEntries*4;\r
\r
/* Accumulator has been programmed */\r
ptr_srioDrvInst->isAccumulatorProgrammed = 1;\r
/* Invalidate the Cache Contents. */\r
Srio_osalBeginMemAccess(&gSRIODriverMCB, sizeof(gSRIODriverMCB));\r
\r
- /* Enable the SRIO Transmit channel for each driver instance. */\r
+#ifndef SIMULATOR_SUPPORT\r
+ /* On the actual device we enable the SRIO Receive and Transmit channels for each driver\r
+ * instance. */\r
{\r
+ Cppi_RxChInitCfg rxCfg;\r
Cppi_TxChInitCfg txCfg;\r
\r
- /* Open the SRIO Transmit Channel and keep it disabled. */\r
- txCfg.channelNum = CPPI_PARAM_NOT_SPECIFIED;\r
-\r
- if (ptr_srioDrvInst->cfg.bAppManagedConfig == 1)\r
+ /* Open the SRIO Receive Channel and keep it disabled */\r
+ rxCfg.channelNum = CPPI_PARAM_NOT_SPECIFIED;\r
+ rxCfg.rxEnable = Cppi_ChState_CHANNEL_DISABLE;\r
+ ptr_srioDrvInst->rxChHnd = Cppi_rxChannelOpen (gSRIODriverMCB.cppiHnd, &rxCfg, &isAllocated);\r
+ if (ptr_srioDrvInst->rxChHnd == NULL)\r
{\r
- txCfg.priority = ptr_srioDrvInst->cfg.u.appManagedCfg.srioPktDmaTxPrio;\r
- }\r
- else\r
- {\r
- txCfg.priority = 0;\r
+ Srio_osalLog ("Error: Opening SRIO Rx channel %d failed\n", rxCfg.channelNum); \r
+ return NULL;\r
}\r
\r
+ /* Open the SRIO Transmit Channel and keep it disabled. */\r
+ txCfg.channelNum = CPPI_PARAM_NOT_SPECIFIED;\r
+ txCfg.priority = 0;\r
txCfg.txEnable = Cppi_ChState_CHANNEL_DISABLE;\r
txCfg.filterEPIB = 0;\r
txCfg.filterPS = 0;\r
return NULL;\r
}\r
}\r
+#endif\r
\r
/* Open the SRIO Transmit Queue; this should lie within the SRIO queue region. */\r
if (ptr_srioDrvInst->cfg.bAppManagedConfig == 1)\r
/* Configure the Transmit Queue Threshold. */\r
Qmss_setQueueThreshold (ptr_srioDrvInst->txQueue, 1, 1);\r
\r
- /* Enable the Transmit Channel. */\r
+#ifndef SIMULATOR_SUPPORT\r
+ /* Enable the Receive and Transmit Channels. */\r
+ if (Cppi_channelEnable (ptr_srioDrvInst->rxChHnd) < 0)\r
+ {\r
+ Srio_osalLog ("Error: Enabling SRIO Rx Channel failed\n");\r
+ return NULL;\r
+ }\r
if (Cppi_channelEnable (ptr_srioDrvInst->txChHnd) < 0)\r
{\r
Srio_osalLog ("Error: Enabling SRIO Tx Channel failed\n");\r
return NULL;\r
}\r
-\r
+#endif\r
Srio_osalLog ("Debug: SRIO Driver Instance 0x%p has been created\n", ptr_srioDrvInst);\r
\r
/* Return the SRIO Driver Handle. */\r
@@ -2246,14 +2268,7 @@ int32_t Srio_sockBind_TYPE11 (Srio_SockHandle srioSock, Srio_SockBindAddrInfo* p
* packets can come from anywhere. */\r
message.mbx = ptr_addr11Info->mbox;\r
message.ltr = ptr_addr11Info->letter;\r
- if (ptr_addr11Info->mbox == SRIO_TYPE11_RX_ACCEPT_ALL_MBOX_VALUE) \r
- {\r
- message.mbxMask = 0x0; /* ignore Mailbox field in RX */\r
- }\r
- else \r
- {\r
- message.mbxMask = 0x3F;\r
- }\r
+ message.mbxMask = 0x3F;\r
if (ptr_addr11Info->letter == SRIO_TYPE11_HW_ASSIGNED_LETTER_VALUE) \r
{\r
message.ltrMask = 0x0; /* ignore Letter field */\r
}\r
case Srio_Opt_REGISTER_DOORBELL:\r
{\r
- uint16_t doorbellBit;\r
- uint16_t doorbellReg;\r
- uint32_t doorbellInfo;\r
+ uint8_t doorbellBit;\r
+ uint8_t doorbellReg;\r
+ uint16_t doorbellInfo;\r
void* csInfo;\r
\r
#ifdef SRIO_DRV_DEBUG\r
/* Option is valid only for DIO sockets. */\r
if (ptr_srioSocket->type != Srio_SocketType_DIO)\r
break;\r
-#endif\r
- /* This option takes a 'uint32_t' configuration data */\r
- if (optlen != sizeof(uint32_t)) \r
- break;\r
\r
+ /* This option takes a 'uint16_t' configuration data */\r
+ if (optlen != sizeof(uint16_t)) \r
+ break;\r
+#endif\r
/* Get the doorbell information. */\r
- doorbellInfo = *(uint32_t *)optval;\r
+ doorbellInfo = *(uint16_t *)optval;\r
\r
/* Extract the doorbell register and bit information. */\r
doorbellReg = SRIO_GET_DBELL_REG((uint32_t)doorbellInfo);\r
diff --git a/srio_drv.h b/srio_drv.h
index 7039cc5e9ae47edab04c7d52708160dd9bf7da3d..897f54761760e3d32065071c84dffbedcaad0dc0 100644 (file)
--- a/srio_drv.h
+++ b/srio_drv.h
*\r
* \par\r
* NOTE:\r
- * (C) Copyright 2009-2012 Texas Instruments, Inc.\r
+ * (C) Copyright 2009 Texas Instruments, Inc.\r
* \r
* Redistribution and use in source and binary forms, with or without \r
* modification, are permitted provided that the following conditions \r
/** @addtogroup SRIO_LLD_SYMBOL\r
@{ */\r
\r
-/* This macro generates compilier error if postulate is true, so \r
- * allows 0 overhead compile time size check. This "works" when\r
- * the expression contains sizeof() which otherwise doesn't work\r
- * with preprocessor */\r
-#define SRIO_COMPILE_TIME_SIZE_CHECK(postulate) \\r
- do { \\r
- typedef struct { \\r
- uint8_t SrioNegativeSizeIfPostulateTrue[1 - ((int)(postulate))*2]; \\r
- } SrioPostulateCheck_t; \\r
- } \\r
- while (0)\r
-\r
-#define SRIO_MAX_CACHE_ALIGN 128 /* Maximum alignment for cache line size */\r
-\r
/**\r
* @brief This defines the maximum depth of the SRIO socket receive queues.\r
* This is the MAX number of packets which can be enqueued in the SRIO socket\r
*/\r
#define SRIO_TYPE11_HW_ASSIGNED_LETTER_VALUE 4\r
\r
-/**\r
- * @brief This value can be used to accept all mailbox values on receive side. \r
- * Setting a mailbox number to this value will set MBX_MASK to "0x000000" in \r
- * RIO_RXU_MAPxx_L register.\r
- */\r
-#define SRIO_TYPE11_RX_ACCEPT_ALL_MBOX_VALUE 0xFFFF\r
-\r
/**\r
@}\r
*/\r
* @brief Accumulator Configuration is exposed to the application which \r
* allows the application to determine the parameters for programming \r
* the accumulator. \r
- * Note: SRIO driver expects accumulator list (Qmss_AccCmdCfg.listAddress)\r
- * to be allocated from local memory (un-cached memory) for performance \r
- * reasons. Using local memory reduces the overhead of cache invalidates \r
- * on every Srio_rxCompletionIsr() call.\r
*/\r
Qmss_AccCmdCfg accCfg;\r
}Srio_DrvManagedRxCfg;\r
Srio_DrvManagedTxCfg txCfg;\r
}Srio_DrvManagedCfg;\r
\r
-/**\r
- * @brief\r
- * SRIO priority level set in the TCHAN_SCHED_CFG_REGn registers.\r
- *\r
- * @details\r
- * This enumeration provides the SRIO PKTDMA TX DMA channels priority.\r
- * The value is encoded as follows: \r
- * 0 = HIGH PRIORITY, 1 = MEDIUM-HIGH PRIORITY,\r
- * 2 = MEDIUM-LOW PRIO, 3 = LOW PRIORITY\r
- *\r
- * The priority order from the CDMA is in the reverse order from \r
- * the SRIO. Thus, "0" maps to "3", "1" to "2", "2" to "1" and "3"\r
- * to "0". The inversed priority level (3 --> 0, 2 --> 1 etc.) is \r
- * copied to the TX_QUEUE_SCH_INFOx register and used by the SRIO \r
- * IP when forming SRIO headers.\r
- */\r
-typedef enum\r
-{\r
- /*\r
- * @brief 0 = High Priority\r
- */\r
- Srio_PktDma_Prio_High = 0,\r
-\r
- /*\r
- * @brief 1 = Medium-High Priority\r
- */\r
- Srio_PktDma_Prio_MediumHigh,\r
-\r
- /*\r
- * @brief 2 = Medium-Low Priority\r
- */\r
- Srio_PktDma_Prio_MediumLow,\r
-\r
- /*\r
- * @brief 3 = Low Priority\r
- */\r
- Srio_PktDma_Prio_Low\r
-}Srio_PktDma_Prio;\r
-\r
/** \r
* @brief\r
* The structure describes the application managed configuration\r
* which don't need invalidation.\r
*/\r
int32_t rxDescSize;\r
-\r
- /**\r
- * @brief\r
- * SRIO priority level set in the TCHAN_SCHED_CFG_REGn registers.\r
- * This value provides the SRIO PKTDMA TX DMA channels priority.\r
- * The value is encoded as follows: \r
- * 0 = HIGH PRIORITY, 1 = MEDIUM-HIGH PRIORITY,\r
- * 2 = MEDIUM-LOW PRIO, 3 = LOW PRIORITY\r
- *\r
- * The priority order from the CDMA is in the reverse order from \r
- * the SRIO. Thus, "0" maps to "3", "1" to "2", "2" to "1" and "3"\r
- * to "0". The inversed priority level (3 --> 0, 2 --> 1 etc.) is \r
- * copied to the TX_QUEUE_SCH_INFOx register and used by the SRIO \r
- * IP when forming SRIO headers.\r
- */\r
- Srio_PktDma_Prio srioPktDmaTxPrio;\r
-\r
}Srio_AppManagedCfg;\r
\r
/**\r
diff --git a/test/Loopback/simtci6634/c66/bios/SRIO_LoopbackSimtci6634C66BiosTestProject.txt b/test/Loopback/simtci6634/c66/bios/SRIO_LoopbackSimtci6634C66BiosTestProject.txt
index c58ce316ed0d26d9f1fc5922cd51daf16cbce067..d68918146b4a6299471035ea2d27267a631eaf38 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/srio/test/Loopback/simtci6634/c66/bios/test_osal.c" \r
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/srio/src/listlib.c"\r
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/srio/src/srio_drv.c"\r
--ccs.setCompilerOptions "-DTEST_MULTICORE -mv6600 -g --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/srio/test/Loopback/src -I${PDK_INSTALL_PATH}/ti/drv/srio/include -I${PDK_INSTALL_PATH}/ti/drv/srio/test/Loopback/simtci6634/c66/bios" -rtsc.enableRtsc \r
+-ccs.setCompilerOptions "-DTEST_MULTICORE -mv6600 -g --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/srio/test/Loopback/src -I${PDK_INSTALL_PATH}/ti/drv/srio/include" -rtsc.enableRtsc \r
index 5a5c216ac9074c84a04dab64a9eca14ad315e373..5083d6ea275fa3c9aaf0e76dd7b90c6d5c62d264 100644 (file)
\r
/* Shared Memory Variable to ensure synchronizing SRIO initialization\r
* with all the other cores. */\r
-/* Created an array to pad the cache line with SRIO_MAX_CACHE_ALIGN size */\r
#pragma DATA_ALIGN (isSRIOInitialized, 128)\r
#pragma DATA_SECTION (isSRIOInitialized, ".srioSharedMem");\r
-volatile Uint32 isSRIOInitialized[(SRIO_MAX_CACHE_ALIGN / sizeof(Uint32))] = { 0 };\r
+volatile Uint32 isSRIOInitialized = 0;\r
\r
Srio_DrvHandle hAppManagedSrioDrv;\r
Srio_DrvHandle hAppManagedSrioDrv1;\r
appCfg.u.appManagedCfg.rawRxFreeDrvBuffer = myAppRawRxFree;\r
appCfg.u.appManagedCfg.txQueueNum = QMSS_PARAM_NOT_SPECIFIED;\r
\r
- /* Set the PKTDMA TX channel priority to low */\r
- appCfg.u.appManagedCfg.srioPktDmaTxPrio = Srio_PktDma_Prio_Low;\r
-\r
/* Start the application Managed SRIO Driver. */\r
hAppManagedSrioDrv = Srio_start(&appCfg);\r
if (hAppManagedSrioDrv == NULL)\r
\r
/* Write to the SHARED memory location at this point in time. The other cores cannot execute\r
* till the SRIO Driver is up and running. */\r
- isSRIOInitialized[0] = 1;\r
+ isSRIOInitialized = 1;\r
\r
/* The SRIO IP block has been initialized. We need to writeback the cache here because it will\r
* ensure that the rest of the cores which are waiting for SRIO to be initialized would now be\r
* woken up. */\r
- CACHE_wbL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);\r
+ CACHE_wbL1d ((void *) &isSRIOInitialized, 128, CACHE_WAIT);\r
}\r
else\r
{\r
\r
/* All other cores loop around forever till the SRIO is up and running. \r
* We need to invalidate the cache so that we always read this from the memory. */\r
- while (isSRIOInitialized[0] == 0)\r
- CACHE_invL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);\r
+ while (isSRIOInitialized == 0)\r
+ CACHE_invL1d ((void *) &isSRIOInitialized, 128, CACHE_WAIT);\r
\r
/* Start the QMSS. */\r
if (Qmss_start() != QMSS_SOK)\r
index 929c7d1bbc9cdd78d19d2e2cc8135fb144a86ab5..3d3130ec1a2ae5aa5d3655c785873fc1f2459bf0 100644 (file)
*\r
* \par\r
* NOTE:\r
- * (C) Copyright 2009-2012 Texas Instruments, Inc.\r
+ * (C) Copyright 2009 Texas Instruments, Inc.\r
* \r
* Redistribution and use in source and binary forms, with or without \r
* modification, are permitted provided that the following conditions \r
#include <ti/csl/csl_cacheAux.h>\r
#include <ti/csl/csl_semAux.h>\r
\r
-/* Device specific include */\r
-#include "srioPlatCfg.h"\r
-\r
/**********************************************************************\r
************************** LOCAL Definitions *************************\r
**********************************************************************/\r
\r
/* Number of cores for which the test is being executed. */\r
-#define NUM_CORES srio_EXAMPLE_NUM_CORES\r
+#define NUM_CORES 4\r
\r
/* SRIO Application Hardware Semaphore. */\r
#define SRIO_APP_HW_SEM 6\r
extern uint32_t DEVICE_ID1_8BIT;\r
extern uint32_t DEVICE_ID2_16BIT;\r
extern uint32_t DEVICE_ID2_8BIT;\r
-#if (NUM_CORES > 2)\r
extern uint32_t DEVICE_ID3_16BIT;\r
extern uint32_t DEVICE_ID3_8BIT_ID;\r
extern uint32_t DEVICE_ID4_16BIT;\r
extern uint32_t DEVICE_ID4_8BIT_ID;\r
-#endif\r
\r
-/* Created an array to pad the cache line with SRIO_MAX_CACHE_ALIGN size */\r
#pragma DATA_ALIGN (isSRIOSocketsCreated, 128)\r
#pragma DATA_SECTION (isSRIOSocketsCreated, ".srioSharedMem");\r
-volatile Uint32 isSRIOSocketsCreated[(SRIO_MAX_CACHE_ALIGN / sizeof(Uint32))] = { 0 };\r
+volatile Uint32 isSRIOSocketsCreated = 0;\r
\r
/**********************************************************************\r
********************** NON Blocking API Functions ********************\r
/* Initialize the core Device IDs: Each core has a seperate device ID. */\r
coreDeviceID[0] = DEVICE_ID1_16BIT;\r
coreDeviceID[1] = DEVICE_ID2_16BIT;\r
-#if (NUM_CORES > 2)\r
coreDeviceID[2] = DEVICE_ID3_16BIT;\r
coreDeviceID[3] = DEVICE_ID4_16BIT;\r
-#endif\r
\r
/* Initialize the core bindings; we use the same mailbox & letter identifiers. */\r
bindInfo.type11.tt = TRUE;\r
while ((CSL_semAcquireDirect (SRIO_APP_HW_SEM)) == 0); \r
\r
/* Invalidate the cache and make sure you get the latest from the memory. */\r
- CACHE_invL1d ((void *) &isSRIOSocketsCreated[0], 128, CACHE_WAIT);\r
+ CACHE_invL1d ((void *) &isSRIOSocketsCreated, 128, CACHE_WAIT);\r
\r
/* The core has created the sockets:*/\r
- isSRIOSocketsCreated[0]++;\r
+ isSRIOSocketsCreated++;\r
\r
/* The SRIO Socket has been created. Writeback the contents to the cache. */\r
- CACHE_wbL1d ((void *) &isSRIOSocketsCreated[0], 128, CACHE_WAIT);\r
+ CACHE_wbL1d ((void *) &isSRIOSocketsCreated, 128, CACHE_WAIT);\r
\r
/* Release the hardware semaphore. */\r
CSL_semReleaseSemaphore (SRIO_APP_HW_SEM);\r
* cores have created and bound their SRIO sockets. This is a simple counter running\r
* in shared memory which allows us to SYNC up the socket creation. Wait till all the\r
* cores have created the sockets */\r
- while (isSRIOSocketsCreated[0] != NUM_CORES)\r
- CACHE_invL1d ((void *) &isSRIOSocketsCreated[0], 128, CACHE_WAIT);\r
+ while (isSRIOSocketsCreated != NUM_CORES)\r
+ CACHE_invL1d ((void *) &isSRIOSocketsCreated, 128, CACHE_WAIT);\r
\r
System_printf ("------------------------------------------------------\n");\r
\r
/* Starting Core: This is a special case because unlike the other cores; this initiates\r
* the whole test cycle by sending the first packet. */\r
sendToCore = coreNum + 1;\r
- if (sendToCore == NUM_CORES)\r
- sendToCore = 0;\r
recvFromCore = coreNum - 1;\r
if (recvFromCore < 0)\r
recvFromCore = NUM_CORES-1;\r
diff --git a/test/Module.xs b/test/Module.xs
index 103375ee662952028475324f07bfe8d351079537..cf91f2053ac7ff5ae979c8a69bead78da26bd7de 100644 (file)
--- a/test/Module.xs
+++ b/test/Module.xs
* DESCRIPTION: \r
* This file contains the module specification for SRIO Driver Test\r
*\r
- * Copyright (C) 2009-2012, Texas Instruments, Inc.\r
+ * Copyright (C) 2009, Texas Instruments, Inc.\r
*****************************************************************************/\r
\r
/* Load the library utility. */\r
var testFiles = libUtility.listAllFiles (".txt", "test");\r
for (var k = 0 ; k < testFiles.length; k++)\r
Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
-\r
- /* Add all the docs to the package */\r
- var testFiles = libUtility.listAllFiles (".doc", "test");\r
- for (var k = 0 ; k < testFiles.length; k++)\r
- Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
-\r
- /* Add all JScript files to the package */\r
- var testFiles = libUtility.listAllFiles (".js", "test");\r
- for (var k = 0 ; k < testFiles.length; k++)\r
- Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
}\r
\r