1 /*\r
2 *\r
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ \r
4 * \r
5 * \r
6 * Redistribution and use in source and binary forms, with or without \r
7 * modification, are permitted provided that the following conditions \r
8 * are met:\r
9 *\r
10 * Redistributions of source code must retain the above copyright \r
11 * notice, this list of conditions and the following disclaimer.\r
12 *\r
13 * Redistributions in binary form must reproduce the above copyright\r
14 * notice, this list of conditions and the following disclaimer in the \r
15 * documentation and/or other materials provided with the \r
16 * distribution.\r
17 *\r
18 * Neither the name of Texas Instruments Incorporated nor the names of\r
19 * its contributors may be used to endorse or promote products derived\r
20 * from this software without specific prior written permission.\r
21 *\r
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
33 *\r
34 */\r
35 \r
36 \r
37 \r
38 /* \r
39 * Copyright (c) 2009\r
40 * Texas Instruments\r
41 *\r
42 * All rights reserved. Property of Texas Instruments\r
43 * Restricted rights to use, duplicate or disclose this code are\r
44 * granted through contract.\r
45 * \r
46 * */\r
47 /*\r
48 * ======== CpIntc.c ========\r
49 */\r
50 \r
51 #include <xdc/std.h>\r
52 #include <xdc/runtime/Error.h>\r
53 #include <xdc/runtime/Startup.h>\r
54 #include <xdc/runtime/System.h>\r
55 \r
56 #include "ti/sysbios/family/c66/tci66xx/package/internal/CpIntc.xdc.h"\r
57 \r
58 /*\r
59 * ======== CpIntc_dispatch ========\r
60 */\r
61 //UInt32 cpintcCntr = 0;\r
62 //UInt32 cpintcCntr1 = 0;\r
63 //UInt32 cpintcCntr2 = 0;\r
64 //UInt32 sysIntTrack[200];\r
65 Void CpIntc_dispatchLoc(UInt hostInt)\r
66 {\r
67 Int32 i;\r
68 UInt32 index;\r
69 UInt32 offset;\r
70 UInt32 srsrVal;\r
71 Int32 sysInt;\r
72 UInt32 id = 0;\r
73 extern volatile cregister UInt32 DNUM;\r
74 \r
75 // cpintcCntr++;\r
76 \r
77 /* for core# 4-7 use INTC1 otherwise use INTC0 */\r
78 if (DNUM > 3) {\r
79 id = 1;\r
80 }\r
81 \r
82 // if ( (*((UInt32*)0x0180000C)) == 0x1 )\r
83 // System_printf("MISS detected\n");\r
84 \r
85 sysInt = CpIntc_module->hostIntToSysInt[hostInt];\r
86 \r
87 // sysIntTrack[cpintcCntr]=((hostInt<<16)|sysInt);\r
88 // sysIntTrack[0]=((hostInt<<16)|sysInt);\r
89 \r
90 /* \r
91 * If only one system interrupt is mapped to a host interrupt\r
92 * we don't need to read the Sys Status Raw Registers. We\r
93 * know exactly which system interrupt triggered the interrupt.\r
94 */ \r
95 if (sysInt != 0xff && sysInt != 0xfe) {\r
96 // cpintcCntr1++;\r
97 /* clear system interrupt associated with host interrupt */\r
98 CpIntc_clearSysInt(id, sysInt);\r
99 \r
100 /* call function with arg */\r
101 CpIntc_module->dispatchTab[sysInt].fxn(\r
102 CpIntc_module->dispatchTab[sysInt].arg);\r
103 }\r
104 else {\r
105 // cpintcCntr2++;\r
106 /*\r
107 * Loop through System Interrupt Status Enabled/Clear Registers for\r
108 * pending enabled interrupts. The highest numbered system interrupt\r
109 * will be processed first from left to right.\r
110 */\r
111 for (i = CpIntc_numStatusRegs - 1; i >= 0; i--) {\r
112 offset = i << 5;\r
113 \r
114 /*\r
115 * SDOCM00062100 - Nyquist CpIntc_dispatch needs to read the\r
116 * correct status pending and enabled register once the\r
117 * Simulator is fixed.\r
118 * Fix is:\r
119 * srsrVal = CpIntc_module->controller[id]->SECR[j - i];\r
120 */\r
121 srsrVal = CpIntc_module->controller[id]->SRSR[i] &\r
122 CpIntc_module->controller[id]->ESR[i];\r
123 \r
124 /* Find pending interrupts from left to right */\r
125 while (srsrVal) {\r
126 index = 31 - _lmbd(1, srsrVal);\r
127 srsrVal &= ~(1 << index);\r
128 \r
129 /* Make sure pending interrupt is mapped to host interrupt */\r
130 if (CpIntc_module->controller[id]->CMR[offset + index]\r
131 == hostInt) {\r
132 /* clear system interrupt first */\r
133 CpIntc_clearSysInt(id, offset + index);\r
134 \r
135 /* call function with arg */\r
136 CpIntc_module->dispatchTab[offset + index].fxn(\r
137 CpIntc_module->dispatchTab[offset + index].arg);\r
138 } \r
139 }\r
140 }\r
141 }\r
142 }\r
143 \r
144 \r