1 /**\r
2 * \file tcp3d_reg.c\r
3 *\r
4 * \brief TCP3D Driver functions for TCP3D register preparation functions.\r
5 *\r
6 * Copyright (C) Texas Instruments Incorporated 2009\r
7 * \r
8 * Redistribution and use in source and binary forms, with or without \r
9 * modification, are permitted provided that the following conditions \r
10 * are met:\r
11 *\r
12 * Redistributions of source code must retain the above copyright \r
13 * notice, this list of conditions and the following disclaimer.\r
14 *\r
15 * Redistributions in binary form must reproduce the above copyright\r
16 * notice, this list of conditions and the following disclaimer in the \r
17 * documentation and/or other materials provided with the \r
18 * distribution.\r
19 *\r
20 * Neither the name of Texas Instruments Incorporated nor the names of\r
21 * its contributors may be used to endorse or promote products derived\r
22 * from this software without specific prior written permission.\r
23 *\r
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
35 *\r
36 */\r
37 \r
38 /**\r
39 * Include Files\r
40 */\r
41 #include <ti/drv/tcp3d/tcp3d_drv.h>\r
42 \r
43 /**\r
44 * \brief TCP3D Driver function for preparing the common control registers\r
45 * from the input structure parameters using the CSL_FINS macro.\r
46 * \r
47 * The outputs could be used to write into the actual TCP3 decoder\r
48 * memory registers directly or DMAed to bring the TCP3 decoder\r
49 * state machine to WAIT for inputs state.\r
50 * \r
51 */\r
52 void Tcp3d_prepControlRegs( IN Tcp3d_CtrlParams *ctrl,\r
53 OUT uint32_t *modeReg,\r
54 OUT uint32_t *endReg,\r
55 OUT uint32_t *exeRegP0,\r
56 OUT uint32_t *exeRegP1)\r
57 {\r
58 /* Set MODE register parameters */\r
59 CSL_FINS (*modeReg, TCP3D_CFG_TCP3_MODE_MODE_SEL, ctrl->mode);\r
60 CSL_FINS (*modeReg, TCP3D_CFG_TCP3_MODE_IN_MEM_DB_EN, ctrl->doubleBuf);\r
61 CSL_FINS (*modeReg, TCP3D_CFG_TCP3_MODE_ITG_EN, ctrl->intTable);\r
62 CSL_FINS (*modeReg, TCP3D_CFG_TCP3_MODE_ERROR_IGNORE_EN, ctrl->errIgnore);\r
63 CSL_FINS (*modeReg, TCP3D_CFG_TCP3_MODE_AUTO_TRIG_EN, ctrl->autoTrig);\r
64 CSL_FINS (*modeReg, TCP3D_CFG_TCP3_MODE_LTE_CRC_ISEL, ctrl->lteCrcSel);\r
65 \r
66 /* Set ENDIAN register parameters */\r
67 CSL_FINS (*endReg, TCP3D_CFG_TCP3_END_ENDIAN_INTR, ctrl->endInt);\r
68 CSL_FINS (*endReg, TCP3D_CFG_TCP3_END_ENDIAN_INDATA, ctrl->endInData);\r
69 \r
70 /* Set EXECUTE P0 register parameters */\r
71 CSL_FINS (*exeRegP0, TCP3D_CFG_TCP3_EXE_P0_EXE_CMD, ctrl->exeP0cmd);\r
72 \r
73 /* Set EXECUTE P1 register parameters */\r
74 CSL_FINS (*exeRegP1, TCP3D_CFG_TCP3_EXE_P1_EXE_CMD, ctrl->exeP1cmd);\r
75 \r
76 } /* end of Tcp3d_prepControlRegs() */\r
77 \r
78 /**\r
79 * \brief This is a utility function provided as part of TCP3D Driver for\r
80 * preparing a fixed set of input config registers that would be\r
81 * fixed for a typical configuration and will not vary from \r
82 * code block to code block.\r
83 * \r
84 * This function is used for preparing IC2, IC3, IC8-IC11 registers\r
85 * only out of 15 registers (IC0-IC14) using CSL_FINS macro.\r
86 * \r
87 * The output outICRegs could be used as template IC registers\r
88 * array when preparing the input config registers for code blocks.\r
89 * \r
90 */\r
91 void Tcp3d_prepFixedConfigRegs(IN Tcp3d_InCfgParams * const RESTRICT param,\r
92 OUT uint32_t * const RESTRICT outICRegs)\r
93 {\r
94 uint32_t *reg;\r
95 \r
96 /* Prepare input config register 2 */\r
97 reg = &outICRegs[2];\r
98 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_INTER_LOAD_SEL, param->intLoadSel);\r
99 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_MAXST_EN, param->maxStar);\r
100 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_FLAG_EN, param->outStsRead);\r
101 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_ORDER_SEL, param->outOrderSel);\r
102 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_EXT_SCALE_EN, param->extScale);\r
103 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_FLAG_EN, param->softOutRead);\r
104 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_ORDER_SEL, param->softOutOrderSel);\r
105 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_FMT, param->softOutFrmtSel);\r
106 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_MIN_ITR, param->minIter);\r
107 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_MAX_ITR, param->maxIter);\r
108 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SNR_VAL, param->snrVal);\r
109 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SNR_REP, param->snrReport);\r
110 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_STOP_SEL, param->stopSel);\r
111 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_ITER_PASS, param->crcIterSel);\r
112 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_SEL, param->crcPolySel);\r
113 \r
114 /* Prepare input config register 3 */\r
115 reg = &outICRegs[3];\r
116 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG3_P0_MAXST_THOLD, param->maxStarThres);\r
117 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG3_P0_MAXST_VALUE, param->maxStarValue);\r
118 \r
119 /* Prepare input config register 8 */\r
120 reg = &outICRegs[8];\r
121 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_0, param->extrScale[0]);\r
122 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_1, param->extrScale[1]);\r
123 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_2, param->extrScale[2]);\r
124 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_3, param->extrScale[3]);\r
125 \r
126 /* Prepare input config register 9 */\r
127 reg = &outICRegs[9];\r
128 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_4, param->extrScale[4]);\r
129 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_5, param->extrScale[5]);\r
130 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_6, param->extrScale[6]);\r
131 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_7, param->extrScale[7]);\r
132 \r
133 /* Prepare input config register 10 */\r
134 reg = &outICRegs[10];\r
135 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_8, param->extrScale[8]);\r
136 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_9, param->extrScale[9]);\r
137 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_10, param->extrScale[10]);\r
138 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_11, param->extrScale[11]);\r
139 \r
140 /* Prepare input config register 11 */\r
141 reg = &outICRegs[11];\r
142 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_12, param->extrScale[12]);\r
143 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_13, param->extrScale[13]);\r
144 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_14, param->extrScale[14]);\r
145 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_15, param->extrScale[15]);\r
146 \r
147 } /* end of Tcp3d_prepFixedConfigRegs() */\r
148 \r
149 /**\r
150 * \brief This is a utility function provided as part of TCP3D Driver for\r
151 * preparing the input config registers that will be used for\r
152 * sending to TCP3 decoder IP memory before sending the LLR data.\r
153 * \r
154 * This function is used for preparing all the 15 input config\r
155 * registers (IC0-IC14) using CSL_FINS macro.\r
156 *\r
157 */\r
158 void Tcp3d_prepConfigRegs( IN uint8_t mode,\r
159 IN Tcp3d_InCfgParams* const RESTRICT param,\r
160 OUT uint32_t * const RESTRICT outICRegs,\r
161 IN uint32_t * const RESTRICT tempICRegs,\r
162 IN uint8_t copyFixedReg)\r
163 {\r
164 uint32_t *reg;\r
165 \r
166 /* Prepare input config register 0 */\r
167 reg = &outICRegs[0];\r
168 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG0_P0_NUM_SW0, param->numsw0);\r
169 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG0_P0_BLK_LN, param->blockLen);\r
170 \r
171 /* Prepare input config register 1 */\r
172 reg = &outICRegs[1];\r
173 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW0_LN_SEL, param->sw0LenSel);\r
174 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW2_LN_SEL, param->sw2LenSel);\r
175 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW1_LN, param->sw1Len);\r
176 \r
177 /* Prepare input config register - 2,3,8-11 */\r
178 if (copyFixedReg)\r
179 {\r
180 /* Copy fixed registers from template IC */\r
181 outICRegs[2] = tempICRegs[2];\r
182 outICRegs[3] = tempICRegs[3];\r
183 outICRegs[8] = tempICRegs[8];\r
184 outICRegs[9] = tempICRegs[9];\r
185 outICRegs[10] = tempICRegs[10];\r
186 outICRegs[11] = tempICRegs[11];\r
187 }\r
188 else\r
189 {\r
190 /* Prepare fixed registers from inCfgParams */\r
191 Tcp3d_prepFixedConfigRegs ( param, outICRegs );\r
192 }\r
193 \r
194 /* Prepare input config register 4 */\r
195 reg = &outICRegs[4];\r
196 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST0_MAP0, param->betaMap0[0]);\r
197 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST1_MAP0, param->betaMap0[1]);\r
198 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST2_MAP0, param->betaMap0[2]);\r
199 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST3_MAP0, param->betaMap0[3]);\r
200 \r
201 /* Prepare input config register 5 */\r
202 reg = &outICRegs[5];\r
203 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST4_MAP0, param->betaMap0[4]);\r
204 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST5_MAP0, param->betaMap0[5]);\r
205 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST6_MAP0, param->betaMap0[6]);\r
206 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST7_MAP0, param->betaMap0[7]);\r
207 \r
208 /* Prepare input config register 6 */\r
209 reg = &outICRegs[6];\r
210 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST0_MAP1, param->betaMap1[0]);\r
211 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST1_MAP1, param->betaMap1[1]);\r
212 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST2_MAP1, param->betaMap1[2]);\r
213 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST3_MAP1, param->betaMap1[3]);\r
214 \r
215 /* Prepare input config register 7 */\r
216 reg = &outICRegs[7];\r
217 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST4_MAP1, param->betaMap1[4]);\r
218 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST5_MAP1, param->betaMap1[5]);\r
219 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST6_MAP1, param->betaMap1[6]);\r
220 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST7_MAP1, param->betaMap1[7]);\r
221 \r
222 /* LTE or WIMAX */\r
223 if ( ( mode == CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_LTE ) ||\r
224 ( mode == CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_WIMAX ) )\r
225 {\r
226 /* Prepare input config register 12 */\r
227 reg = &outICRegs[12];\r
228 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM0, param->itgParam[0]);\r
229 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM1, param->itgParam[1]);\r
230 \r
231 /* Prepare input config register 13 */\r
232 reg = &outICRegs[13];\r
233 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM2, param->itgParam[2]);\r
234 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM3, param->itgParam[3]);\r
235 \r
236 /* Prepare input config register 14 */\r
237 reg = &outICRegs[14];\r
238 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG14_P0_ITG_PARAM4, param->itgParam[4]);\r
239 }\r
240 else\r
241 {\r
242 /* ITG Params are not required for 3GPP */\r
243 outICRegs[12] = 0;\r
244 outICRegs[13] = 0;\r
245 outICRegs[14] = 0;\r
246 }\r
247 \r
248 } /* end of Tcp3d_prepConfigRegs() */\r
249 \r
250 /**\r
251 * \brief This is a utility function is provided as part of TCP3D Driver\r
252 * for preparing the specific input config registers which depend\r
253 * on the block size.\r
254 *\r
255 * This function can be used for preparing IC0, IC1, IC12-IC14\r
256 * registers only out of 15 registers (IC0-IC14) using \r
257 * CSL_FINS macro.\r
258 *\r
259 */ \r
260 void Tcp3d_prepBlockSizeDepConfigRegs ( IN uint8_t mode,\r
261 OUT uint32_t * const RESTRICT outICRegs,\r
262 IN uint8_t numsw0,\r
263 IN uint16_t blockLen,\r
264 IN uint8_t sw0LenSel,\r
265 IN uint8_t sw2LenSel,\r
266 IN uint8_t sw1Len,\r
267 IN uint16_t * const RESTRICT itgParam)\r
268 {\r
269 uint32_t *reg;\r
270 \r
271 /* Prepare input config register 0 */\r
272 reg = &outICRegs[0];\r
273 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG0_P0_NUM_SW0, numsw0);\r
274 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG0_P0_BLK_LN, blockLen);\r
275 \r
276 /* Prepare input config register 1 */\r
277 reg = &outICRegs[1];\r
278 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW0_LN_SEL, sw0LenSel);\r
279 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW2_LN_SEL, sw2LenSel);\r
280 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW1_LN, sw1Len);\r
281 \r
282 /* LTE or WIMAX */\r
283 if ( ( mode == CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_LTE ) ||\r
284 ( mode == CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_WIMAX ) )\r
285 {\r
286 /* Prepare input config register 12 */\r
287 reg = &outICRegs[12];\r
288 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM0, itgParam[0]);\r
289 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM1, itgParam[1]);\r
290 \r
291 /* Prepare input config register 13 */\r
292 reg = &outICRegs[13];\r
293 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM2, itgParam[2]);\r
294 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM3, itgParam[3]);\r
295 \r
296 /* Prepare input config register 14 */\r
297 reg = &outICRegs[14];\r
298 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG14_P0_ITG_PARAM4, itgParam[4]);\r
299 }\r
300 \r
301 } /* end of Tcp3d_prepBlockSizeDepConfigRegs() */\r
302 \r
303 /**\r
304 * \brief This is a utility function is provided as part of TCP3D Driver\r
305 * for preparing the beta state value dependent input config\r
306 * registers only.\r
307 *\r
308 * This function can be used for preparing IC4-IC7 registers only\r
309 * out of 15 registers (IC0-IC14) using CSL_FINS macro.\r
310 *\r
311 */ \r
312 void Tcp3d_prepBetaStateConfigRegs( IN uint8_t mode,\r
313 OUT uint32_t * const RESTRICT outICRegs,\r
314 IN int8_t * const RESTRICT betaMap0,\r
315 IN int8_t * const RESTRICT betaMap1)\r
316 {\r
317 uint32_t *reg;\r
318 \r
319 /* Prepare input config register 4 */\r
320 reg = &outICRegs[4];\r
321 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST0_MAP0, betaMap0[0]);\r
322 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST1_MAP0, betaMap0[1]);\r
323 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST2_MAP0, betaMap0[2]);\r
324 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST3_MAP0, betaMap0[3]);\r
325 \r
326 /* Prepare input config register 5 */\r
327 reg = &outICRegs[5];\r
328 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST4_MAP0, betaMap0[4]);\r
329 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST5_MAP0, betaMap0[5]);\r
330 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST6_MAP0, betaMap0[6]);\r
331 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST7_MAP0, betaMap0[7]);\r
332 \r
333 /* Prepare input config register 6 */\r
334 reg = &outICRegs[6];\r
335 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST0_MAP1, betaMap1[0]);\r
336 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST1_MAP1, betaMap1[1]);\r
337 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST2_MAP1, betaMap1[2]);\r
338 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST3_MAP1, betaMap1[3]);\r
339 \r
340 /* Prepare input config register 7 */\r
341 reg = &outICRegs[7];\r
342 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST4_MAP1, betaMap1[4]);\r
343 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST5_MAP1, betaMap1[5]);\r
344 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST6_MAP1, betaMap1[6]);\r
345 CSL_FINS (*reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST7_MAP1, betaMap1[7]);\r
346 \r
347 } /* end of Tcp3d_prepBetaStateConfigRegs() */\r
348 \r
349 /* end of file */\r