1 /*\r
2 *\r
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ \r
4 * \r
5 * \r
6 * Redistribution and use in source and binary forms, with or without \r
7 * modification, are permitted provided that the following conditions \r
8 * are met:\r
9 *\r
10 * Redistributions of source code must retain the above copyright \r
11 * notice, this list of conditions and the following disclaimer.\r
12 *\r
13 * Redistributions in binary form must reproduce the above copyright\r
14 * notice, this list of conditions and the following disclaimer in the \r
15 * documentation and/or other materials provided with the \r
16 * distribution.\r
17 *\r
18 * Neither the name of Texas Instruments Incorporated nor the names of\r
19 * its contributors may be used to endorse or promote products derived\r
20 * from this software without specific prior written permission.\r
21 *\r
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
33 *\r
34 */\r
35 \r
36 \r
37 \r
38 #ifndef SIM_PARAM_H\r
39 #define SIM_PARAM_H\r
40 #include "typedefs.h"\r
41 \r
42 \r
43 /** \r
44 * \struct _TCP3_SIM_PARMS\r
45 * \r
46 * \brief The structure holds main simulation parameters that are read from the configuration file\r
47 * \r
48 * \sa \r
49 * \r
50 */\r
51 typedef struct _TCP3_SIM_PARMS\r
52 {\r
53 int32_t CodingStandard; /**< 0 - UMTS, 1 - LTE, 2 - WiMAX, 3 - HSUPA Split mode */ \r
54 int32_t frameLenInd; /**< For LTE and WiMAX: index of the block size (LTE: 0-187, Wimax: 0-16), For UMTS/HSUPA block size (40-5114) */ \r
55 int32_t MaxNumTurboIterations; /**< Maximum number of turbo iterations */ \r
56 int32_t MinNumTurboIterations; /**< Minimum number of turbo iterations */ \r
57 int32_t RateTimesOneTwenty; /**< Currently not used */ \r
58 int32_t mappingSign; /**< Currently hardcoded to 1 */ \r
59 \r
60 int32_t NumInfoBits; /**< Number of info bits */ \r
61 int32_t NumInfoSymb; /**< Half of the number of info bits */\r
62 int32_t NumInfoBytes; /**< Number of info bytes */\r
63 int32_t NumCodedBits; /**< Number of coded bits at the output of turbo encoder */\r
64 int32_t NumTransmitBits; /**< Number of transmitted bits (after rate matching) */\r
65 \r
66 \r
67 int32_t MinNumFecBlocks; /**< For BER calculation - maximum number of FEC blocks at one SNR point */ \r
68 int32_t MaxNumFecBlocks; /**< For BER calculation - minimum number of FEC blocks at one SNR point */\r
69 int32_t MinNumFerErrors; /**< For BER calculation - minimum number of FEC erros at one SNR point */\r
70 \r
71 int32_t PrevFerComputed; /**< FER calculated for the previous point*/\r
72 float PrevFer; /**< FER of the previous snr point*/\r
73 int32_t FrameErrorRateLimit; /**< Exponent value of the minimum frame error rate of the FER curve. For example -4 means stop curve computation when FER=10^-4 is reached. */ \r
74 float SnrInitValue; /**< Initial SNR value in dB */ \r
75 float SnrIncrementStep; /**< SNR increment steps for BER calculation */ \r
76 float SnrLimitValue; /**< Stop BER calculation if snr reaches this value */\r
77 float noiseSigma; /**< Noise RMS value */\r
78 float SnrPointValue; /**< Current SNR value during the calculation of BER/FER */\r
79 int32_t AdaptiveSnrStep; /**< =1 Enables adaptive SNR step. If the previous_FER/current_FER > 4 SNR step is divided in two */\r
80 int32_t seed; /**< Noise seed */\r
81 int32_t NoiseSwitch; /**< =1 nose addition to signal in the chanel enabled */\r
82 uint32_t Scr2318ShiftReg; /**< Initial value of the 23-bit scrambler shift register for info bit generation */\r
83 \r
84 \r
85 uint32_t SnrPointCounter; /**< Counts the SNR points during BER/FER curve calculation */\r
86 uint32_t FecBlockCntrLimit; /**< Maximum number of FEC blocks at the current SNR point */\r
87 \r
88 uint32_t AccBitErrors; /**< Accumulated bit errors at the current SNR point */\r
89 uint32_t AccFrameErrors; /**< Accumulated frame errors at the current SNR point */\r
90 uint32_t FecBlockCounter; /**< FEC block counter at the current SNR point */\r
91 uint32_t AccParity0BitErrors; /**< Accumulated bit errors at the current SNR point */\r
92 uint32_t AccParity1BitErrors; /**< Accumulated bit errors at the current SNR point */\r
93 \r
94 int32_t ErrorProcessingOption; /**< =1 coded error processing, =0 raw error processing */\r
95 \r
96 \r
97 int32_t simulationState; /**< simulaton state */\r
98 \r
99 int32_t bitWidthInt; /**< Input LLR bit width integer part including sign bit */\r
100 int32_t bitWidthFrac; /**< Number of fractional bits of input LLR */\r
101 int32_t maxStarEn; /**< =1 MaxStar enabled */\r
102 int32_t maxStarThreshold; /**< MaxStar thershold - width of the step function that approximates MaxStar correction term*/\r
103 int32_t maxStarValue; /**< MaxStar value - hight of the step function that approximates MaxStar correction term */\r
104 \r
105 int32_t alternateProcInd; /**< =1 alternates process index (0 or 1) during BER/FER computation */\r
106 int32_t initialProcInd; /**< (0or 1) initial process index */\r
107 \r
108 \r
109 int32_t extrinsicScales[16]; /**< Extrinsic scales for first 16 half iterations in Q5 format */\r
110 int32_t tcp3_SW0_length; /**< Sliding window 0 length in bits {16,32, 48, 64, 96 128} */\r
111 int32_t tcp3_SNR_stopVal; /**< SNR threshold in dB used as a stopping criterion (0-20) */\r
112 int32_t tcp3_SNR_Report; /**< =1 report SNR, =0 do not report SNR */\r
113 int32_t tcp3_stopSel; /**< Stopping criteria: =0 Max iter, =1 CRC, =2 or 3 SNR */\r
114 int32_t tcp3_crcSel; /**< CRC polynomial selector: =0 gCRC24B, =1 gCRC24A */\r
115 int32_t tcp3_intlvGenEn; /**< =0 Internal LTE interleaver table generation disabled, =1 enabled */\r
116 int32_t tcp3_intlvLoadSel; /**< =0 do not load or generate intlv table, =1 load or generate intlv table */\r
117 int32_t tcp3_extrScaleEn; /**< =0 Extrinsic scale disabled, =1 Extrinsics scale enabled */\r
118 int32_t tcp3_softOutBitFormat; /**< =0 - Soft output is truncated from 9 to 8-bits for storage in RAM (i.e. LSB truncated), =1 - Soft output is saturated from 9 to 8-bits for storage in RAM.*/\r
119 int32_t tcp3_outBitOrderSel; /**< =0 - LSB bit first in time, =1 - MSB bit first in time */\r
120 int32_t tcp3_lteCrcInitSel; /**< =0 Use 0x000000 as initial value, =1 Use 0xffffff as initial value */\r
121 int32_t tcp3_lteCrcIterPass; /**< Select number of consecutive LTE CRC matches as stopping criterion =0: 1 match, =1: 2 matches, =2: 3 matches, =3: 4 matches */\r
122 int32_t tcp3_softOutBitsReadEn; /**< =1 sends out soft output bits */\r
123 int32_t tcp3_outStatusReadEn; /**< =1 sends out output status */\r
124 \r
125 \r
126 /*For device verificaton*/\r
127 int32_t enableTopLvlDeviceVerification; /**< =1 Top level device verification enabled, =0 disabled */\r
128 int32_t enableDeviceVerification; /**< =1 Device verification enabled, =0 disabled */\r
129 int32_t disableBeliefPropagation; /**< =1 Belief propagation enabled, =0 disabled */\r
130 int32_t disableAlphaBeliefPropagation;/**< =1 Belief Alpha propagation enabled, =0 disabled */\r
131 int32_t disableBetaBeliefPropagation; /**< =1 Belief Beta propagation enabled, =0 disabled */\r
132 \r
133 int32_t devVerAlphaBlockNumber; /**< Alpha block number used for comparison in device verification */\r
134 int32_t devVerBetaBlockNumber; /**< Beta block number used for comparison in device verification*/\r
135 int32_t devVerExtrBlockNumber; /**< Extrinsic block number used for comparison in device verification*/\r
136 int32_t devVerSendIntermediteInternalMemories; /**< =1 send, =0 do not send */\r
137 int32_t devVerUseLinearInterleaver; /**< =1 interleaver is linear (for testing) =0 regular interleaver*/\r
138 int32_t devVerZeroAprioriInHardDec; /**< Only for device verification, =1 : soft decision = extrinisc + systematic (no apriori) */\r
139 \r
140 int32_t saveIntermediateData; /**< =1 Intermediate data recording to files enabled, =0 disabled */\r
141 int32_t beliefPropWithinTurboIterEnabled; /**< =1 Belief propagation within turbo iteration is enabled, =0 disabled, default = 0 */\r
142 \r
143 int32_t punctureInterval; /**< Used for testing: punctures (punctureInterval-1) out of punctureInterval parity bits, =-1 puncturing disabled, default = -1 */\r
144 int32_t enableRateMatching; /**< =1 Rate matching enabled, =0 disabled, default = 0 */\r
145 float codingRate; /**< If rate matching is enabled, coding rate */\r
146 int32_t redundancyVersionNumber; /**< Reundancy version number for LTE rate matching */\r
147 int32_t loadInfoBitsFromFile; /**< =0 info bits generated internally, =1 info bits read from file */\r
148 int32_t infoBitsFileIncludesCRC; /**< =1 File with info bits includes crc, =0 crc not included */\r
149 char infoBitsFileName[128]; /**< File name with the input bits to the encoder, used if loadInfoBitsFromFile=1 or storeInfoBitsToFile=1 */\r
150 int32_t storeCodedBitsToFile; /**< =1 coded bits stored to file, =0 not stored */\r
151 int32_t storeInfoBitsToFile; /**< =1 info bits stored to file, =0 not stored */\r
152 char codedBitsFileName[128]; /**< File name with the coded bits, used if storeCodedBitsToFile=1 */\r
153 int32_t use_tcp3_encoder_c_model; /**< =1 Use TCP3 encoder C model, =0 use existing encoders within the transmitter */\r
154 } TCP3_SIM_PARMS;\r
155 \r
156 \r
157 /** \r
158 * \struct _TCP3_SIM_PARMS\r
159 * \r
160 * \brief The structure holds all tcp3d control and configuration register parameters\r
161 * \r
162 * \sa \r
163 * \r
164 */\r
165 typedef struct _TCP3_REGS\r
166 {\r
167 int32_t mode_sel; //TCP3_MODE\r
168 int32_t in_mem_db_en; \r
169 int32_t itg_en;\r
170 int32_t err_ignore_en;\r
171 int32_t auto_trig_en;\r
172 int32_t lte_crc_init_sel;\r
173 int32_t trig; //TRIGGER_REG\r
174 int32_t endian_intr; //TCP_ENDIAN\r
175 int32_t endian_indata;\r
176 int32_t exe_cmd; //TCP3_EXE\r
177 int32_t num_sw0; //CFG0 \r
178 int32_t blk_ln;\r
179 int32_t sw1_ln; //CFG1\r
180 int32_t sw2_ln_sel;\r
181 int32_t sw0_ln_sel;\r
182 int32_t inter_load_sel; //CFG2\r
183 int32_t maxst_en;\r
184 int32_t out_flag_en;\r
185 int32_t out_order_sel;\r
186 int32_t ext_scale_en;\r
187 int32_t soft_out_flag_en;\r
188 int32_t soft_out_order_sel;\r
189 int32_t soft_out_fmt;\r
190 int32_t min_itr;\r
191 int32_t max_itr;\r
192 int32_t snr_val;\r
193 int32_t snr_rep;\r
194 int32_t stop_sel;\r
195 int32_t crc_iter_pass;\r
196 int32_t crc_sel;\r
197 int32_t maxst_thold; //CFG3\r
198 int32_t maxst_value;\r
199 int32_t beta_st0_map0; //CFG4\r
200 int32_t beta_st1_map0;\r
201 int32_t beta_st2_map0;\r
202 int32_t beta_st3_map0;\r
203 int32_t beta_st4_map0; //CFG5\r
204 int32_t beta_st5_map0;\r
205 int32_t beta_st6_map0;\r
206 int32_t beta_st7_map0;\r
207 int32_t beta_st0_map1; //CFG6\r
208 int32_t beta_st1_map1;\r
209 int32_t beta_st2_map1;\r
210 int32_t beta_st3_map1;\r
211 int32_t beta_st4_map1; //CFG7\r
212 int32_t beta_st5_map1;\r
213 int32_t beta_st6_map1;\r
214 int32_t beta_st7_map1;\r
215 int32_t ext_scale_0; //CFG8\r
216 int32_t ext_scale_1;\r
217 int32_t ext_scale_2;\r
218 int32_t ext_scale_3;\r
219 int32_t ext_scale_4; //CFG9\r
220 int32_t ext_scale_5;\r
221 int32_t ext_scale_6;\r
222 int32_t ext_scale_7;\r
223 int32_t ext_scale_8; //CFG10\r
224 int32_t ext_scale_9;\r
225 int32_t ext_scale_10;\r
226 int32_t ext_scale_11;\r
227 int32_t ext_scale_12; //CFG11\r
228 int32_t ext_scale_13;\r
229 int32_t ext_scale_14;\r
230 int32_t ext_scale_15;\r
231 int32_t itg_param_0; //CFG12\r
232 int32_t itg_param_1;\r
233 int32_t itg_param_2; //CFG13\r
234 int32_t itg_param_3;\r
235 int32_t itg_param_4; //CFG14\r
236 //Not part of tcp3 registers:\r
237 int32_t proc_id; \r
238 int32_t ExtndNumInfoBits;\r
239 int32_t NumInfoBits;\r
240 int32_t IntlvLen;\r
241 int32_t SW0_length;\r
242 } TCP3_REGS;\r
243 \r
244 \r
245 \r
246 \r
247 typedef struct _CODE_BLOCK_PARMS\r
248 {\r
249 TCP3_SIM_PARMS sparms;\r
250 TCP3_REGS reg;\r
251 int8_t sysLLR[8192];\r
252 int8_t par0LLR[8192];\r
253 int8_t par1LLR[8192];\r
254 int8_t tailLLRs[12];\r
255 int16_t interleaver[8192];\r
256 uint32_t ref_infoBits[256];\r
257 uint32_t ref_hardDecisions[256];\r
258 int8_t ref_softDecisions[3][8192];\r
259 uint32_t ref_outStatus[3];\r
260 \r
261 uint32_t ssi_hardDecisions[256];\r
262 int8_t ssi_softDecisions[3][8192];\r
263 uint32_t ssi_outStatus[3];\r
264 \r
265 int32_t codeBlockNumber; //block number read from the codeBlockList file\r
266 \r
267 int32_t transferError;\r
268 \r
269 } CODE_BLOCK_PARMS;\r
270 \r
271 \r
272 #endif