1 /*\r
2 * sample_cfg.c\r
3 *\r
4 * Platform specific EDMA3 hardware related information like number of transfer\r
5 * controllers, various interrupt ids etc. It is used while interrupts\r
6 * enabling / disabling. It needs to be ported for different SoCs.\r
7 *\r
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9 * \r
10 * Redistribution and use in source and binary forms, with or without \r
11 * modification, are permitted provided that the following conditions \r
12 * are met:\r
13 *\r
14 * Redistributions of source code must retain the above copyright \r
15 * notice, this list of conditions and the following disclaimer.\r
16 *\r
17 * Redistributions in binary form must reproduce the above copyright\r
18 * notice, this list of conditions and the following disclaimer in the \r
19 * documentation and/or other materials provided with the \r
20 * distribution.\r
21 *\r
22 * Neither the name of Texas Instruments Incorporated nor the names of\r
23 * its contributors may be used to endorse or promote products derived\r
24 * from this software without specific prior written permission.\r
25 *\r
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
37 *\r
38 */\r
39 \r
40 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
41 \r
42 /* Number of EDMA3 controllers present in the system */\r
43 #define NUM_EDMA3_INSTANCES 3u\r
44 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
45 \r
46 /* Number of DSPs present in the system */\r
47 #define NUM_DSPS 4u\r
48 //const unsigned int numDsps = NUM_DSPS;\r
49 \r
50 #define CGEM_REG_START (0x01800000)\r
51 \r
52 /* Determine the processor id by reading DNUM register. */\r
53 unsigned short determineProcId()\r
54 {\r
55 volatile unsigned int *addr;\r
56 unsigned int core_no;\r
57 \r
58 /* Identify the core number */\r
59 addr = (unsigned int *)(CGEM_REG_START+0x40000);\r
60 core_no = ((*addr) & 0x000F0000)>>16;\r
61 \r
62 return core_no;\r
63 }\r
64 \r
65 /** Whether global configuration required for EDMA3 or not.\r
66 * This configuration should be done only once for the EDMA3 hardware by\r
67 * any one of the masters (i.e. DSPs).\r
68 * It can be changed depending on the use-case.\r
69 */\r
70 unsigned int gblCfgReqdArray [NUM_DSPS] = {\r
71 0, /* DSP#0 is Master, will do the global init */\r
72 1, /* DSP#1 is Slave, will not do the global init */\r
73 1, /* DSP#2 is Slave, will not do the global init */\r
74 1, /* DSP#3 is Slave, will not do the global init */\r
75 };\r
76 \r
77 unsigned short isGblConfigRequired(unsigned int dspNum)\r
78 {\r
79 return gblCfgReqdArray[dspNum];\r
80 }\r
81 \r
82 /* Semaphore handles */\r
83 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};\r
84 \r
85 \r
86 /* Variable which will be used internally for referring number of Event Queues. */\r
87 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};\r
88 \r
89 /* Variable which will be used internally for referring number of TCs. */\r
90 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};\r
91 \r
92 /**\r
93 * Variable which will be used internally for referring transfer completion\r
94 * interrupt. Completion interrupts for all the shadow regions and all the\r
95 * EDMA3 controllers are captured since it is a multi-DSP platform.\r
96 */\r
97 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {\r
98 {\r
99 38u, 39u, 40u, 41u,\r
100 42u, 43u, 44u, 45u,\r
101 },\r
102 {\r
103 8u, 9u, 10u, 11u,\r
104 12u, 13u, 14u, 15u,\r
105 },\r
106 {\r
107 24u, 25u, 26u, 27u,\r
108 28u, 29u, 30u, 31u,\r
109 },\r
110 };\r
111 \r
112 /**\r
113 * Variable which will be used internally for referring channel controller's\r
114 * error interrupt.\r
115 */\r
116 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};\r
117 \r
118 /**\r
119 * Variable which will be used internally for referring transfer controllers'\r
120 * error interrupts.\r
121 */\r
122 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {\r
123 {\r
124 34u, 35u, 0u, 0u,\r
125 0u, 0u, 0u, 0u,\r
126 },\r
127 {\r
128 2u, 3u, 4u, 5u,\r
129 0u, 0u, 0u, 0u,\r
130 },\r
131 {\r
132 18u, 19u, 20u, 21u,\r
133 0u, 0u, 0u, 0u,\r
134 },\r
135 };\r
136 \r
137 /* Driver Object Initialization Configuration */\r
138 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
139 {\r
140 {\r
141 /* EDMA3 INSTANCE# 0 */\r
142 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
143 16u,\r
144 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
145 8u,\r
146 /** Total number of TCCs supported by the EDMA3 Controller */\r
147 16u,\r
148 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
149 128u,\r
150 /** Total number of Event Queues in the EDMA3 Controller */\r
151 2u,\r
152 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
153 2u,\r
154 /** Number of Regions on this EDMA3 controller */\r
155 8u,\r
156 \r
157 /**\r
158 * \brief Channel mapping existence\r
159 * A value of 0 (No channel mapping) implies that there is fixed association\r
160 * for a channel number to a parameter entry number or, in other words,\r
161 * PaRAM entry n corresponds to channel n.\r
162 */\r
163 1u,\r
164 \r
165 /** Existence of memory protection feature */\r
166 1u,\r
167 \r
168 /** Global Register Region of CC Registers */\r
169 (void *)0x02700000u,\r
170 /** Transfer Controller (TC) Registers */\r
171 {\r
172 (void *)0x02760000u,\r
173 (void *)0x02768000u,\r
174 (void *)NULL,\r
175 (void *)NULL,\r
176 (void *)NULL,\r
177 (void *)NULL,\r
178 (void *)NULL,\r
179 (void *)NULL\r
180 },\r
181 /** Interrupt no. for Transfer Completion */\r
182 38u,\r
183 /** Interrupt no. for CC Error */\r
184 32u,\r
185 /** Interrupt no. for TCs Error */\r
186 {\r
187 34u,\r
188 35u,\r
189 0u,\r
190 0u,\r
191 0u,\r
192 0u,\r
193 0u,\r
194 0u,\r
195 },\r
196 \r
197 /**\r
198 * \brief EDMA3 TC priority setting\r
199 *\r
200 * User can program the priority of the Event Queues\r
201 * at a system-wide level. This means that the user can set the\r
202 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
203 * relative to IO initiated by the other bus masters on the\r
204 * device (ARM, DSP, USB, etc)\r
205 */\r
206 {\r
207 0u,\r
208 1u,\r
209 0u,\r
210 0u,\r
211 0u,\r
212 0u,\r
213 0u,\r
214 0u\r
215 },\r
216 /**\r
217 * \brief To Configure the Threshold level of number of events\r
218 * that can be queued up in the Event queues. EDMA3CC error register\r
219 * (CCERR) will indicate whether or not at any instant of time the\r
220 * number of events queued up in any of the event queues exceeds\r
221 * or equals the threshold/watermark value that is set\r
222 * in the queue watermark threshold register (QWMTHRA).\r
223 */\r
224 {\r
225 16u,\r
226 16u,\r
227 0u,\r
228 0u,\r
229 0u,\r
230 0u,\r
231 0u,\r
232 0u\r
233 },\r
234 \r
235 /**\r
236 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
237 * An optimally-sized command is defined by the transfer controller\r
238 * default burst size (DBS). Different TCs can have different\r
239 * DBS values. It is defined in Bytes.\r
240 */\r
241 {\r
242 16u,\r
243 16u,\r
244 0u,\r
245 0u,\r
246 0u,\r
247 0u,\r
248 0u,\r
249 0u\r
250 },\r
251 \r
252 /**\r
253 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
254 * if it exists, otherwise of no use.\r
255 */\r
256 {\r
257 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
258 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
259 /* DMA channels 16-63 DOES NOT exist */\r
260 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
261 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
262 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
263 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
264 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
265 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
266 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
267 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
268 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
269 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
270 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
271 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
272 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
273 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
274 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
275 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
276 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
277 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
278 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
279 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
280 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
281 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
282 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
283 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS\r
284 },\r
285 \r
286 /**\r
287 * \brief Mapping from each DMA channel to a TCC. This specific\r
288 * TCC code will be returned when the transfer is completed\r
289 * on the mapped channel.\r
290 */\r
291 {\r
292 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
293 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
294 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
295 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
296 /* DMA channels 16-63 DOES NOT exist */\r
297 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
298 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
299 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
300 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
301 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
302 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
303 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
304 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
305 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
306 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
307 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
308 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC\r
309 },\r
310 \r
311 /**\r
312 * \brief Mapping of DMA channels to Hardware Events from\r
313 * various peripherals, which use EDMA for data transfer.\r
314 * All channels need not be mapped, some can be free also.\r
315 */\r
316 {\r
317 0x00003333u,\r
318 0x00000000u\r
319 }\r
320 },\r
321 \r
322 {\r
323 /* EDMA3 INSTANCE# 1 */\r
324 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
325 64u,\r
326 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
327 8u,\r
328 /** Total number of TCCs supported by the EDMA3 Controller */\r
329 64u,\r
330 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
331 512u,\r
332 /** Total number of Event Queues in the EDMA3 Controller */\r
333 4u,\r
334 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
335 4u,\r
336 /** Number of Regions on this EDMA3 controller */\r
337 8u,\r
338 \r
339 /**\r
340 * \brief Channel mapping existence\r
341 * A value of 0 (No channel mapping) implies that there is fixed association\r
342 * for a channel number to a parameter entry number or, in other words,\r
343 * PaRAM entry n corresponds to channel n.\r
344 */\r
345 1u,\r
346 \r
347 /** Existence of memory protection feature */\r
348 1u,\r
349 \r
350 /** Global Register Region of CC Registers */\r
351 (void *)0x02720000u,\r
352 /** Transfer Controller (TC) Registers */\r
353 {\r
354 (void *)0x02770000u,\r
355 (void *)0x02778000u,\r
356 (void *)0x02780000u,\r
357 (void *)0x02788000u,\r
358 (void *)NULL,\r
359 (void *)NULL,\r
360 (void *)NULL,\r
361 (void *)NULL\r
362 },\r
363 /** Interrupt no. for Transfer Completion */\r
364 8u,\r
365 /** Interrupt no. for CC Error */\r
366 0u,\r
367 /** Interrupt no. for TCs Error */\r
368 {\r
369 2u,\r
370 3u,\r
371 4u,\r
372 5u,\r
373 0u,\r
374 0u,\r
375 0u,\r
376 0u,\r
377 },\r
378 \r
379 /**\r
380 * \brief EDMA3 TC priority setting\r
381 *\r
382 * User can program the priority of the Event Queues\r
383 * at a system-wide level. This means that the user can set the\r
384 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
385 * relative to IO initiated by the other bus masters on the\r
386 * device (ARM, DSP, USB, etc)\r
387 */\r
388 {\r
389 0u,\r
390 1u,\r
391 2u,\r
392 3u,\r
393 0u,\r
394 0u,\r
395 0u,\r
396 0u\r
397 },\r
398 /**\r
399 * \brief To Configure the Threshold level of number of events\r
400 * that can be queued up in the Event queues. EDMA3CC error register\r
401 * (CCERR) will indicate whether or not at any instant of time the\r
402 * number of events queued up in any of the event queues exceeds\r
403 * or equals the threshold/watermark value that is set\r
404 * in the queue watermark threshold register (QWMTHRA).\r
405 */\r
406 {\r
407 16u,\r
408 16u,\r
409 16u,\r
410 16u,\r
411 0u,\r
412 0u,\r
413 0u,\r
414 0u\r
415 },\r
416 \r
417 /**\r
418 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
419 * An optimally-sized command is defined by the transfer controller\r
420 * default burst size (DBS). Different TCs can have different\r
421 * DBS values. It is defined in Bytes.\r
422 */\r
423 {\r
424 8u,\r
425 8u,\r
426 8u,\r
427 8u,\r
428 0u,\r
429 0u,\r
430 0u,\r
431 0u\r
432 },\r
433 \r
434 /**\r
435 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
436 * if it exists, otherwise of no use.\r
437 */\r
438 {\r
439 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
440 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
441 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
442 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
443 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
444 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
445 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
446 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
447 },\r
448 \r
449 /**\r
450 * \brief Mapping from each DMA channel to a TCC. This specific\r
451 * TCC code will be returned when the transfer is completed\r
452 * on the mapped channel.\r
453 */\r
454 {\r
455 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
456 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
457 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
458 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
459 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
460 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
461 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
462 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
463 },\r
464 \r
465 /**\r
466 * \brief Mapping of DMA channels to Hardware Events from\r
467 * various peripherals, which use EDMA for data transfer.\r
468 * All channels need not be mapped, some can be free also.\r
469 */\r
470 {\r
471 0x3FFF3FFFu,\r
472 0x3FFF3FFFu\r
473 }\r
474 },\r
475 \r
476 {\r
477 /* EDMA3 INSTANCE# 2 */\r
478 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
479 64u,\r
480 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
481 8u,\r
482 /** Total number of TCCs supported by the EDMA3 Controller */\r
483 64u,\r
484 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
485 512u,\r
486 /** Total number of Event Queues in the EDMA3 Controller */\r
487 4u,\r
488 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
489 4u,\r
490 /** Number of Regions on this EDMA3 controller */\r
491 8u,\r
492 \r
493 /**\r
494 * \brief Channel mapping existence\r
495 * A value of 0 (No channel mapping) implies that there is fixed association\r
496 * for a channel number to a parameter entry number or, in other words,\r
497 * PaRAM entry n corresponds to channel n.\r
498 */\r
499 1u,\r
500 \r
501 /** Existence of memory protection feature */\r
502 1u,\r
503 \r
504 /** Global Register Region of CC Registers */\r
505 (void *)0x02740000u,\r
506 /** Transfer Controller (TC) Registers */\r
507 {\r
508 (void *)0x02790000u,\r
509 (void *)0x02798000u,\r
510 (void *)0x027A0000u,\r
511 (void *)0x027A8000u,\r
512 (void *)NULL,\r
513 (void *)NULL,\r
514 (void *)NULL,\r
515 (void *)NULL\r
516 },\r
517 /** Interrupt no. for Transfer Completion */\r
518 24u,\r
519 /** Interrupt no. for CC Error */\r
520 16u,\r
521 /** Interrupt no. for TCs Error */\r
522 {\r
523 18u,\r
524 19u,\r
525 20u,\r
526 21u,\r
527 0u,\r
528 0u,\r
529 0u,\r
530 0u,\r
531 },\r
532 \r
533 /**\r
534 * \brief EDMA3 TC priority setting\r
535 *\r
536 * User can program the priority of the Event Queues\r
537 * at a system-wide level. This means that the user can set the\r
538 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
539 * relative to IO initiated by the other bus masters on the\r
540 * device (ARM, DSP, USB, etc)\r
541 */\r
542 {\r
543 0u,\r
544 1u,\r
545 2u,\r
546 3u,\r
547 0u,\r
548 0u,\r
549 0u,\r
550 0u\r
551 },\r
552 /**\r
553 * \brief To Configure the Threshold level of number of events\r
554 * that can be queued up in the Event queues. EDMA3CC error register\r
555 * (CCERR) will indicate whether or not at any instant of time the\r
556 * number of events queued up in any of the event queues exceeds\r
557 * or equals the threshold/watermark value that is set\r
558 * in the queue watermark threshold register (QWMTHRA).\r
559 */\r
560 {\r
561 16u,\r
562 16u,\r
563 16u,\r
564 16u,\r
565 0u,\r
566 0u,\r
567 0u,\r
568 0u\r
569 },\r
570 \r
571 /**\r
572 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
573 * An optimally-sized command is defined by the transfer controller\r
574 * default burst size (DBS). Different TCs can have different\r
575 * DBS values. It is defined in Bytes.\r
576 */\r
577 {\r
578 8u,\r
579 8u,\r
580 8u,\r
581 8u,\r
582 0u,\r
583 0u,\r
584 0u,\r
585 0u\r
586 },\r
587 \r
588 /**\r
589 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
590 * if it exists, otherwise of no use.\r
591 */\r
592 {\r
593 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
594 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
595 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
596 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
597 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
598 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
599 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
600 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
601 },\r
602 \r
603 /**\r
604 * \brief Mapping from each DMA channel to a TCC. This specific\r
605 * TCC code will be returned when the transfer is completed\r
606 * on the mapped channel.\r
607 */\r
608 {\r
609 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
610 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
611 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 18u, 19u, 20u, 21u, 22u, 23u,\r
612 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
613 32u, 33u, 34u, 35u, 36u, 37u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
614 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
615 48u, 49u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
616 56u, 57u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
617 },\r
618 \r
619 /**\r
620 * \brief Mapping of DMA channels to Hardware Events from\r
621 * various peripherals, which use EDMA for data transfer.\r
622 * All channels need not be mapped, some can be free also.\r
623 */\r
624 {\r
625 0x3FFC3FFFu,\r
626 0x03033F3Fu\r
627 }\r
628 },\r
629 };\r
630 \r
631 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
632 {\r
633 /* EDMA3 INSTANCE# 0 */\r
634 {\r
635 /* Resources owned/reserved by region 0 */\r
636 {\r
637 /* ownPaRAMSets */\r
638 /* 31 0 63 32 95 64 127 96 */\r
639 {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,\r
640 /* 159 128 191 160 223 192 255 224 */\r
641 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
642 /* 287 256 319 288 351 320 383 352 */\r
643 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
644 /* 415 384 447 416 479 448 511 480 */\r
645 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
646 \r
647 /* ownDmaChannels */\r
648 /* 31 0 63 32 */\r
649 {0x0000000Fu, 0x00000000u},\r
650 \r
651 /* ownQdmaChannels */\r
652 /* 31 0 */\r
653 {0x00000003u},\r
654 \r
655 /* ownTccs */\r
656 /* 31 0 63 32 */\r
657 {0x0000000Fu, 0x00000000u},\r
658 \r
659 /* resvdPaRAMSets */\r
660 /* 31 0 63 32 95 64 127 96 */\r
661 {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,\r
662 /* 159 128 191 160 223 192 255 224 */\r
663 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
664 /* 287 256 319 288 351 320 383 352 */\r
665 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
666 /* 415 384 447 416 479 448 511 480 */\r
667 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
668 \r
669 /* resvdDmaChannels */\r
670 /* 31 0 */\r
671 {0x00000003u, 0x00000000u},\r
672 \r
673 /* resvdQdmaChannels */\r
674 /* 31 0 */\r
675 {0x00000000u},\r
676 \r
677 /* resvdTccs */\r
678 /* 31 0 */\r
679 {0x00000003u, 0x00000000u},\r
680 },\r
681 \r
682 /* Resources owned/reserved by region 1 */\r
683 {\r
684 /* ownPaRAMSets */\r
685 /* 31 0 63 32 95 64 127 96 */\r
686 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,\r
687 /* 159 128 191 160 223 192 255 224 */\r
688 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
689 /* 287 256 319 288 351 320 383 352 */\r
690 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
691 /* 415 384 447 416 479 448 511 480 */\r
692 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
693 \r
694 /* ownDmaChannels */\r
695 /* 31 0 63 32 */\r
696 {0x000000F0u, 0x00000000u},\r
697 \r
698 /* ownQdmaChannels */\r
699 /* 31 0 */\r
700 {0x0000000Cu},\r
701 \r
702 /* ownTccs */\r
703 /* 31 0 63 32 */\r
704 {0x000000F0u, 0x00000000u},\r
705 \r
706 /* resvdPaRAMSets */\r
707 /* 31 0 63 32 95 64 127 96 */\r
708 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,\r
709 /* 159 128 191 160 223 192 255 224 */\r
710 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
711 /* 287 256 319 288 351 320 383 352 */\r
712 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
713 /* 415 384 447 416 479 448 511 480 */\r
714 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
715 \r
716 /* resvdDmaChannels */\r
717 /* 31 0 63 32 */\r
718 {0x00000030u, 0x00000000u},\r
719 \r
720 /* resvdQdmaChannels */\r
721 /* 31 0 */\r
722 {0x00000000u},\r
723 \r
724 /* resvdTccs */\r
725 /* 31 0 63 32 */\r
726 {0x00000030u, 0x00000000u},\r
727 },\r
728 \r
729 /* Resources owned/reserved by region 2 */\r
730 {\r
731 /* ownPaRAMSets */\r
732 /* 31 0 63 32 95 64 127 96 */\r
733 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,\r
734 /* 159 128 191 160 223 192 255 224 */\r
735 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
736 /* 287 256 319 288 351 320 383 352 */\r
737 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
738 /* 415 384 447 416 479 448 511 480 */\r
739 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
740 \r
741 /* ownDmaChannels */\r
742 /* 31 0 63 32 */\r
743 {0x00000F00u, 0x00000000u},\r
744 \r
745 /* ownQdmaChannels */\r
746 /* 31 0 */\r
747 {0x00000030u},\r
748 \r
749 /* ownTccs */\r
750 /* 31 0 63 32 */\r
751 {0x00000F00u, 0x00000000u},\r
752 \r
753 /* resvdPaRAMSets */\r
754 /* 31 0 63 32 95 64 127 96 */\r
755 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,\r
756 /* 159 128 191 160 223 192 255 224 */\r
757 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
758 /* 287 256 319 288 351 320 383 352 */\r
759 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
760 /* 415 384 447 416 479 448 511 480 */\r
761 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
762 \r
763 /* resvdDmaChannels */\r
764 /* 31 0 63 32 */\r
765 {0x00000300u, 0x00000000u},\r
766 \r
767 /* resvdQdmaChannels */\r
768 /* 31 0 */\r
769 {0x00000000u},\r
770 \r
771 /* resvdTccs */\r
772 /* 31 0 63 32 */\r
773 {0x00000300u, 0x00000000u},\r
774 },\r
775 \r
776 /* Resources owned/reserved by region 3 */\r
777 {\r
778 /* ownPaRAMSets */\r
779 /* 31 0 63 32 95 64 127 96 */\r
780 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,\r
781 /* 159 128 191 160 223 192 255 224 */\r
782 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
783 /* 287 256 319 288 351 320 383 352 */\r
784 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
785 /* 415 384 447 416 479 448 511 480 */\r
786 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
787 \r
788 /* ownDmaChannels */\r
789 /* 31 0 63 32 */\r
790 {0x0000F000u, 0x00000000u},\r
791 \r
792 /* ownQdmaChannels */\r
793 /* 31 0 */\r
794 {0x000000C0u},\r
795 \r
796 /* ownTccs */\r
797 /* 31 0 63 32 */\r
798 {0x0000F000u, 0x00000000u},\r
799 \r
800 /* resvdPaRAMSets */\r
801 /* 31 0 63 32 95 64 127 96 */\r
802 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
803 /* 159 128 191 160 223 192 255 224 */\r
804 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
805 /* 287 256 319 288 351 320 383 352 */\r
806 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
807 /* 415 384 447 416 479 448 511 480 */\r
808 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
809 \r
810 /* resvdDmaChannels */\r
811 /* 31 0 63 32 */\r
812 {0x00003000u, 0x00000000u},\r
813 \r
814 /* resvdQdmaChannels */\r
815 /* 31 0 */\r
816 {0x00000000u},\r
817 \r
818 /* resvdTccs */\r
819 /* 31 0 63 32 */\r
820 {0x00003000u, 0x00000000u},\r
821 },\r
822 \r
823 /* Resources owned/reserved by region 4 */\r
824 {\r
825 /* ownPaRAMSets */\r
826 /* 31 0 63 32 95 64 127 96 */\r
827 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
828 /* 159 128 191 160 223 192 255 224 */\r
829 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
830 /* 287 256 319 288 351 320 383 352 */\r
831 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
832 /* 415 384 447 416 479 448 511 480 */\r
833 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
834 \r
835 /* ownDmaChannels */\r
836 /* 31 0 63 32 */\r
837 {0x00000000u, 0x00000000u},\r
838 \r
839 /* ownQdmaChannels */\r
840 /* 31 0 */\r
841 {0x00000000u},\r
842 \r
843 /* ownTccs */\r
844 /* 31 0 63 32 */\r
845 {0x00000000u, 0x00000000u},\r
846 \r
847 /* resvdPaRAMSets */\r
848 /* 31 0 63 32 95 64 127 96 */\r
849 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
850 /* 159 128 191 160 223 192 255 224 */\r
851 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
852 /* 287 256 319 288 351 320 383 352 */\r
853 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
854 /* 415 384 447 416 479 448 511 480 */\r
855 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
856 \r
857 /* resvdDmaChannels */\r
858 /* 31 0 63 32 */\r
859 {0x00000000u, 0x00000000u},\r
860 \r
861 /* resvdQdmaChannels */\r
862 /* 31 0 */\r
863 {0x00000000u},\r
864 \r
865 /* resvdTccs */\r
866 /* 31 0 63 32 */\r
867 {0x00000000u, 0x00000000u},\r
868 },\r
869 \r
870 /* Resources owned/reserved by region 5 */\r
871 {\r
872 /* ownPaRAMSets */\r
873 /* 31 0 63 32 95 64 127 96 */\r
874 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
875 /* 159 128 191 160 223 192 255 224 */\r
876 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
877 /* 287 256 319 288 351 320 383 352 */\r
878 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
879 /* 415 384 447 416 479 448 511 480 */\r
880 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
881 \r
882 /* ownDmaChannels */\r
883 /* 31 0 63 32 */\r
884 {0x00000000u, 0x00000000u},\r
885 \r
886 /* ownQdmaChannels */\r
887 /* 31 0 */\r
888 {0x00000000u},\r
889 \r
890 /* ownTccs */\r
891 /* 31 0 63 32 */\r
892 {0x00000000u, 0x00000000u},\r
893 \r
894 /* resvdPaRAMSets */\r
895 /* 31 0 63 32 95 64 127 96 */\r
896 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
897 /* 159 128 191 160 223 192 255 224 */\r
898 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
899 /* 287 256 319 288 351 320 383 352 */\r
900 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
901 /* 415 384 447 416 479 448 511 480 */\r
902 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
903 \r
904 /* resvdDmaChannels */\r
905 /* 31 0 63 32 */\r
906 {0x00000000u, 0x00000000u},\r
907 \r
908 /* resvdQdmaChannels */\r
909 /* 31 0 */\r
910 {0x00000000u},\r
911 \r
912 /* resvdTccs */\r
913 /* 31 0 63 32 */\r
914 {0x00000000u, 0x00000000u},\r
915 },\r
916 \r
917 /* Resources owned/reserved by region 6 */\r
918 {\r
919 /* ownPaRAMSets */\r
920 /* 31 0 63 32 95 64 127 96 */\r
921 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
922 /* 159 128 191 160 223 192 255 224 */\r
923 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
924 /* 287 256 319 288 351 320 383 352 */\r
925 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
926 /* 415 384 447 416 479 448 511 480 */\r
927 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
928 \r
929 /* ownDmaChannels */\r
930 /* 31 0 63 32 */\r
931 {0x00000000u, 0x00000000u},\r
932 \r
933 /* ownQdmaChannels */\r
934 /* 31 0 */\r
935 {0x00000000u},\r
936 \r
937 /* ownTccs */\r
938 /* 31 0 63 32 */\r
939 {0x00000000u, 0x00000000u},\r
940 \r
941 /* resvdPaRAMSets */\r
942 /* 31 0 63 32 95 64 127 96 */\r
943 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
944 /* 159 128 191 160 223 192 255 224 */\r
945 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
946 /* 287 256 319 288 351 320 383 352 */\r
947 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
948 /* 415 384 447 416 479 448 511 480 */\r
949 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
950 \r
951 /* resvdDmaChannels */\r
952 /* 31 0 63 32 */\r
953 {0x00000000u, 0x00000000u},\r
954 \r
955 /* resvdQdmaChannels */\r
956 /* 31 0 */\r
957 {0x00000000u},\r
958 \r
959 /* resvdTccs */\r
960 /* 31 0 63 32 */\r
961 {0x00000000u, 0x00000000u},\r
962 },\r
963 \r
964 /* Resources owned/reserved by region 7 */\r
965 {\r
966 /* ownPaRAMSets */\r
967 /* 31 0 63 32 95 64 127 96 */\r
968 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
969 /* 159 128 191 160 223 192 255 224 */\r
970 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
971 /* 287 256 319 288 351 320 383 352 */\r
972 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
973 /* 415 384 447 416 479 448 511 480 */\r
974 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
975 \r
976 /* ownDmaChannels */\r
977 /* 31 0 63 32 */\r
978 {0x00000000u, 0x00000000u},\r
979 \r
980 /* ownQdmaChannels */\r
981 /* 31 0 */\r
982 {0x00000000u},\r
983 \r
984 /* ownTccs */\r
985 /* 31 0 63 32 */\r
986 {0x00000000u, 0x00000000u},\r
987 \r
988 /* resvdPaRAMSets */\r
989 /* 31 0 63 32 95 64 127 96 */\r
990 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
991 /* 159 128 191 160 223 192 255 224 */\r
992 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
993 /* 287 256 319 288 351 320 383 352 */\r
994 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
995 /* 415 384 447 416 479 448 511 480 */\r
996 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
997 \r
998 /* resvdDmaChannels */\r
999 /* 31 0 63 32 */\r
1000 {0x00000000u, 0x00000000u},\r
1001 \r
1002 /* resvdQdmaChannels */\r
1003 /* 31 0 */\r
1004 {0x00000000u},\r
1005 \r
1006 /* resvdTccs */\r
1007 /* 31 0 63 32 */\r
1008 {0x00000000u, 0x00000000u},\r
1009 },\r
1010 },\r
1011 \r
1012 /* EDMA3 INSTANCE# 1 */\r
1013 {\r
1014 /* Resources owned/reserved by region 0 */\r
1015 {\r
1016 /* ownPaRAMSets */\r
1017 /* 31 0 63 32 95 64 127 96 */\r
1018 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1019 /* 159 128 191 160 223 192 255 224 */\r
1020 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
1021 /* 287 256 319 288 351 320 383 352 */\r
1022 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1023 /* 415 384 447 416 479 448 511 480 */\r
1024 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1025 \r
1026 /* ownDmaChannels */\r
1027 /* 31 0 63 32 */\r
1028 {0x0000FFFFu, 0x00000000u},\r
1029 \r
1030 /* ownQdmaChannels */\r
1031 /* 31 0 */\r
1032 {0x00000003u},\r
1033 \r
1034 /* ownTccs */\r
1035 /* 31 0 63 32 */\r
1036 {0x0000FFFFu, 0x00000000u},\r
1037 \r
1038 /* resvdPaRAMSets */\r
1039 /* 31 0 63 32 95 64 127 96 */\r
1040 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
1041 /* 159 128 191 160 223 192 255 224 */\r
1042 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1043 /* 287 256 319 288 351 320 383 352 */\r
1044 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1045 /* 415 384 447 416 479 448 511 480 */\r
1046 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1047 \r
1048 /* resvdDmaChannels */\r
1049 /* 31 0 63 32 */\r
1050 {0x00003FFFu, 0x00000000u},\r
1051 \r
1052 /* resvdQdmaChannels */\r
1053 /* 31 0 */\r
1054 {0x00000000u},\r
1055 \r
1056 /* resvdTccs */\r
1057 /* 31 0 63 32 */\r
1058 {0x00003FFFu, 0x00000000u},\r
1059 },\r
1060 \r
1061 /* Resources owned/reserved by region 1 */\r
1062 {\r
1063 /* ownPaRAMSets */\r
1064 /* 31 0 63 32 95 64 127 96 */\r
1065 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1066 /* 159 128 191 160 223 192 255 224 */\r
1067 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1068 /* 287 256 319 288 351 320 383 352 */\r
1069 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
1070 /* 415 384 447 416 479 448 511 480 */\r
1071 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1072 \r
1073 /* ownDmaChannels */\r
1074 /* 31 0 63 32 */\r
1075 {0xFFFF0000u, 0x00000000u},\r
1076 \r
1077 /* ownQdmaChannels */\r
1078 /* 31 0 */\r
1079 {0x0000000Cu},\r
1080 \r
1081 /* ownTccs */\r
1082 /* 31 0 63 32 */\r
1083 {0xFFFF0000u, 0x00000000u},\r
1084 \r
1085 /* resvdPaRAMSets */\r
1086 /* 31 0 63 32 95 64 127 96 */\r
1087 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1088 /* 159 128 191 160 223 192 255 224 */\r
1089 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1090 /* 287 256 319 288 351 320 383 352 */\r
1091 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1092 /* 415 384 447 416 479 448 511 480 */\r
1093 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1094 \r
1095 /* resvdDmaChannels */\r
1096 /* 31 0 63 32 */\r
1097 {0x3FFF0000u, 0x00000000u},\r
1098 \r
1099 /* resvdQdmaChannels */\r
1100 /* 31 0 */\r
1101 {0x00000000u},\r
1102 \r
1103 /* resvdTccs */\r
1104 /* 31 0 63 32 */\r
1105 {0x3FFF0000u, 0x00000000u},\r
1106 },\r
1107 \r
1108 /* Resources owned/reserved by region 2 */\r
1109 {\r
1110 /* ownPaRAMSets */\r
1111 /* 31 0 63 32 95 64 127 96 */\r
1112 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
1113 /* 159 128 191 160 223 192 255 224 */\r
1114 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1115 /* 287 256 319 288 351 320 383 352 */\r
1116 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1117 /* 415 384 447 416 479 448 511 480 */\r
1118 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1119 \r
1120 /* ownDmaChannels */\r
1121 /* 31 0 63 32 */\r
1122 {0x00000000u, 0x0000FFFFu},\r
1123 \r
1124 /* ownQdmaChannels */\r
1125 /* 31 0 */\r
1126 {0x00000030u},\r
1127 \r
1128 /* ownTccs */\r
1129 /* 31 0 63 32 */\r
1130 {0x00000000u, 0x0000FFFFu},\r
1131 \r
1132 /* resvdPaRAMSets */\r
1133 /* 31 0 63 32 95 64 127 96 */\r
1134 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
1135 /* 159 128 191 160 223 192 255 224 */\r
1136 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1137 /* 287 256 319 288 351 320 383 352 */\r
1138 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1139 /* 415 384 447 416 479 448 511 480 */\r
1140 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1141 \r
1142 /* resvdDmaChannels */\r
1143 /* 31 0 63 32 */\r
1144 {0x00000000u, 0x00003FFFu},\r
1145 \r
1146 /* resvdQdmaChannels */\r
1147 /* 31 0 */\r
1148 {0x00000000u},\r
1149 \r
1150 /* resvdTccs */\r
1151 /* 31 0 63 32 */\r
1152 {0x00000000u, 0x00003FFFu},\r
1153 },\r
1154 \r
1155 /* Resources owned/reserved by region 3 */\r
1156 {\r
1157 /* ownPaRAMSets */\r
1158 /* 31 0 63 32 95 64 127 96 */\r
1159 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,\r
1160 /* 159 128 191 160 223 192 255 224 */\r
1161 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1162 /* 287 256 319 288 351 320 383 352 */\r
1163 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1164 /* 415 384 447 416 479 448 511 480 */\r
1165 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},\r
1166 \r
1167 /* ownDmaChannels */\r
1168 /* 31 0 63 32 */\r
1169 {0x00000000u, 0xFFFF0000u},\r
1170 \r
1171 /* ownQdmaChannels */\r
1172 /* 31 0 */\r
1173 {0x000000C0u},\r
1174 \r
1175 /* ownTccs */\r
1176 /* 31 0 63 32 */\r
1177 {0x00000000u, 0xFFFF0000u},\r
1178 \r
1179 /* resvdPaRAMSets */\r
1180 /* 31 0 63 32 95 64 127 96 */\r
1181 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,\r
1182 /* 159 128 191 160 223 192 255 224 */\r
1183 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1184 /* 287 256 319 288 351 320 383 352 */\r
1185 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1186 /* 415 384 447 416 479 448 511 480 */\r
1187 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1188 \r
1189 /* resvdDmaChannels */\r
1190 /* 31 0 63 32 */\r
1191 {0x00000000u, 0x3FFF0000u},\r
1192 \r
1193 /* resvdQdmaChannels */\r
1194 /* 31 0 */\r
1195 {0x00000000u},\r
1196 \r
1197 /* resvdTccs */\r
1198 /* 31 0 63 32 */\r
1199 {0x00000000u, 0x3FFF0000u},\r
1200 },\r
1201 \r
1202 /* Resources owned/reserved by region 4 */\r
1203 {\r
1204 /* ownPaRAMSets */\r
1205 /* 31 0 63 32 95 64 127 96 */\r
1206 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1207 /* 159 128 191 160 223 192 255 224 */\r
1208 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1209 /* 287 256 319 288 351 320 383 352 */\r
1210 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1211 /* 415 384 447 416 479 448 511 480 */\r
1212 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1213 \r
1214 /* ownDmaChannels */\r
1215 /* 31 0 63 32 */\r
1216 {0x00000000u, 0x00000000u},\r
1217 \r
1218 /* ownQdmaChannels */\r
1219 /* 31 0 */\r
1220 {0x00000000u},\r
1221 \r
1222 /* ownTccs */\r
1223 /* 31 0 63 32 */\r
1224 {0x00000000u, 0x00000000u},\r
1225 \r
1226 /* resvdPaRAMSets */\r
1227 /* 31 0 63 32 95 64 127 96 */\r
1228 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1229 /* 159 128 191 160 223 192 255 224 */\r
1230 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1231 /* 287 256 319 288 351 320 383 352 */\r
1232 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1233 /* 415 384 447 416 479 448 511 480 */\r
1234 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1235 \r
1236 /* resvdDmaChannels */\r
1237 /* 31 0 63 32 */\r
1238 {0x00000000u, 0x00000000u},\r
1239 \r
1240 /* resvdQdmaChannels */\r
1241 /* 31 0 */\r
1242 {0x00000000u},\r
1243 \r
1244 /* resvdTccs */\r
1245 /* 31 0 63 32 */\r
1246 {0x00000000u, 0x00000000u},\r
1247 },\r
1248 \r
1249 /* Resources owned/reserved by region 5 */\r
1250 {\r
1251 /* ownPaRAMSets */\r
1252 /* 31 0 63 32 95 64 127 96 */\r
1253 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1254 /* 159 128 191 160 223 192 255 224 */\r
1255 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1256 /* 287 256 319 288 351 320 383 352 */\r
1257 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1258 /* 415 384 447 416 479 448 511 480 */\r
1259 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1260 \r
1261 /* ownDmaChannels */\r
1262 /* 31 0 63 32 */\r
1263 {0x00000000u, 0x00000000u},\r
1264 \r
1265 /* ownQdmaChannels */\r
1266 /* 31 0 */\r
1267 {0x00000000u},\r
1268 \r
1269 /* ownTccs */\r
1270 /* 31 0 63 32 */\r
1271 {0x00000000u, 0x00000000u},\r
1272 \r
1273 /* resvdPaRAMSets */\r
1274 /* 31 0 63 32 95 64 127 96 */\r
1275 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1276 /* 159 128 191 160 223 192 255 224 */\r
1277 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1278 /* 287 256 319 288 351 320 383 352 */\r
1279 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1280 /* 415 384 447 416 479 448 511 480 */\r
1281 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1282 \r
1283 /* resvdDmaChannels */\r
1284 /* 31 0 63 32 */\r
1285 {0x00000000u, 0x00000000u},\r
1286 \r
1287 /* resvdQdmaChannels */\r
1288 /* 31 0 */\r
1289 {0x00000000u},\r
1290 \r
1291 /* resvdTccs */\r
1292 /* 31 0 63 32 */\r
1293 {0x00000000u, 0x00000000u},\r
1294 },\r
1295 \r
1296 /* Resources owned/reserved by region 6 */\r
1297 {\r
1298 /* ownPaRAMSets */\r
1299 /* 31 0 63 32 95 64 127 96 */\r
1300 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1301 /* 159 128 191 160 223 192 255 224 */\r
1302 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1303 /* 287 256 319 288 351 320 383 352 */\r
1304 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1305 /* 415 384 447 416 479 448 511 480 */\r
1306 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1307 \r
1308 /* ownDmaChannels */\r
1309 /* 31 0 63 32 */\r
1310 {0x00000000u, 0x00000000u},\r
1311 \r
1312 /* ownQdmaChannels */\r
1313 /* 31 0 */\r
1314 {0x00000000u},\r
1315 \r
1316 /* ownTccs */\r
1317 /* 31 0 63 32 */\r
1318 {0x00000000u, 0x00000000u},\r
1319 \r
1320 /* resvdPaRAMSets */\r
1321 /* 31 0 63 32 95 64 127 96 */\r
1322 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1323 /* 159 128 191 160 223 192 255 224 */\r
1324 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1325 /* 287 256 319 288 351 320 383 352 */\r
1326 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1327 /* 415 384 447 416 479 448 511 480 */\r
1328 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1329 \r
1330 /* resvdDmaChannels */\r
1331 /* 31 0 63 32 */\r
1332 {0x00000000u, 0x00000000u},\r
1333 \r
1334 /* resvdQdmaChannels */\r
1335 /* 31 0 */\r
1336 {0x00000000u},\r
1337 \r
1338 /* resvdTccs */\r
1339 /* 31 0 63 32 */\r
1340 {0x00000000u, 0x00000000u},\r
1341 },\r
1342 \r
1343 /* Resources owned/reserved by region 7 */\r
1344 {\r
1345 /* ownPaRAMSets */\r
1346 /* 31 0 63 32 95 64 127 96 */\r
1347 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1348 /* 159 128 191 160 223 192 255 224 */\r
1349 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1350 /* 287 256 319 288 351 320 383 352 */\r
1351 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1352 /* 415 384 447 416 479 448 511 480 */\r
1353 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1354 \r
1355 /* ownDmaChannels */\r
1356 /* 31 0 63 32 */\r
1357 {0x00000000u, 0x00000000u},\r
1358 \r
1359 /* ownQdmaChannels */\r
1360 /* 31 0 */\r
1361 {0x00000000u},\r
1362 \r
1363 /* ownTccs */\r
1364 /* 31 0 63 32 */\r
1365 {0x00000000u, 0x00000000u},\r
1366 \r
1367 /* resvdPaRAMSets */\r
1368 /* 31 0 63 32 95 64 127 96 */\r
1369 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1370 /* 159 128 191 160 223 192 255 224 */\r
1371 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1372 /* 287 256 319 288 351 320 383 352 */\r
1373 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1374 /* 415 384 447 416 479 448 511 480 */\r
1375 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1376 \r
1377 /* resvdDmaChannels */\r
1378 /* 31 0 63 32 */\r
1379 {0x00000000u, 0x00000000u},\r
1380 \r
1381 /* resvdQdmaChannels */\r
1382 /* 31 0 */\r
1383 {0x00000000u},\r
1384 \r
1385 /* resvdTccs */\r
1386 /* 31 0 63 32 */\r
1387 {0x00000000u, 0x00000000u},\r
1388 },\r
1389 },\r
1390 \r
1391 /* EDMA3 INSTANCE# 2 */\r
1392 {\r
1393 /* Resources owned/reserved by region 0 */\r
1394 {\r
1395 /* ownPaRAMSets */\r
1396 /* 31 0 63 32 95 64 127 96 */\r
1397 {0x0000FFF0u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1398 /* 159 128 191 160 223 192 255 224 */\r
1399 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
1400 /* 287 256 319 288 351 320 383 352 */\r
1401 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1402 /* 415 384 447 416 479 448 511 480 */\r
1403 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1404 \r
1405 /* ownDmaChannels */\r
1406 /* 31 0 63 32 */\r
1407 {0x0000FFF0u, 0x00000000u},\r
1408 \r
1409 /* ownQdmaChannels */\r
1410 /* 31 0 */\r
1411 {0x00000003u},\r
1412 \r
1413 /* ownTccs */\r
1414 /* 31 0 63 32 */\r
1415 {0x0000FFF0u, 0x00000000u},\r
1416 \r
1417 /* resvdPaRAMSets */\r
1418 /* 31 0 63 32 95 64 127 96 */\r
1419 {0x00003FF0u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1420 /* 159 128 191 160 223 192 255 224 */\r
1421 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1422 /* 287 256 319 288 351 320 383 352 */\r
1423 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1424 /* 415 384 447 416 479 448 511 480 */\r
1425 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1426 \r
1427 /* resvdDmaChannels */\r
1428 /* 31 0 63 32 */\r
1429 {0x00003FF0u, 0x00000000u},\r
1430 \r
1431 /* resvdQdmaChannels */\r
1432 /* 31 0 */\r
1433 {0x00000000u},\r
1434 \r
1435 /* resvdTccs */\r
1436 /* 31 0 63 32 */\r
1437 {0x00003FF0u, 0x00000000u},\r
1438 },\r
1439 \r
1440 /* Resources owned/reserved by region 1 */\r
1441 {\r
1442 /* ownPaRAMSets */\r
1443 /* 31 0 63 32 95 64 127 96 */\r
1444 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1445 /* 159 128 191 160 223 192 255 224 */\r
1446 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1447 /* 287 256 319 288 351 320 383 352 */\r
1448 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
1449 /* 415 384 447 416 479 448 511 480 */\r
1450 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1451 \r
1452 /* ownDmaChannels */\r
1453 /* 31 0 63 32 */\r
1454 {0xFFFF0000u, 0x00000000u},\r
1455 \r
1456 /* ownQdmaChannels */\r
1457 /* 31 0 */\r
1458 {0x0000000Cu},\r
1459 \r
1460 /* ownTccs */\r
1461 /* 31 0 63 32 */\r
1462 {0xFFFF0000u, 0x00000000u},\r
1463 \r
1464 /* resvdPaRAMSets */\r
1465 /* 31 0 63 32 95 64 127 96 */\r
1466 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1467 /* 159 128 191 160 223 192 255 224 */\r
1468 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1469 /* 287 256 319 288 351 320 383 352 */\r
1470 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1471 /* 415 384 447 416 479 448 511 480 */\r
1472 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1473 \r
1474 /* resvdDmaChannels */\r
1475 /* 31 0 63 32 */\r
1476 {0x3FFF0000u, 0x00000000u},\r
1477 \r
1478 /* resvdQdmaChannels */\r
1479 /* 31 0 */\r
1480 {0x00000000u},\r
1481 \r
1482 /* resvdTccs */\r
1483 /* 31 0 63 32 */\r
1484 {0x3FFF0000u, 0x00000000u},\r
1485 },\r
1486 \r
1487 /* Resources owned/reserved by region 2 */\r
1488 {\r
1489 /* ownPaRAMSets */\r
1490 /* 31 0 63 32 95 64 127 96 */\r
1491 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
1492 /* 159 128 191 160 223 192 255 224 */\r
1493 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1494 /* 287 256 319 288 351 320 383 352 */\r
1495 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
1496 /* 415 384 447 416 479 448 511 480 */\r
1497 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1498 \r
1499 /* ownDmaChannels */\r
1500 /* 31 0 63 32 */\r
1501 {0x00000000u, 0x0000FFFFu},\r
1502 \r
1503 /* ownQdmaChannels */\r
1504 /* 31 0 */\r
1505 {0x00000030u},\r
1506 \r
1507 /* ownTccs */\r
1508 /* 31 0 63 32 */\r
1509 {0x00000000u, 0x0000FFFFu},\r
1510 \r
1511 /* resvdPaRAMSets */\r
1512 /* 31 0 63 32 95 64 127 96 */\r
1513 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
1514 /* 159 128 191 160 223 192 255 224 */\r
1515 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1516 /* 287 256 319 288 351 320 383 352 */\r
1517 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1518 /* 415 384 447 416 479 448 511 480 */\r
1519 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1520 \r
1521 /* resvdDmaChannels */\r
1522 /* 31 0 63 32 */\r
1523 {0x00000000u, 0x00003FFFu},\r
1524 \r
1525 /* resvdQdmaChannels */\r
1526 /* 31 0 */\r
1527 {0x00000000u},\r
1528 \r
1529 /* resvdTccs */\r
1530 /* 31 0 63 32 */\r
1531 {0x00000000u, 0x00003FFFu},\r
1532 },\r
1533 \r
1534 /* Resources owned/reserved by region 3 */\r
1535 {\r
1536 /* ownPaRAMSets */\r
1537 /* 31 0 63 32 95 64 127 96 */\r
1538 {0x0000000Fu, 0xFFFF00FFu, 0x00000000u, 0x00000000u,\r
1539 /* 159 128 191 160 223 192 255 224 */\r
1540 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1541 /* 287 256 319 288 351 320 383 352 */\r
1542 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1543 /* 415 384 447 416 479 448 511 480 */\r
1544 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},\r
1545 \r
1546 /* ownDmaChannels */\r
1547 /* 31 0 63 32 */\r
1548 {0x0000000Fu, 0xFFFF00FFu},\r
1549 \r
1550 /* ownQdmaChannels */\r
1551 /* 31 0 */\r
1552 {0x000000C0u},\r
1553 \r
1554 /* ownTccs */\r
1555 /* 31 0 63 32 */\r
1556 {0x0000000Fu, 0xFFFF00FFu},\r
1557 \r
1558 /* resvdPaRAMSets */\r
1559 /* 31 0 63 32 95 64 127 96 */\r
1560 {0x0000000Fu, 0x0303003Cu, 0x00000000u, 0x00000000u,\r
1561 /* 159 128 191 160 223 192 255 224 */\r
1562 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1563 /* 287 256 319 288 351 320 383 352 */\r
1564 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1565 /* 415 384 447 416 479 448 511 480 */\r
1566 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1567 \r
1568 /* resvdDmaChannels */\r
1569 /* 31 0 63 32 */\r
1570 {0x0000000Fu, 0x0303003Cu},\r
1571 \r
1572 /* resvdQdmaChannels */\r
1573 /* 31 0 */\r
1574 {0x00000000u},\r
1575 \r
1576 /* resvdTccs */\r
1577 /* 31 0 63 32 */\r
1578 {0x0000000Fu, 0x0303003Cu},\r
1579 },\r
1580 \r
1581 /* Resources owned/reserved by region 4 */\r
1582 {\r
1583 /* ownPaRAMSets */\r
1584 /* 31 0 63 32 95 64 127 96 */\r
1585 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1586 /* 159 128 191 160 223 192 255 224 */\r
1587 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1588 /* 287 256 319 288 351 320 383 352 */\r
1589 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1590 /* 415 384 447 416 479 448 511 480 */\r
1591 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1592 \r
1593 /* ownDmaChannels */\r
1594 /* 31 0 63 32 */\r
1595 {0x00000000u, 0x00000000u},\r
1596 \r
1597 /* ownQdmaChannels */\r
1598 /* 31 0 */\r
1599 {0x00000000u},\r
1600 \r
1601 /* ownTccs */\r
1602 /* 31 0 63 32 */\r
1603 {0x00000000u, 0x00000000u},\r
1604 \r
1605 /* resvdPaRAMSets */\r
1606 /* 31 0 63 32 95 64 127 96 */\r
1607 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1608 /* 159 128 191 160 223 192 255 224 */\r
1609 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1610 /* 287 256 319 288 351 320 383 352 */\r
1611 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1612 /* 415 384 447 416 479 448 511 480 */\r
1613 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1614 \r
1615 /* resvdDmaChannels */\r
1616 /* 31 0 63 32 */\r
1617 {0x00000000u, 0x00000000u},\r
1618 \r
1619 /* resvdQdmaChannels */\r
1620 /* 31 0 */\r
1621 {0x00000000u},\r
1622 \r
1623 /* resvdTccs */\r
1624 /* 31 0 63 32 */\r
1625 {0x00000000u, 0x00000000u},\r
1626 },\r
1627 \r
1628 /* Resources owned/reserved by region 5 */\r
1629 {\r
1630 /* ownPaRAMSets */\r
1631 /* 31 0 63 32 95 64 127 96 */\r
1632 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1633 /* 159 128 191 160 223 192 255 224 */\r
1634 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1635 /* 287 256 319 288 351 320 383 352 */\r
1636 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1637 /* 415 384 447 416 479 448 511 480 */\r
1638 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1639 \r
1640 /* ownDmaChannels */\r
1641 /* 31 0 63 32 */\r
1642 {0x00000000u, 0x00000000u},\r
1643 \r
1644 /* ownQdmaChannels */\r
1645 /* 31 0 */\r
1646 {0x00000000u},\r
1647 \r
1648 /* ownTccs */\r
1649 /* 31 0 63 32 */\r
1650 {0x00000000u, 0x00000000u},\r
1651 \r
1652 /* resvdPaRAMSets */\r
1653 /* 31 0 63 32 95 64 127 96 */\r
1654 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1655 /* 159 128 191 160 223 192 255 224 */\r
1656 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1657 /* 287 256 319 288 351 320 383 352 */\r
1658 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1659 /* 415 384 447 416 479 448 511 480 */\r
1660 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1661 \r
1662 /* resvdDmaChannels */\r
1663 /* 31 0 63 32 */\r
1664 {0x00000000u, 0x00000000u},\r
1665 \r
1666 /* resvdQdmaChannels */\r
1667 /* 31 0 */\r
1668 {0x00000000u},\r
1669 \r
1670 /* resvdTccs */\r
1671 /* 31 0 63 32 */\r
1672 {0x00000000u, 0x00000000u},\r
1673 },\r
1674 \r
1675 /* Resources owned/reserved by region 6 */\r
1676 {\r
1677 /* ownPaRAMSets */\r
1678 /* 31 0 63 32 95 64 127 96 */\r
1679 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1680 /* 159 128 191 160 223 192 255 224 */\r
1681 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1682 /* 287 256 319 288 351 320 383 352 */\r
1683 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1684 /* 415 384 447 416 479 448 511 480 */\r
1685 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1686 \r
1687 /* ownDmaChannels */\r
1688 /* 31 0 63 32 */\r
1689 {0x00000000u, 0x00000000u},\r
1690 \r
1691 /* ownQdmaChannels */\r
1692 /* 31 0 */\r
1693 {0x00000000u},\r
1694 \r
1695 /* ownTccs */\r
1696 /* 31 0 63 32 */\r
1697 {0x00000000u, 0x00000000u},\r
1698 \r
1699 /* resvdPaRAMSets */\r
1700 /* 31 0 63 32 95 64 127 96 */\r
1701 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1702 /* 159 128 191 160 223 192 255 224 */\r
1703 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1704 /* 287 256 319 288 351 320 383 352 */\r
1705 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1706 /* 415 384 447 416 479 448 511 480 */\r
1707 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1708 \r
1709 /* resvdDmaChannels */\r
1710 /* 31 0 63 32 */\r
1711 {0x00000000u, 0x00000000u},\r
1712 \r
1713 /* resvdQdmaChannels */\r
1714 /* 31 0 */\r
1715 {0x00000000u},\r
1716 \r
1717 /* resvdTccs */\r
1718 /* 31 0 63 32 */\r
1719 {0x00000000u, 0x00000000u},\r
1720 },\r
1721 \r
1722 /* Resources owned/reserved by region 7 */\r
1723 {\r
1724 /* ownPaRAMSets */\r
1725 /* 31 0 63 32 95 64 127 96 */\r
1726 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1727 /* 159 128 191 160 223 192 255 224 */\r
1728 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1729 /* 287 256 319 288 351 320 383 352 */\r
1730 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1731 /* 415 384 447 416 479 448 511 480 */\r
1732 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1733 \r
1734 /* ownDmaChannels */\r
1735 /* 31 0 63 32 */\r
1736 {0x00000000u, 0x00000000u},\r
1737 \r
1738 /* ownQdmaChannels */\r
1739 /* 31 0 */\r
1740 {0x00000000u},\r
1741 \r
1742 /* ownTccs */\r
1743 /* 31 0 63 32 */\r
1744 {0x00000000u, 0x00000000u},\r
1745 \r
1746 /* resvdPaRAMSets */\r
1747 /* 31 0 63 32 95 64 127 96 */\r
1748 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1749 /* 159 128 191 160 223 192 255 224 */\r
1750 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1751 /* 287 256 319 288 351 320 383 352 */\r
1752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1753 /* 415 384 447 416 479 448 511 480 */\r
1754 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1755 \r
1756 /* resvdDmaChannels */\r
1757 /* 31 0 63 32 */\r
1758 {0x00000000u, 0x00000000u},\r
1759 \r
1760 /* resvdQdmaChannels */\r
1761 /* 31 0 */\r
1762 {0x00000000u},\r
1763 \r
1764 /* resvdTccs */\r
1765 /* 31 0 63 32 */\r
1766 {0x00000000u, 0x00000000u},\r
1767 },\r
1768 },\r
1769 };\r
1770 \r
1771 /* End of File */\r