index f5e1cff9809d85fd0d2a5891bfd23c481818c451..803c6061f718422ea91bea353bed86f168c0b937 100644 (file)
/*\r
*\r
- * Copyright (C) 2010-2013 Texas Instruments Incorporated - http://www.ti.com/ \r
+ * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com/\r
* \r
* \r
* Redistribution and use in source and binary forms, with or without \r
int cpswSimTest = 0;\r
int cpswLpbkMode = CPSW_LOOPBACK_NONE;\r
#endif\r
-int cpswEvm6678 = 0;\r
+\r
+uint32_t gNum_Mac_Ports;\r
\r
/** ============================================================================\r
- * @n@b Init_SGMII_SERDES\r
+ * @n@b initSGMII\r
*\r
* @b Description\r
- * @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz\r
- * reference clock.\r
+ * @n SGMII peripheral initialization code.\r
*\r
* @param[in]\r
- * @n None\r
+ * @n macPortNum MAC port number for which the SGMII port setup must\r
+ * be performed.\r
*\r
* @return\r
* @n None\r
* =============================================================================\r
*/\r
-static int32_t initSGMIISerdes(void)\r
+static int32_t initSGMII (uint32_t macPortNum)\r
{\r
- CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
\r
- if(!cpswSimTest)\r
+ CSL_SGMII_ADVABILITY sgmiiCfg;\r
+ CSL_SGMII_STATUS sgmiiStatus;\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
+ /* Configure SGMII Port 1 only since it is connected to RJ45 at all known EVMs */\r
+ if(cpswSimTest || (macPortNum == 1))\r
{\r
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;\r
+#endif\r
+ /* Reset the port before configuring it */\r
+ CSL_SGMII_doSoftReset (macPortNum);\r
+ while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);\r
\r
- memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));\r
- serdes_lane_enable_params.base_addr = CSL_NETCP_SERDES_CFG_REGS;\r
- serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
- serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
- serdes_lane_enable_params.num_lanes = UTF_NUM_MAC_PORTS;\r
- serdes_lane_enable_params.phy_type = SERDES_SGMII;\r
- for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ /* Hold the port in soft reset and set up\r
+ * the SGMII control register:\r
+ * (1) Enable Master Mode (default)\r
+ * (2) Enable Auto-negotiation\r
+ */\r
+ CSL_SGMII_startRxTxSoftReset (macPortNum);\r
+ if (cpswLpbkMode == CPSW_LOOPBACK_NONE)\r
{\r
- serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
- serdes_lane_enable_params.loopback_mode[i] = lpbk_mode;\r
- \r
- /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
- serdes_lane_enable_params.rx_coeff.att_start[i] = 7;\r
- serdes_lane_enable_params.rx_coeff.boost_start[i] = 5;\r
-\r
- /* For higher speeds PHY-A, force attenuation and boost values */\r
- serdes_lane_enable_params.rx_coeff.force_att_val[i] = 1;\r
- serdes_lane_enable_params.rx_coeff.force_boost_val[i] = 1;\r
-\r
- /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
- serdes_lane_enable_params.tx_coeff.cm_coeff[i] = 0;\r
- serdes_lane_enable_params.tx_coeff.c1_coeff[i] = 0;\r
- serdes_lane_enable_params.tx_coeff.c2_coeff[i] = 0;\r
- serdes_lane_enable_params.tx_coeff.tx_att[i] = 12;\r
- serdes_lane_enable_params.tx_coeff.tx_vreg[i] = 4;\r
+ CSL_SGMII_disableMasterMode (macPortNum);\r
}\r
- \r
- serdes_lane_enable_params.lane_mask = (1 << serdes_lane_enable_params.num_lanes) - 1;\r
- serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
- \r
- /* Att and Boost values are obtained through Serdes Diagnostic PRBS calibration test */\r
- /* For higher speeds PHY-A, force attenuation and boost values */\r
- serdes_lane_enable_params.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params.base_addr,\r
- serdes_lane_enable_params.ref_clock,\r
- serdes_lane_enable_params.linkrate);\r
-\r
- if (csl_retval != 0)\r
+ else\r
{\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
+ CSL_SGMII_enableMasterMode (macPortNum);\r
\r
- /* Common Init Mode */\r
- /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
- /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
- serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
- serdes_lane_enable_params.lane_mask = 0xF;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Common Init\n");\r
- exit(0);\r
- }\r
- System_printf("SGMII Serdes Common Init Complete\n");\r
-\r
- /* Lane Init Mode */\r
- /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
- iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
- /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
- serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
- for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
- {\r
- serdes_lane_enable_params.lane_mask = 1<<i;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Enable Init\n");\r
- exit(0);\r
+ if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)\r
+ {\r
+ CSL_SGMII_enableLoopback (macPortNum);\r
+ }\r
}\r
- System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
- }\r
-\r
\r
-#elif defined(DEVICE_K2E)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
- int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
- CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
-\r
- memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
- memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+ /* Setup the Advertised Ability register for this port:\r
+ * (1) Enable Full duplex mode\r
+ * (2) Enable Auto Negotiation\r
+ */\r
+ sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;\r
+ sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
+ CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
\r
- serdes_lane_enable_params1.base_addr = CSL_NETCP_SERDES_0_CFG_REGS;\r
- serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
- serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
- serdes_lane_enable_params1.num_lanes = numPort1;\r
- serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
- serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+ CSL_SGMII_enableAutoNegotiation (macPortNum);\r
+ CSL_SGMII_endRxTxSoftReset (macPortNum);\r
\r
- for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ /* Wait for SGMII Link */\r
+ if (!cpswSimTest)\r
{\r
- serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
- serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
-\r
- /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
- serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
- serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+ do\r
+ {\r
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
+ } while (sgmiiStatus.bIsLinkUp != 1);\r
\r
- /* For higher speeds PHY-A, force attenuation and boost values */\r
- serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
- serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+ /* Wait for SGMII Autonegotiation to complete without error */\r
+ do\r
+ {\r
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
+ if (sgmiiStatus.bIsAutoNegError != 0)\r
+ return -1;\r
+ } while (sgmiiStatus.bIsAutoNegComplete != 1);\r
\r
- /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
- serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
- serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
- serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
- serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
- serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ /*\r
+ * May need to wait some more time for the external PHY to be ready to transmit packets reliabily.\r
+ * It is possible to access the PHY status register through the MDIO interface to check when\r
+ * the PHY is ready.\r
+ * To avoid platform-dependent code, we just introduce about 2ms wait here\r
+ */\r
+ if((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))\r
+ utilCycleDelay(2000000);\r
}\r
- serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
- serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
+ }\r
+#endif\r
+ /* All done with configuration. Return Now. */\r
+ return 0;\r
+}\r
\r
- serdes_lane_enable_params2.base_addr = CSL_NETCP_SERDES_1_CFG_REGS;\r
- serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
- serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
- serdes_lane_enable_params2.num_lanes = numPort2;\r
- serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
- serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
- for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
- {\r
- serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
- serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
- /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
- serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
- serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+/** ============================================================================\r
+ * @n@b initMAC\r
+ *\r
+ * @b Description\r
+ * @n This API initializes the CPGMAC Sliver (MAC Port) port.\r
+ *\r
+ * @param[in]\r
+ * @n macPortNum MAC port number for which the initialization must be done.\r
+ *\r
+ * @param[in]\r
+ * @n macAddress MAC address to configure on this port.\r
+ *\r
+ * @param[in]\r
+ * @n mtu Maximum Frame length to configure on this port.\r
+ *\r
+ * @return\r
+ * @n None\r
+ * =============================================================================\r
+ */\r
+static int initMAC (uint32_t macPortNum, uint8_t macAddress[6], uint32_t mtu)\r
+{\r
+ /* Reset MAC Sliver 0 */\r
+ CSL_CPGMAC_SL_resetMac (macPortNum);\r
+ while (CSL_CPGMAC_SL_isMACResetDone (macPortNum) != TRUE);\r
\r
- /* For higher speeds PHY-A, force attenuation and boost values */\r
- serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
- serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+ /* Setup the MAC Control Register for this port:\r
+ * (1) Enable Full duplex\r
+ * (2) Enable GMII\r
+ * (3) Enable Gigabit\r
+ * (4) Enable External Configuration. This enables\r
+ * the "Full duplex" and "Gigabit" settings to be\r
+ * controlled externally from SGMII\r
+ * (5) Don't enable any control/error/short frames\r
+ */\r
+ CSL_CPGMAC_SL_enableFullDuplex (macPortNum);\r
+ CSL_CPGMAC_SL_enableGMII (macPortNum);\r
+ CSL_CPGMAC_SL_enableGigabit (macPortNum);\r
+ CSL_CPGMAC_SL_enableExtControl (macPortNum);\r
\r
- /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
- serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
- serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
- serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
- serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
- serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
- }\r
+ /* Configure VLAN ID/CFI/Priority.\r
+ *\r
+ * For now, we are not using VLANs so just configure them\r
+ * to all zeros.\r
+ */\r
+ CSL_CPSW_setPortVlanReg (macPortNum, 0, 0, 0);\r
\r
- serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
- serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+ /* Configure the Receive Maximum length on this port,\r
+ * i.e., the maximum size the port can receive without\r
+ * any errors.\r
+ *\r
+ * Set the Rx Max length to the MTU configured for the\r
+ * interface.\r
+ */\r
+ CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu);\r
\r
+ /* Done setting up the MAC port */\r
+ return 0;\r
\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
- serdes_lane_enable_params1.ref_clock,\r
- serdes_lane_enable_params1.linkrate); /* 4 port switch1 */\r
\r
- if (numPort2)\r
- {\r
- csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
- serdes_lane_enable_params2.ref_clock,\r
- serdes_lane_enable_params2.linkrate); /* 4 port switch2 */\r
- } \r
- \r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
+}\r
\r
- /* Common Init Mode */\r
- /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
- /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
- serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
- serdes_lane_enable_params1.lane_mask = 0xF;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Common Init\n");\r
- exit(0);\r
- }\r
- System_printf("SGMII Serdes Common Init Complete\n");\r
+/** ============================================================================\r
+ * @n@b initMDIO\r
+ *\r
+ * @b Description\r
+ * @n Not supported at moment. MDIO is not simulated yet.\r
+ *\r
+ * @param[in]\r
+ * @n None\r
+ *\r
+ * @return\r
+ * @n None\r
+ * =============================================================================\r
+ */\r
+static void initMDIO (void)\r
+{\r
+ /* Return success. */\r
+ return;\r
+}\r
\r
- /* Lane Init Mode */\r
- /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
- iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
- /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
- serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
- for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+/** ============================================================================\r
+ * @n@b initSwitch\r
+ *\r
+ * @b Description\r
+ * @n This API sets up the ethernet switch subsystem and its Address Lookup\r
+ * Engine (ALE) in "Switch" mode.\r
+ *\r
+ * @param[in]\r
+ * @n mtu Maximum Frame length to configure on the switch.\r
+ *\r
+ * @return\r
+ * @n None\r
+ * =============================================================================\r
+ */\r
+static void initSwitch (uint32_t mtu)\r
+{\r
+ CSL_CPSW_PORTSTAT portStatCfg;\r
+\r
+ /* Enable the CPPI port, i.e., port 0 that does all\r
+ * the data streaming in/out of EMAC.\r
+ */\r
+ CSL_CPSW_enablePort0 ();\r
+ CSL_CPSW_disableVlanAware ();\r
+ CSL_CPSW_setPort0VlanReg (0, 0, 0);\r
+ CSL_CPSW_setPort0RxMaxLen (mtu);\r
+\r
+ /* Enable statistics on both the port groups:\r
+ *\r
+ * MAC Sliver ports - Port 1, Port 2\r
+ * CPPI Port - Port 0\r
+ */\r
+ #if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
+ portStatCfg.p0AStatEnable = 1;\r
+ portStatCfg.p0BStatEnable = 1;\r
+ portStatCfg.p1StatEnable = 1;\r
+ portStatCfg.p2StatEnable = 1;\r
+ #else\r
+ portStatCfg.p0StatEnable = 1;\r
+ portStatCfg.p1StatEnable = 1;\r
+ portStatCfg.p2StatEnable = 1;\r
+ portStatCfg.p3StatEnable = 1;\r
+ portStatCfg.p4StatEnable = 1;\r
+ portStatCfg.p5StatEnable = 1;\r
+ portStatCfg.p6StatEnable = 1;\r
+ portStatCfg.p7StatEnable = 1;\r
+ portStatCfg.p8StatEnable = 1;\r
+ #endif\r
+ CSL_CPSW_setPortStatsEnableReg (&portStatCfg);\r
+\r
+ /* Setup the Address Lookup Engine (ALE) Configuration:\r
+ * (1) Enable ALE.\r
+ * (2) Clear stale ALE entries.\r
+ * (3) Disable VLAN Aware lookups in ALE since\r
+ * we are not using VLANs by default.\r
+ * (4) No Flow control\r
+ * (5) Configure the Unknown VLAN processing\r
+ * properties for the switch, i.e., which\r
+ * ports to send the packets to.\r
+ */\r
+ CSL_CPSW_enableAle ();\r
+ CSL_CPSW_clearAleTable ();\r
+\r
+ CSL_CPSW_disableAleVlanAware ();\r
+ CSL_CPSW_disableAleTxRateLimit ();\r
+ CSL_CPSW_setAlePrescaleReg (125000000u/1000u);\r
+ CSL_CPSW_setAleUnkownVlanReg (7, 3, 3, 7);\r
+\r
+ if(cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
+ CSL_CPSW_enableAleBypass();\r
+\r
+ /* Done with switch configuration */\r
+ return;\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b switch_update_addr\r
+ *\r
+ * @b Description\r
+ * @n This API add/delete entries in the Address Lookup Engine (ALE) in "Switch" mode.\r
+ *\r
+ * @param[in]\r
+ * @n portNum Switch port number.\r
+\r
+ * @param[in]\r
+ * @n macAddress MAC address to configure on the switch.\r
+ *\r
+ * @param[in]\r
+ * @n add 0:add; 1:delete.\r
+ *\r
+ * @return\r
+ * @n None\r
+ *\r
+ * @Note It supports "add" operation only now.\r
+ * =============================================================================\r
+ */\r
+static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t add)\r
+{\r
+ Uint32 i;\r
+ CSL_CPSW_ALE_PORTCONTROL alePortControlCfg;\r
+ CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;\r
+\r
+\r
+ /* Configure the address in "Learning"/"Forward" state */\r
+ alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;\r
+ alePortControlCfg.dropUntaggedEnable = 0;\r
+ alePortControlCfg.vidIngressCheckEnable = 0;\r
+ alePortControlCfg.noLearnModeEnable = (cpswLpbkMode != CPSW_LOOPBACK_NONE)?1:0;\r
+ alePortControlCfg.mcastLimit = 0;\r
+ alePortControlCfg.bcastLimit = 0;\r
+\r
+ CSL_CPSW_setAlePortControlReg (portNum, &alePortControlCfg);\r
+\r
+ /*\r
+ * The following code is required for device simulator only.\r
+ * It is also served as an example of adding MAC address to the ALE table manually\r
+ */\r
+\r
+ if (cpswSimTest)\r
+ {\r
+ /* Program the ALE with the MAC address.\r
+ *\r
+ * The ALE entries determine the switch port to which any\r
+ * matching received packet must be forwarded to.\r
+ */\r
+ /* Get the next free ALE entry to program */\r
+ for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++)\r
{\r
- serdes_lane_enable_params1.lane_mask = 1<<i;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
- if (lane_retval != 0)\r
+ if (CSL_CPSW_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)\r
{\r
- System_printf ("Invalid Serdes Lane Enable Init\n");\r
- exit(0);\r
+ /* Found a free entry */\r
+ break;\r
}\r
- System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
}\r
-\r
- if(numPort2)\r
+ if (i == CSL_CPSW_NUMALE_ENTRIES)\r
{\r
- /* Common Init Mode */\r
- /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
- /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
- serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
- serdes_lane_enable_params2.lane_mask = 0xF;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Common Init\n");\r
- exit(0);\r
- }\r
- System_printf("SGMII Serdes Common Init Complete\n");\r
+ /* No free ALE entry found. return error. */\r
+ return -1;\r
+ }\r
+ else\r
+ {\r
+ /* Found a free ALE entry to program our MAC address */\r
+ memcpy (ucastAddrCfg.macAddress, macAddress, 6); // Set the MAC address\r
+ ucastAddrCfg.ucastType = ALE_UCASTTYPE_UCAST_NOAGE; // Add a permanent unicast address entryALE_UCASTTYPE_UCAST_NOAGE.\r
+ ucastAddrCfg.secureEnable = FALSE;\r
+ ucastAddrCfg.blockEnable = FALSE;\r
+ ucastAddrCfg.portNumber = portNum; // Add the ALE entry for this port\r
\r
- /* Lane Init Mode */\r
- /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
- iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
- /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
- serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
- for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
- {\r
- serdes_lane_enable_params2.lane_mask = 1<<i;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Enable Init\n");\r
- exit(0);\r
- }\r
- System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
- }\r
+ /* Setup the ALE entry for this port's MAC address */\r
+ CSL_CPSW_setAleUnicastAddrEntry (i, &ucastAddrCfg);\r
}\r
+ }\r
\r
-#elif defined(DEVICE_K2L)\r
- uint32_t i;\r
+ /* Done with upading address */\r
+ return 0;\r
+}\r
+\r
+/** ============================================================================\r
+ * @n@b Init_SGMII_SERDES\r
+ *\r
+ * @b Description\r
+ * @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz\r
+ * reference clock.\r
+ *\r
+ * @param[in]\r
+ * @n None\r
+ *\r
+ * @return\r
+ * @n None\r
+ * =============================================================================\r
+ */\r
+static int32_t initSGMIISerdes(void)\r
+{\r
+\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES || cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+\r
+ if(!cpswSimTest)\r
+ {\r
+#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
CSL_SERDES_RESULT csl_retval;\r
CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- uint32_t serdes_mux_ethernet_sel;\r
- int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
- int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;\r
+ uint32_t i;\r
+\r
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));\r
+ serdes_lane_enable_params.base_addr = CSL_NETCP_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params.num_lanes = gNum_Mac_Ports;\r
+ serdes_lane_enable_params.phy_type = SERDES_SGMII;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params.loopback_mode[i] = lpbk_mode;\r
+ \r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ \r
+ /* if the system has 4 lanes, lane mask = 0xF. If the system has 2 lanes, lane mask = 0x3 etc */\r
+ serdes_lane_enable_params.lane_mask = (1 << serdes_lane_enable_params.num_lanes) - 1;\r
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+ \r
+ /* Att and Boost values are obtained through Serdes Diagnostic PRBS calibration test */\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ /* CMU, COMLANE, and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params.base_addr,\r
+ serdes_lane_enable_params.ref_clock,\r
+ serdes_lane_enable_params.linkrate);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lanes Init Complete\n");\r
\r
\r
+#elif defined(DEVICE_K2E)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = 0;\r
+ CSL_SERDES_STATUS pllstat;\r
+ int numPort1 = (gNum_Mac_Ports > 4)?4:gNum_Mac_Ports;\r
+ int numPort2 = (gNum_Mac_Ports > 4)?gNum_Mac_Ports - 4:0;\r
+ \r
CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
\r
memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
\r
- serdes_lane_enable_params1.base_addr = CSL_CSISC2_2_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params1.base_addr = CSL_NETCP_SERDES_0_CFG_REGS;\r
serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
- serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
serdes_lane_enable_params1.num_lanes = numPort1;\r
serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
\r
for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
{\r
- serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
\r
/* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
}\r
- serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ /* if the system has 4 lanes, lane mask = 0xF. If the system has 2 lanes, lane mask = 0x3 etc */\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_NETCP_SERDES_1_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ /* if the system has 4 lanes, lane mask = 0xF. If the system has 2 lanes, lane mask = 0x3 etc */\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* 4 port switch1 */\r
+\r
+ if (numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* 4 port switch2 */\r
+ } \r
+ \r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lanes Init Complete\n");\r
+\r
+ if(numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lanes Init Complete\n");\r
+ }\r
+\r
+#elif defined(DEVICE_K2L)\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ uint32_t serdes_mux_ethernet_sel, i;\r
+ int numPort1 = (gNum_Mac_Ports > 2)?2:gNum_Mac_Ports;\r
+ int numPort2 = (gNum_Mac_Ports > 2)?gNum_Mac_Ports - 2:0;\r
+ \r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_CSISC2_2_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ /* if the system has 4 lanes, lane mask = 0xF. If the system has 2 lanes, lane mask = 0x3 etc */\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
\r
serdes_lane_enable_params2.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;\r
serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
}\r
- serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ /* if the system has 4 lanes, lane mask = 0xF. If the system has 2 lanes, lane mask = 0x3 etc */\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
\r
\r
} \r
\r
/* Common Init Mode */\r
- /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
- /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ /* Iteration Mode needs to be set to Common Init Mode first */\r
serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
- serdes_lane_enable_params1.lane_mask = 0xF;\r
lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
if (lane_retval != 0)\r
{\r
\r
/* Lane Init Mode */\r
/* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
- iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
- /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT */\r
serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
- for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
{\r
- serdes_lane_enable_params1.lane_mask = 1<<i;\r
- lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Enable Init\n");\r
- exit(0);\r
- }\r
- System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
}\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
\r
- if(serdes_mux_ethernet_sel && numPort2)\r
- {\r
+ if(serdes_mux_ethernet_sel && numPort2)\r
+ {\r
/* Common Init Mode */\r
- /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
- /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ /* Iteration Mode needs to be set to Common Init Mode first */\r
serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
- serdes_lane_enable_params2.lane_mask = 0xF;\r
lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
if (lane_retval != 0)\r
{\r
\r
/* Lane Init Mode */\r
/* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
- iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
- /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT */\r
serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
- for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
- {\r
- serdes_lane_enable_params2.lane_mask = 1<<i;\r
lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
if (lane_retval != 0)\r
{\r
System_printf ("Invalid Serdes Lane Enable Init\n");\r
exit(0);\r
}\r
- System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
- }\r
- }\r
-#endif\r
-\r
- }\r
+ System_printf("SGMII Serdes Lanes Init Complete\n");\r
+ }\r
\r
- /* SGMII SERDES Configuration complete. Return. */\r
- return 0;\r
-}\r
-/** ============================================================================\r
- * @n@b initSGMII\r
- *\r
- * @b Description\r
- * @n SGMII peripheral initialization code.\r
- *\r
- * @param[in]\r
- * @n macPortNum MAC port number for which the SGMII port setup must\r
- * be performed.\r
- *\r
- * @return\r
- * @n None\r
- * =============================================================================\r
- */\r
-static int32_t initSGMII (uint32_t macPortNum)\r
-{\r
- \r
- CSL_SGMII_ADVABILITY sgmiiCfg;\r
- CSL_SGMII_STATUS sgmiiStatus;\r
-#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
- /* Configure SGMII Port 1 only since it is connected to RJ45 at all known EVMs */\r
- if(cpswSimTest || (macPortNum == 1))\r
- {\r
#endif\r
- /* Reset the port before configuring it */\r
- CSL_SGMII_doSoftReset (macPortNum);\r
- while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);\r
-\r
- /* Hold the port in soft reset and set up\r
- * the SGMII control register:\r
- * (1) Enable Master Mode (default)\r
- * (2) Enable Auto-negotiation\r
- */\r
- CSL_SGMII_startRxTxSoftReset (macPortNum);\r
- if (cpswLpbkMode == CPSW_LOOPBACK_NONE)\r
- {\r
- CSL_SGMII_disableMasterMode (macPortNum);\r
- }\r
- else\r
- {\r
- CSL_SGMII_enableMasterMode (macPortNum);\r
-\r
- if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)\r
- {\r
- CSL_SGMII_enableLoopback (macPortNum);\r
- }\r
- }\r
-\r
- /* Setup the Advertised Ability register for this port:\r
- * (1) Enable Full duplex mode\r
- * (2) Enable Auto Negotiation\r
- */\r
- sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;\r
- sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
- CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
-\r
- CSL_SGMII_enableAutoNegotiation (macPortNum);\r
- CSL_SGMII_endRxTxSoftReset (macPortNum);\r
-\r
- /* Wait for SGMII Link */\r
- if (!cpswSimTest)\r
- {\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- } while (sgmiiStatus.bIsLinkUp != 1);\r
-\r
- /* Wait for SGMII Autonegotiation to complete without error */\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- if (sgmiiStatus.bIsAutoNegError != 0)\r
- return -1;\r
- } while (sgmiiStatus.bIsAutoNegComplete != 1);\r
\r
- /*\r
- * May need to wait some more time for the external PHY to be ready to transmit packets reliabily.\r
- * It is possible to access the PHY status register through the MDIO interface to check when\r
- * the PHY is ready.\r
- * To avoid platform-dependent code, we just introduce about 2ms wait here\r
- */\r
- if((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))\r
- utilCycleDelay(2000000);\r
- }\r
-#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
}\r
-#endif\r
- /* All done with configuration. Return Now. */\r
- return 0;\r
-}\r
-\r
-/** ============================================================================\r
- * @n@b initMAC\r
- *\r
- * @b Description\r
- * @n This API initializes the CPGMAC Sliver (MAC Port) port.\r
- *\r
- * @param[in]\r
- * @n macPortNum MAC port number for which the initialization must be done.\r
- *\r
- * @param[in]\r
- * @n macAddress MAC address to configure on this port.\r
- *\r
- * @param[in]\r
- * @n mtu Maximum Frame length to configure on this port.\r
- *\r
- * @return\r
- * @n None\r
- * =============================================================================\r
- */\r
-static int initMAC (uint32_t macPortNum, uint8_t macAddress[6], uint32_t mtu)\r
-{\r
- /* Reset MAC Sliver 0 */\r
- CSL_CPGMAC_SL_resetMac (macPortNum);\r
- while (CSL_CPGMAC_SL_isMACResetDone (macPortNum) != TRUE);\r
-\r
- /* Setup the MAC Control Register for this port:\r
- * (1) Enable Full duplex\r
- * (2) Enable GMII\r
- * (3) Enable Gigabit\r
- * (4) Enable External Configuration. This enables\r
- * the "Full duplex" and "Gigabit" settings to be\r
- * controlled externally from SGMII\r
- * (5) Don't enable any control/error/short frames\r
- */\r
- CSL_CPGMAC_SL_enableFullDuplex (macPortNum);\r
- CSL_CPGMAC_SL_enableGMII (macPortNum);\r
- CSL_CPGMAC_SL_enableGigabit (macPortNum);\r
- CSL_CPGMAC_SL_enableExtControl (macPortNum);\r
-\r
- /* Configure VLAN ID/CFI/Priority.\r
- *\r
- * For now, we are not using VLANs so just configure them\r
- * to all zeros.\r
- */\r
- CSL_CPSW_nGF_setPortVlanReg (macPortNum, 0, 0, 0);\r
-\r
- /* Configure the Receive Maximum length on this port,\r
- * i.e., the maximum size the port can receive without\r
- * any errors.\r
- *\r
- * Set the Rx Max length to the MTU configured for the\r
- * interface.\r
- */\r
- CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu);\r
\r
- /* Done setting up the MAC port */\r
+ /* SGMII SERDES Configuration complete. Return. */\r
return 0;\r
-\r
-\r
}\r
\r
-/** ============================================================================\r
- * @n@b initMDIO\r
- *\r
- * @b Description\r
- * @n Not supported at moment. MDIO is not simulated yet.\r
- *\r
- * @param[in]\r
- * @n None\r
- *\r
- * @return\r
- * @n None\r
- * =============================================================================\r
- */\r
-static void initMDIO (void)\r
-{\r
- /* Return success. */\r
- return;\r
-}\r
-/** ============================================================================\r
- * @n@b switch_update_addr\r
- *\r
- * @b Description\r
- * @n This API add/delete entries in the Address Lookup Engine (ALE) in "Switch" mode.\r
- *\r
- * @param[in]\r
- * @n portNum Switch port number.\r
-\r
- * @param[in]\r
- * @n macAddress MAC address to configure on the switch.\r
- *\r
- * @param[in]\r
- * @n add 0:add; 1:delete.\r
- *\r
- * @return\r
- * @n None\r
- *\r
- * @Note It supports "add" operation only now.\r
- * =============================================================================\r
- */\r
-static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t add)\r
+/* Setup the cpsw used in the example */\r
+int initCpsw (void)\r
{\r
- Uint32 i;\r
- CSL_CPSW_5GF_ALE_PORTCONTROL alePortControlCfg;\r
- CSL_CPSW_5GF_ALE_UNICASTADDR_ENTRY ucastAddrCfg;\r
-\r
-\r
- /* Configure the address in "Learning"/"Forward" state */\r
- alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;\r
- alePortControlCfg.dropUntaggedEnable = 0;\r
- alePortControlCfg.vidIngressCheckEnable = 0;\r
- alePortControlCfg.noLearnModeEnable = (cpswLpbkMode != CPSW_LOOPBACK_NONE)?1:0;\r
- alePortControlCfg.mcastLimit = 0;\r
- alePortControlCfg.bcastLimit = 0;\r
-\r
- CSL_CPSW_nGF_setAlePortControlReg (portNum, &alePortControlCfg);\r
-\r
- /*\r
- * The following code is required for device simulator only.\r
- * It is also served as an example of adding MAC address to the ALE table manually\r
- */\r
+ Uint32 macPortNum, mtuSize = 1518;\r
+ Uint8 macSrcAddress [][6] = {{0x10, 0x11, 0x12, 0x13, 0x14, 0x15},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x25},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x35},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x45},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x55},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x65},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x75},\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x85},\r
+ };\r
+ \r
+ Uint8 macAddress[] [6] = {{0x00, 0x01, 0x02, 0x03, 0x04, 0x05}, /* MAC address for (CPPI) Port 0 */\r
+ {0x10, 0x11, 0x12, 0x13, 0x14, 0x15}, /* MAC address for (EMAC) Port 1 */\r
+ {0x20, 0x21, 0x22, 0x23, 0x24, 0x25}, /* MAC address for (EMAC) Port 2 */\r
+ {0x30, 0x31, 0x32, 0x33, 0x34, 0x35}, /* MAC address for (EMAC) Port 3 */\r
+ {0x40, 0x41, 0x42, 0x43, 0x44, 0x45}, /* MAC address for (EMAC) Port 4 */\r
+ {0x50, 0x51, 0x52, 0x53, 0x54, 0x55}, /* MAC address for (EMAC) Port 5 */\r
+ {0x60, 0x61, 0x62, 0x63, 0x64, 0x65}, /* MAC address for (EMAC) Port 6 */\r
+ {0x70, 0x71, 0x72, 0x73, 0x74, 0x75}, /* MAC address for (EMAC) Port 7 */\r
+ {0x80, 0x81, 0x82, 0x83, 0x84, 0x85} /* MAC address for (EMAC) Port 8 */\r
+ }; \r
+ Uint32 portNum;\r
+ \r
\r
- if (cpswSimTest)\r
+ /* Set the global Num Mac Ports to 2 when running in non loopback mode */\r
+ if(cpswLpbkMode == CPSW_LOOPBACK_NONE)\r
{\r
- /* Program the ALE with the MAC address.\r
- *\r
- * The ALE entries determine the switch port to which any\r
- * matching received packet must be forwarded to.\r
- */\r
- /* Get the next free ALE entry to program */\r
- for (i = 0; i < CSL_CPSW_5GF_NUMALE_ENTRIES; i++)\r
- {\r
- if (CSL_CPSW_nGF_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)\r
- {\r
- /* Found a free entry */\r
- break;\r
- }\r
- }\r
- if (i == CSL_CPSW_5GF_NUMALE_ENTRIES)\r
- {\r
- /* No free ALE entry found. return error. */\r
- return -1;\r
- }\r
- else\r
- {\r
- /* Found a free ALE entry to program our MAC address */\r
- memcpy (ucastAddrCfg.macAddress, macAddress, 6); // Set the MAC address\r
- ucastAddrCfg.ucastType = ALE_UCASTTYPE_UCAST_NOAGE; // Add a permanent unicast address entryALE_UCASTTYPE_UCAST_NOAGE.\r
- ucastAddrCfg.secureEnable = FALSE;\r
- ucastAddrCfg.blockEnable = FALSE;\r
- ucastAddrCfg.portNumber = portNum; // Add the ALE entry for this port\r
-\r
- /* Setup the ALE entry for this port's MAC address */\r
- CSL_CPSW_nGF_setAleUnicastAddrEntry (i, &ucastAddrCfg);\r
- }\r
+ gNum_Mac_Ports = 2;\r
+ }\r
+ /* Set global Num Mac Ports to total number of ports on the device (NUM_PORTS-1) */\r
+ else\r
+ {\r
+ gNum_Mac_Ports = UTF_NUM_PORTS - 1;\r
}\r
\r
- /* Done with upading address */\r
- return 0;\r
-}\r
-\r
-/** ============================================================================\r
- * @n@b initSwitch\r
- *\r
- * @b Description\r
- * @n This API sets up the ethernet switch subsystem and its Address Lookup\r
- * Engine (ALE) in "Switch" mode.\r
- *\r
- * @param[in]\r
- * @n mtu Maximum Frame length to configure on the switch.\r
- *\r
- * @return\r
- * @n None\r
- * =============================================================================\r
- */\r
-static void initSwitch (uint32_t mtu)\r
-{\r
- CSL_CPSW_5GF_PORTSTAT portStatCfg;\r
-\r
- /* Enable the CPPI port, i.e., port 0 that does all\r
- * the data streaming in/out of EMAC.\r
- */\r
- CSL_CPSW_nGF_enablePort0 ();\r
- CSL_CPSW_nGF_disableVlanAware ();\r
- CSL_CPSW_nGF_setPort0VlanReg (0, 0, 0);\r
- CSL_CPSW_nGF_setPort0RxMaxLen (mtu);\r
-\r
- /* Enable statistics on both the port groups:\r
- *\r
- * MAC Sliver ports - Port 1, Port 2\r
- * CPPI Port - Port 0\r
- */\r
- portStatCfg.p0AStatEnable = 1;\r
- portStatCfg.p0BStatEnable = 1;\r
- portStatCfg.p1StatEnable = 1;\r
- portStatCfg.p2StatEnable = 1;\r
-\r
- CSL_CPSW_nGF_setPortStatsEnableReg (&portStatCfg);\r
-\r
- /* Setup the Address Lookup Engine (ALE) Configuration:\r
- * (1) Enable ALE.\r
- * (2) Clear stale ALE entries.\r
- * (3) Disable VLAN Aware lookups in ALE since\r
- * we are not using VLANs by default.\r
- * (4) No Flow control\r
- * (5) Configure the Unknown VLAN processing\r
- * properties for the switch, i.e., which\r
- * ports to send the packets to.\r
- */\r
- CSL_CPSW_nGF_enableAle ();\r
- CSL_CPSW_nGF_clearAleTable ();\r
-\r
- CSL_CPSW_nGF_disableAleVlanAware ();\r
- CSL_CPSW_nGF_disableAleTxRateLimit ();\r
- CSL_CPSW_nGF_setAlePrescaleReg (125000000u/1000u);\r
- CSL_CPSW_nGF_setAleUnkownVlanReg (7, 3, 3, 7);\r
-\r
- if(cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
- CSL_CPSW_nGF_enableAleBypass();\r
-\r
- /* Done with switch configuration */\r
- return;\r
-}\r
-\r
-/* Setup the cpsw used in the example */\r
-int initCpsw (void)\r
-{\r
- uint32_t macPortNum, mtuSize = 1518, portNum;\r
- uint8_t macSrcAddress [2][6] = {{0x10, 0x11, 0x12, 0x13, 0x14, 0x15},\r
- {0x20, 0x21, 0x22, 0x23, 0x24, 0x25}};\r
- uint8_t macAddress [] [6] = {{0x00, 0x01, 0x02, 0x03, 0x04, 0x05}, /* MAC address for (CPPI) Port 0 */\r
- {0x10, 0x11, 0x12, 0x13, 0x14, 0x15}, /* MAC address for (EMAC1) Port 1 */\r
- {0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}; /* MAC address for (EMAC2) Port 2 */\r
-\r
+ /* Initialize the serdes modules */\r
initSGMIISerdes();\r
\r
/* Initialize the SGMII/Sliver submodules for the\r
* two corresponding MAC ports.\r
*/\r
- for (macPortNum = 0; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
+ for (macPortNum = 0; macPortNum < gNum_Mac_Ports; macPortNum++)\r
{\r
if (initSGMII (macPortNum))\r
return -1;\r