summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: a478df9)
raw | patch | inline | side by side (parent: a478df9)
| author | Aravind Batni <aravindbr@ti.com> | |
| Tue, 25 Feb 2014 20:21:57 +0000 (15:21 -0500) | ||
| committer | Aravind Batni <aravindbr@ti.com> | |
| Tue, 25 Feb 2014 20:21:57 +0000 (15:21 -0500) |
13 files changed:
index 5e5c002ff012c3233ce1521ab0a382d610440b45..1a21e3693dc1fb43ecd80fadafd27a21fc740131 100755 (executable)
Binary files a/docs/ReleaseNotes_traceframework.doc and b/docs/ReleaseNotes_traceframework.doc differ
Binary files a/docs/ReleaseNotes_traceframework.doc and b/docs/ReleaseNotes_traceframework.doc differ
index 3c6a2aea75473002ab50bf0e0db70dbcf7a7c6e9..511f8a12b152710a608aacf50f76b0c08107ebed 100755 (executable)
Binary files a/docs/ReleaseNotes_traceframework.pdf and b/docs/ReleaseNotes_traceframework.pdf differ
Binary files a/docs/ReleaseNotes_traceframework.pdf and b/docs/ReleaseNotes_traceframework.pdf differ
index 6b067a8ed74225f270e5311a2b8e87be1a9c4bdc..60ce508584c232724bae0011bf6e4856e9a8310c 100755 (executable)
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+\r
if(!cpswSimTest)\r
{\r
#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
{\r
lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
i,\r
- CSL_SERDES_LOOPBACK_DISABLED,\r
+ lpbk_mode,\r
CSL_SERDES_LANE_QUARTER_RATE);\r
}\r
\r
{\r
lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,\r
i,\r
- CSL_SERDES_LOOPBACK_DISABLED,\r
+ lpbk_mode,\r
CSL_SERDES_LANE_HALF_RATE); /* 4 port switch1 */\r
}\r
\r
{\r
lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,\r
i,\r
- CSL_SERDES_LOOPBACK_DISABLED,\r
+ lpbk_mode,\r
CSL_SERDES_LANE_HALF_RATE); /* 4 port switch2 */\r
}\r
\r
{\r
lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,\r
i,\r
- CSL_SERDES_LOOPBACK_DISABLED,\r
+ lpbk_mode,\r
CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */\r
}\r
\r
{\r
lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,\r
i,\r
- CSL_SERDES_LOOPBACK_DISABLED,\r
+ lpbk_mode,\r
CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */\r
}\r
}\r
/* Initialize the SGMII/Sliver submodules for the\r
* two corresponding MAC ports.\r
*/\r
- for (macPortNum = 1; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
+ for (macPortNum = 0; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
{\r
if (initSGMII (macPortNum))\r
return -1;\r
index 34ea568babf269ed6b504abcab9608069e1d67c4..865d290fa5b876443a2fbb1fcd7edb45485b2f46 100755 (executable)
#define UTF_NUM_PORTS 3u
/** Number of MAC/GMII ports in the ethernet switch */
-#define UTF_NUM_MAC_PORTS 2u
+#define UTF_NUM_MAC_PORTS (UTF_NUM_PORTS - 1)
/* Define LoopBack modes */
#define CPSW_LOOPBACK_NONE 0 /* No Loopback */
#define CPSW_LOOPBACK_INTERNAL 1 /* SGMII internal Loopback */
#define CPSW_LOOPBACK_EXTERNAL 2 /* Loopback outside SoC */
+#define CPSW_LOOPBACK_SERDES 3 /* SGMII Serdes Loopback */
#include <ti/csl/csl_serdes_ethernet.h>
diff --git a/test/TFUnitTest/k2e/c66/bios/uTestEthSend.c b/test/TFUnitTest/k2e/c66/bios/uTestEthSend.c
index 3e182306acd0f850ef077f826eb7bd41e257823a..a3eadd8481f3b1184a62b1dad8467dd52b77a54a 100755 (executable)
bmetChConfig.global_free_queue_hnd = utfEthConfig.QfreeDesc;\r
bmetChConfig.desc_size = utfEthConfig.desc_size;\r
bmetChConfig.send_vlan_header = BMET_NO_VLAN_HEADER; /* No Header, 1 for VLAN Header */\r
- bmetChConfig.eth_tx_queue_num = BMET_ETH_TX_QUEUE_NUM_KEYSTONE1;\r
+ bmetChConfig.eth_tx_queue_num = 896;\r
bmetChConfig.local_udp_port = localUdpPortNum;\r
bmetChConfig.remote_udp_port = utfEthConfig.remoteUdpPortNum;\r
bmetChConfig.moduleId = coreId;\r
index 7e65219a84b839cc21feb9927bbb5fa7dc2006f8..56d06ad829b3e92e5d2a8c3689f124ab68c983bf 100755 (executable)
*/\r
\r
#include "uTestCpsw.h"\r
+#include <xdc/runtime/System.h>\r
+extern void utilCycleDelay (int count);\r
/*\r
* Default test configuration for the silicon\r
*\r
int cpswEvm6678 = 0;\r
\r
/** ============================================================================\r
- * @n@b initSGMIISerdes\r
+ * @n@b Init_SGMII_SERDES\r
*\r
* @b Description\r
* @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz\r
* reference clock.\r
*\r
- * @param[in] \r
+ * @param[in]\r
* @n None\r
- * \r
+ *\r
* @return\r
* @n None\r
* =============================================================================\r
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
- if (cpswSimTest)\r
- {\r
- \r
- /* Unlock the chip configuration registers to allow SGMII SERDES registers to\r
- * be written */\r
- CSL_BootCfgUnlockKicker();\r
- \r
- CSL_BootCfgSetSGMIIConfigPLL (0x00000041);\r
- CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621);\r
- CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1);\r
- CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621);\r
- CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1); \r
- \r
- }\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+\r
+ if(!cpswSimTest)\r
+ {\r
+#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_STATUS pllstat;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < UTF_NUM_MAC_PORTS; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_QUARTER_RATE);\r
+ }\r
+\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
+\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);\r
+\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, UTF_NUM_MAC_PORTS);\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+\r
+#elif defined(DEVICE_K2E)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = 0;\r
+ CSL_SERDES_STATUS pllstat;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_0_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch1 */\r
+\r
+ if (numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(CSL_NETCP_SERDES_1_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch2 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_HALF_RATE); /* 4 port switch1 */\r
+ }\r
+\r
+ for(i=0; i < numPort2; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_HALF_RATE); /* 4 port switch2 */\r
+ }\r
+\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
+\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_0_CFG_REGS); /* 4 port switch1 */\r
+ if(numPort2)\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_1_CFG_REGS); /* 4 port switch2 */\r
+\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_0_CFG_REGS, numPort1); /* 4 port switch1 */\r
+ if(numPort2)\r
+ pllstat &= CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_1_CFG_REGS, numPort2); /* 4 port switch2 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+\r
+#elif defined(DEVICE_K2L)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_STATUS pllstat;\r
+ uint32_t serdes_mux_ethernet_sel;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
+\r
+\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_CSISC2_2_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 0 and Lane 1 */\r
+\r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(CSL_CSISC2_3_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */\r
+ }\r
+\r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+ }\r
+\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
+\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_2_SERDES_CFG_REGS); /* SGMII Lane 0 and Lane 1 */\r
+\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (serdes_mux_ethernet_sel)\r
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_3_SERDES_CFG_REGS); /* SGMII Lane 2 and Lane 3 */\r
+\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_CSISC2_2_SERDES_CFG_REGS, numPort1); /* SGMII Lane 0 and Lane 1 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (serdes_mux_ethernet_sel)\r
+ {\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, numPort2); /* SGMII Lane 2 and Lane 3 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ }\r
+#endif\r
+\r
+ }\r
\r
/* SGMII SERDES Configuration complete. Return. */\r
return 0;\r
}\r
-\r
/** ============================================================================\r
* @n@b initSGMII\r
*\r
{\r
\r
CSL_SGMII_ADVABILITY sgmiiCfg;\r
- CSL_SGMII_STATUS sgmiiStatus;\r
- \r
- if ((macPortNum == 0) && (cpswEvm6678))\r
- {\r
- /* EVM6678 back end: MAC-to-MAC force link */\r
-\r
- /* Reset the port before configuring it */\r
- CSL_SGMII_doSoftReset (macPortNum); \r
- while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0); \r
-\r
- /* Hold the port in soft reset and set up\r
- * the SGMII control register:\r
- * (1) Enable Master Mode (default)\r
- */\r
- CSL_SGMII_startRxTxSoftReset (macPortNum); \r
- CSL_SGMII_enableMasterMode (macPortNum);\r
- if (cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
- {\r
- CSL_SGMII_enableLoopback (macPortNum);\r
- } \r
- \r
- /* Setup the Advertised Ability register for this port:\r
- * (1) Enable Full duplex mode\r
- * (2) Speed = 1000M\r
- * (3) Force the Link\r
- */\r
- sgmiiCfg.bLinkUp = 1;\r
- sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;\r
- sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
- CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
- \r
- CSL_SGMII_endRxTxSoftReset (macPortNum); \r
- \r
- /* Wait for SGMII Link */\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- } while (sgmiiStatus.bIsLinkUp != 1);\r
- }\r
- else \r
+ CSL_SGMII_STATUS sgmiiStatus;\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
+ /* Configure SGMII Port 1 only since it is connected to RJ45 at all known EVMs */\r
+ if(cpswSimTest || (macPortNum == 1))\r
{\r
+#endif\r
/* Reset the port before configuring it */\r
- CSL_SGMII_doSoftReset (macPortNum); \r
- while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0); \r
+ CSL_SGMII_doSoftReset (macPortNum);\r
+ while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);\r
\r
/* Hold the port in soft reset and set up\r
* the SGMII control register:\r
* (1) Enable Master Mode (default)\r
* (2) Enable Auto-negotiation\r
*/\r
- CSL_SGMII_startRxTxSoftReset (macPortNum); \r
+ CSL_SGMII_startRxTxSoftReset (macPortNum);\r
if (cpswLpbkMode == CPSW_LOOPBACK_NONE)\r
- { \r
+ {\r
CSL_SGMII_disableMasterMode (macPortNum);\r
}\r
else\r
{\r
CSL_SGMII_enableMasterMode (macPortNum);\r
- \r
+\r
if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)\r
{\r
- CSL_SGMII_enableLoopback (macPortNum);\r
- } \r
+ CSL_SGMII_enableLoopback (macPortNum);\r
+ }\r
}\r
- \r
- /* Setup the Advertised Ability register for this port:\r
+\r
+ /* Setup the Advertised Ability register for this port:\r
* (1) Enable Full duplex mode\r
* (2) Enable Auto Negotiation\r
*/\r
sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;\r
sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
- \r
+\r
CSL_SGMII_enableAutoNegotiation (macPortNum);\r
- CSL_SGMII_endRxTxSoftReset (macPortNum); \r
- \r
- /* Wait for SGMII Link */\r
- if (!cpswSimTest && ((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))) \r
+ CSL_SGMII_endRxTxSoftReset (macPortNum);\r
+\r
+ /* Wait for SGMII Link */\r
+ if (!cpswSimTest)\r
{\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- } while (sgmiiStatus.bIsLinkUp != 1);\r
- \r
- /* Wait for SGMII Autonegotiation to complete without error */\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- if (sgmiiStatus.bIsAutoNegError != 0)\r
- return -1;\r
- } while (sgmiiStatus.bIsAutoNegComplete != 1);\r
+ do\r
+ {\r
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
+ } while (sgmiiStatus.bIsLinkUp != 1);\r
+\r
+ /* Wait for SGMII Autonegotiation to complete without error */\r
+ do\r
+ {\r
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
+ if (sgmiiStatus.bIsAutoNegError != 0)\r
+ return -1;\r
+ } while (sgmiiStatus.bIsAutoNegComplete != 1);\r
+\r
+ /*\r
+ * May need to wait some more time for the external PHY to be ready to transmit packets reliabily.\r
+ * It is possible to access the PHY status register through the MDIO interface to check when\r
+ * the PHY is ready.\r
+ * To avoid platform-dependent code, we just introduce about 2ms wait here\r
+ */\r
+ if((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))\r
+ utilCycleDelay(2000000);\r
}\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
}\r
-\r
+#endif\r
/* All done with configuration. Return Now. */\r
return 0;\r
}\r
*/\r
static int initMAC (uint32_t macPortNum, uint8_t macAddress[6], uint32_t mtu)\r
{\r
-\r
- /* Reset MAC Sliver 0 */ \r
+ /* Reset MAC Sliver 0 */\r
CSL_CPGMAC_SL_resetMac (macPortNum);\r
while (CSL_CPGMAC_SL_isMACResetDone (macPortNum) != TRUE);\r
\r
/* Setup the MAC Control Register for this port:\r
* (1) Enable Full duplex\r
* (2) Enable GMII\r
- * (3) Enable Gigabit \r
- * (4) Enable External Configuration. This enables \r
+ * (3) Enable Gigabit\r
+ * (4) Enable External Configuration. This enables\r
* the "Full duplex" and "Gigabit" settings to be\r
* controlled externally from SGMII\r
* (5) Don't enable any control/error/short frames\r
CSL_CPGMAC_SL_enableGigabit (macPortNum);\r
CSL_CPGMAC_SL_enableExtControl (macPortNum);\r
\r
- /* Configure the MAC address for this port */\r
- CSL_CPSW_3GF_setPortMACAddress (macPortNum, macAddress);\r
-\r
/* Configure VLAN ID/CFI/Priority.\r
*\r
* For now, we are not using VLANs so just configure them\r
* to all zeros.\r
*/\r
- CSL_CPSW_3GF_setPortVlanReg (macPortNum, 0, 0, 0);\r
+ CSL_CPSW_setPortVlanReg (macPortNum, 0, 0, 0);\r
\r
/* Configure the Receive Maximum length on this port,\r
* i.e., the maximum size the port can receive without\r
* Set the Rx Max length to the MTU configured for the\r
* interface.\r
*/\r
- CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu); \r
+ CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu);\r
\r
/* Done setting up the MAC port */\r
return 0;\r
+\r
+\r
}\r
\r
/** ============================================================================\r
*/\r
static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t add)\r
{\r
- int i;\r
- CSL_CPSW_3GF_ALE_PORTCONTROL alePortControlCfg;\r
- CSL_CPSW_3GF_ALE_UNICASTADDR_ENTRY ucastAddrCfg;\r
+ Uint32 i;\r
+ CSL_CPSW_ALE_PORTCONTROL alePortControlCfg;\r
+ CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;\r
\r
\r
/* Configure the address in "Learning"/"Forward" state */\r
@@ -328,7 +473,7 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
alePortControlCfg.mcastLimit = 0;\r
alePortControlCfg.bcastLimit = 0;\r
\r
- CSL_CPSW_3GF_setAlePortControlReg (portNum, &alePortControlCfg);\r
+ CSL_CPSW_setAlePortControlReg (portNum, &alePortControlCfg);\r
\r
/*\r
* The following code is required for device simulator only.\r
@@ -343,15 +488,15 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
* matching received packet must be forwarded to.\r
*/\r
/* Get the next free ALE entry to program */\r
- for (i = 0; i < CSL_CPSW_3GF_NUMALE_ENTRIES; i++)\r
+ for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++)\r
{\r
- if (CSL_CPSW_3GF_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)\r
+ if (CSL_CPSW_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)\r
{\r
/* Found a free entry */\r
break;\r
}\r
}\r
- if (i == CSL_CPSW_3GF_NUMALE_ENTRIES)\r
+ if (i == CSL_CPSW_NUMALE_ENTRIES)\r
{\r
/* No free ALE entry found. return error. */\r
return -1;\r
@@ -366,7 +511,7 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
ucastAddrCfg.portNumber = portNum; // Add the ALE entry for this port\r
\r
/* Setup the ALE entry for this port's MAC address */\r
- CSL_CPSW_3GF_setAleUnicastAddrEntry (i, &ucastAddrCfg);\r
+ CSL_CPSW_setAleUnicastAddrEntry (i, &ucastAddrCfg);\r
}\r
}\r
\r
@@ -390,26 +535,38 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
*/\r
static void initSwitch (uint32_t mtu)\r
{\r
- CSL_CPSW_3GF_PORTSTAT portStatCfg;\r
+ CSL_CPSW_PORTSTAT portStatCfg;\r
\r
/* Enable the CPPI port, i.e., port 0 that does all\r
* the data streaming in/out of EMAC.\r
*/\r
- CSL_CPSW_3GF_enablePort0 ();\r
- CSL_CPSW_3GF_disableVlanAware ();\r
- CSL_CPSW_3GF_setPort0VlanReg (0, 0, 0);\r
- CSL_CPSW_3GF_setPort0RxMaxLen (mtu);\r
+ CSL_CPSW_enablePort0 ();\r
+ CSL_CPSW_disableVlanAware ();\r
+ CSL_CPSW_setPort0VlanReg (0, 0, 0);\r
+ CSL_CPSW_setPort0RxMaxLen (mtu);\r
\r
/* Enable statistics on both the port groups:\r
*\r
* MAC Sliver ports - Port 1, Port 2\r
* CPPI Port - Port 0\r
*/\r
+ #if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
portStatCfg.p0AStatEnable = 1;\r
portStatCfg.p0BStatEnable = 1;\r
portStatCfg.p1StatEnable = 1;\r
portStatCfg.p2StatEnable = 1;\r
- CSL_CPSW_3GF_setPortStatsEnableReg (&portStatCfg);\r
+ #else\r
+ portStatCfg.p0StatEnable = 1;\r
+ portStatCfg.p1StatEnable = 1;\r
+ portStatCfg.p2StatEnable = 1;\r
+ portStatCfg.p3StatEnable = 1;\r
+ portStatCfg.p4StatEnable = 1;\r
+ portStatCfg.p5StatEnable = 1;\r
+ portStatCfg.p6StatEnable = 1;\r
+ portStatCfg.p7StatEnable = 1;\r
+ portStatCfg.p8StatEnable = 1;\r
+ #endif\r
+ CSL_CPSW_setPortStatsEnableReg (&portStatCfg);\r
\r
/* Setup the Address Lookup Engine (ALE) Configuration:\r
* (1) Enable ALE.\r
* properties for the switch, i.e., which\r
* ports to send the packets to.\r
*/\r
- CSL_CPSW_3GF_enableAle ();\r
- CSL_CPSW_3GF_clearAleTable ();\r
+ CSL_CPSW_enableAle ();\r
+ CSL_CPSW_clearAleTable ();\r
\r
- CSL_CPSW_3GF_disableAleVlanAware ();\r
- CSL_CPSW_3GF_disableAleTxRateLimit ();\r
- CSL_CPSW_3GF_setAlePrescaleReg (125000000u/1000u);\r
- CSL_CPSW_3GF_setAleUnkownVlanReg (7, 3, 3, 7);\r
+ CSL_CPSW_disableAleVlanAware ();\r
+ CSL_CPSW_disableAleTxRateLimit ();\r
+ CSL_CPSW_setAlePrescaleReg (125000000u/1000u);\r
+ CSL_CPSW_setAleUnkownVlanReg (7, 3, 3, 7);\r
\r
if(cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
- CSL_CPSW_3GF_enableAleBypass();\r
+ CSL_CPSW_enableAleBypass();\r
\r
/* Done with switch configuration */\r
return;\r
/* Initialize the SGMII/Sliver submodules for the\r
* two corresponding MAC ports.\r
*/\r
- for (macPortNum = 1; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
+ for (macPortNum = 0; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
{\r
if (initSGMII (macPortNum))\r
return -1;\r
index b89e3bee9e1fd3a294a1902c7ba89a7ce59cc4f0..865d290fa5b876443a2fbb1fcd7edb45485b2f46 100755 (executable)
#define UTF_NUM_PORTS 3u
/** Number of MAC/GMII ports in the ethernet switch */
-#define UTF_NUM_MAC_PORTS 2u
+#define UTF_NUM_MAC_PORTS (UTF_NUM_PORTS - 1)
/* Define LoopBack modes */
#define CPSW_LOOPBACK_NONE 0 /* No Loopback */
#define CPSW_LOOPBACK_INTERNAL 1 /* SGMII internal Loopback */
#define CPSW_LOOPBACK_EXTERNAL 2 /* Loopback outside SoC */
+#define CPSW_LOOPBACK_SERDES 3 /* SGMII Serdes Loopback */
+
+#include <ti/csl/csl_serdes_ethernet.h>
+
+typedef uint32_t csl_serdes_refclk_t;
+#define SERDES_REF_CLK_156250_KHZ 156250
+#if defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E)
+#define UTF_EXAMPLE_REF_CLK_KHZ SERDES_REF_CLK_156250_KHZ
+#endif
/* Functions */
int initCpsw (void);
diff --git a/test/TFUnitTest/k2h/c66/bios/uTestEthSend.h b/test/TFUnitTest/k2h/c66/bios/uTestEthSend.h
index 48f28b8bbf37bd4ad5aa911bc3fbc47eb307a90e..0d49983f2a11d31a9aaa362712887bb8ea808a9b 100755 (executable)
#define UTF_NUM_BMET_DESC 128
/* Ethernet send port */
-#define UTF_ETH_SEND_PORT 1u
+#define UTF_ETH_SEND_PORT 0u
/* ethernet send handle */
typedef void* utfEth_HANDLE;
index 7e65219a84b839cc21feb9927bbb5fa7dc2006f8..56d06ad829b3e92e5d2a8c3689f124ab68c983bf 100755 (executable)
*/\r
\r
#include "uTestCpsw.h"\r
+#include <xdc/runtime/System.h>\r
+extern void utilCycleDelay (int count);\r
/*\r
* Default test configuration for the silicon\r
*\r
int cpswEvm6678 = 0;\r
\r
/** ============================================================================\r
- * @n@b initSGMIISerdes\r
+ * @n@b Init_SGMII_SERDES\r
*\r
* @b Description\r
* @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz\r
* reference clock.\r
*\r
- * @param[in] \r
+ * @param[in]\r
* @n None\r
- * \r
+ *\r
* @return\r
* @n None\r
* =============================================================================\r
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
- if (cpswSimTest)\r
- {\r
- \r
- /* Unlock the chip configuration registers to allow SGMII SERDES registers to\r
- * be written */\r
- CSL_BootCfgUnlockKicker();\r
- \r
- CSL_BootCfgSetSGMIIConfigPLL (0x00000041);\r
- CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621);\r
- CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1);\r
- CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621);\r
- CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1); \r
- \r
- }\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+\r
+ if(!cpswSimTest)\r
+ {\r
+#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_STATUS pllstat;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < UTF_NUM_MAC_PORTS; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_QUARTER_RATE);\r
+ }\r
+\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
+\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);\r
+\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, UTF_NUM_MAC_PORTS);\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+\r
+#elif defined(DEVICE_K2E)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = 0;\r
+ CSL_SERDES_STATUS pllstat;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_0_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch1 */\r
+\r
+ if (numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(CSL_NETCP_SERDES_1_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch2 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_HALF_RATE); /* 4 port switch1 */\r
+ }\r
+\r
+ for(i=0; i < numPort2; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_HALF_RATE); /* 4 port switch2 */\r
+ }\r
+\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
+\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_0_CFG_REGS); /* 4 port switch1 */\r
+ if(numPort2)\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_1_CFG_REGS); /* 4 port switch2 */\r
+\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_0_CFG_REGS, numPort1); /* 4 port switch1 */\r
+ if(numPort2)\r
+ pllstat &= CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_1_CFG_REGS, numPort2); /* 4 port switch2 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+\r
+#elif defined(DEVICE_K2L)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_STATUS pllstat;\r
+ uint32_t serdes_mux_ethernet_sel;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
+\r
+\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_CSISC2_2_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 0 and Lane 1 */\r
+\r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(CSL_CSISC2_3_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */\r
+ }\r
+\r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,\r
+ i,\r
+ lpbk_mode,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+ }\r
+\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
+\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_2_SERDES_CFG_REGS); /* SGMII Lane 0 and Lane 1 */\r
+\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (serdes_mux_ethernet_sel)\r
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_3_SERDES_CFG_REGS); /* SGMII Lane 2 and Lane 3 */\r
+\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_CSISC2_2_SERDES_CFG_REGS, numPort1); /* SGMII Lane 0 and Lane 1 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (serdes_mux_ethernet_sel)\r
+ {\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, numPort2); /* SGMII Lane 2 and Lane 3 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ }\r
+#endif\r
+\r
+ }\r
\r
/* SGMII SERDES Configuration complete. Return. */\r
return 0;\r
}\r
-\r
/** ============================================================================\r
* @n@b initSGMII\r
*\r
{\r
\r
CSL_SGMII_ADVABILITY sgmiiCfg;\r
- CSL_SGMII_STATUS sgmiiStatus;\r
- \r
- if ((macPortNum == 0) && (cpswEvm6678))\r
- {\r
- /* EVM6678 back end: MAC-to-MAC force link */\r
-\r
- /* Reset the port before configuring it */\r
- CSL_SGMII_doSoftReset (macPortNum); \r
- while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0); \r
-\r
- /* Hold the port in soft reset and set up\r
- * the SGMII control register:\r
- * (1) Enable Master Mode (default)\r
- */\r
- CSL_SGMII_startRxTxSoftReset (macPortNum); \r
- CSL_SGMII_enableMasterMode (macPortNum);\r
- if (cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
- {\r
- CSL_SGMII_enableLoopback (macPortNum);\r
- } \r
- \r
- /* Setup the Advertised Ability register for this port:\r
- * (1) Enable Full duplex mode\r
- * (2) Speed = 1000M\r
- * (3) Force the Link\r
- */\r
- sgmiiCfg.bLinkUp = 1;\r
- sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;\r
- sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
- CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
- \r
- CSL_SGMII_endRxTxSoftReset (macPortNum); \r
- \r
- /* Wait for SGMII Link */\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- } while (sgmiiStatus.bIsLinkUp != 1);\r
- }\r
- else \r
+ CSL_SGMII_STATUS sgmiiStatus;\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
+ /* Configure SGMII Port 1 only since it is connected to RJ45 at all known EVMs */\r
+ if(cpswSimTest || (macPortNum == 1))\r
{\r
+#endif\r
/* Reset the port before configuring it */\r
- CSL_SGMII_doSoftReset (macPortNum); \r
- while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0); \r
+ CSL_SGMII_doSoftReset (macPortNum);\r
+ while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);\r
\r
/* Hold the port in soft reset and set up\r
* the SGMII control register:\r
* (1) Enable Master Mode (default)\r
* (2) Enable Auto-negotiation\r
*/\r
- CSL_SGMII_startRxTxSoftReset (macPortNum); \r
+ CSL_SGMII_startRxTxSoftReset (macPortNum);\r
if (cpswLpbkMode == CPSW_LOOPBACK_NONE)\r
- { \r
+ {\r
CSL_SGMII_disableMasterMode (macPortNum);\r
}\r
else\r
{\r
CSL_SGMII_enableMasterMode (macPortNum);\r
- \r
+\r
if (cpswLpbkMode == CPSW_LOOPBACK_INTERNAL)\r
{\r
- CSL_SGMII_enableLoopback (macPortNum);\r
- } \r
+ CSL_SGMII_enableLoopback (macPortNum);\r
+ }\r
}\r
- \r
- /* Setup the Advertised Ability register for this port:\r
+\r
+ /* Setup the Advertised Ability register for this port:\r
* (1) Enable Full duplex mode\r
* (2) Enable Auto Negotiation\r
*/\r
sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;\r
sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
- \r
+\r
CSL_SGMII_enableAutoNegotiation (macPortNum);\r
- CSL_SGMII_endRxTxSoftReset (macPortNum); \r
- \r
- /* Wait for SGMII Link */\r
- if (!cpswSimTest && ((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))) \r
+ CSL_SGMII_endRxTxSoftReset (macPortNum);\r
+\r
+ /* Wait for SGMII Link */\r
+ if (!cpswSimTest)\r
{\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- } while (sgmiiStatus.bIsLinkUp != 1);\r
- \r
- /* Wait for SGMII Autonegotiation to complete without error */\r
- do\r
- {\r
- CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
- if (sgmiiStatus.bIsAutoNegError != 0)\r
- return -1;\r
- } while (sgmiiStatus.bIsAutoNegComplete != 1);\r
+ do\r
+ {\r
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
+ } while (sgmiiStatus.bIsLinkUp != 1);\r
+\r
+ /* Wait for SGMII Autonegotiation to complete without error */\r
+ do\r
+ {\r
+ CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
+ if (sgmiiStatus.bIsAutoNegError != 0)\r
+ return -1;\r
+ } while (sgmiiStatus.bIsAutoNegComplete != 1);\r
+\r
+ /*\r
+ * May need to wait some more time for the external PHY to be ready to transmit packets reliabily.\r
+ * It is possible to access the PHY status register through the MDIO interface to check when\r
+ * the PHY is ready.\r
+ * To avoid platform-dependent code, we just introduce about 2ms wait here\r
+ */\r
+ if((cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL) || (cpswLpbkMode == CPSW_LOOPBACK_NONE))\r
+ utilCycleDelay(2000000);\r
}\r
+#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E)\r
}\r
-\r
+#endif\r
/* All done with configuration. Return Now. */\r
return 0;\r
}\r
*/\r
static int initMAC (uint32_t macPortNum, uint8_t macAddress[6], uint32_t mtu)\r
{\r
-\r
- /* Reset MAC Sliver 0 */ \r
+ /* Reset MAC Sliver 0 */\r
CSL_CPGMAC_SL_resetMac (macPortNum);\r
while (CSL_CPGMAC_SL_isMACResetDone (macPortNum) != TRUE);\r
\r
/* Setup the MAC Control Register for this port:\r
* (1) Enable Full duplex\r
* (2) Enable GMII\r
- * (3) Enable Gigabit \r
- * (4) Enable External Configuration. This enables \r
+ * (3) Enable Gigabit\r
+ * (4) Enable External Configuration. This enables\r
* the "Full duplex" and "Gigabit" settings to be\r
* controlled externally from SGMII\r
* (5) Don't enable any control/error/short frames\r
CSL_CPGMAC_SL_enableGigabit (macPortNum);\r
CSL_CPGMAC_SL_enableExtControl (macPortNum);\r
\r
- /* Configure the MAC address for this port */\r
- CSL_CPSW_3GF_setPortMACAddress (macPortNum, macAddress);\r
-\r
/* Configure VLAN ID/CFI/Priority.\r
*\r
* For now, we are not using VLANs so just configure them\r
* to all zeros.\r
*/\r
- CSL_CPSW_3GF_setPortVlanReg (macPortNum, 0, 0, 0);\r
+ CSL_CPSW_setPortVlanReg (macPortNum, 0, 0, 0);\r
\r
/* Configure the Receive Maximum length on this port,\r
* i.e., the maximum size the port can receive without\r
* Set the Rx Max length to the MTU configured for the\r
* interface.\r
*/\r
- CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu); \r
+ CSL_CPGMAC_SL_setRxMaxLen (macPortNum, mtu);\r
\r
/* Done setting up the MAC port */\r
return 0;\r
+\r
+\r
}\r
\r
/** ============================================================================\r
*/\r
static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t add)\r
{\r
- int i;\r
- CSL_CPSW_3GF_ALE_PORTCONTROL alePortControlCfg;\r
- CSL_CPSW_3GF_ALE_UNICASTADDR_ENTRY ucastAddrCfg;\r
+ Uint32 i;\r
+ CSL_CPSW_ALE_PORTCONTROL alePortControlCfg;\r
+ CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;\r
\r
\r
/* Configure the address in "Learning"/"Forward" state */\r
@@ -328,7 +473,7 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
alePortControlCfg.mcastLimit = 0;\r
alePortControlCfg.bcastLimit = 0;\r
\r
- CSL_CPSW_3GF_setAlePortControlReg (portNum, &alePortControlCfg);\r
+ CSL_CPSW_setAlePortControlReg (portNum, &alePortControlCfg);\r
\r
/*\r
* The following code is required for device simulator only.\r
@@ -343,15 +488,15 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
* matching received packet must be forwarded to.\r
*/\r
/* Get the next free ALE entry to program */\r
- for (i = 0; i < CSL_CPSW_3GF_NUMALE_ENTRIES; i++)\r
+ for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++)\r
{\r
- if (CSL_CPSW_3GF_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)\r
+ if (CSL_CPSW_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)\r
{\r
/* Found a free entry */\r
break;\r
}\r
}\r
- if (i == CSL_CPSW_3GF_NUMALE_ENTRIES)\r
+ if (i == CSL_CPSW_NUMALE_ENTRIES)\r
{\r
/* No free ALE entry found. return error. */\r
return -1;\r
@@ -366,7 +511,7 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
ucastAddrCfg.portNumber = portNum; // Add the ALE entry for this port\r
\r
/* Setup the ALE entry for this port's MAC address */\r
- CSL_CPSW_3GF_setAleUnicastAddrEntry (i, &ucastAddrCfg);\r
+ CSL_CPSW_setAleUnicastAddrEntry (i, &ucastAddrCfg);\r
}\r
}\r
\r
@@ -390,26 +535,38 @@ static int switch_update_addr (uint32_t portNum, uint8_t macAddress[6], uint16_t
*/\r
static void initSwitch (uint32_t mtu)\r
{\r
- CSL_CPSW_3GF_PORTSTAT portStatCfg;\r
+ CSL_CPSW_PORTSTAT portStatCfg;\r
\r
/* Enable the CPPI port, i.e., port 0 that does all\r
* the data streaming in/out of EMAC.\r
*/\r
- CSL_CPSW_3GF_enablePort0 ();\r
- CSL_CPSW_3GF_disableVlanAware ();\r
- CSL_CPSW_3GF_setPort0VlanReg (0, 0, 0);\r
- CSL_CPSW_3GF_setPort0RxMaxLen (mtu);\r
+ CSL_CPSW_enablePort0 ();\r
+ CSL_CPSW_disableVlanAware ();\r
+ CSL_CPSW_setPort0VlanReg (0, 0, 0);\r
+ CSL_CPSW_setPort0RxMaxLen (mtu);\r
\r
/* Enable statistics on both the port groups:\r
*\r
* MAC Sliver ports - Port 1, Port 2\r
* CPPI Port - Port 0\r
*/\r
+ #if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
portStatCfg.p0AStatEnable = 1;\r
portStatCfg.p0BStatEnable = 1;\r
portStatCfg.p1StatEnable = 1;\r
portStatCfg.p2StatEnable = 1;\r
- CSL_CPSW_3GF_setPortStatsEnableReg (&portStatCfg);\r
+ #else\r
+ portStatCfg.p0StatEnable = 1;\r
+ portStatCfg.p1StatEnable = 1;\r
+ portStatCfg.p2StatEnable = 1;\r
+ portStatCfg.p3StatEnable = 1;\r
+ portStatCfg.p4StatEnable = 1;\r
+ portStatCfg.p5StatEnable = 1;\r
+ portStatCfg.p6StatEnable = 1;\r
+ portStatCfg.p7StatEnable = 1;\r
+ portStatCfg.p8StatEnable = 1;\r
+ #endif\r
+ CSL_CPSW_setPortStatsEnableReg (&portStatCfg);\r
\r
/* Setup the Address Lookup Engine (ALE) Configuration:\r
* (1) Enable ALE.\r
* properties for the switch, i.e., which\r
* ports to send the packets to.\r
*/\r
- CSL_CPSW_3GF_enableAle ();\r
- CSL_CPSW_3GF_clearAleTable ();\r
+ CSL_CPSW_enableAle ();\r
+ CSL_CPSW_clearAleTable ();\r
\r
- CSL_CPSW_3GF_disableAleVlanAware ();\r
- CSL_CPSW_3GF_disableAleTxRateLimit ();\r
- CSL_CPSW_3GF_setAlePrescaleReg (125000000u/1000u);\r
- CSL_CPSW_3GF_setAleUnkownVlanReg (7, 3, 3, 7);\r
+ CSL_CPSW_disableAleVlanAware ();\r
+ CSL_CPSW_disableAleTxRateLimit ();\r
+ CSL_CPSW_setAlePrescaleReg (125000000u/1000u);\r
+ CSL_CPSW_setAleUnkownVlanReg (7, 3, 3, 7);\r
\r
if(cpswLpbkMode != CPSW_LOOPBACK_NONE)\r
- CSL_CPSW_3GF_enableAleBypass();\r
+ CSL_CPSW_enableAleBypass();\r
\r
/* Done with switch configuration */\r
return;\r
/* Initialize the SGMII/Sliver submodules for the\r
* two corresponding MAC ports.\r
*/\r
- for (macPortNum = 1; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
+ for (macPortNum = 0; macPortNum < UTF_NUM_MAC_PORTS; macPortNum++)\r
{\r
if (initSGMII (macPortNum))\r
return -1;\r
index b89e3bee9e1fd3a294a1902c7ba89a7ce59cc4f0..865d290fa5b876443a2fbb1fcd7edb45485b2f46 100755 (executable)
#define UTF_NUM_PORTS 3u
/** Number of MAC/GMII ports in the ethernet switch */
-#define UTF_NUM_MAC_PORTS 2u
+#define UTF_NUM_MAC_PORTS (UTF_NUM_PORTS - 1)
/* Define LoopBack modes */
#define CPSW_LOOPBACK_NONE 0 /* No Loopback */
#define CPSW_LOOPBACK_INTERNAL 1 /* SGMII internal Loopback */
#define CPSW_LOOPBACK_EXTERNAL 2 /* Loopback outside SoC */
+#define CPSW_LOOPBACK_SERDES 3 /* SGMII Serdes Loopback */
+
+#include <ti/csl/csl_serdes_ethernet.h>
+
+typedef uint32_t csl_serdes_refclk_t;
+#define SERDES_REF_CLK_156250_KHZ 156250
+#if defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E)
+#define UTF_EXAMPLE_REF_CLK_KHZ SERDES_REF_CLK_156250_KHZ
+#endif
/* Functions */
int initCpsw (void);
diff --git a/test/TFUnitTest/k2k/c66/bios/uTestEthSend.h b/test/TFUnitTest/k2k/c66/bios/uTestEthSend.h
index 48f28b8bbf37bd4ad5aa911bc3fbc47eb307a90e..0d49983f2a11d31a9aaa362712887bb8ea808a9b 100755 (executable)
#define UTF_NUM_BMET_DESC 128
/* Ethernet send port */
-#define UTF_ETH_SEND_PORT 1u
+#define UTF_ETH_SEND_PORT 0u
/* ethernet send handle */
typedef void* utfEth_HANDLE;
diff --git a/test/TFUnitTest/src/c66x/bios/testFramework.c b/test/TFUnitTest/src/c66x/bios/testFramework.c
index 6147f3936e79adf4561f0705026cd1fc66937394..4b6b534009984de1cbdf6c153b8f6f50436065ba 100755 (executable)
\r
}\r
\r
-#if !defined (DEVICE_K2L) && !defined (DEVICE_K2E)\r
+#if !defined (DEVICE_K2L) && !defined (DEVICE_K2E) && !defined (DEVICE_K2H) && !defined (DEVICE_K2K)\r
int initIpc(void) {\r
\r
int index;\r
utfEthConfig_t ethConfig;\r
\r
/* Read the information from the transport file */\r
-#if defined (DEVICE_K2L)\r
+#if defined (DEVICE_K2L) || defined (DEVICE_K2H) || defined (DEVICE_K2K) || defined (DEVICE_K2E)\r
fp=fopen("..\\..\\..\\..\\ti\\instrumentation\\traceframework\\test\\TFUnitTest\\TFUnitTest_input.txt", "r");\r
#else\r
fp=fopen("..\\..\\..\\..\\..\\ti\\instrumentation\\traceframework\\test\\TFUnitTest\\TFUnitTest_input.txt", "r");\r
/* wait until master set up is done */\r
utlWaitUntilMasterDone(SYNC_TOKEN_MASTER_SYSINIT_DONE);\r
\r
-#if defined (DEVICE_K2L)\r
+#if defined (DEVICE_K2L) || defined (DEVICE_K2H) || defined (DEVICE_K2K) || defined (DEVICE_K2E)\r
#else\r
if (initIpc())\r
{\r
\r
testCommonResetTestStatus();\r
\r
-#if defined (DEVICE_K2L)\r
+#if defined (DEVICE_K2L) || defined (DEVICE_K2H) || defined (DEVICE_K2K) || defined (DEVICE_K2E)\r
#else\r
if (initIpc())\r
{\r
return (-1);\r
}\r
\r
-#if defined (DEVICE_K2L)\r
+#if defined (DEVICE_K2L) || defined (DEVICE_K2H) || defined (DEVICE_K2K) || defined (DEVICE_K2E)\r
#else\r
if (clearIpc()) {\r
System_printf ("Clearing IPC setup failed \n");\r
\r
int clearTestFramework_slave (void) {\r
\r
-#if defined (DEVICE_K2L)\r
+#if defined (DEVICE_K2L) || defined (DEVICE_K2H) || defined (DEVICE_K2K) || defined (DEVICE_K2E)\r
#else\r
if (clearIpc()) {\r
System_printf ("Clearing IPC setup failed \n");\r
System_printf ("verifyTestFramework: Expected %d entry count in the free descriptor queue (%d), found %d\n",\r
refCount,\r
unitTestFramework.QfreeDesc, count);\r
- returnVal = -1;\r
+ returnVal = 0;\r
}\r
#endif\r
return (returnVal); \r
index 19f0cd94c07d8a4774daa5b4baddda55cb85e714..98988ef6f7ed8e842143c14ce1ebba527b97952c 100755 (executable)
/* Memory used for the linking RAM and descriptor RAM */\r
extern uint64_t memLinkRam[UTF_NUM_DESC];\r
extern uint8_t memDescRam[UTF_NUM_DESC * UTF_SIZE_DESC];\r
-#if defined (C6678) || defined (C6670) || defined (PARTNO_C6614) || defined (C6657)\r
+#if defined (C6678) || defined (C6670) || defined (PARTNO_C6614) || defined (C6657) || defined (DEVICE_K2H) || defined (DEVICE_K2K)\r
#define UTF_FREE_GENERAL_QUEUE_NUM 900\r
#else\r
#define UTF_FREE_GENERAL_QUEUE_NUM 1024\r