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raw | patch | inline | side by side (parent: 807b9ac)
raw | patch | inline | side by side (parent: 807b9ac)
| author | Aravind Batni <aravindbr@ti.com> | |
| Wed, 10 Jun 2015 14:58:31 +0000 (10:58 -0400) | ||
| committer | Aravind Batni <aravindbr@ti.com> | |
| Wed, 10 Jun 2015 14:58:31 +0000 (10:58 -0400) |
| test/TFUnitTest/k2e/c66/bios/uTestCpsw.c | [changed mode: 0755->0644] | patch | blob | history |
| test/TFUnitTest/k2h/c66/bios/uTestCpsw.c | [changed mode: 0755->0644] | patch | blob | history |
| test/TFUnitTest/k2k/c66/bios/uTestCpsw.c | [changed mode: 0755->0644] | patch | blob | history |
| test/TFUnitTest/k2l/c66/bios/uTestCpsw.c | [changed mode: 0755->0644] | patch | blob | history |
*/\r
\r
#include "uTestCpsw.h"\r
+#include <stdlib.h>\r
#include <xdc/runtime/System.h>\r
extern void utilCycleDelay (int count);\r
/*\r
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
- CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
\r
- if(!cpswSimTest)\r
- {\r
+ if(!cpswSimTest)\r
+ {\r
#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G);\r
-\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
-\r
- //SB Lane Enable\r
- for(i=0; i < NUM_MAC_PORTS; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE);\r
- }\r
-\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);\r
-\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, NUM_MAC_PORTS);\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;\r
+\r
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));\r
+ serdes_lane_enable_params.base_addr = CSL_NETCP_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params.num_lanes = NUM_MAC_PORTS;\r
+ serdes_lane_enable_params.phy_type = SERDES_SGMII;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params.loopback_mode[i] = lpbk_mode;\r
+ \r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ \r
+ serdes_lane_enable_params.lane_mask = (1 << serdes_lane_enable_params.num_lanes) - 1;\r
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+ \r
+ /* Att and Boost values are obtained through Serdes Diagnostic PRBS calibration test */\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params.base_addr,\r
+ serdes_lane_enable_params.ref_clock,\r
+ serdes_lane_enable_params.linkrate);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
\r
#elif defined(DEVICE_K2E)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_0_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch1 */\r
+ serdes_lane_enable_params1.base_addr = CSL_NETCP_SERDES_0_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_NETCP_SERDES_1_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* 4 port switch1 */\r
\r
if (numPort2)\r
{\r
- csl_retval |= CSL_EthernetSerdesInit(CSL_NETCP_SERDES_1_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch2 */\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* 4 port switch2 */\r
+ } \r
+ \r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
}\r
\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
- //SB Lane Enable\r
- for(i=0; i < numPort1; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch1 */\r
- }\r
-\r
- for(i=0; i < numPort2; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch2 */\r
- }\r
-\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_0_CFG_REGS); /* 4 port switch1 */\r
- if(numPort2)\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_1_CFG_REGS); /* 4 port switch2 */\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_0_CFG_REGS, numPort1); /* 4 port switch1 */\r
- if(numPort2)\r
- pllstat &= CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_1_CFG_REGS, numPort2); /* 4 port switch2 */\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ if(numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
\r
#elif defined(DEVICE_K2L)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
- uint32_t serdes_mux_ethernet_sel;\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ uint32_t serdes_mux_ethernet_sel;\r
int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
\r
\r
- /* Check CSISC2_3_MUXSEL bit */\r
- if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
- serdes_mux_ethernet_sel = 1;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_CSISC2_2_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 0 and Lane 1 */\r
-\r
- if (serdes_mux_ethernet_sel && numPort2)\r
- {\r
- csl_retval |= CSL_EthernetSerdesInit(CSL_CSISC2_3_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 2 and Lane 3 */\r
- }\r
-\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
- //SB Lane Enable\r
- for(i=0; i < numPort1; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */\r
- }\r
-\r
- if (serdes_mux_ethernet_sel && numPort2)\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_CSISC2_2_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
{\r
- for(i=0; i < numPort1; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */\r
- }\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ \r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* SGMII Lane 0 and Lane 1 */\r
+ \r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* SGMII Lane 2 and Lane 3 */\r
}\r
\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_CSISC2_2_SERDES_CFG_REGS); /* SGMII Lane 0 and Lane 1 */\r
-\r
- /* Check CSISC2_3_MUXSEL bit */\r
- if (serdes_mux_ethernet_sel)\r
- CSL_EthernetSerdesPllEnable(CSL_CSISC2_3_SERDES_CFG_REGS); /* SGMII Lane 2 and Lane 3 */\r
-\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_CSISC2_2_SERDES_CFG_REGS, numPort1); /* SGMII Lane 0 and Lane 1 */\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
-\r
- /* Check CSISC2_3_MUXSEL bit */\r
- if (serdes_mux_ethernet_sel)\r
- {\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, numPort2); /* SGMII Lane 2 and Lane 3 */\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
- }\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ } \r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+ if(serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
#endif\r
\r
- }\r
+ }\r
\r
/* SGMII SERDES Configuration complete. Return. */\r
return 0;\r
*/\r
\r
#include "uTestCpsw.h"\r
+#include <stdlib.h>\r
#include <xdc/runtime/System.h>\r
extern void utilCycleDelay (int count);\r
/*\r
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
- CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
\r
- if(!cpswSimTest)\r
- {\r
+ if(!cpswSimTest)\r
+ {\r
#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G);\r
-\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
- /* SB Lane Setup */\r
- for(i=0; i < UTF_NUM_MAC_PORTS; i++)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;\r
+\r
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));\r
+ serdes_lane_enable_params.base_addr = CSL_NETCP_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params.num_lanes = UTF_NUM_MAC_PORTS;\r
+ serdes_lane_enable_params.phy_type = SERDES_SGMII;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params.loopback_mode[i] = lpbk_mode;\r
+ \r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ \r
+ serdes_lane_enable_params.lane_mask = (1 << serdes_lane_enable_params.num_lanes) - 1;\r
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+ \r
+ /* Att and Boost values are obtained through Serdes Diagnostic PRBS calibration test */\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params.base_addr,\r
+ serdes_lane_enable_params.ref_clock,\r
+ serdes_lane_enable_params.linkrate);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+\r
+#elif defined(DEVICE_K2E)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_NETCP_SERDES_0_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_NETCP_SERDES_1_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
{\r
- CSL_EthernetSerdesLaneConfig(CSL_NETCP_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G, i);\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
}\r
\r
- //SB CMU and COMLANE Enable\r
- CSL_EthernetSerdesComEnable(CSL_NETCP_SERDES_CFG_REGS);\r
-\r
- //SB Lane Enable\r
- for(i=0; i < UTF_NUM_MAC_PORTS; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE);\r
- }\r
-\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);\r
-\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, UTF_NUM_MAC_PORTS);\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* 4 port switch1 */\r
+\r
+ if (numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* 4 port switch2 */\r
+ } \r
+ \r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+ if(numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
+\r
+#elif defined(DEVICE_K2L)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ uint32_t serdes_mux_ethernet_sel;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
+\r
+\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_CSISC2_2_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ \r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* SGMII Lane 0 and Lane 1 */\r
+ \r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ } \r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+ if(serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
#endif\r
- }\r
+\r
+ }\r
\r
/* SGMII SERDES Configuration complete. Return. */\r
return 0;\r
*/\r
\r
#include "uTestCpsw.h"\r
+#include <stdlib.h>\r
#include <xdc/runtime/System.h>\r
extern void utilCycleDelay (int count);\r
/*\r
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
- CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
\r
- if(!cpswSimTest)\r
- {\r
+ if(!cpswSimTest)\r
+ {\r
#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G);\r
-\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
- /* SB Lane Setup */\r
- for(i=0; i < UTF_NUM_MAC_PORTS; i++)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;\r
+\r
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));\r
+ serdes_lane_enable_params.base_addr = CSL_NETCP_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params.num_lanes = UTF_NUM_MAC_PORTS;\r
+ serdes_lane_enable_params.phy_type = SERDES_SGMII;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params.loopback_mode[i] = lpbk_mode;\r
+ \r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ \r
+ serdes_lane_enable_params.lane_mask = (1 << serdes_lane_enable_params.num_lanes) - 1;\r
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+ \r
+ /* Att and Boost values are obtained through Serdes Diagnostic PRBS calibration test */\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params.base_addr,\r
+ serdes_lane_enable_params.ref_clock,\r
+ serdes_lane_enable_params.linkrate);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+\r
+#elif defined(DEVICE_K2E)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_NETCP_SERDES_0_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_NETCP_SERDES_1_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
{\r
- CSL_EthernetSerdesLaneConfig(CSL_NETCP_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G, i);\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
}\r
\r
- //SB CMU and COMLANE Enable\r
- CSL_EthernetSerdesComEnable(CSL_NETCP_SERDES_CFG_REGS);\r
-\r
- //SB Lane Enable\r
- for(i=0; i < UTF_NUM_MAC_PORTS; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE);\r
- }\r
-\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);\r
-\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, UTF_NUM_MAC_PORTS);\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* 4 port switch1 */\r
+\r
+ if (numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* 4 port switch2 */\r
+ } \r
+ \r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+ if(numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
+\r
+#elif defined(DEVICE_K2L)\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ uint32_t serdes_mux_ethernet_sel;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
+\r
+\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_CSISC2_2_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ \r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* SGMII Lane 0 and Lane 1 */\r
+ \r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ } \r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+ if(serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
#endif\r
- }\r
+\r
+ }\r
\r
/* SGMII SERDES Configuration complete. Return. */\r
return 0;\r
*/\r
\r
#include "uTestCpsw.h"\r
+#include <stdlib.h>\r
#include <xdc/runtime/System.h>\r
extern void utilCycleDelay (int count);\r
/*\r
*/\r
static int32_t initSGMIISerdes(void)\r
{\r
- CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
+ CSL_SERDES_LOOPBACK lpbk_mode = (cpswLpbkMode == CPSW_LOOPBACK_SERDES)?CSL_SERDES_LOOPBACK_ENABLED:CSL_SERDES_LOOPBACK_DISABLED;\r
\r
- if(!cpswSimTest)\r
- {\r
+ if(!cpswSimTest)\r
+ {\r
#if defined(DEVICE_K2K) || defined(DEVICE_K2H)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G);\r
-\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
-\r
- //SB Lane Enable\r
- for(i=0; i < NUM_MAC_PORTS; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE);\r
- }\r
-\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_CFG_REGS);\r
-\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_CFG_REGS, NUM_MAC_PORTS);\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params;\r
+\r
+ memset(&serdes_lane_enable_params, 0, sizeof(serdes_lane_enable_params));\r
+ serdes_lane_enable_params.base_addr = CSL_NETCP_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params.num_lanes = UTF_NUM_MAC_PORTS;\r
+ serdes_lane_enable_params.phy_type = SERDES_SGMII;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params.loopback_mode[i] = lpbk_mode;\r
+ \r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ \r
+ serdes_lane_enable_params.lane_mask = (1 << serdes_lane_enable_params.num_lanes) - 1;\r
+ serdes_lane_enable_params.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+ \r
+ /* Att and Boost values are obtained through Serdes Diagnostic PRBS calibration test */\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params.base_addr,\r
+ serdes_lane_enable_params.ref_clock,\r
+ serdes_lane_enable_params.linkrate);\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
\r
#elif defined(DEVICE_K2E)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = 0;\r
- CSL_SERDES_STATUS pllstat;\r
- int numPort1 = (NUM_MAC_PORTS > 4)?4:NUM_MAC_PORTS;\r
- int numPort2 = (NUM_MAC_PORTS > 4)?NUM_MAC_PORTS - 4:0;\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ int numPort1 = (UTF_NUM_MAC_PORTS > 4)?4:UTF_NUM_MAC_PORTS;\r
+ int numPort2 = (UTF_NUM_MAC_PORTS > 4)?UTF_NUM_MAC_PORTS - 4:0;\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_NETCP_SERDES_0_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_NETCP_SERDES_1_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_3p125G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_HALF_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
\r
\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_0_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch1 */\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* 4 port switch1 */\r
\r
if (numPort2)\r
{\r
- csl_retval |= CSL_EthernetSerdesInit(CSL_NETCP_SERDES_1_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch2 */\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* 4 port switch2 */\r
+ } \r
+ \r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
}\r
\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
- //SB Lane Enable\r
- for(i=0; i < numPort1; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch1 */\r
- }\r
-\r
- for(i=0; i < numPort2; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch2 */\r
- }\r
-\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_0_CFG_REGS); /* 4 port switch1 */\r
- if(numPort2)\r
- CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_1_CFG_REGS); /* 4 port switch2 */\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_0_CFG_REGS, numPort1); /* 4 port switch1 */\r
- if(numPort2)\r
- pllstat &= CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_1_CFG_REGS, numPort2); /* 4 port switch2 */\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ if(numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
\r
#elif defined(DEVICE_K2L)\r
- uint32_t i;\r
- CSL_SERDES_RESULT csl_retval;\r
- CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
- CSL_SERDES_STATUS pllstat;\r
- uint32_t serdes_mux_ethernet_sel;\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ uint32_t serdes_mux_ethernet_sel;\r
int numPort1 = (UTF_NUM_MAC_PORTS > 2)?2:UTF_NUM_MAC_PORTS;\r
int numPort2 = (UTF_NUM_MAC_PORTS > 2)?UTF_NUM_MAC_PORTS - 2:0;\r
\r
\r
- /* Check CSISC2_3_MUXSEL bit */\r
- if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
- serdes_mux_ethernet_sel = 1;\r
-\r
- /* SB CMU and COMLANE and Lane Setup */\r
- csl_retval = CSL_EthernetSerdesInit(CSL_CSISC2_2_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 0 and Lane 1 */\r
-\r
- if (serdes_mux_ethernet_sel && numPort2)\r
- {\r
- csl_retval |= CSL_EthernetSerdesInit(CSL_CSISC2_3_SERDES_CFG_REGS,\r
- CSL_SERDES_REF_CLOCK_156p25M,\r
- CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 2 and Lane 3 */\r
- }\r
-\r
- if (csl_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Init Params\n");\r
- }\r
-\r
- //SB Lane Enable\r
- for(i=0; i < numPort1; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */\r
- }\r
-\r
- if (serdes_mux_ethernet_sel && numPort2)\r
+ CSL_SERDES_LANE_ENABLE_PARAMS_T serdes_lane_enable_params1, serdes_lane_enable_params2;\r
+\r
+ memset(&serdes_lane_enable_params1, 0, sizeof(serdes_lane_enable_params1));\r
+ memset(&serdes_lane_enable_params2, 0, sizeof(serdes_lane_enable_params2));\r
+\r
+ serdes_lane_enable_params1.base_addr = CSL_CSISC2_2_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params1.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params1.num_lanes = numPort1;\r
+ serdes_lane_enable_params1.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params1.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
+\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
{\r
- for(i=0; i < numPort1; i++)\r
- {\r
- lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,\r
- i,\r
- lpbk_mode,\r
- CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */\r
- }\r
+ serdes_lane_enable_params1.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params1.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params1.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params1.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params1.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params1.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params1.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params1.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params1.tx_coeff.tx_vreg[i] = 4;\r
}\r
+ serdes_lane_enable_params1.lane_mask = (1 << serdes_lane_enable_params1.num_lanes) - 1;;\r
+ serdes_lane_enable_params1.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ serdes_lane_enable_params2.base_addr = CSL_CSISC2_3_SERDES_CFG_REGS;\r
+ serdes_lane_enable_params2.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;\r
+ serdes_lane_enable_params2.linkrate = CSL_SERDES_LINK_RATE_1p25G;\r
+ serdes_lane_enable_params2.num_lanes = numPort2;\r
+ serdes_lane_enable_params2.phy_type = SERDES_SGMII;\r
+ serdes_lane_enable_params2.forceattboost = CSL_SERDES_FORCE_ATT_BOOST_DISABLED;\r
\r
- if (lane_retval != 0)\r
- {\r
- System_printf ("Invalid Serdes Lane Rate\n");\r
- }\r
-\r
- /* SB PLL Enable */\r
- CSL_EthernetSerdesPllEnable(CSL_CSISC2_2_SERDES_CFG_REGS); /* SGMII Lane 0 and Lane 1 */\r
-\r
- /* Check CSISC2_3_MUXSEL bit */\r
- if (serdes_mux_ethernet_sel)\r
- CSL_EthernetSerdesPllEnable(CSL_CSISC2_3_SERDES_CFG_REGS); /* SGMII Lane 2 and Lane 3 */\r
-\r
- /* SB PLL Status Poll */\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetStatus(CSL_CSISC2_2_SERDES_CFG_REGS, numPort1); /* SGMII Lane 0 and Lane 1 */\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
-\r
- /* Check CSISC2_3_MUXSEL bit */\r
- if (serdes_mux_ethernet_sel)\r
- {\r
- do\r
- {\r
- pllstat = CSL_EthernetSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, numPort2); /* SGMII Lane 2 and Lane 3 */\r
- }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
- }\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_ctrl_rate[i] = CSL_SERDES_LANE_QUARTER_RATE;\r
+ serdes_lane_enable_params2.loopback_mode[i] = lpbk_mode;\r
+\r
+ /* When RX auto adaptation is on, these are the starting values used for att, boost adaptation */\r
+ serdes_lane_enable_params2.rx_coeff.att_start[i] = 7;\r
+ serdes_lane_enable_params2.rx_coeff.boost_start[i] = 5;\r
+\r
+ /* For higher speeds PHY-A, force attenuation and boost values */\r
+ serdes_lane_enable_params2.rx_coeff.force_att_val[i] = 1;\r
+ serdes_lane_enable_params2.rx_coeff.force_boost_val[i] = 1;\r
+\r
+ /* CM, C1, C2 are obtained through Serdes Diagnostic BER test */\r
+ serdes_lane_enable_params2.tx_coeff.cm_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c1_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.c2_coeff[i] = 0;\r
+ serdes_lane_enable_params2.tx_coeff.tx_att[i] = 12;\r
+ serdes_lane_enable_params2.tx_coeff.tx_vreg[i] = 4;\r
+ }\r
+ serdes_lane_enable_params2.lane_mask = (1 << serdes_lane_enable_params2.num_lanes) - 1;;\r
+ serdes_lane_enable_params2.operating_mode = CSL_SERDES_FUNCTIONAL_MODE;\r
+\r
+ \r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(serdes_lane_enable_params1.base_addr,\r
+ serdes_lane_enable_params1.ref_clock,\r
+ serdes_lane_enable_params1.linkrate); /* SGMII Lane 0 and Lane 1 */\r
+ \r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(serdes_lane_enable_params2.base_addr,\r
+ serdes_lane_enable_params2.ref_clock,\r
+ serdes_lane_enable_params2.linkrate); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+\r
+ if (csl_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Init Params\n");\r
+ } \r
+\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params1.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params1.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params1.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params1.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params1);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+\r
+ if(serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ /* Common Init Mode */\r
+ /* Iteration Mode needs to be set to Common Init Mode first with a lane_mask value equal to the total number of lanes being configured */\r
+ /* The lane_mask is a don't care for Common Init as it operates on all lanes. It always sets it to 0xF internally in the API */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT;\r
+ serdes_lane_enable_params2.lane_mask = 0xF;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Common Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Common Init Complete\n");\r
+\r
+ /* Lane Init Mode */\r
+ /* Once CSL_SerdesLaneEnable is called with iteration_mode = CSL_SERDES_LANE_ENABLE_COMMON_INIT, the lanes needs to be enabled by setting\r
+ iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT with the lane_mask equal to the specific lane being configured */\r
+ /* For example, if lane 0 is being configured, lane mask needs to be set to 0x1. if lane 1 is being configured, lane mask needs to be 0x2 etc */\r
+ serdes_lane_enable_params2.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;\r
+ for(i=0; i< serdes_lane_enable_params2.num_lanes; i++)\r
+ {\r
+ serdes_lane_enable_params2.lane_mask = 1<<i;\r
+ lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params2);\r
+ if (lane_retval != 0)\r
+ {\r
+ System_printf ("Invalid Serdes Lane Enable Init\n");\r
+ exit(0);\r
+ }\r
+ System_printf("SGMII Serdes Lane %d Init Complete\n", i);\r
+ }\r
+ }\r
#endif\r
\r
- }\r
+ }\r
\r
/* SGMII SERDES Configuration complete. Return. */\r
return 0;\r