]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - keystone-rtos/uart-lld.git/commitdiff
PDK-3715: Migrate to new CSL SOC alias change
authorSivaraj R <sivaraj@ti.com>
Tue, 5 Mar 2019 05:23:08 +0000 (10:53 +0530)
committerSivaraj R <sivaraj@ti.com>
Wed, 6 Mar 2019 01:33:39 +0000 (19:33 -0600)
Signed-off-by: Sivaraj R <sivaraj@ti.com>
soc/j721e/UART_soc.c

index d192a0b38446a57efa93d4c6c1179c7c1bac664b..7278bc07e9df28dc79d7b158148f51b9923d91b9 100644 (file)
@@ -56,10 +56,10 @@ UART_HwAttrs uartInitCfg[CSL_UART_PER_CNT] =
     {
 #if defined (__aarch64__) /* main */
         CSL_UART0_BASE,                      /* baseAddr */
-        CSL_GIC0_INTR_UART0_USART_IRQ,       /* intNum */
+        CSLR_COMPUTE_CLUSTER0_GIC_SPI_UART0_USART_IRQ_0,       /* intNum */
 #else /* mcu */
         CSL_MCU_UART0_BASE,
-        CSL_MCU0_INTR_MCU_UART0_USART_IRQ,
+        CSLR_MCU_ARMSS0_CPU0_INTR_MCU_UART0_USART_IRQ_0,
 #endif
         0,                              /* eventId, used only for C6x */
 #if defined (__aarch64__) /* main */
@@ -86,7 +86,7 @@ UART_HwAttrs uartInitCfg[CSL_UART_PER_CNT] =
     {
 #if defined (__aarch64__)
         CSL_UART1_BASE,                      /* baseAddr */
-        CSL_GIC0_INTR_UART1_USART_IRQ,  /* intNum */
+        CSLR_COMPUTE_CLUSTER0_GIC_SPI_UART1_USART_IRQ_0,  /* intNum */
 #else
         0,
         0,
@@ -110,7 +110,7 @@ UART_HwAttrs uartInitCfg[CSL_UART_PER_CNT] =
     {
 #if defined (__aarch64__)
         CSL_UART2_BASE,                      /* baseAddr */
-        CSL_GIC0_INTR_UART2_USART_IRQ,  /* intNum */
+        CSLR_COMPUTE_CLUSTER0_GIC_SPI_UART2_USART_IRQ_0,  /* intNum */
 #else
         0,
         0,