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raw | patch | inline | side by side (parent: 90c5e5e)
raw | patch | inline | side by side (parent: 90c5e5e)
author | Frank Livingston <frank-livingston@ti.com> | |
Thu, 7 Feb 2019 16:22:39 +0000 (10:22 -0600) | ||
committer | Raghu Nambiath <a0850439@ti.com> | |
Thu, 7 Feb 2019 23:32:02 +0000 (17:32 -0600) |
Loopback Pair 0: disabled (since this pair includes HW IP instance)
Loopback Pari 2: enabled
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
Loopback Pari 2: enabled
Signed-off-by: Frank Livingston <frank-livingston@ti.com>
test/firmware_test/src/test_utils.c | patch | blob | history |
index a50e2772dd8ed7b49feb9eab4e77e3f64a37a249..e062dc015dd2264b806694a6f504e9f858cd08ea 100644 (file)
@@ -298,9 +298,9 @@ uint16_t gTestStressRdData16bP2S1[TEST_STRESS_MAX_RD_DATA_SZ] __attribute__ ((al
// All baud rate 115200
TestStressUartCfgPrms gTestStressUartCfgPrms[TEST_STRESS_NUM_UART_LB_PAIR] = {
- {BAUD_RATE_115200, UART_LEN_8, UART_STOP_TWO, UART_PAR_ODD, UART_FC_HW, 0x10}, // Pair 0: UART1 HW IP <-> PRU0 UART0 SW IP
+ {BAUD_RATE_115200, UART_LEN_8, UART_STOP_TWO, UART_PAR_ODD, UART_FC_NONE, 0x0}, // Pair 0: UART1 HW IP <-> PRU0 UART0 SW IP
{BAUD_RATE_115200, UART_LEN_9, UART_STOP_ONEP5, UART_PAR_EVEN, UART_FC_NONE, 0x0}, // Pair 1: PRU0 UART2 SW IP <-> PRU0 UART1 SW IP
- {BAUD_RATE_115200, UART_LEN_5, UART_STOP_ONE, UART_PAR_NONE, UART_FC_NONE, 0x0}, // Pair 2: PRU1 UART2 SW IP <-> PRU1 UART1 SW IP
+ {BAUD_RATE_115200, UART_LEN_5, UART_STOP_ONE, UART_PAR_NONE, UART_FC_HW, 0x10}, // Pair 2: PRU1 UART2 SW IP <-> PRU1 UART1 SW IP
};
// Small number of transfers
//TestStressUartXferPrms gTestStressUartXferPrms[TEST_STRESS_NUM_UART_LB_PAIR][TEST_STRESS_NUM_SIDE_PER_LB_PAIR] = {