Bug Fix: PDK-4174

[UDMA] Application ring, descriptor and buffers alloc size should be cacheline aligned

Resolution:
Fixed the app to allocate multipel of 128 byte for
these entries

Signed-off-by: Sivaraj R <sivaraj@ti.com>

diff --git a/examples/udma_adc_test/udma_adc_test.c b/examples/udma_adc_test/udma_adc_test.c
index 99c0e2f5ef76a9a52d9734ca614c8586118212b8..581ce433f58175161fc6a6c38244e7950b76bc83 100644 (file)
--- a/examples/udma_adc_test/udma_adc_test.c
+++ b/examples/udma_adc_test/udma_adc_test.c
@@ -84,12 +84,12 @@
 /** \brief Total ring memory */
 #define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_TEST_APP_RING_ENTRIES * \
                                          UDMA_TEST_APP_RING_ENTRY_SIZE)
-/**
- *  \brief UDMA host mode buffer descriptor memory size.
- *  Make it multiple of 128 byte alignment
- */
-#define UDMA_TEST_APP_DESC_SIZE         (sizeof(CSL_UdmapCppi5HMPD) + \
-                                            (128U - sizeof(CSL_UdmapCppi5HMPD)))
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
+/** \brief UDMA host mode buffer descriptor memory size. */
+#define UDMA_TEST_APP_DESC_SIZE         (sizeof(CSL_UdmapCppi5HMPD))
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_DESC_SIZE_ALIGN   ((UDMA_TEST_APP_DESC_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 
 /* ========================================================================== */
 /*                         Structure Declarations                             */
@@ -145,10 +145,10 @@ struct Udma_EventObj    gUdmaTdCqEventObj;
 /*
  * UDMA Memories
  */
-static uint8_t gRxFqRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gRxCqRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gRxTdCqRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaRxHpdMem[UDMA_TEST_APP_DESC_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gRxFqRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gRxCqRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gRxTdCqRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaRxHpdMem[UDMA_TEST_APP_DESC_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 /*
  * Application Buffers

diff --git a/examples/udma_chaining_test/udma_chaining_test.c b/examples/udma_chaining_test/udma_chaining_test.c
index b5b948dc55b73c305541abc2711d4a2e020497e5..28590d96c66d94a13607552d744dc747024f1975 100644 (file)
--- a/examples/udma_chaining_test/udma_chaining_test.c
+++ b/examples/udma_chaining_test/udma_chaining_test.c
@@ -64,6 +64,8 @@
  */
 /** \brief Number of bytes to copy and buffer allocation */
 #define UDMA_TEST_APP_NUM_BYTES         (1000U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_BUF_SIZE_ALIGN    ((UDMA_TEST_APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 /** \brief Number of times to perform the memcpy operation */
 #define UDMA_TEST_APP_LOOP_CNT          (100U)
 /** \brief Number of channels */
@@ -91,8 +93,6 @@
 #define UDMA_TEST_APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
 /** \brief This ensures every channel memory is aligned */
 #define UDMA_TEST_APP_TRPD_SIZE_ALIGN   ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
-/** \brief This ensures every channel memory is aligned */
-#define UDMA_TEST_APP_BUF_SIZE_ALIGN    ((UDMA_TEST_APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 
 /* ========================================================================== */
 /*                         Structure Declarations                             */

diff --git a/examples/udma_crc_test/udma_crc_test.c b/examples/udma_crc_test/udma_crc_test.c
index cdbe30c3e02ff6818540def63a9dc4083c6668dc..f6254d26c62fc4033b56b63828da8666459438ef 100644 (file)
--- a/examples/udma_crc_test/udma_crc_test.c
+++ b/examples/udma_crc_test/udma_crc_test.c
@@ -72,6 +72,8 @@
 /** \brief Total ring memory */
 #define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_TEST_APP_RING_ENTRIES * \
                                          UDMA_TEST_APP_RING_ENTRY_SIZE)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 /**
  *  \brief UDMA TR packet descriptor memory.
  *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
@@ -80,6 +82,8 @@
  *  CSL_UdmapTR15 for alignment.
  */
 #define UDMA_TEST_APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_TRPD_SIZE_ALIGN   ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 
 /* Pre-calculated crc signature value for given data pattern */
 #define APP_CRC_REFERENCE_SIGN_VAL_L    (0x83A8C73AU)
@@ -89,6 +93,7 @@
 #define APP_FRAME_HEIGHT                ((uint32_t) 200U)
 #define APP_FRAME_WIDTH                 ((uint32_t) 100U)
 #define APP_FRAME_SIZE                  (APP_FRAME_HEIGHT * APP_FRAME_WIDTH)
+#define APP_FRAME_SIZE_ALIGN            ((APP_FRAME_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 
 /* CRC channel parameters */
 #define APP_CRC_CHANNEL                 (CRC_CHANNEL_1)
@@ -156,15 +161,15 @@ struct Udma_EventObj    gUdmaTdCqEventObj;
 /*
  * UDMA Memories
  */
-static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 /*
  * Application Buffers
  */
-static uint8_t gCrcSrcBuf[APP_FRAME_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".data"))) = {1U};
+static uint8_t gCrcSrcBuf[APP_FRAME_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".data"))) = {1U};
 
 /* Semaphore to indicate transfer completion */
 static SemaphoreP_Handle gUdmaAppDoneSem = NULL;

diff --git a/examples/udma_dru_direct_tr_test/udma_dru_direct_tr_test.c b/examples/udma_dru_direct_tr_test/udma_dru_direct_tr_test.c
index 1c69a73294022c4839cbdb72791b4325d749c0ce..abcc93c0230a0aa85ef563f4d1aabcfa00d9c089 100644 (file)
--- a/examples/udma_dru_direct_tr_test/udma_dru_direct_tr_test.c
+++ b/examples/udma_dru_direct_tr_test/udma_dru_direct_tr_test.c
@@ -58,6 +58,9 @@
  */
 /** \brief Number of bytes to copy and buffer allocation */
 #define UDMA_TEST_APP_NUM_BYTES         (100U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_NUM_BYTES_ALIGN    ((UDMA_TEST_APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
+
 /** \brief Number of times to perform the memcpy operation */
 #define UDMA_TEST_APP_LOOP_CNT          (10U)
 
@@ -109,8 +112,8 @@ struct Udma_EventObj    gUdmaTrEventObj;
 /*
  * Application Buffers
  */
-static uint8_t gUdmaTestSrcBuf[UDMA_TEST_APP_NUM_BYTES] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaTestDestBuf[UDMA_TEST_APP_NUM_BYTES] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTestSrcBuf[UDMA_TEST_APP_NUM_BYTES_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTestDestBuf[UDMA_TEST_APP_NUM_BYTES_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 /* Semaphore to indicate transfer completion */
 static SemaphoreP_Handle gUdmaAppDoneSem = NULL;

diff --git a/examples/udma_dru_test/udma_dru_test.c b/examples/udma_dru_test/udma_dru_test.c
index 1d053f894b0f8e6d00a47214f1d8519dd2a4e97b..8d564c935b80d62787da9adf0e6691241b0f42e2 100644 (file)
--- a/examples/udma_dru_test/udma_dru_test.c
+++ b/examples/udma_dru_test/udma_dru_test.c
@@ -59,6 +59,8 @@
  */
 /** \brief Number of bytes to copy and buffer allocation */
 #define UDMA_TEST_APP_NUM_BYTES         (1000U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_NUM_BYTES_ALIGN   ((UDMA_TEST_APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 /** \brief Number of times to perform the memcpy operation */
 #define UDMA_TEST_APP_LOOP_CNT          (100U)
 
@@ -72,6 +74,8 @@
 /** \brief Total ring memory */
 #define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_TEST_APP_RING_ENTRIES * \
                                          UDMA_TEST_APP_RING_ENTRY_SIZE)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 /**
  *  \brief UDMA TR packet descriptor memory.
  *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
@@ -80,6 +84,8 @@
  *  CSL_UdmapTR15 for alignment.
  */
 #define UDMA_TEST_APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_TRPD_SIZE_ALIGN   ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 
 /* ========================================================================== */
 /*                         Structure Declarations                             */
@@ -130,16 +136,16 @@ struct Udma_EventObj    gUdmaTdCqEventObj;
 /*
  * UDMA Memories
  */
-static uint8_t gDruRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gDruCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gDruTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gDruRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gDruCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gDruTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 /*
  * Application Buffers
  */
-static uint8_t gUdmaTestSrcBuf[UDMA_TEST_APP_NUM_BYTES] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaTestDestBuf[UDMA_TEST_APP_NUM_BYTES] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTestSrcBuf[UDMA_TEST_APP_NUM_BYTES_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTestDestBuf[UDMA_TEST_APP_NUM_BYTES_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 /* Semaphore to indicate transfer completion */
 static SemaphoreP_Handle gUdmaAppDoneSem = NULL;

diff --git a/examples/udma_memcpy_test/udma_memcpy_test.c b/examples/udma_memcpy_test/udma_memcpy_test.c
index b17353e0ea526a029ec44c06425c147769bb2726..3627ab04169a554f70ed69b01c01aed647b99df8 100644 (file)
--- a/examples/udma_memcpy_test/udma_memcpy_test.c
+++ b/examples/udma_memcpy_test/udma_memcpy_test.c
@@ -59,6 +59,8 @@
  */
 /** \brief Number of bytes to copy and buffer allocation */
 #define UDMA_TEST_APP_NUM_BYTES         (1000U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_NUM_BYTES_ALIGN    ((UDMA_TEST_APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 /** \brief Number of times to perform the memcpy operation */
 #define UDMA_TEST_APP_LOOP_CNT          (100U)
 
@@ -69,9 +71,13 @@
 #define UDMA_TEST_APP_RING_ENTRIES      (1U)
 /** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
 #define UDMA_TEST_APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
-/** \brief Total ring memory */
-#define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_TEST_APP_RING_ENTRIES * \
-                                         UDMA_TEST_APP_RING_ENTRY_SIZE)
+/** \brief Total ring memory - this should be cache line aligned so that
+ *   when cache ops are performed it doesn't corrupt the data adjacent to it.
+ *   Also this should be greater than or equal to
+ *   (UDMA_TEST_APP_RING_ENTRIES * UDMA_TEST_APP_RING_ENTRY_SIZE) */
+#define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_CACHELINE_ALIGNMENT)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 /**
  *  \brief UDMA TR packet descriptor memory.
  *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
@@ -80,6 +86,8 @@
  *  CSL_UdmapTR15 for alignment.
  */
 #define UDMA_TEST_APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
+/** \brief This ensures every channel memory is aligned */
+#define UDMA_TEST_APP_TRPD_SIZE_ALIGN   ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
 
 #define UDMA_TEST_INTR
 
@@ -138,16 +146,16 @@ struct Udma_EventObj    gUdmaTdCqEventObj;
 /*
  * UDMA Memories
  */
-static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 /*
  * Application Buffers
  */
-static uint8_t gUdmaTestSrcBuf[UDMA_TEST_APP_NUM_BYTES] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
-static uint8_t gUdmaTestDestBuf[UDMA_TEST_APP_NUM_BYTES] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTestSrcBuf[UDMA_TEST_APP_NUM_BYTES_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
+static uint8_t gUdmaTestDestBuf[UDMA_TEST_APP_NUM_BYTES_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
 
 #if defined (UDMA_TEST_INTR)
 /* Semaphore to indicate transfer completion */