]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - keystone-rtos/vps.git/commitdiff
PDK-2798 Adding Cache Invalidate All API
authorPiyali Goswami <piyali_g@ti.com>
Tue, 22 May 2018 05:30:53 +0000 (11:00 +0530)
committerPiyali Goswami <a0131625@ti.com>
Tue, 22 May 2018 09:14:21 +0000 (14:44 +0530)
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
include/osal/bsp_osal.h
src/osal/baremetal/osal_cache.c
src/osal/tirtos/bsp_osal.c

index 10765ea94d5351665f0c0eb8d364a0bb2886d6a8..3fec48afe2e6e677798c79f756a528c1a16003ce 100644 (file)
@@ -544,6 +544,11 @@ void BspOsal_cacheWb(void *blockPtr, UInt32 byteCnt, UInt32 type,
  */
 void BspOsal_cacheWbAll(void);
 
+/**
+ *  \brief API to Invalidate the complete cache
+ */
+void BspOsal_cacheInvAll(void);
+
 /**
  *  \brief API to invalidate the write back for cache module
  *
index 5324d4d7ca8da260b25666cda89dc834ffb17c7d..e2d1031cebdf10cb2884c5abc0b21afd94576d7a 100644 (file)
@@ -150,6 +150,22 @@ void BspOsal_cacheInv(void *blockPtr,
     return;
 }
 
+void BspOsal_cacheInvAll(void)
+{
+#if defined (__ARM_ARCH_7A__)
+    CACHEA15InvalidateL1IAll();
+    CACHEA15InvalidateL1DAll();
+#endif
+
+#if defined (__TI_ARM_V7M4__)
+    UNICACHEInvalidateAll(
+        SOC_IPU1_UNICACHE_MMU_CONF_REGS_BASE,
+        UNICACHE_WAIT_INFINITE);
+#endif
+
+    return;
+}
+
 void BspOsal_cacheWb(void *blockPtr,
                      UInt32 byteCnt,
                      UInt32 type,
index 76a794abd6443ac15cbca7d108bd472b195146df..8989a851446e0adef3903bdc532eb47f4cb15b2f 100644 (file)
@@ -52,7 +52,7 @@
 /* Include Family specific hwi files */
 #if defined (__TI_ARM_V7M4__) || defined (BUILD_M3)
 #include <ti/sysbios/family/arm/m3/Hwi.h>
-#include <ti/sysbios/hal/Cache.h>
+#include <ti/sysbios/hal/unicache/Cache.h>
 #elif defined (_TMS320C6X)
 #include <ti/sysbios/family/c64p/EventCombiner.h>
 #include <ti/sysbios/family/c64p/Hwi.h>
@@ -1137,6 +1137,23 @@ void BspOsal_cacheWbAll(void)
     return;
 }
 
+void BspOsal_cacheInvAll(void)
+{
+    UInt32 savedSafetyMode =
+        BspSafetyOsal_setSafetyMode(BSP_SAFETY_OSAL_MODE_ASIL);
+#if defined (__ARM_ARCH_7A__)
+#if !defined (BSP_OSAL_SMP_MODE_ENABLE)
+    Cache_invL1dAll();
+#endif
+    Cache_invL1pAll();
+#endif
+#if defined (__TI_ARM_V7M4__)
+    Cache_invAll();
+#endif
+    BspSafetyOsal_setSafetyMode(savedSafetyMode);
+    return;
+}
+
 void BspOsal_cacheWbInv(void  *blockPtr,
                         UInt32 byteCnt,
                         UInt32 type,