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PDK-2508 Pad Configuration changes for Cascade Radar
authorPiyali Goswami <a0131625@ti.com>
Fri, 4 May 2018 19:35:25 +0000 (01:05 +0530)
committerPiyali Goswami <a0131625@ti.com>
Fri, 4 May 2018 20:21:14 +0000 (01:51 +0530)
Signed-off-by: Piyali Goswami <a0131625@ti.com>
src/boards/src/bsp_boardTda2xx.c patch | blob | history

diff --git a/src/boards/src/bsp_boardTda2xx.c b/src/boards/src/bsp_boardTda2xx.c
index 316fed3f85aee53a5418f2d378f797003f8243c1..28def08586cff7dd1e4edfa974ebb1c1932ebece 100755 (executable)
--- a/src/boards/src/bsp_boardTda2xx.c
+++ b/src/boards/src/bsp_boardTda2xx.c
@@ -71,6 +71,9 @@
 #if defined (SOC_TDA2PX)
 #include <bsp_boardTda2pxCalDev.h>
 #endif
+#if defined (BOARD_TYPE_TDA2XX_CASCADE_RADAR)
+#include <ti/drv/stw_lld/platform/platform.h>
+#endif
 
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
@@ -233,6 +236,11 @@ static Int32 Bsp_boardTda2xxMmcsdLdoPwr(void);
 static void Bsp_boardSetPinMuxTda2xxMC(void);
 #endif
 
+#if defined (BOARD_TYPE_TDA2XX_CASCADE_RADAR)
+static void Bsp_boardTda2xxCascadeAwr12xxPadConfig(void);
+static void Bsp_boardTda2xxCascadeVipPadConfig(void);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
@@ -415,6 +423,10 @@ extern Bsp_BoardData        gBoardTda3xxDefaultData;
 Int32 Bsp_boardTda2xxInit(void)
 {
 #if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA75x) || defined (SOC_TDA2EX)
+#if defined (BOARD_TYPE_TDA2XX_CASCADE_RADAR)
+    Bsp_boardTda2xxCascadeAwr12xxPadConfig();
+    Bsp_boardTda2xxCascadeVipPadConfig();
+#else
     /* Enable GPIO required for video mux as output */
     GPIOModuleEnable(BOARD_GPIO_BASE_MUX_SEL);
     GPIOModuleEnable(BOARD_GPIO_BASE_POWER_DWN);
@@ -472,6 +484,7 @@ Int32 Bsp_boardTda2xxInit(void)
 #if defined (TDA2XX_MC_BUILD)
     Bsp_boardSetPinMuxTda2xxMC();
 #endif
+#endif
 #endif
 
     return (BSP_SOK);
@@ -3348,3 +3361,306 @@ static Int32 Bsp_boardTda2xxMmcsdLdoPwr(void)
 }
 
 #endif
+
+#if defined (BOARD_TYPE_TDA2XX_CASCADE_RADAR)
+void Bsp_boardTda2xxCascadeAwr12xxPadConfig(void)
+{
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_UART1_CTSN,   /* gpio7_24 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_A12,     /* gpio2_2 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_VOUT1_D16,   /* gpio8_16 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_A19,     /* gpio2_9 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_VOUT1_D17,     /* gpio8_17 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_A20,     /* gpio2_10 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_UART1_RTSN,     /* gpio7_25 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_A21,    /* gpio2_11 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_A22,     /* gpio2_12 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_CLK,     /* gpio2_22 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_WEN,     /* gpio2_25 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_GPMC_A23,     /* 0x18 - gpio2_13 */
+                            0x8);
+    Bsp_platformSetPinmuxRegs((UInt32) 0x1,
+                            (UInt32) CTRL_CORE_PAD_MMC3_DAT2,     /* SPI3 */
+                            0x6);
+    Bsp_platformSetPinmuxRegs((UInt32) 0x1,
+                            (UInt32) CTRL_CORE_PAD_MMC3_DAT3,     /* SPI3 */
+                            0x6);
+    Bsp_platformSetPinmuxRegs((UInt32) 0x1,
+                            (UInt32) CTRL_CORE_PAD_MMC3_DAT0,     /* SPI3 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0x1,
+                            (UInt32) CTRL_CORE_PAD_MMC3_DAT1,     /* SPI3 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0x1,
+                            (UInt32) CTRL_CORE_PAD_MMC3_CMD,     /* SPI3 */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_MCASP1_AXR8,     /* SPI Int */
+                            0xC);
+    Bsp_platformSetPinmuxRegs((UInt32) 0xE,
+                            (UInt32) CTRL_CORE_PAD_MCASP1_AXR9,     /* SPI Int */
+                            0xC);
+    PlatformMCSPI1SetPinMux();
+    PlatformMCSPI2SetPinMux();
+}
+
+void Bsp_boardTda2xxCascadeVipPadConfig(void)
+{
+    /* VIN1A */
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_CLK0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_DE0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                               (UInt32) CTRL_CORE_PAD_VIN1A_VSYNC0,
+                               BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D1,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D2,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D3,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D4,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D5,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D6,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D7,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D8,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D9,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D10,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D11,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D12,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D13,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D14,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN1A_D15,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    /* VIP2A */
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_CLK0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_DE0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_VSYNC0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D1,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D2,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D3,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D4,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D5,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D6,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D7,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D8,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D9,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D10,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D11,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D12,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D13,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D14,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 0,
+                              (UInt32) CTRL_CORE_PAD_VIN2A_D15,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    /* VIN3A */
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_CS3,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_A10,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_A9,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD1,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD2,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD3,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD4,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD5,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD6,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD7,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD8,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD9,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD10,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD11,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD12,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD13,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD14,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 2,
+                              (UInt32) CTRL_CORE_PAD_GPMC_AD15,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    /* VIN4A */
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_XREF_CLK2,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_XREF_CLK3,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_GPIO6_15,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_ACLKR,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_FSR,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_AXR2,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_AXR3,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_AXR4,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_AXR5,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_AXR6,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP1_AXR7,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_ACLKR,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_FSR,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_AXR0,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_AXR1,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_AXR4,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_AXR5,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_AXR6,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+    Bsp_platformSetPinmuxRegs((UInt32) 8,
+                              (UInt32) CTRL_CORE_PAD_MCASP2_AXR7,
+                              BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI);
+}
+#endif
+
+
Project to include GIT repos for RTOS components including user mode CSL & NetCP LLDs (CPPI/QMSS/PA/RM), PDK components (NWAL/PKTLIB) and Transport Net Lib components (NetAPI/HPLIB) - Common driver module supporting VIP,VPE and DSS peripherals. Includes capture, display and M2M interface.