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32 //*****************************************************************************\r
33 //\r
34 // adc12_a.c - Driver for the adc12_a Module.\r
35 //\r
36 //*****************************************************************************\r
37 \r
38 //*****************************************************************************\r
39 //\r
40 //! \addtogroup adc12_a_api\r
41 //! @{\r
42 //\r
43 //*****************************************************************************\r
44 \r
45 #include "inc/hw_regaccess.h"\r
46 #include "inc/hw_memmap.h"\r
47 \r
48 #ifdef __MSP430_HAS_ADC12_PLUS__\r
49 #include "adc12_a.h"\r
50 \r
51 #include <assert.h>\r
52 \r
53 //*****************************************************************************\r
54 //\r
55 //! \brief Initializes the ADC12_A Module.\r
56 //!\r
57 //! This function initializes the ADC module to allow for analog-to-digital\r
58 //! conversions. Specifically this function sets up the sample-and-hold signal\r
59 //! and clock sources for the ADC core to use for conversions. Upon successful\r
60 //! completion of the initialization all of the ADC control registers will be\r
61 //! reset, excluding the memory controls and reference module bits, the given\r
62 //! parameters will be set, and the ADC core will be turned on (Note, that the\r
63 //! ADC core only draws power during conversions and remains off when not\r
64 //! converting).Note that sample/hold signal sources are device dependent. Note\r
65 //! that if re-initializing the ADC after starting a conversion with the\r
66 //! startConversion() function, the disableConversion() must be called BEFORE\r
67 //! this function can be called.\r
68 //!\r
69 //! \param baseAddress is the base address of the ADC12_A module.\r
70 //! \param sampleHoldSignalSourceSelect is the signal that will trigger a\r
71 //! sample-and-hold for an input signal to be converted. This parameter\r
72 //! is device specific and sources should be found in the device's\r
73 //! datasheet.\r
74 //! Valid values are:\r
75 //! - \b ADC12_A_SAMPLEHOLDSOURCE_SC [Default]\r
76 //! - \b ADC12_A_SAMPLEHOLDSOURCE_1\r
77 //! - \b ADC12_A_SAMPLEHOLDSOURCE_2\r
78 //! - \b ADC12_A_SAMPLEHOLDSOURCE_3 - This parameter is device specific\r
79 //! and sources should be found in the device's datasheet.\r
80 //! \n Modified bits are \b ADC12SHSx of \b ADC12CTL1 register.\r
81 //! \param clockSourceSelect selects the clock that will be used by the ADC12_A\r
82 //! core, and the sampling timer if a sampling pulse mode is enabled.\r
83 //! Valid values are:\r
84 //! - \b ADC12_A_CLOCKSOURCE_ADC12OSC [Default] - MODOSC 5 MHz\r
85 //! oscillator from the UCS\r
86 //! - \b ADC12_A_CLOCKSOURCE_ACLK - The Auxiliary Clock\r
87 //! - \b ADC12_A_CLOCKSOURCE_MCLK - The Master Clock\r
88 //! - \b ADC12_A_CLOCKSOURCE_SMCLK - The Sub-Master Clock\r
89 //! \n Modified bits are \b ADC12SSELx of \b ADC12CTL1 register.\r
90 //! \param clockSourceDivider selects the amount that the clock will be\r
91 //! divided.\r
92 //! Valid values are:\r
93 //! - \b ADC12_A_CLOCKDIVIDER_1 [Default]\r
94 //! - \b ADC12_A_CLOCKDIVIDER_2\r
95 //! - \b ADC12_A_CLOCKDIVIDER_3\r
96 //! - \b ADC12_A_CLOCKDIVIDER_4\r
97 //! - \b ADC12_A_CLOCKDIVIDER_5\r
98 //! - \b ADC12_A_CLOCKDIVIDER_6\r
99 //! - \b ADC12_A_CLOCKDIVIDER_7\r
100 //! - \b ADC12_A_CLOCKDIVIDER_8\r
101 //! - \b ADC12_A_CLOCKDIVIDER_12\r
102 //! - \b ADC12_A_CLOCKDIVIDER_16\r
103 //! - \b ADC12_A_CLOCKDIVIDER_20\r
104 //! - \b ADC12_A_CLOCKDIVIDER_24\r
105 //! - \b ADC12_A_CLOCKDIVIDER_28\r
106 //! - \b ADC12_A_CLOCKDIVIDER_32\r
107 //! \n Modified bits are \b ADC12PDIV of \b ADC12CTL2 register; bits \b\r
108 //! ADC12DIVx of \b ADC12CTL1 register.\r
109 //!\r
110 //! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process.\r
111 //\r
112 //*****************************************************************************\r
113 bool ADC12_A_init(uint16_t baseAddress,\r
114 uint16_t sampleHoldSignalSourceSelect,\r
115 uint8_t clockSourceSelect,\r
116 uint16_t clockSourceDivider)\r
117 {\r
118 assert(sampleHoldSignalSourceSelect <= ADC12_A_SAMPLEHOLDSOURCE_3);\r
119 assert(clockSourceSelect <= ADC12_A_CLOCKSOURCE_SMCLK);\r
120 assert(clockSourceDivider <= ADC12_A_CLOCKDIVIDER_32);\r
121 \r
122 //Make sure the ENC bit is cleared before initializing the ADC12_A\r
123 HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;\r
124 \r
125 bool retVal = STATUS_SUCCESS;\r
126 \r
127 //Turn OFF ADC12_A Module & Clear Interrupt Registers\r
128 HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12OVIE + ADC12TOVIE\r
129 + ADC12ENC + ADC12SC);\r
130 HWREG16(baseAddress + OFS_ADC12IE) &= 0x0000; //Reset ALL interrupt enables\r
131 HWREG16(baseAddress + OFS_ADC12IFG) &= 0x0000; //Reset ALL interrupt flags\r
132 \r
133 //Set ADC12_A Control 1\r
134 HWREG16(baseAddress + OFS_ADC12CTL1) =\r
135 sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source\r
136 + (clockSourceDivider & ADC12DIV_7) //Set Clock Divider\r
137 + clockSourceSelect; //Setup Clock Source\r
138 \r
139 //Set ADC12_A Control 2\r
140 HWREG16(baseAddress + OFS_ADC12CTL2) =\r
141 (clockSourceDivider & ADC12PDIV) //Set Clock Pre-Divider\r
142 + ADC12RES_2; //Default resolution to 12-bits\r
143 \r
144 return retVal;\r
145 }\r
146 \r
147 //*****************************************************************************\r
148 //\r
149 //! \brief Enables the ADC12_A block.\r
150 //!\r
151 //! This will enable operation of the ADC12_A block.\r
152 //!\r
153 //! \param baseAddress is the base address of the ADC12_A module.\r
154 //!\r
155 //! Modified bits are \b ADC12ON of \b ADC12CTL0 register.\r
156 //!\r
157 //! \return None\r
158 //\r
159 //*****************************************************************************\r
160 void ADC12_A_enable(uint16_t baseAddress)\r
161 {\r
162 //Enable the ADC12_A Module\r
163 HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ON;\r
164 }\r
165 \r
166 //*****************************************************************************\r
167 //\r
168 //! \brief Disables the ADC12_A block.\r
169 //!\r
170 //! This will disable operation of the ADC12_A block.\r
171 //!\r
172 //! \param baseAddress is the base address of the ADC12_A module.\r
173 //!\r
174 //! Modified bits are \b ADC12ON of \b ADC12CTL0 register.\r
175 //!\r
176 //! \return None\r
177 //\r
178 //*****************************************************************************\r
179 void ADC12_A_disable(uint16_t baseAddress)\r
180 {\r
181 //Disable ADC12_A module\r
182 HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ON;\r
183 }\r
184 \r
185 //*****************************************************************************\r
186 //\r
187 //! \brief Sets up and enables the Sampling Timer Pulse Mode.\r
188 //!\r
189 //! This function sets up the sampling timer pulse mode which allows the\r
190 //! sample/hold signal to trigger a sampling timer to sample-and-hold an input\r
191 //! signal for a specified number of clock cycles without having to hold the\r
192 //! sample/hold signal for the entire period of sampling. Note that if a\r
193 //! conversion has been started with the startConversion() function, then a\r
194 //! call to disableConversions() is required before this function may be\r
195 //! called.\r
196 //!\r
197 //! \param baseAddress is the base address of the ADC12_A module.\r
198 //! \param clockCycleHoldCountLowMem sets the amount of clock cycles to sample-\r
199 //! and-hold for the higher memory buffers 0-7.\r
200 //! Valid values are:\r
201 //! - \b ADC12_A_CYCLEHOLD_4_CYCLES [Default]\r
202 //! - \b ADC12_A_CYCLEHOLD_8_CYCLES\r
203 //! - \b ADC12_A_CYCLEHOLD_16_CYCLES\r
204 //! - \b ADC12_A_CYCLEHOLD_32_CYCLES\r
205 //! - \b ADC12_A_CYCLEHOLD_64_CYCLES\r
206 //! - \b ADC12_A_CYCLEHOLD_96_CYCLES\r
207 //! - \b ADC12_A_CYCLEHOLD_128_CYCLES\r
208 //! - \b ADC12_A_CYCLEHOLD_192_CYCLES\r
209 //! - \b ADC12_A_CYCLEHOLD_256_CYCLES\r
210 //! - \b ADC12_A_CYCLEHOLD_384_CYCLES\r
211 //! - \b ADC12_A_CYCLEHOLD_512_CYCLES\r
212 //! - \b ADC12_A_CYCLEHOLD_768_CYCLES\r
213 //! - \b ADC12_A_CYCLEHOLD_1024_CYCLES\r
214 //! \n Modified bits are \b ADC12SHT0x of \b ADC12CTL0 register.\r
215 //! \param clockCycleHoldCountHighMem sets the amount of clock cycles to\r
216 //! sample-and-hold for the higher memory buffers 8-15.\r
217 //! Valid values are:\r
218 //! - \b ADC12_A_CYCLEHOLD_4_CYCLES [Default]\r
219 //! - \b ADC12_A_CYCLEHOLD_8_CYCLES\r
220 //! - \b ADC12_A_CYCLEHOLD_16_CYCLES\r
221 //! - \b ADC12_A_CYCLEHOLD_32_CYCLES\r
222 //! - \b ADC12_A_CYCLEHOLD_64_CYCLES\r
223 //! - \b ADC12_A_CYCLEHOLD_96_CYCLES\r
224 //! - \b ADC12_A_CYCLEHOLD_128_CYCLES\r
225 //! - \b ADC12_A_CYCLEHOLD_192_CYCLES\r
226 //! - \b ADC12_A_CYCLEHOLD_256_CYCLES\r
227 //! - \b ADC12_A_CYCLEHOLD_384_CYCLES\r
228 //! - \b ADC12_A_CYCLEHOLD_512_CYCLES\r
229 //! - \b ADC12_A_CYCLEHOLD_768_CYCLES\r
230 //! - \b ADC12_A_CYCLEHOLD_1024_CYCLES\r
231 //! \n Modified bits are \b ADC12SHT1x of \b ADC12CTL0 register.\r
232 //! \param multipleSamplesEnabled allows multiple conversions to start without\r
233 //! a trigger signal from the sample/hold signal\r
234 //! Valid values are:\r
235 //! - \b ADC12_A_MULTIPLESAMPLESDISABLE [Default] - a timer trigger will\r
236 //! be needed to start every ADC conversion.\r
237 //! - \b ADC12_A_MULTIPLESAMPLESENABLE - during a sequenced and/or\r
238 //! repeated conversion mode, after the first conversion, no\r
239 //! sample/hold signal is necessary to start subsequent sample/hold\r
240 //! and convert processes.\r
241 //! \n Modified bits are \b ADC12MSC of \b ADC12CTL0 register.\r
242 //!\r
243 //! \return None\r
244 //\r
245 //*****************************************************************************\r
246 void ADC12_A_setupSamplingTimer(uint16_t baseAddress,\r
247 uint16_t clockCycleHoldCountLowMem,\r
248 uint16_t clockCycleHoldCountHighMem,\r
249 uint16_t multipleSamplesEnabled)\r
250 {\r
251 //Make sure the ENC bit is cleared before setting up sampling pulse mode\r
252 assert( !(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );\r
253 \r
254 assert(clockCycleHoldCountLowMem <= ADC12_A_CYCLEHOLD_1024_CYCLES);\r
255 assert(clockCycleHoldCountHighMem <= ADC12_A_CYCLEHOLD_1024_CYCLES);\r
256 \r
257 HWREG16(baseAddress + OFS_ADC12CTL1) |= ADC12SHP;\r
258 \r
259 //Reset clock cycle hold counts and msc bit before setting them\r
260 HWREG16(baseAddress + OFS_ADC12CTL0) &=\r
261 ~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC);\r
262 \r
263 //Set clock cycle hold counts and msc bit\r
264 HWREG16(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem\r
265 + (clockCycleHoldCountHighMem << 4)\r
266 + multipleSamplesEnabled;\r
267 }\r
268 \r
269 //*****************************************************************************\r
270 //\r
271 //! \brief Disables Sampling Timer Pulse Mode.\r
272 //!\r
273 //! Disables the Sampling Timer Pulse Mode. Note that if a conversion has been\r
274 //! started with the startConversion() function, then a call to\r
275 //! disableConversions() is required before this function may be called.\r
276 //!\r
277 //! \param baseAddress is the base address of the ADC12_A module.\r
278 //!\r
279 //! Modified bits are \b ADC12SHP of \b ADC12CTL0 register.\r
280 //!\r
281 //! \return None\r
282 //\r
283 //*****************************************************************************\r
284 void ADC12_A_disableSamplingTimer(uint16_t baseAddress)\r
285 {\r
286 //Make sure the ENC bit is cleared before disabling sampling pulse mode\r
287 assert( !(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );\r
288 \r
289 HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP);\r
290 }\r
291 \r
292 //*****************************************************************************\r
293 //\r
294 //! \brief DEPRECATED - Configures the controls of the selected memory buffer.\r
295 //!\r
296 //! Maps an input signal conversion into the selected memory buffer, as well as\r
297 //! the positive and negative reference voltages for each conversion being\r
298 //! stored into this memory buffer. If the internal reference is used for the\r
299 //! positive reference voltage, the internal REF module must be used to control\r
300 //! the voltage level. Note that if a conversion has been started with the\r
301 //! startConversion() function, then a call to disableConversions() is required\r
302 //! before this function may be called.\r
303 //!\r
304 //! \param baseAddress is the base address of the ADC12_A module.\r
305 //! \param memoryBufferControlIndex is the selected memory buffer to set the\r
306 //! configuration for.\r
307 //! Valid values are:\r
308 //! - \b ADC12_A_MEMORY_0 [Default]\r
309 //! - \b ADC12_A_MEMORY_1\r
310 //! - \b ADC12_A_MEMORY_2\r
311 //! - \b ADC12_A_MEMORY_3\r
312 //! - \b ADC12_A_MEMORY_4\r
313 //! - \b ADC12_A_MEMORY_5\r
314 //! - \b ADC12_A_MEMORY_6\r
315 //! - \b ADC12_A_MEMORY_7\r
316 //! - \b ADC12_A_MEMORY_8\r
317 //! - \b ADC12_A_MEMORY_9\r
318 //! - \b ADC12_A_MEMORY_10\r
319 //! - \b ADC12_A_MEMORY_11\r
320 //! - \b ADC12_A_MEMORY_12\r
321 //! - \b ADC12_A_MEMORY_13\r
322 //! - \b ADC12_A_MEMORY_14\r
323 //! - \b ADC12_A_MEMORY_15\r
324 //! \param inputSourceSelect is the input that will store the converted data\r
325 //! into the specified memory buffer.\r
326 //! Valid values are:\r
327 //! - \b ADC12_A_INPUT_A0 [Default]\r
328 //! - \b ADC12_A_INPUT_A1\r
329 //! - \b ADC12_A_INPUT_A2\r
330 //! - \b ADC12_A_INPUT_A3\r
331 //! - \b ADC12_A_INPUT_A4\r
332 //! - \b ADC12_A_INPUT_A5\r
333 //! - \b ADC12_A_INPUT_A6\r
334 //! - \b ADC12_A_INPUT_A7\r
335 //! - \b ADC12_A_INPUT_A8\r
336 //! - \b ADC12_A_INPUT_A9\r
337 //! - \b ADC12_A_INPUT_TEMPSENSOR\r
338 //! - \b ADC12_A_INPUT_BATTERYMONITOR\r
339 //! - \b ADC12_A_INPUT_A12\r
340 //! - \b ADC12_A_INPUT_A13\r
341 //! - \b ADC12_A_INPUT_A14\r
342 //! - \b ADC12_A_INPUT_A15\r
343 //! \n Modified bits are \b ADC12INCHx of \b ADC12MCTLx register.\r
344 //! \param positiveRefVoltageSourceSelect is the reference voltage source to\r
345 //! set as the upper limit for the conversion stored in the specified\r
346 //! memory.\r
347 //! Valid values are:\r
348 //! - \b ADC12_A_VREFPOS_AVCC [Default]\r
349 //! - \b ADC12_A_VREFPOS_EXT\r
350 //! - \b ADC12_A_VREFPOS_INT\r
351 //! \n Modified bits are \b ADC12SREF of \b ADC12MCTLx register.\r
352 //! \param negativeRefVoltageSourceSelect is the reference voltage source to\r
353 //! set as the lower limit for the conversion stored in the specified\r
354 //! memory.\r
355 //! Valid values are:\r
356 //! - \b ADC12_A_VREFNEG_AVSS [Default]\r
357 //! - \b ADC12_A_VREFNEG_EXT\r
358 //! \n Modified bits are \b ADC12SREF of \b ADC12MCTLx register.\r
359 //! \param endOfSequence indicates that the specified memory buffer will be the\r
360 //! end of the sequence if a sequenced conversion mode is selected\r
361 //! Valid values are:\r
362 //! - \b ADC12_A_NOTENDOFSEQUENCE [Default] - The specified memory\r
363 //! buffer will NOT be the end of the sequence OR a sequenced\r
364 //! conversion mode is not selected.\r
365 //! - \b ADC12_A_ENDOFSEQUENCE - The specified memory buffer will be the\r
366 //! end of the sequence.\r
367 //! \n Modified bits are \b ADC12EOS of \b ADC12MCTLx register.\r
368 //!\r
369 //! \return None\r
370 //\r
371 //*****************************************************************************\r
372 void ADC12_A_memoryConfigure(uint16_t baseAddress,\r
373 uint8_t memoryBufferControlIndex,\r
374 uint8_t inputSourceSelect,\r
375 uint8_t positiveRefVoltageSourceSelect,\r
376 uint8_t negativeRefVoltageSourceSelect,\r
377 uint8_t endOfSequence)\r
378 {\r
379 ADC12_A_configureMemoryParam param = { 0 };\r
380 \r
381 param.memoryBufferControlIndex = memoryBufferControlIndex;\r
382 param.inputSourceSelect = inputSourceSelect;\r
383 param.positiveRefVoltageSourceSelect = positiveRefVoltageSourceSelect;\r
384 param.negativeRefVoltageSourceSelect = negativeRefVoltageSourceSelect;\r
385 param.endOfSequence = endOfSequence;\r
386 \r
387 ADC12_A_configureMemory(baseAddress, ¶m);\r
388 }\r
389 \r
390 //*****************************************************************************\r
391 //\r
392 //! \brief Configures the controls of the selected memory buffer.\r
393 //!\r
394 //! Maps an input signal conversion into the selected memory buffer, as well as\r
395 //! the positive and negative reference voltages for each conversion being\r
396 //! stored into this memory buffer. If the internal reference is used for the\r
397 //! positive reference voltage, the internal REF module must be used to control\r
398 //! the voltage level. Note that if a conversion has been started with the\r
399 //! startConversion() function, then a call to disableConversions() is required\r
400 //! before this function may be called.\r
401 //!\r
402 //! \param baseAddress is the base address of the ADC12_A module.\r
403 //! \param param is the pointer to struct for memory configuration.\r
404 //!\r
405 //! \return None\r
406 //\r
407 //*****************************************************************************\r
408 void ADC12_A_configureMemory(uint16_t baseAddress,\r
409 ADC12_A_configureMemoryParam *param)\r
410 {\r
411 assert(param != 0);\r
412 \r
413 //Make sure the ENC bit is cleared before configuring a Memory Buffer Control\r
414 assert(!(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );\r
415 \r
416 assert(param->memoryBufferControlIndex <= ADC12_A_MEMORY_15);\r
417 assert(param->inputSourceSelect <= ADC12_A_INPUT_A15);\r
418 assert(param->positiveRefVoltageSourceSelect <= ADC12_A_VREFPOS_INT);\r
419 assert(param->negativeRefVoltageSourceSelect <= ADC12_A_VREFNEG_EXT);\r
420 \r
421 //Set the offset in respect to ADC12MCTL0\r
422 uint16_t memoryBufferControlOffset =\r
423 (OFS_ADC12MCTL0 + param->memoryBufferControlIndex);\r
424 \r
425 //Reset the memory buffer control and Set the input source\r
426 HWREG8(baseAddress + memoryBufferControlOffset) =\r
427 param->inputSourceSelect //Set Input Source\r
428 + param->positiveRefVoltageSourceSelect //Set Vref+\r
429 + param->negativeRefVoltageSourceSelect //Set Vref-\r
430 + param->endOfSequence; //Set End of Sequence\r
431 } //*****************************************************************************\r
432 //\r
433 //! \brief Enables selected ADC12_A interrupt sources.\r
434 //!\r
435 //! Enables the indicated ADC12_A interrupt sources. Only the sources that are\r
436 //! enabled can be reflected to the processor interrupt, disabled sources have\r
437 //! no effect on the processor. Does not clear interrupt flags.\r
438 //!\r
439 //! \param baseAddress is the base address of the ADC12_A module.\r
440 //! \param interruptMask\r
441 //! Mask value is the logical OR of any of the following:\r
442 //! - \b ADC12_A_IE0\r
443 //! - \b ADC12_A_IE1\r
444 //! - \b ADC12_A_IE2\r
445 //! - \b ADC12_A_IE3\r
446 //! - \b ADC12_A_IE4\r
447 //! - \b ADC12_A_IE5\r
448 //! - \b ADC12_A_IE6\r
449 //! - \b ADC12_A_IE7\r
450 //! - \b ADC12_A_IE8\r
451 //! - \b ADC12_A_IE9\r
452 //! - \b ADC12_A_IE10\r
453 //! - \b ADC12_A_IE11\r
454 //! - \b ADC12_A_IE12\r
455 //! - \b ADC12_A_IE13\r
456 //! - \b ADC12_A_IE14\r
457 //! - \b ADC12_A_IE15\r
458 //! - \b ADC12_A_OVERFLOW_IE\r
459 //! - \b ADC12_A_CONVERSION_TIME_OVERFLOW_IE\r
460 //!\r
461 //! Modified bits of \b ADC12IE register and bits of \b ADC12CTL0 register.\r
462 //!\r
463 //! \return None\r
464 //\r
465 //*****************************************************************************\r
466 void ADC12_A_enableInterrupt(uint16_t baseAddress,\r
467 uint32_t interruptMask)\r
468 {\r
469 assert(interruptMask <= (ADC12IE0 +\r
470 ADC12IE1 +\r
471 ADC12IE2 +\r
472 ADC12IE3 +\r
473 ADC12IE4 +\r
474 ADC12IE5 +\r
475 ADC12IE6 +\r
476 ADC12IE7 +\r
477 ADC12IE8 +\r
478 ADC12IE9 +\r
479 ADC12IE10 +\r
480 ADC12IE11 +\r
481 ADC12IE12 +\r
482 ADC12IE13 +\r
483 ADC12IE14 +\r
484 ADC12IE15 +\r
485 ADC12OVIE0 +\r
486 ADC12TOVIE0\r
487 ));\r
488 \r
489 if (interruptMask & ADC12_A_CONVERSION_TIME_OVERFLOW_IE) {\r
490 HWREG16(baseAddress + OFS_ADC12CTL0) |= ADC12TOVIE;\r
491 interruptMask &= ~ADC12TOVIE0;\r
492 }\r
493 if (interruptMask & ADC12_A_OVERFLOW_IE) {\r
494 HWREG16(baseAddress + OFS_ADC12CTL0) |= ADC12OVIE;\r
495 interruptMask &= ~ADC12OVIE0;\r
496 }\r
497 \r
498 HWREG16(baseAddress + OFS_ADC12IE) |= interruptMask;\r
499 }\r
500 \r
501 //*****************************************************************************\r
502 //\r
503 //! \brief Disables selected ADC12_A interrupt sources.\r
504 //!\r
505 //! Disables the indicated ADC12_A interrupt sources. Only the sources that\r
506 //! are enabled can be reflected to the processor interrupt, disabled sources\r
507 //! have no effect on the processor.\r
508 //!\r
509 //! \param baseAddress is the base address of the ADC12_A module.\r
510 //! \param interruptMask\r
511 //! Mask value is the logical OR of any of the following:\r
512 //! - \b ADC12_A_IE0\r
513 //! - \b ADC12_A_IE1\r
514 //! - \b ADC12_A_IE2\r
515 //! - \b ADC12_A_IE3\r
516 //! - \b ADC12_A_IE4\r
517 //! - \b ADC12_A_IE5\r
518 //! - \b ADC12_A_IE6\r
519 //! - \b ADC12_A_IE7\r
520 //! - \b ADC12_A_IE8\r
521 //! - \b ADC12_A_IE9\r
522 //! - \b ADC12_A_IE10\r
523 //! - \b ADC12_A_IE11\r
524 //! - \b ADC12_A_IE12\r
525 //! - \b ADC12_A_IE13\r
526 //! - \b ADC12_A_IE14\r
527 //! - \b ADC12_A_IE15\r
528 //! - \b ADC12_A_OVERFLOW_IE\r
529 //! - \b ADC12_A_CONVERSION_TIME_OVERFLOW_IE\r
530 //!\r
531 //! Modified bits of \b ADC12IE register and bits of \b ADC12CTL0 register.\r
532 //!\r
533 //! \return None\r
534 //\r
535 //*****************************************************************************\r
536 void ADC12_A_disableInterrupt(uint16_t baseAddress,\r
537 uint32_t interruptMask)\r
538 {\r
539 assert(interruptMask <= (ADC12IE0 +\r
540 ADC12IE1 +\r
541 ADC12IE2 +\r
542 ADC12IE3 +\r
543 ADC12IE4 +\r
544 ADC12IE5 +\r
545 ADC12IE6 +\r
546 ADC12IE7 +\r
547 ADC12IE8 +\r
548 ADC12IE9 +\r
549 ADC12IE10 +\r
550 ADC12IE11 +\r
551 ADC12IE12 +\r
552 ADC12IE13 +\r
553 ADC12IE14 +\r
554 ADC12IE15 +\r
555 ADC12OVIE0 +\r
556 ADC12TOVIE0\r
557 ));\r
558 \r
559 if (interruptMask & ADC12_A_CONVERSION_TIME_OVERFLOW_IE) {\r
560 HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12TOVIE);\r
561 interruptMask &= ~ADC12TOVIE0;\r
562 }\r
563 if (interruptMask & ADC12_A_OVERFLOW_IE) {\r
564 HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12OVIE);\r
565 interruptMask &= ~ADC12OVIE0;\r
566 }\r
567 \r
568 HWREG16(baseAddress + OFS_ADC12IE) &= ~(interruptMask);\r
569 }\r
570 \r
571 //*****************************************************************************\r
572 //\r
573 //! \brief Clears ADC12_A selected interrupt flags.\r
574 //!\r
575 //! The selected ADC12_A interrupt flags are cleared, so that it no longer\r
576 //! asserts. The memory buffer interrupt flags are only cleared when the memory\r
577 //! buffer is accessed. Note that the overflow interrupts do not have an\r
578 //! interrupt flag to clear; they must be accessed directly from the interrupt\r
579 //! vector.\r
580 //!\r
581 //! \param baseAddress is the base address of the ADC12_A module.\r
582 //! \param memoryInterruptFlagMask is a bit mask of the interrupt flags to be\r
583 //! cleared.\r
584 //! Mask value is the logical OR of any of the following:\r
585 //! - \b ADC12_A_IFG0\r
586 //! - \b ADC12_A_IFG1\r
587 //! - \b ADC12_A_IFG2\r
588 //! - \b ADC12_A_IFG3\r
589 //! - \b ADC12_A_IFG4\r
590 //! - \b ADC12_A_IFG5\r
591 //! - \b ADC12_A_IFG6\r
592 //! - \b ADC12_A_IFG7\r
593 //! - \b ADC12_A_IFG8\r
594 //! - \b ADC12_A_IFG9\r
595 //! - \b ADC12_A_IFG10\r
596 //! - \b ADC12_A_IFG11\r
597 //! - \b ADC12_A_IFG12\r
598 //! - \b ADC12_A_IFG13\r
599 //! - \b ADC12_A_IFG14\r
600 //! - \b ADC12_A_IFG15\r
601 //!\r
602 //! Modified bits of \b ADC12IFG register.\r
603 //!\r
604 //! \return None\r
605 //\r
606 //*****************************************************************************\r
607 void ADC12_A_clearInterrupt(uint16_t baseAddress,\r
608 uint16_t memoryInterruptFlagMask)\r
609 {\r
610 HWREG16(baseAddress + OFS_ADC12IFG) &= ~(memoryInterruptFlagMask);\r
611 }\r
612 \r
613 //*****************************************************************************\r
614 //\r
615 //! \brief Returns the status of the selected memory interrupt flags.\r
616 //!\r
617 //! Returns the status of the selected memory interrupt flags. Note that the\r
618 //! overflow interrupts do not have an interrupt flag to clear; they must be\r
619 //! accessed directly from the interrupt vector.\r
620 //!\r
621 //! \param baseAddress is the base address of the ADC12_A module.\r
622 //! \param memoryInterruptFlagMask is a bit mask of the interrupt flags status\r
623 //! to be returned.\r
624 //! Mask value is the logical OR of any of the following:\r
625 //! - \b ADC12_A_IFG0\r
626 //! - \b ADC12_A_IFG1\r
627 //! - \b ADC12_A_IFG2\r
628 //! - \b ADC12_A_IFG3\r
629 //! - \b ADC12_A_IFG4\r
630 //! - \b ADC12_A_IFG5\r
631 //! - \b ADC12_A_IFG6\r
632 //! - \b ADC12_A_IFG7\r
633 //! - \b ADC12_A_IFG8\r
634 //! - \b ADC12_A_IFG9\r
635 //! - \b ADC12_A_IFG10\r
636 //! - \b ADC12_A_IFG11\r
637 //! - \b ADC12_A_IFG12\r
638 //! - \b ADC12_A_IFG13\r
639 //! - \b ADC12_A_IFG14\r
640 //! - \b ADC12_A_IFG15\r
641 //!\r
642 //! \return The current interrupt flag status for the corresponding mask.\r
643 //\r
644 //*****************************************************************************\r
645 uint8_t ADC12_A_getInterruptStatus(uint16_t baseAddress,\r
646 uint16_t memoryInterruptFlagMask)\r
647 {\r
648 return HWREG16(baseAddress + OFS_ADC12IFG) & memoryInterruptFlagMask;\r
649 }\r
650 \r
651 //*****************************************************************************\r
652 //\r
653 //! \brief Enables/Starts an Analog-to-Digital Conversion.\r
654 //!\r
655 //! This function enables/starts the conversion process of the ADC. If the\r
656 //! sample/hold signal source chosen during initialization was ADC12OSC, then\r
657 //! the conversion is started immediately, otherwise the chosen sample/hold\r
658 //! signal source starts the conversion by a rising edge of the signal. Keep in\r
659 //! mind when selecting conversion modes, that for sequenced and/or repeated\r
660 //! modes, to keep the sample/hold-and-convert process continuing without a\r
661 //! trigger from the sample/hold signal source, the multiple samples must be\r
662 //! enabled using the ADC12_A_setupSamplingTimer() function. Note that after\r
663 //! this function is called, the ADC12_A_disableConversions() has to be called\r
664 //! to re-initialize the ADC, reconfigure a memory buffer control,\r
665 //! enable/disable the sampling timer, or to change the internal reference\r
666 //! voltage.\r
667 //!\r
668 //! \param baseAddress is the base address of the ADC12_A module.\r
669 //! \param startingMemoryBufferIndex is the memory buffer that will hold the\r
670 //! first or only conversion.\r
671 //! Valid values are:\r
672 //! - \b ADC12_A_MEMORY_0 [Default]\r
673 //! - \b ADC12_A_MEMORY_1\r
674 //! - \b ADC12_A_MEMORY_2\r
675 //! - \b ADC12_A_MEMORY_3\r
676 //! - \b ADC12_A_MEMORY_4\r
677 //! - \b ADC12_A_MEMORY_5\r
678 //! - \b ADC12_A_MEMORY_6\r
679 //! - \b ADC12_A_MEMORY_7\r
680 //! - \b ADC12_A_MEMORY_8\r
681 //! - \b ADC12_A_MEMORY_9\r
682 //! - \b ADC12_A_MEMORY_10\r
683 //! - \b ADC12_A_MEMORY_11\r
684 //! - \b ADC12_A_MEMORY_12\r
685 //! - \b ADC12_A_MEMORY_13\r
686 //! - \b ADC12_A_MEMORY_14\r
687 //! - \b ADC12_A_MEMORY_15\r
688 //! \n Modified bits are \b ADC12STARTADDx of \b ADC12CTL1 register.\r
689 //! \param conversionSequenceModeSelect determines the ADC operating mode.\r
690 //! Valid values are:\r
691 //! - \b ADC12_A_SINGLECHANNEL [Default] - one-time conversion of a\r
692 //! single channel into a single memory buffer.\r
693 //! - \b ADC12_A_SEQOFCHANNELS - one time conversion of multiple\r
694 //! channels into the specified starting memory buffer and each\r
695 //! subsequent memory buffer up until the conversion is stored in a\r
696 //! memory buffer dedicated as the end-of-sequence by the memory's\r
697 //! control register.\r
698 //! - \b ADC12_A_REPEATED_SINGLECHANNEL - repeated conversions of one\r
699 //! channel into a single memory buffer.\r
700 //! - \b ADC12_A_REPEATED_SEQOFCHANNELS - repeated conversions of\r
701 //! multiple channels into the specified starting memory buffer and\r
702 //! each subsequent memory buffer up until the conversion is stored\r
703 //! in a memory buffer dedicated as the end-of-sequence by the\r
704 //! memory's control register.\r
705 //! \n Modified bits are \b ADC12CONSEQx of \b ADC12CTL1 register.\r
706 //!\r
707 //! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register.\r
708 //!\r
709 //! \return None\r
710 //\r
711 //*****************************************************************************\r
712 void ADC12_A_startConversion(uint16_t baseAddress,\r
713 uint16_t startingMemoryBufferIndex,\r
714 uint8_t conversionSequenceModeSelect)\r
715 {\r
716 assert(startingMemoryBufferIndex <= ADC12_A_MEMORY_15);\r
717 assert(conversionSequenceModeSelect <= ADC12_A_REPEATED_SEQOFCHANNELS);\r
718 \r
719 //Reset the ENC bit to set the starting memory address and conversion mode\r
720 //sequence\r
721 HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);\r
722 //Reset the bits about to be set\r
723 HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12CSTARTADD_15 + ADC12CONSEQ_3);\r
724 \r
725 HWREG8(baseAddress + OFS_ADC12CTL1_H) |= (startingMemoryBufferIndex << 4);\r
726 HWREG8(baseAddress + OFS_ADC12CTL1_L) |= conversionSequenceModeSelect;\r
727 HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC;\r
728 }\r
729 \r
730 //*****************************************************************************\r
731 //\r
732 //! \brief Disables the ADC from converting any more signals.\r
733 //!\r
734 //! Disables the ADC from converting any more signals. If there is a conversion\r
735 //! in progress, this function can stop it immediately if the preempt parameter\r
736 //! is set as TRUE, by changing the conversion mode to single-channel, single-\r
737 //! conversion and disabling conversions. If the conversion mode is set as\r
738 //! single-channel, single-conversion and this function is called without\r
739 //! preemption, then the ADC core conversion status is polled until the\r
740 //! conversion is complete before disabling conversions to prevent\r
741 //! unpredictable data. If the ADC12_A_startConversion() has been called, then\r
742 //! this function has to be called to re-initialize the ADC, reconfigure a\r
743 //! memory buffer control, enable/disable the sampling pulse mode, or change\r
744 //! the internal reference voltage.\r
745 //!\r
746 //! \param baseAddress is the base address of the ADC12_A module.\r
747 //! \param preempt specifies if the current conversion should be pre-empted\r
748 //! before the end of the conversion.\r
749 //! Valid values are:\r
750 //! - \b ADC12_A_COMPLETECONVERSION - Allows the ADC12_A to end the\r
751 //! current conversion before disabling conversions.\r
752 //! - \b ADC12_A_PREEMPTCONVERSION - Stops the ADC12_A immediately, with\r
753 //! unpredictable results of the current conversion.\r
754 //!\r
755 //! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register.\r
756 //!\r
757 //! \return None\r
758 //\r
759 //*****************************************************************************\r
760 void ADC12_A_disableConversions(uint16_t baseAddress, bool preempt)\r
761 {\r
762 if (ADC12_A_PREEMPTCONVERSION == preempt)\r
763 HWREG8(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3);\r
764 //Reset conversion sequence mode to single-channel, single-conversion\r
765 else if (~(HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3)) {\r
766 //To prevent preemoption of a single-channel, single-conversion we must\r
767 //wait for the ADC core to finish the conversion.\r
768 while (ADC12_A_isBusy(baseAddress)) ;\r
769 }\r
770 \r
771 HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);\r
772 }\r
773 \r
774 //*****************************************************************************\r
775 //\r
776 //! \brief A Signed Integer of the contents of the specified memory buffer\r
777 //!\r
778 //! Returns the raw contents of the specified memory buffer. The format of the\r
779 //! content depends on the read-back format of the data: if the data is in\r
780 //! signed 2's complement format then the contents in the memory buffer will be\r
781 //! left-justified with the least-significant bits as 0's, whereas if the data\r
782 //! is in unsigned format then the contents in the memory buffer will be right-\r
783 //! justified with the most-significant bits as 0's.\r
784 //!\r
785 //! \param baseAddress is the base address of the ADC12_A module.\r
786 //! \param memoryBufferIndex is the specified Memory Buffer to read.\r
787 //! Valid values are:\r
788 //! - \b ADC12_A_MEMORY_0 [Default]\r
789 //! - \b ADC12_A_MEMORY_1\r
790 //! - \b ADC12_A_MEMORY_2\r
791 //! - \b ADC12_A_MEMORY_3\r
792 //! - \b ADC12_A_MEMORY_4\r
793 //! - \b ADC12_A_MEMORY_5\r
794 //! - \b ADC12_A_MEMORY_6\r
795 //! - \b ADC12_A_MEMORY_7\r
796 //! - \b ADC12_A_MEMORY_8\r
797 //! - \b ADC12_A_MEMORY_9\r
798 //! - \b ADC12_A_MEMORY_10\r
799 //! - \b ADC12_A_MEMORY_11\r
800 //! - \b ADC12_A_MEMORY_12\r
801 //! - \b ADC12_A_MEMORY_13\r
802 //! - \b ADC12_A_MEMORY_14\r
803 //! - \b ADC12_A_MEMORY_15\r
804 //!\r
805 //! \return A signed integer of the contents of the specified memory buffer\r
806 //\r
807 //*****************************************************************************\r
808 uint16_t ADC12_A_getResults(uint16_t baseAddress, uint8_t memoryBufferIndex)\r
809 {\r
810 assert(memoryBufferIndex <= ADC12_A_MEMORY_15);\r
811 \r
812 return HWREG16(baseAddress + (0x20 + (memoryBufferIndex * 2)));\r
813 //(0x20 + (memoryBufferIndex * 2)) == offset of ADC12MEMx\r
814 }\r
815 \r
816 //*****************************************************************************\r
817 //\r
818 //! \brief Use to change the resolution of the converted data.\r
819 //!\r
820 //! This function can be used to change the resolution of the converted data\r
821 //! from the default of 12-bits.\r
822 //!\r
823 //! \param baseAddress is the base address of the ADC12_A module.\r
824 //! \param resolutionSelect determines the resolution of the converted data.\r
825 //! Valid values are:\r
826 //! - \b ADC12_A_RESOLUTION_8BIT\r
827 //! - \b ADC12_A_RESOLUTION_10BIT\r
828 //! - \b ADC12_A_RESOLUTION_12BIT [Default]\r
829 //! \n Modified bits are \b ADC12RESx of \b ADC12CTL2 register.\r
830 //!\r
831 //! \return None\r
832 //\r
833 //*****************************************************************************\r
834 void ADC12_A_setResolution(uint16_t baseAddress,\r
835 uint8_t resolutionSelect)\r
836 {\r
837 assert(resolutionSelect <= ADC12_A_RESOLUTION_12BIT);\r
838 \r
839 HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3);\r
840 HWREG8(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect;\r
841 }\r
842 \r
843 //*****************************************************************************\r
844 //\r
845 //! \brief Use to invert or un-invert the sample/hold signal.\r
846 //!\r
847 //! This function can be used to invert or un-invert the sample/hold signal.\r
848 //! Note that if a conversion has been started with the startConversion()\r
849 //! function, then a call to disableConversions() is required before this\r
850 //! function may be called.\r
851 //!\r
852 //! \param baseAddress is the base address of the ADC12_A module.\r
853 //! \param invertedSignal set if the sample/hold signal should be inverted\r
854 //! Valid values are:\r
855 //! - \b ADC12_A_NONINVERTEDSIGNAL [Default] - a sample-and-hold of an\r
856 //! input signal for conversion will be started on a rising edge of\r
857 //! the sample/hold signal.\r
858 //! - \b ADC12_A_INVERTEDSIGNAL - a sample-and-hold of an input signal\r
859 //! for conversion will be started on a falling edge of the\r
860 //! sample/hold signal.\r
861 //! \n Modified bits are \b ADC12ISSH of \b ADC12CTL1 register.\r
862 //!\r
863 //! \return None\r
864 //\r
865 //*****************************************************************************\r
866 void ADC12_A_setSampleHoldSignalInversion(uint16_t baseAddress,\r
867 uint16_t invertedSignal)\r
868 {\r
869 //Make sure the ENC bit is cleared before using this function\r
870 assert( !(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );\r
871 \r
872 HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH);\r
873 HWREG16(baseAddress + OFS_ADC12CTL1) |= invertedSignal;\r
874 }\r
875 \r
876 //*****************************************************************************\r
877 //\r
878 //! \brief Use to set the read-back format of the converted data.\r
879 //!\r
880 //! Sets the format of the converted data: how it will be stored into the\r
881 //! memory buffer, and how it should be read back. The format can be set as\r
882 //! right-justified (default), which indicates that the number will be\r
883 //! unsigned, or left-justified, which indicates that the number will be signed\r
884 //! in 2's complement format. This change affects all memory buffers for\r
885 //! subsequent conversions.\r
886 //!\r
887 //! \param baseAddress is the base address of the ADC12_A module.\r
888 //! \param readBackFormat is the specified format to store the conversions in\r
889 //! the memory buffer.\r
890 //! Valid values are:\r
891 //! - \b ADC12_A_UNSIGNED_BINARY [Default]\r
892 //! - \b ADC12_A_SIGNED_2SCOMPLEMENT\r
893 //! \n Modified bits are \b ADC12DF of \b ADC12CTL2 register.\r
894 //!\r
895 //! \return None\r
896 //\r
897 //*****************************************************************************\r
898 void ADC12_A_setDataReadBackFormat(uint16_t baseAddress,\r
899 uint8_t readBackFormat)\r
900 {\r
901 assert(readBackFormat <= ADC12_A_SIGNED_2SCOMPLEMENT);\r
902 \r
903 HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF);\r
904 HWREG8(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat;\r
905 }\r
906 \r
907 //*****************************************************************************\r
908 //\r
909 //! \brief Enables the reference buffer's burst ability.\r
910 //!\r
911 //! Enables the reference buffer's burst ability, allowing the reference buffer\r
912 //! to turn off while the ADC is not converting, and automatically turning on\r
913 //! when the ADC needs the generated reference voltage for a conversion.\r
914 //!\r
915 //! \param baseAddress is the base address of the ADC12_A module.\r
916 //!\r
917 //! \return None\r
918 //\r
919 //*****************************************************************************\r
920 void ADC12_A_enableReferenceBurst(uint16_t baseAddress)\r
921 {\r
922 HWREG8(baseAddress + OFS_ADC12CTL2_L) |= ADC12REFBURST;\r
923 }\r
924 \r
925 //*****************************************************************************\r
926 //\r
927 //! \brief Disables the reference buffer's burst ability.\r
928 //!\r
929 //! Disables the reference buffer's burst ability, forcing the reference buffer\r
930 //! to remain on continuously.\r
931 //!\r
932 //! \param baseAddress is the base address of the ADC12_A module.\r
933 //!\r
934 //! \return None\r
935 //\r
936 //*****************************************************************************\r
937 void ADC12_A_disableReferenceBurst(uint16_t baseAddress)\r
938 {\r
939 HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12REFBURST);\r
940 }\r
941 \r
942 //*****************************************************************************\r
943 //\r
944 //! \brief Use to set the reference buffer's sampling rate.\r
945 //!\r
946 //! Sets the reference buffer's sampling rate to the selected sampling rate.\r
947 //! The default sampling rate is maximum of 200-ksps, and can be reduced to a\r
948 //! maximum of 50-ksps to conserve power.\r
949 //!\r
950 //! \param baseAddress is the base address of the ADC12_A module.\r
951 //! \param samplingRateSelect is the specified maximum sampling rate.\r
952 //! Valid values are:\r
953 //! - \b ADC12_A_MAXSAMPLINGRATE_200KSPS [Default]\r
954 //! - \b ADC12_A_MAXSAMPLINGRATE_50KSPS\r
955 //! \n Modified bits are \b ADC12SR of \b ADC12CTL2 register.\r
956 //!\r
957 //! \return None\r
958 //\r
959 //*****************************************************************************\r
960 void ADC12_A_setReferenceBufferSamplingRate(uint16_t baseAddress,\r
961 uint8_t samplingRateSelect)\r
962 {\r
963 assert(samplingRateSelect <= ADC12_A_MAXSAMPLINGRATE_50KSPS);\r
964 \r
965 HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12SR);\r
966 HWREG8(baseAddress + OFS_ADC12CTL2_L) |= samplingRateSelect;\r
967 }\r
968 \r
969 //*****************************************************************************\r
970 //\r
971 //! \brief Returns the address of the specified memory buffer for the DMA\r
972 //! module.\r
973 //!\r
974 //! Returns the address of the specified memory buffer. This can be used in\r
975 //! conjunction with the DMA to store the converted data directly to memory.\r
976 //!\r
977 //! \param baseAddress is the base address of the ADC12_A module.\r
978 //! \param memoryIndex is the memory buffer to return the address of.\r
979 //! Valid values are:\r
980 //! - \b ADC12_A_MEMORY_0 [Default]\r
981 //! - \b ADC12_A_MEMORY_1\r
982 //! - \b ADC12_A_MEMORY_2\r
983 //! - \b ADC12_A_MEMORY_3\r
984 //! - \b ADC12_A_MEMORY_4\r
985 //! - \b ADC12_A_MEMORY_5\r
986 //! - \b ADC12_A_MEMORY_6\r
987 //! - \b ADC12_A_MEMORY_7\r
988 //! - \b ADC12_A_MEMORY_8\r
989 //! - \b ADC12_A_MEMORY_9\r
990 //! - \b ADC12_A_MEMORY_10\r
991 //! - \b ADC12_A_MEMORY_11\r
992 //! - \b ADC12_A_MEMORY_12\r
993 //! - \b ADC12_A_MEMORY_13\r
994 //! - \b ADC12_A_MEMORY_14\r
995 //! - \b ADC12_A_MEMORY_15\r
996 //!\r
997 //! \return address of the specified memory buffer\r
998 //\r
999 //*****************************************************************************\r
1000 uint32_t ADC12_A_getMemoryAddressForDMA(uint16_t baseAddress,\r
1001 uint8_t memoryIndex)\r
1002 {\r
1003 return baseAddress + (0x20 + (memoryIndex * 2));\r
1004 }\r
1005 \r
1006 //*****************************************************************************\r
1007 //\r
1008 //! \brief Returns the busy status of the ADC12_A core.\r
1009 //!\r
1010 //! Returns the status of the ADC core if there is a conversion currently\r
1011 //! taking place.\r
1012 //!\r
1013 //! \param baseAddress is the base address of the ADC12_A module.\r
1014 //!\r
1015 //! \return One of the following:\r
1016 //! - \b ADC12_A_NOTBUSY\r
1017 //! - \b ADC12_A_BUSY\r
1018 //! \n indicating if a conversion is taking place\r
1019 //\r
1020 //*****************************************************************************\r
1021 uint16_t ADC12_A_isBusy(uint16_t baseAddress)\r
1022 {\r
1023 return HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY;\r
1024 }\r
1025 \r
1026 \r
1027 #endif\r
1028 //*****************************************************************************\r
1029 //\r
1030 //! Close the doxygen group for adc12_a_api\r
1031 //! @}\r
1032 //\r
1033 //*****************************************************************************\r