[msp430-bsl/msp430-bsl.git] / source / driverlib / MSP430F5xx_6xx / deprecated / IAR / msp430f5xx_6xxgeneric.h
1 /* --COPYRIGHT--,BSD\r
2 * Copyright (c) 2014, Texas Instruments Incorporated\r
3 * All rights reserved.\r
4 *\r
5 * Redistribution and use in source and binary forms, with or without\r
6 * modification, are permitted provided that the following conditions\r
7 * are met:\r
8 *\r
9 * * Redistributions of source code must retain the above copyright\r
10 * notice, this list of conditions and the following disclaimer.\r
11 *\r
12 * * Redistributions in binary form must reproduce the above copyright\r
13 * notice, this list of conditions and the following disclaimer in the\r
14 * documentation and/or other materials provided with the distribution.\r
15 *\r
16 * * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 * --/COPYRIGHT--*/\r
32 /********************************************************************\r
33 *\r
34 * Standard register and bit definitions for the Texas Instruments\r
35 * MSP430 microcontroller.\r
36 *\r
37 * This file supports assembler and C development for\r
38 * MSP430F5XX_F6XXGENERIC device.\r
39 *\r
40 * Texas Instruments, Version 1.0\r
41 *\r
42 * Rev. 1.0, Setup\r
43 *\r
44 *\r
45 ********************************************************************/\r
46 \r
47 #ifndef __msp430F5XX_F6XXGENERIC\r
48 #define __msp430F5XX_F6XXGENERIC\r
49 \r
50 //#define __MSP430_HEADER_VERSION__ 1125\r
51 \r
52 #ifdef __IAR_SYSTEMS_ICC__\r
53 #ifndef _SYSTEM_BUILD\r
54 #pragma system_include\r
55 #endif\r
56 #endif\r
57 \r
58 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */\r
59 #error msp430f5xx_6xxgeneric.h file for use with ICC430/A430 only\r
60 #endif\r
61 \r
62 \r
63 #ifdef __IAR_SYSTEMS_ICC__\r
64 #include "in430.h"\r
65 #pragma language=extended\r
66 \r
67 #define DEFC(name, address) __no_init volatile unsigned char name @ address;\r
68 #define DEFW(name, address) __no_init volatile unsigned short name @ address;\r
69 \r
70 #define DEFCW(name, address) __no_init union \\r
71 { \\r
72 struct \\r
73 { \\r
74 volatile unsigned char name##_L; \\r
75 volatile unsigned char name##_H; \\r
76 }; \\r
77 volatile unsigned short name; \\r
78 } @ address;\r
79 \r
80 #define READ_ONLY_DEFCW(name, address) __no_init union \\r
81 { \\r
82 struct \\r
83 { \\r
84 volatile READ_ONLY unsigned char name##_L; \\r
85 volatile READ_ONLY unsigned char name##_H; \\r
86 }; \\r
87 volatile READ_ONLY unsigned short name; \\r
88 } @ address;\r
89 \r
90 \r
91 #if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__\r
92 #define __ACCESS_20BIT_REG__ void __data20 * volatile\r
93 #else\r
94 #define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */\r
95 #endif\r
96 \r
97 #define DEFA(name, address) __no_init union \\r
98 { \\r
99 struct \\r
100 { \\r
101 volatile unsigned char name##_L; \\r
102 volatile unsigned char name##_H; \\r
103 }; \\r
104 struct \\r
105 { \\r
106 volatile unsigned short name##L; \\r
107 volatile unsigned short name##H; \\r
108 }; \\r
109 __ACCESS_20BIT_REG__ name; \\r
110 } @ address;\r
111 \r
112 #endif /* __IAR_SYSTEMS_ICC__ */\r
113 \r
114 \r
115 #ifdef __IAR_SYSTEMS_ASM__\r
116 #define DEFC(name, address) sfrb name = address;\r
117 #define DEFW(name, address) sfrw name = address;\r
118 \r
119 #define DEFCW(name, address) sfrbw name, name##_L, name##_H, address;\r
120 sfrbw macro name, name_L, name_H, address;\r
121 sfrb name_L = address;\r
122 sfrb name_H = address+1;\r
123 sfrw name = address;\r
124 endm\r
125 \r
126 #define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address;\r
127 const_sfrbw macro name, name_L, name_H, address;\r
128 const sfrb name_L = address;\r
129 const sfrb name_H = address+1;\r
130 const sfrw name = address;\r
131 endm\r
132 \r
133 #define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address;\r
134 sfrba macro name, nameL, nameH, name_L, name_H, address;\r
135 sfrb name_L = address;\r
136 sfrb name_H = address+1;\r
137 sfrw nameL = address;\r
138 sfrw nameH = address+2;\r
139 sfrl name = address;\r
140 endm\r
141 \r
142 #endif /* __IAR_SYSTEMS_ASM__*/\r
143 \r
144 #ifdef __cplusplus\r
145 #define READ_ONLY\r
146 #else\r
147 #define READ_ONLY const\r
148 #endif\r
149 \r
150 /************************************************************\r
151 * STANDARD BITS\r
152 ************************************************************/\r
153 \r
154 #define BIT0 (0x0001u)\r
155 #define BIT1 (0x0002u)\r
156 #define BIT2 (0x0004u)\r
157 #define BIT3 (0x0008u)\r
158 #define BIT4 (0x0010u)\r
159 #define BIT5 (0x0020u)\r
160 #define BIT6 (0x0040u)\r
161 #define BIT7 (0x0080u)\r
162 #define BIT8 (0x0100u)\r
163 #define BIT9 (0x0200u)\r
164 #define BITA (0x0400u)\r
165 #define BITB (0x0800u)\r
166 #define BITC (0x1000u)\r
167 #define BITD (0x2000u)\r
168 #define BITE (0x4000u)\r
169 #define BITF (0x8000u)\r
170 \r
171 /************************************************************\r
172 * STATUS REGISTER BITS\r
173 ************************************************************/\r
174 \r
175 #define C (0x0001u)\r
176 #define Z (0x0002u)\r
177 #define N (0x0004u)\r
178 #define V (0x0100u)\r
179 #define GIE (0x0008u)\r
180 #define CPUOFF (0x0010u)\r
181 #define OSCOFF (0x0020u)\r
182 #define SCG0 (0x0040u)\r
183 #define SCG1 (0x0080u)\r
184 \r
185 /* Low Power Modes coded with Bits 4-7 in SR */\r
186 \r
187 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */\r
188 #define LPM0 (CPUOFF)\r
189 #define LPM1 (SCG0+CPUOFF)\r
190 #define LPM2 (SCG1+CPUOFF)\r
191 #define LPM3 (SCG1+SCG0+CPUOFF)\r
192 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)\r
193 /* End #defines for assembler */\r
194 \r
195 #else /* Begin #defines for C */\r
196 #define LPM0_bits (CPUOFF)\r
197 #define LPM1_bits (SCG0+CPUOFF)\r
198 #define LPM2_bits (SCG1+CPUOFF)\r
199 #define LPM3_bits (SCG1+SCG0+CPUOFF)\r
200 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)\r
201 \r
202 #include "in430.h"\r
203 \r
204 #if __MSP430_HEADER_VERSION__ < 1107\r
205 #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */\r
206 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */\r
207 #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */\r
208 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */\r
209 #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */\r
210 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */\r
211 #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */\r
212 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */\r
213 #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */\r
214 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */\r
215 #else\r
216 #define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */\r
217 #define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */\r
218 #define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */\r
219 #define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */\r
220 #define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */\r
221 #define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */\r
222 #define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */\r
223 #define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */\r
224 #define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */\r
225 #define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */\r
226 #endif\r
227 #endif /* End #defines for C */\r
228 \r
229 /************************************************************\r
230 * CPU\r
231 ************************************************************/\r
232 #define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */\r
233 \r
234 #if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \\r
235 || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \\r
236 || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \\r
237 || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)\r
238 #define __MSP430_HAS_TxA7__\r
239 #endif\r
240 #if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \\r
241 || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)\r
242 #define __MSP430_HAS_TxB7__\r
243 #endif\r
244 #if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \\r
245 || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)\r
246 #define __MSP430_HAS_TxD7__\r
247 #endif\r
248 #if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)\r
249 #define __MSP430_HAS_USCI_Ax__\r
250 #endif\r
251 #if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)\r
252 #define __MSP430_HAS_USCI_Bx__\r
253 #endif\r
254 #if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)\r
255 #define __MSP430_HAS_EUSCI_Ax__\r
256 #endif\r
257 #if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)\r
258 #define __MSP430_HAS_EUSCI_Bx__\r
259 #endif\r
260 #ifdef __MSP430_HAS_EUSCI_B0__\r
261 #define __MSP430_HAS_EUSCI_Bx__\r
262 #endif\r
263 \r
264 /************************************************************\r
265 * ADC10_A\r
266 ************************************************************/\r
267 #ifdef __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */\r
268 \r
269 #define OFS_ADC10CTL0 (0x0000u) /* ADC10 Control 0 */\r
270 #define OFS_ADC10CTL0_L OFS_ADC10CTL0\r
271 #define OFS_ADC10CTL0_H OFS_ADC10CTL0+1\r
272 #define OFS_ADC10CTL1 (0x0002u) /* ADC10 Control 1 */\r
273 #define OFS_ADC10CTL1_L OFS_ADC10CTL1\r
274 #define OFS_ADC10CTL1_H OFS_ADC10CTL1+1\r
275 #define OFS_ADC10CTL2 (0x0004u) /* ADC10 Control 2 */\r
276 #define OFS_ADC10CTL2_L OFS_ADC10CTL2\r
277 #define OFS_ADC10CTL2_H OFS_ADC10CTL2+1\r
278 #define OFS_ADC10LO (0x0006u) /* ADC10 Window Comparator High Threshold */\r
279 #define OFS_ADC10LO_L OFS_ADC10LO\r
280 #define OFS_ADC10LO_H OFS_ADC10LO+1\r
281 #define OFS_ADC10HI (0x0008u) /* ADC10 Window Comparator High Threshold */\r
282 #define OFS_ADC10HI_L OFS_ADC10HI\r
283 #define OFS_ADC10HI_H OFS_ADC10HI+1\r
284 #define OFS_ADC10MCTL0 (0x000Au) /* ADC10 Memory Control 0 */\r
285 #define OFS_ADC10MCTL0_L OFS_ADC10MCTL0\r
286 #define OFS_ADC10MCTL0_H OFS_ADC10MCTL0+1\r
287 #define OFS_ADC10MEM0 (0x0012u) /* ADC10 Conversion Memory 0 */\r
288 #define OFS_ADC10MEM0_L OFS_ADC10MEM0\r
289 #define OFS_ADC10MEM0_H OFS_ADC10MEM0+1\r
290 #define OFS_ADC10IE (0x001Au) /* ADC10 Interrupt Enable */\r
291 #define OFS_ADC10IE_L OFS_ADC10IE\r
292 #define OFS_ADC10IE_H OFS_ADC10IE+1\r
293 #define OFS_ADC10IFG (0x001Cu) /* ADC10 Interrupt Flag */\r
294 #define OFS_ADC10IFG_L OFS_ADC10IFG\r
295 #define OFS_ADC10IFG_H OFS_ADC10IFG+1\r
296 #define OFS_ADC10IV (0x001Eu) /* ADC10 Interrupt Vector Word */\r
297 #define OFS_ADC10IV_L OFS_ADC10IV\r
298 #define OFS_ADC10IV_H OFS_ADC10IV+1\r
299 \r
300 /* ADC10CTL0 Control Bits */\r
301 #define ADC10SC (0x0001u) /* ADC10 Start Conversion */\r
302 #define ADC10ENC (0x0002u) /* ADC10 Enable Conversion */\r
303 #define ADC10ON (0x0010u) /* ADC10 On/enable */\r
304 #define ADC10MSC (0x0080u) /* ADC10 Multiple SampleConversion */\r
305 #define ADC10SHT0 (0x0100u) /* ADC10 Sample Hold Select Bit: 0 */\r
306 #define ADC10SHT1 (0x0200u) /* ADC10 Sample Hold Select Bit: 1 */\r
307 #define ADC10SHT2 (0x0400u) /* ADC10 Sample Hold Select Bit: 2 */\r
308 #define ADC10SHT3 (0x0800u) /* ADC10 Sample Hold Select Bit: 3 */\r
309 \r
310 /* ADC10CTL0 Control Bits */\r
311 #define ADC10SC_L (0x0001u) /* ADC10 Start Conversion */\r
312 #define ADC10ENC_L (0x0002u) /* ADC10 Enable Conversion */\r
313 #define ADC10ON_L (0x0010u) /* ADC10 On/enable */\r
314 #define ADC10MSC_L (0x0080u) /* ADC10 Multiple SampleConversion */\r
315 \r
316 /* ADC10CTL0 Control Bits */\r
317 #define ADC10SHT0_H (0x0001u) /* ADC10 Sample Hold Select Bit: 0 */\r
318 #define ADC10SHT1_H (0x0002u) /* ADC10 Sample Hold Select Bit: 1 */\r
319 #define ADC10SHT2_H (0x0004u) /* ADC10 Sample Hold Select Bit: 2 */\r
320 #define ADC10SHT3_H (0x0008u) /* ADC10 Sample Hold Select Bit: 3 */\r
321 \r
322 #define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */\r
323 #define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */\r
324 #define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */\r
325 #define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */\r
326 #define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */\r
327 #define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */\r
328 #define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */\r
329 #define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */\r
330 #define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */\r
331 #define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */\r
332 #define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */\r
333 #define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */\r
334 #define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */\r
335 #define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */\r
336 #define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */\r
337 #define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */\r
338 \r
339 /* ADC10CTL1 Control Bits */\r
340 #define ADC10BUSY (0x0001u) /* ADC10 Busy */\r
341 #define ADC10CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */\r
342 #define ADC10CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */\r
343 #define ADC10SSEL0 (0x0008u) /* ADC10 Clock Source Select 0 */\r
344 #define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select 1 */\r
345 #define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select 0 */\r
346 #define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select 1 */\r
347 #define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select 2 */\r
348 #define ADC10ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */\r
349 #define ADC10SHP (0x0200u) /* ADC10 Sample/Hold Pulse Mode */\r
350 #define ADC10SHS0 (0x0400u) /* ADC10 Sample/Hold Source 0 */\r
351 #define ADC10SHS1 (0x0800u) /* ADC10 Sample/Hold Source 1 */\r
352 \r
353 /* ADC10CTL1 Control Bits */\r
354 #define ADC10BUSY_L (0x0001u) /* ADC10 Busy */\r
355 #define ADC10CONSEQ0_L (0x0002u) /* ADC10 Conversion Sequence Select 0 */\r
356 #define ADC10CONSEQ1_L (0x0004u) /* ADC10 Conversion Sequence Select 1 */\r
357 #define ADC10SSEL0_L (0x0008u) /* ADC10 Clock Source Select 0 */\r
358 #define ADC10SSEL1_L (0x0010u) /* ADC10 Clock Source Select 1 */\r
359 #define ADC10DIV0_L (0x0020u) /* ADC10 Clock Divider Select 0 */\r
360 #define ADC10DIV1_L (0x0040u) /* ADC10 Clock Divider Select 1 */\r
361 #define ADC10DIV2_L (0x0080u) /* ADC10 Clock Divider Select 2 */\r
362 \r
363 /* ADC10CTL1 Control Bits */\r
364 #define ADC10ISSH_H (0x0001u) /* ADC10 Invert Sample Hold Signal */\r
365 #define ADC10SHP_H (0x0002u) /* ADC10 Sample/Hold Pulse Mode */\r
366 #define ADC10SHS0_H (0x0004u) /* ADC10 Sample/Hold Source 0 */\r
367 #define ADC10SHS1_H (0x0008u) /* ADC10 Sample/Hold Source 1 */\r
368 \r
369 #define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */\r
370 #define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */\r
371 #define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */\r
372 #define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */\r
373 \r
374 #define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */\r
375 #define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */\r
376 #define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */\r
377 #define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */\r
378 \r
379 #define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */\r
380 #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */\r
381 #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */\r
382 #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */\r
383 #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */\r
384 #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */\r
385 #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */\r
386 #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */\r
387 \r
388 #define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */\r
389 #define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */\r
390 #define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */\r
391 #define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */\r
392 \r
393 /* ADC10CTL2 Control Bits */\r
394 #define ADC10REFBURST (0x0001u) /* ADC10 Reference Burst */\r
395 #define ADC10SR (0x0004u) /* ADC10 Sampling Rate */\r
396 #define ADC10DF (0x0008u) /* ADC10 Data Format */\r
397 #define ADC10RES (0x0010u) /* ADC10 Resolution Bit */\r
398 #define ADC10PDIV0 (0x0100u) /* ADC10 predivider Bit: 0 */\r
399 #define ADC10PDIV1 (0x0200u) /* ADC10 predivider Bit: 1 */\r
400 \r
401 /* ADC10CTL2 Control Bits */\r
402 #define ADC10REFBURST_L (0x0001u) /* ADC10 Reference Burst */\r
403 #define ADC10SR_L (0x0004u) /* ADC10 Sampling Rate */\r
404 #define ADC10DF_L (0x0008u) /* ADC10 Data Format */\r
405 #define ADC10RES_L (0x0010u) /* ADC10 Resolution Bit */\r
406 \r
407 /* ADC10CTL2 Control Bits */\r
408 #define ADC10PDIV0_H (0x0001u) /* ADC10 predivider Bit: 0 */\r
409 #define ADC10PDIV1_H (0x0002u) /* ADC10 predivider Bit: 1 */\r
410 \r
411 #define ADC10PDIV_0 (0x0000u) /* ADC10 predivider /1 */\r
412 #define ADC10PDIV_1 (0x0100u) /* ADC10 predivider /2 */\r
413 #define ADC10PDIV_2 (0x0200u) /* ADC10 predivider /64 */\r
414 #define ADC10PDIV_3 (0x0300u) /* ADC10 predivider reserved */\r
415 \r
416 #define ADC10PDIV__1 (0x0000u) /* ADC10 predivider /1 */\r
417 #define ADC10PDIV__4 (0x0100u) /* ADC10 predivider /2 */\r
418 #define ADC10PDIV__64 (0x0200u) /* ADC10 predivider /64 */\r
419 \r
420 /* ADC10MCTL0 Control Bits */\r
421 #define ADC10INCH0 (0x0001u) /* ADC10 Input Channel Select Bit 0 */\r
422 #define ADC10INCH1 (0x0002u) /* ADC10 Input Channel Select Bit 1 */\r
423 #define ADC10INCH2 (0x0004u) /* ADC10 Input Channel Select Bit 2 */\r
424 #define ADC10INCH3 (0x0008u) /* ADC10 Input Channel Select Bit 3 */\r
425 #define ADC10SREF0 (0x0010u) /* ADC10 Select Reference Bit 0 */\r
426 #define ADC10SREF1 (0x0020u) /* ADC10 Select Reference Bit 1 */\r
427 #define ADC10SREF2 (0x0040u) /* ADC10 Select Reference Bit 2 */\r
428 \r
429 /* ADC10MCTL0 Control Bits */\r
430 #define ADC10INCH0_L (0x0001u) /* ADC10 Input Channel Select Bit 0 */\r
431 #define ADC10INCH1_L (0x0002u) /* ADC10 Input Channel Select Bit 1 */\r
432 #define ADC10INCH2_L (0x0004u) /* ADC10 Input Channel Select Bit 2 */\r
433 #define ADC10INCH3_L (0x0008u) /* ADC10 Input Channel Select Bit 3 */\r
434 #define ADC10SREF0_L (0x0010u) /* ADC10 Select Reference Bit 0 */\r
435 #define ADC10SREF1_L (0x0020u) /* ADC10 Select Reference Bit 1 */\r
436 #define ADC10SREF2_L (0x0040u) /* ADC10 Select Reference Bit 2 */\r
437 \r
438 #define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */\r
439 #define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */\r
440 #define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */\r
441 #define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */\r
442 #define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */\r
443 #define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */\r
444 #define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */\r
445 #define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */\r
446 #define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */\r
447 #define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */\r
448 #define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */\r
449 #define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */\r
450 #define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */\r
451 #define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */\r
452 #define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */\r
453 #define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */\r
454 \r
455 #define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */\r
456 #define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */\r
457 #define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */\r
458 #define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */\r
459 #define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */\r
460 #define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */\r
461 #define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */\r
462 #define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */\r
463 \r
464 /* ADC10IE Interrupt Enable Bits */\r
465 #define ADC10IE0 (0x0001u) /* ADC10_A Interrupt enable */\r
466 #define ADC10INIE (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */\r
467 #define ADC10LOIE (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */\r
468 #define ADC10HIIE (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */\r
469 #define ADC10OVIE (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */\r
470 #define ADC10TOVIE (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */\r
471 \r
472 /* ADC10IE Interrupt Enable Bits */\r
473 #define ADC10IE0_L (0x0001u) /* ADC10_A Interrupt enable */\r
474 #define ADC10INIE_L (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */\r
475 #define ADC10LOIE_L (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */\r
476 #define ADC10HIIE_L (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */\r
477 #define ADC10OVIE_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */\r
478 #define ADC10TOVIE_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */\r
479 \r
480 /* ADC10IFG Interrupt Flag Bits */\r
481 #define ADC10IFG0 (0x0001u) /* ADC10_A Interrupt Flag */\r
482 #define ADC10INIFG (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */\r
483 #define ADC10LOIFG (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */\r
484 #define ADC10HIIFG (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */\r
485 #define ADC10OVIFG (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */\r
486 #define ADC10TOVIFG (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */\r
487 \r
488 /* ADC10IFG Interrupt Flag Bits */\r
489 #define ADC10IFG0_L (0x0001u) /* ADC10_A Interrupt Flag */\r
490 #define ADC10INIFG_L (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */\r
491 #define ADC10LOIFG_L (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */\r
492 #define ADC10HIIFG_L (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */\r
493 #define ADC10OVIFG_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */\r
494 #define ADC10TOVIFG_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */\r
495 \r
496 /* ADC10IV Definitions */\r
497 #define ADC10IV_NONE (0x0000u) /* No Interrupt pending */\r
498 #define ADC10IV_ADC10OVIFG (0x0002u) /* ADC10OVIFG */\r
499 #define ADC10IV_ADC10TOVIFG (0x0004u) /* ADC10TOVIFG */\r
500 #define ADC10IV_ADC10HIIFG (0x0006u) /* ADC10HIIFG */\r
501 #define ADC10IV_ADC10LOIFG (0x0008u) /* ADC10LOIFG */\r
502 #define ADC10IV_ADC10INIFG (0x000Au) /* ADC10INIFG */\r
503 #define ADC10IV_ADC10IFG (0x000Cu) /* ADC10IFG */\r
504 \r
505 #endif\r
506 /************************************************************\r
507 * ADC12 PLUS\r
508 ************************************************************/\r
509 #ifdef __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */\r
510 \r
511 #define OFS_ADC12CTL0 (0x0000u) /* ADC12+ Control 0 */\r
512 #define OFS_ADC12CTL0_L OFS_ADC12CTL0\r
513 #define OFS_ADC12CTL0_H OFS_ADC12CTL0+1\r
514 #define OFS_ADC12CTL1 (0x0002u) /* ADC12+ Control 1 */\r
515 #define OFS_ADC12CTL1_L OFS_ADC12CTL1\r
516 #define OFS_ADC12CTL1_H OFS_ADC12CTL1+1\r
517 #define OFS_ADC12CTL2 (0x0004u) /* ADC12+ Control 2 */\r
518 #define OFS_ADC12CTL2_L OFS_ADC12CTL2\r
519 #define OFS_ADC12CTL2_H OFS_ADC12CTL2+1\r
520 #define OFS_ADC12IFG (0x000Au) /* ADC12+ Interrupt Flag */\r
521 #define OFS_ADC12IFG_L OFS_ADC12IFG\r
522 #define OFS_ADC12IFG_H OFS_ADC12IFG+1\r
523 #define OFS_ADC12IE (0x000Cu) /* ADC12+ Interrupt Enable */\r
524 #define OFS_ADC12IE_L OFS_ADC12IE\r
525 #define OFS_ADC12IE_H OFS_ADC12IE+1\r
526 #define OFS_ADC12IV (0x000Eu) /* ADC12+ Interrupt Vector Word */\r
527 #define OFS_ADC12IV_L OFS_ADC12IV\r
528 #define OFS_ADC12IV_H OFS_ADC12IV+1\r
529 \r
530 #define OFS_ADC12MEM0 (0x0020u) /* ADC12 Conversion Memory 0 */\r
531 #define OFS_ADC12MEM0_L OFS_ADC12MEM0\r
532 #define OFS_ADC12MEM0_H OFS_ADC12MEM0+1\r
533 #define OFS_ADC12MEM1 (0x0022u) /* ADC12 Conversion Memory 1 */\r
534 #define OFS_ADC12MEM1_L OFS_ADC12MEM1\r
535 #define OFS_ADC12MEM1_H OFS_ADC12MEM1+1\r
536 #define OFS_ADC12MEM2 (0x0024u) /* ADC12 Conversion Memory 2 */\r
537 #define OFS_ADC12MEM2_L OFS_ADC12MEM2\r
538 #define OFS_ADC12MEM2_H OFS_ADC12MEM2+1\r
539 #define OFS_ADC12MEM3 (0x0026u) /* ADC12 Conversion Memory 3 */\r
540 #define OFS_ADC12MEM3_L OFS_ADC12MEM3\r
541 #define OFS_ADC12MEM3_H OFS_ADC12MEM3+1\r
542 #define OFS_ADC12MEM4 (0x0028u) /* ADC12 Conversion Memory 4 */\r
543 #define OFS_ADC12MEM4_L OFS_ADC12MEM4\r
544 #define OFS_ADC12MEM4_H OFS_ADC12MEM4+1\r
545 #define OFS_ADC12MEM5 (0x002Au) /* ADC12 Conversion Memory 5 */\r
546 #define OFS_ADC12MEM5_L OFS_ADC12MEM5\r
547 #define OFS_ADC12MEM5_H OFS_ADC12MEM5+1\r
548 #define OFS_ADC12MEM6 (0x002Cu) /* ADC12 Conversion Memory 6 */\r
549 #define OFS_ADC12MEM6_L OFS_ADC12MEM6\r
550 #define OFS_ADC12MEM6_H OFS_ADC12MEM6+1\r
551 #define OFS_ADC12MEM7 (0x002Eu) /* ADC12 Conversion Memory 7 */\r
552 #define OFS_ADC12MEM7_L OFS_ADC12MEM7\r
553 #define OFS_ADC12MEM7_H OFS_ADC12MEM7+1\r
554 #define OFS_ADC12MEM8 (0x0030u) /* ADC12 Conversion Memory 8 */\r
555 #define OFS_ADC12MEM8_L OFS_ADC12MEM8\r
556 #define OFS_ADC12MEM8_H OFS_ADC12MEM8+1\r
557 #define OFS_ADC12MEM9 (0x0032u) /* ADC12 Conversion Memory 9 */\r
558 #define OFS_ADC12MEM9_L OFS_ADC12MEM9\r
559 #define OFS_ADC12MEM9_H OFS_ADC12MEM9+1\r
560 #define OFS_ADC12MEM10 (0x0034u) /* ADC12 Conversion Memory 10 */\r
561 #define OFS_ADC12MEM10_L OFS_ADC12MEM10\r
562 #define OFS_ADC12MEM10_H OFS_ADC12MEM10+1\r
563 #define OFS_ADC12MEM11 (0x0036u) /* ADC12 Conversion Memory 11 */\r
564 #define OFS_ADC12MEM11_L OFS_ADC12MEM11\r
565 #define OFS_ADC12MEM11_H OFS_ADC12MEM11+1\r
566 #define OFS_ADC12MEM12 (0x0038u) /* ADC12 Conversion Memory 12 */\r
567 #define OFS_ADC12MEM12_L OFS_ADC12MEM12\r
568 #define OFS_ADC12MEM12_H OFS_ADC12MEM12+1\r
569 #define OFS_ADC12MEM13 (0x003Au) /* ADC12 Conversion Memory 13 */\r
570 #define OFS_ADC12MEM13_L OFS_ADC12MEM13\r
571 #define OFS_ADC12MEM13_H OFS_ADC12MEM13+1\r
572 #define OFS_ADC12MEM14 (0x003Cu) /* ADC12 Conversion Memory 14 */\r
573 #define OFS_ADC12MEM14_L OFS_ADC12MEM14\r
574 #define OFS_ADC12MEM14_H OFS_ADC12MEM14+1\r
575 #define OFS_ADC12MEM15 (0x003Eu) /* ADC12 Conversion Memory 15 */\r
576 #define OFS_ADC12MEM15_L OFS_ADC12MEM15\r
577 #define OFS_ADC12MEM15_H OFS_ADC12MEM15+1\r
578 #define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */\r
579 #ifndef __IAR_SYSTEMS_ICC__\r
580 #define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */\r
581 #else\r
582 #define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */\r
583 #endif\r
584 \r
585 #define OFS_ADC12MCTL0 (0x0010u) /* ADC12 Memory Control 0 */\r
586 #define OFS_ADC12MCTL1 (0x0011u) /* ADC12 Memory Control 1 */\r
587 #define OFS_ADC12MCTL2 (0x0012u) /* ADC12 Memory Control 2 */\r
588 #define OFS_ADC12MCTL3 (0x0013u) /* ADC12 Memory Control 3 */\r
589 #define OFS_ADC12MCTL4 (0x0014u) /* ADC12 Memory Control 4 */\r
590 #define OFS_ADC12MCTL5 (0x0015u) /* ADC12 Memory Control 5 */\r
591 #define OFS_ADC12MCTL6 (0x0016u) /* ADC12 Memory Control 6 */\r
592 #define OFS_ADC12MCTL7 (0x0017u) /* ADC12 Memory Control 7 */\r
593 #define OFS_ADC12MCTL8 (0x0018u) /* ADC12 Memory Control 8 */\r
594 #define OFS_ADC12MCTL9 (0x0019u) /* ADC12 Memory Control 9 */\r
595 #define OFS_ADC12MCTL10 (0x001Au) /* ADC12 Memory Control 10 */\r
596 #define OFS_ADC12MCTL11 (0x001Bu) /* ADC12 Memory Control 11 */\r
597 #define OFS_ADC12MCTL12 (0x001Cu) /* ADC12 Memory Control 12 */\r
598 #define OFS_ADC12MCTL13 (0x001Du) /* ADC12 Memory Control 13 */\r
599 #define OFS_ADC12MCTL14 (0x001Eu) /* ADC12 Memory Control 14 */\r
600 #define OFS_ADC12MCTL15 (0x001Fu) /* ADC12 Memory Control 15 */\r
601 #define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */\r
602 #ifndef __IAR_SYSTEMS_ICC__\r
603 #define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */\r
604 #else\r
605 #define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */\r
606 #endif\r
607 \r
608 /* ADC12CTL0 Control Bits */\r
609 #define ADC12SC (0x0001u) /* ADC12 Start Conversion */\r
610 #define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */\r
611 #define ADC12TOVIE (0x0004u) /* ADC12 Timer Overflow interrupt enable */\r
612 #define ADC12OVIE (0x0008u) /* ADC12 Overflow interrupt enable */\r
613 #define ADC12ON (0x0010u) /* ADC12 On/enable */\r
614 #define ADC12REFON (0x0020u) /* ADC12 Reference on */\r
615 #define ADC12REF2_5V (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */\r
616 #define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */\r
617 #define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
618 #define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
619 #define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
620 #define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
621 #define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
622 #define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
623 #define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
624 #define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
625 \r
626 /* ADC12CTL0 Control Bits */\r
627 #define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */\r
628 #define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */\r
629 #define ADC12TOVIE_L (0x0004u) /* ADC12 Timer Overflow interrupt enable */\r
630 #define ADC12OVIE_L (0x0008u) /* ADC12 Overflow interrupt enable */\r
631 #define ADC12ON_L (0x0010u) /* ADC12 On/enable */\r
632 #define ADC12REFON_L (0x0020u) /* ADC12 Reference on */\r
633 #define ADC12REF2_5V_L (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */\r
634 #define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */\r
635 \r
636 /* ADC12CTL0 Control Bits */\r
637 #define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
638 #define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
639 #define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
640 #define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
641 #define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
642 #define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
643 #define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
644 #define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
645 \r
646 #define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
647 #define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
648 #define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
649 #define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
650 #define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */\r
651 #define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */\r
652 #define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */\r
653 #define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */\r
654 #define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */\r
655 #define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */\r
656 #define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */\r
657 #define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */\r
658 #define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */\r
659 #define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */\r
660 #define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */\r
661 #define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */\r
662 \r
663 #define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
664 #define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
665 #define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
666 #define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
667 #define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */\r
668 #define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */\r
669 #define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */\r
670 #define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */\r
671 #define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */\r
672 #define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */\r
673 #define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */\r
674 #define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */\r
675 #define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */\r
676 #define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */\r
677 #define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */\r
678 #define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */\r
679 \r
680 /* ADC12CTL1 Control Bits */\r
681 #define ADC12BUSY (0x0001u) /* ADC12 Busy */\r
682 #define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */\r
683 #define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */\r
684 #define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */\r
685 #define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */\r
686 #define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */\r
687 #define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */\r
688 #define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */\r
689 #define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */\r
690 #define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */\r
691 #define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */\r
692 #define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */\r
693 #define ADC12CSTARTADD0 (0x1000u) /* ADC12 Conversion Start Address Bit: 0 */\r
694 #define ADC12CSTARTADD1 (0x2000u) /* ADC12 Conversion Start Address Bit: 1 */\r
695 #define ADC12CSTARTADD2 (0x4000u) /* ADC12 Conversion Start Address Bit: 2 */\r
696 #define ADC12CSTARTADD3 (0x8000u) /* ADC12 Conversion Start Address Bit: 3 */\r
697 \r
698 /* ADC12CTL1 Control Bits */\r
699 #define ADC12BUSY_L (0x0001u) /* ADC12 Busy */\r
700 #define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */\r
701 #define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */\r
702 #define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */\r
703 #define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */\r
704 #define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */\r
705 #define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */\r
706 #define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */\r
707 \r
708 /* ADC12CTL1 Control Bits */\r
709 #define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */\r
710 #define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */\r
711 #define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */\r
712 #define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */\r
713 #define ADC12CSTARTADD0_H (0x0010u) /* ADC12 Conversion Start Address Bit: 0 */\r
714 #define ADC12CSTARTADD1_H (0x0020u) /* ADC12 Conversion Start Address Bit: 1 */\r
715 #define ADC12CSTARTADD2_H (0x0040u) /* ADC12 Conversion Start Address Bit: 2 */\r
716 #define ADC12CSTARTADD3_H (0x0080u) /* ADC12 Conversion Start Address Bit: 3 */\r
717 \r
718 #define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */\r
719 #define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */\r
720 #define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */\r
721 #define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */\r
722 \r
723 #define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */\r
724 #define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */\r
725 #define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */\r
726 #define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */\r
727 \r
728 #define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */\r
729 #define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */\r
730 #define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */\r
731 #define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */\r
732 #define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */\r
733 #define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */\r
734 #define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */\r
735 #define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */\r
736 \r
737 #define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */\r
738 #define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */\r
739 #define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */\r
740 #define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */\r
741 \r
742 #define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */\r
743 #define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */\r
744 #define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */\r
745 #define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */\r
746 #define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */\r
747 #define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */\r
748 #define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */\r
749 #define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */\r
750 #define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */\r
751 #define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */\r
752 #define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */\r
753 #define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */\r
754 #define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */\r
755 #define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */\r
756 #define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */\r
757 #define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */\r
758 \r
759 /* ADC12CTL2 Control Bits */\r
760 #define ADC12REFBURST (0x0001u) /* ADC12+ Reference Burst */\r
761 #define ADC12REFOUT (0x0002u) /* ADC12+ Reference Out */\r
762 #define ADC12SR (0x0004u) /* ADC12+ Sampling Rate */\r
763 #define ADC12DF (0x0008u) /* ADC12+ Data Format */\r
764 #define ADC12RES0 (0x0010u) /* ADC12+ Resolution Bit: 0 */\r
765 #define ADC12RES1 (0x0020u) /* ADC12+ Resolution Bit: 1 */\r
766 #define ADC12TCOFF (0x0080u) /* ADC12+ Temperature Sensor Off */\r
767 #define ADC12PDIV (0x0100u) /* ADC12+ predivider 0:/1 1:/4 */\r
768 \r
769 /* ADC12CTL2 Control Bits */\r
770 #define ADC12REFBURST_L (0x0001u) /* ADC12+ Reference Burst */\r
771 #define ADC12REFOUT_L (0x0002u) /* ADC12+ Reference Out */\r
772 #define ADC12SR_L (0x0004u) /* ADC12+ Sampling Rate */\r
773 #define ADC12DF_L (0x0008u) /* ADC12+ Data Format */\r
774 #define ADC12RES0_L (0x0010u) /* ADC12+ Resolution Bit: 0 */\r
775 #define ADC12RES1_L (0x0020u) /* ADC12+ Resolution Bit: 1 */\r
776 #define ADC12TCOFF_L (0x0080u) /* ADC12+ Temperature Sensor Off */\r
777 \r
778 /* ADC12CTL2 Control Bits */\r
779 #define ADC12PDIV_H (0x0001u) /* ADC12+ predivider 0:/1 1:/4 */\r
780 \r
781 #define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */\r
782 #define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */\r
783 #define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */\r
784 #define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */\r
785 \r
786 /* ADC12MCTLx Control Bits */\r
787 #define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */\r
788 #define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */\r
789 #define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */\r
790 #define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */\r
791 #define ADC12SREF0 (0x0010u) /* ADC12 Select Reference Bit 0 */\r
792 #define ADC12SREF1 (0x0020u) /* ADC12 Select Reference Bit 1 */\r
793 #define ADC12SREF2 (0x0040u) /* ADC12 Select Reference Bit 2 */\r
794 #define ADC12EOS (0x0080u) /* ADC12 End of Sequence */\r
795 \r
796 #define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */\r
797 #define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */\r
798 #define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */\r
799 #define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */\r
800 #define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */\r
801 #define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */\r
802 #define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */\r
803 #define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */\r
804 #define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */\r
805 #define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */\r
806 #define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */\r
807 #define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */\r
808 #define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */\r
809 #define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */\r
810 #define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */\r
811 #define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */\r
812 \r
813 #define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */\r
814 #define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */\r
815 #define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */\r
816 #define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */\r
817 #define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */\r
818 #define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */\r
819 #define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */\r
820 #define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */\r
821 \r
822 #define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */\r
823 #define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */\r
824 #define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */\r
825 #define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */\r
826 #define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */\r
827 #define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */\r
828 #define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */\r
829 #define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */\r
830 #define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */\r
831 #define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */\r
832 #define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */\r
833 #define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */\r
834 #define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */\r
835 #define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */\r
836 #define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */\r
837 #define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */\r
838 \r
839 #define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */\r
840 #define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */\r
841 #define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */\r
842 #define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */\r
843 #define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */\r
844 #define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */\r
845 #define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */\r
846 #define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */\r
847 \r
848 #define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */\r
849 #define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */\r
850 #define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */\r
851 #define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */\r
852 #define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */\r
853 #define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */\r
854 #define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */\r
855 #define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */\r
856 \r
857 #define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */\r
858 #define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */\r
859 #define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */\r
860 #define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */\r
861 #define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */\r
862 #define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */\r
863 #define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */\r
864 #define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */\r
865 #define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */\r
866 #define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */\r
867 #define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */\r
868 #define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */\r
869 #define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */\r
870 #define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */\r
871 #define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */\r
872 #define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */\r
873 \r
874 #define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */\r
875 #define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */\r
876 #define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */\r
877 #define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */\r
878 #define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */\r
879 #define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */\r
880 #define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */\r
881 #define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */\r
882 \r
883 #define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */\r
884 #define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */\r
885 #define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */\r
886 #define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */\r
887 #define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */\r
888 #define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */\r
889 #define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */\r
890 #define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */\r
891 \r
892 /* ADC12IV Definitions */\r
893 #define ADC12IV_NONE (0x0000u) /* No Interrupt pending */\r
894 #define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */\r
895 #define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */\r
896 #define ADC12IV_ADC12IFG0 (0x0006u) /* ADC12IFG0 */\r
897 #define ADC12IV_ADC12IFG1 (0x0008u) /* ADC12IFG1 */\r
898 #define ADC12IV_ADC12IFG2 (0x000Au) /* ADC12IFG2 */\r
899 #define ADC12IV_ADC12IFG3 (0x000Cu) /* ADC12IFG3 */\r
900 #define ADC12IV_ADC12IFG4 (0x000Eu) /* ADC12IFG4 */\r
901 #define ADC12IV_ADC12IFG5 (0x0010u) /* ADC12IFG5 */\r
902 #define ADC12IV_ADC12IFG6 (0x0012u) /* ADC12IFG6 */\r
903 #define ADC12IV_ADC12IFG7 (0x0014u) /* ADC12IFG7 */\r
904 #define ADC12IV_ADC12IFG8 (0x0016u) /* ADC12IFG8 */\r
905 #define ADC12IV_ADC12IFG9 (0x0018u) /* ADC12IFG9 */\r
906 #define ADC12IV_ADC12IFG10 (0x001Au) /* ADC12IFG10 */\r
907 #define ADC12IV_ADC12IFG11 (0x001Cu) /* ADC12IFG11 */\r
908 #define ADC12IV_ADC12IFG12 (0x001Eu) /* ADC12IFG12 */\r
909 #define ADC12IV_ADC12IFG13 (0x0020u) /* ADC12IFG13 */\r
910 #define ADC12IV_ADC12IFG14 (0x0022u) /* ADC12IFG14 */\r
911 #define ADC12IV_ADC12IFG15 (0x0024u) /* ADC12IFG15 */\r
912 \r
913 #endif\r
914 /************************************************************\r
915 * AES Accelerator\r
916 ************************************************************/\r
917 #ifdef __MSP430_HAS_AES__ /* Definition to show that Module is available */\r
918 \r
919 #define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */\r
920 #define OFS_AESACTL0_L OFS_AESACTL0\r
921 #define OFS_AESACTL0_H OFS_AESACTL0+1\r
922 #define OFS_AESASTAT (0x0004u) /* AES accelerator status register */\r
923 #define OFS_AESASTAT_L OFS_AESASTAT\r
924 #define OFS_AESASTAT_H OFS_AESASTAT+1\r
925 #define OFS_AESAKEY (0x0006u) /* AES accelerator key register */\r
926 #define OFS_AESAKEY_L OFS_AESAKEY\r
927 #define OFS_AESAKEY_H OFS_AESAKEY+1\r
928 #define OFS_AESADIN (0x0008u) /* AES accelerator data in register */\r
929 #define OFS_AESADIN_L OFS_AESADIN\r
930 #define OFS_AESADIN_H OFS_AESADIN+1\r
931 #define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */\r
932 #define OFS_AESADOUT_L OFS_AESADOUT\r
933 #define OFS_AESADOUT_H OFS_AESADOUT+1\r
934 \r
935 /* AESACTL0 Control Bits */\r
936 #define AESOP0 (0x0001u) /* AES Operation Bit: 0 */\r
937 #define AESOP1 (0x0002u) /* AES Operation Bit: 1 */\r
938 #define AESSWRST (0x0080u) /* AES Software Reset */\r
939 #define AESRDYIFG (0x0100u) /* AES ready interrupt flag */\r
940 #define AESERRFG (0x0800u) /* AES Error Flag */\r
941 #define AESRDYIE (0x1000u) /* AES ready interrupt enable*/\r
942 \r
943 /* AESACTL0 Control Bits */\r
944 #define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */\r
945 #define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */\r
946 #define AESSWRST_L (0x0080u) /* AES Software Reset */\r
947 \r
948 /* AESACTL0 Control Bits */\r
949 #define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */\r
950 #define AESERRFG_H (0x0008u) /* AES Error Flag */\r
951 #define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/\r
952 \r
953 #define AESOP_0 (0x0000u) /* AES Operation: Encrypt */\r
954 #define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */\r
955 #define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */\r
956 #define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */\r
957 \r
958 /* AESASTAT Control Bits */\r
959 #define AESBUSY (0x0001u) /* AES Busy */\r
960 #define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */\r
961 #define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */\r
962 #define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */\r
963 #define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */\r
964 #define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */\r
965 #define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */\r
966 #define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */\r
967 #define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */\r
968 #define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */\r
969 #define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */\r
970 #define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */\r
971 #define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */\r
972 #define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */\r
973 #define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */\r
974 #define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */\r
975 \r
976 /* AESASTAT Control Bits */\r
977 #define AESBUSY_L (0x0001u) /* AES Busy */\r
978 #define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */\r
979 #define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */\r
980 #define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */\r
981 #define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */\r
982 #define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */\r
983 #define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */\r
984 #define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */\r
985 \r
986 /* AESASTAT Control Bits */\r
987 #define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */\r
988 #define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */\r
989 #define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */\r
990 #define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */\r
991 #define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */\r
992 #define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */\r
993 #define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */\r
994 #define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */\r
995 \r
996 #endif\r
997 /*************************************************************\r
998 * Backup RAM Module\r
999 *************************************************************/\r
1000 #ifdef __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */\r
1001 \r
1002 #define OFS_BAKMEM0 (0x0000u) /* Battery Backup Memory 0 */\r
1003 #define OFS_BAKMEM0_L OFS_BAKMEM0\r
1004 #define OFS_BAKMEM0_H OFS_BAKMEM0+1\r
1005 #define OFS_BAKMEM1 (0x0002u) /* Battery Backup Memory 1 */\r
1006 #define OFS_BAKMEM1_L OFS_BAKMEM1\r
1007 #define OFS_BAKMEM1_H OFS_BAKMEM1+1\r
1008 #define OFS_BAKMEM2 (0x0004u) /* Battery Backup Memory 2 */\r
1009 #define OFS_BAKMEM2_L OFS_BAKMEM2\r
1010 #define OFS_BAKMEM2_H OFS_BAKMEM2+1\r
1011 #define OFS_BAKMEM3 (0x0006u) /* Battery Backup Memory 3 */\r
1012 #define OFS_BAKMEM3_L OFS_BAKMEM3\r
1013 #define OFS_BAKMEM3_H OFS_BAKMEM3+1\r
1014 \r
1015 #endif\r
1016 /*************************************************************\r
1017 * Battery Charger Module\r
1018 *************************************************************/\r
1019 #ifdef __MSP430_HAS_BATTERY_CHARGER__ /* Definition to show that Module is available */\r
1020 \r
1021 #define OFS_BAKCTL (0x0000u) /* Battery Backup Control */\r
1022 #define OFS_BAKCTL_L OFS_BAKCTL\r
1023 #define OFS_BAKCTL_H OFS_BAKCTL+1\r
1024 #define OFS_BAKCHCTL (0x0002u) /* Battery Charger Control */\r
1025 #define OFS_BAKCHCTL_L OFS_BAKCHCTL\r
1026 #define OFS_BAKCHCTL_H OFS_BAKCHCTL+1\r
1027 \r
1028 /* BAKCTL Control Bits */\r
1029 #define LOCKBAK (0x0001u) /* Lock backup sub-system */\r
1030 #define BAKSW (0x0002u) /* Manual switch to battery backup supply */\r
1031 #define BAKADC (0x0004u) /* Battery backup supply to ADC. */\r
1032 #define BAKDIS (0x0008u) /* Disable backup supply switching. */\r
1033 \r
1034 /* BAKCTL Control Bits */\r
1035 #define LOCKBAK_L (0x0001u) /* Lock backup sub-system */\r
1036 #define BAKSW_L (0x0002u) /* Manual switch to battery backup supply */\r
1037 #define BAKADC_L (0x0004u) /* Battery backup supply to ADC. */\r
1038 #define BAKDIS_L (0x0008u) /* Disable backup supply switching. */\r
1039 \r
1040 /* BAKCHCTL Control Bits */\r
1041 #define CHEN (0x0001u) /* Charger enable */\r
1042 #define CHC0 (0x0002u) /* Charger charge current Bit 0 */\r
1043 #define CHC1 (0x0004u) /* Charger charge current Bit 1 */\r
1044 #define CHV0 (0x0010u) /* Charger end voltage Bit 0 */\r
1045 #define CHV1 (0x0020u) /* Charger end voltage Bit 1 */\r
1046 \r
1047 /* BAKCHCTL Control Bits */\r
1048 #define CHEN_L (0x0001u) /* Charger enable */\r
1049 #define CHC0_L (0x0002u) /* Charger charge current Bit 0 */\r
1050 #define CHC1_L (0x0004u) /* Charger charge current Bit 1 */\r
1051 #define CHV0_L (0x0010u) /* Charger end voltage Bit 0 */\r
1052 #define CHV1_L (0x0020u) /* Charger end voltage Bit 1 */\r
1053 \r
1054 #define CHPWD (0x6900u) /* Charger write password. */\r
1055 \r
1056 #endif\r
1057 /************************************************************\r
1058 * Comparator B\r
1059 ************************************************************/\r
1060 #ifdef __MSP430_HAS_COMPB__ /* Definition to show that Module is available */\r
1061 \r
1062 #define OFS_CBCTL0 (0x0000u) /* Comparator B Control Register 0 */\r
1063 #define OFS_CBCTL0_L OFS_CBCTL0\r
1064 #define OFS_CBCTL0_H OFS_CBCTL0+1\r
1065 #define OFS_CBCTL1 (0x0002u) /* Comparator B Control Register 1 */\r
1066 #define OFS_CBCTL1_L OFS_CBCTL1\r
1067 #define OFS_CBCTL1_H OFS_CBCTL1+1\r
1068 #define OFS_CBCTL2 (0x0004u) /* Comparator B Control Register 2 */\r
1069 #define OFS_CBCTL2_L OFS_CBCTL2\r
1070 #define OFS_CBCTL2_H OFS_CBCTL2+1\r
1071 #define OFS_CBCTL3 (0x0006u) /* Comparator B Control Register 3 */\r
1072 #define OFS_CBCTL3_L OFS_CBCTL3\r
1073 #define OFS_CBCTL3_H OFS_CBCTL3+1\r
1074 #define OFS_CBINT (0x000Cu) /* Comparator B Interrupt Register */\r
1075 #define OFS_CBINT_L OFS_CBINT\r
1076 #define OFS_CBINT_H OFS_CBINT+1\r
1077 #define OFS_CBIV (0x000Eu) /* Comparator B Interrupt Vector Word */\r
1078 \r
1079 /* CBCTL0 Control Bits */\r
1080 #define CBIPSEL0 (0x0001u) /* Comp. B Pos. Channel Input Select 0 */\r
1081 #define CBIPSEL1 (0x0002u) /* Comp. B Pos. Channel Input Select 1 */\r
1082 #define CBIPSEL2 (0x0004u) /* Comp. B Pos. Channel Input Select 2 */\r
1083 #define CBIPSEL3 (0x0008u) /* Comp. B Pos. Channel Input Select 3 */\r
1084 //#define RESERVED (0x0010u) /* Comp. B */\r
1085 //#define RESERVED (0x0020u) /* Comp. B */\r
1086 //#define RESERVED (0x0040u) /* Comp. B */\r
1087 #define CBIPEN (0x0080u) /* Comp. B Pos. Channel Input Enable */\r
1088 #define CBIMSEL0 (0x0100u) /* Comp. B Neg. Channel Input Select 0 */\r
1089 #define CBIMSEL1 (0x0200u) /* Comp. B Neg. Channel Input Select 1 */\r
1090 #define CBIMSEL2 (0x0400u) /* Comp. B Neg. Channel Input Select 2 */\r
1091 #define CBIMSEL3 (0x0800u) /* Comp. B Neg. Channel Input Select 3 */\r
1092 //#define RESERVED (0x1000u) /* Comp. B */\r
1093 //#define RESERVED (0x2000u) /* Comp. B */\r
1094 //#define RESERVED (0x4000u) /* Comp. B */\r
1095 #define CBIMEN (0x8000u) /* Comp. B Neg. Channel Input Enable */\r
1096 \r
1097 /* CBCTL0 Control Bits */\r
1098 #define CBIPSEL0_L (0x0001u) /* Comp. B Pos. Channel Input Select 0 */\r
1099 #define CBIPSEL1_L (0x0002u) /* Comp. B Pos. Channel Input Select 1 */\r
1100 #define CBIPSEL2_L (0x0004u) /* Comp. B Pos. Channel Input Select 2 */\r
1101 #define CBIPSEL3_L (0x0008u) /* Comp. B Pos. Channel Input Select 3 */\r
1102 //#define RESERVED (0x0010u) /* Comp. B */\r
1103 //#define RESERVED (0x0020u) /* Comp. B */\r
1104 //#define RESERVED (0x0040u) /* Comp. B */\r
1105 #define CBIPEN_L (0x0080u) /* Comp. B Pos. Channel Input Enable */\r
1106 //#define RESERVED (0x1000u) /* Comp. B */\r
1107 //#define RESERVED (0x2000u) /* Comp. B */\r
1108 //#define RESERVED (0x4000u) /* Comp. B */\r
1109 \r
1110 /* CBCTL0 Control Bits */\r
1111 //#define RESERVED (0x0010u) /* Comp. B */\r
1112 //#define RESERVED (0x0020u) /* Comp. B */\r
1113 //#define RESERVED (0x0040u) /* Comp. B */\r
1114 #define CBIMSEL0_H (0x0001u) /* Comp. B Neg. Channel Input Select 0 */\r
1115 #define CBIMSEL1_H (0x0002u) /* Comp. B Neg. Channel Input Select 1 */\r
1116 #define CBIMSEL2_H (0x0004u) /* Comp. B Neg. Channel Input Select 2 */\r
1117 #define CBIMSEL3_H (0x0008u) /* Comp. B Neg. Channel Input Select 3 */\r
1118 //#define RESERVED (0x1000u) /* Comp. B */\r
1119 //#define RESERVED (0x2000u) /* Comp. B */\r
1120 //#define RESERVED (0x4000u) /* Comp. B */\r
1121 #define CBIMEN_H (0x0080u) /* Comp. B Neg. Channel Input Enable */\r
1122 \r
1123 #define CBIPSEL_0 (0x0000u) /* Comp. B V+ terminal Input Select: Channel 0 */\r
1124 #define CBIPSEL_1 (0x0001u) /* Comp. B V+ terminal Input Select: Channel 1 */\r
1125 #define CBIPSEL_2 (0x0002u) /* Comp. B V+ terminal Input Select: Channel 2 */\r
1126 #define CBIPSEL_3 (0x0003u) /* Comp. B V+ terminal Input Select: Channel 3 */\r
1127 #define CBIPSEL_4 (0x0004u) /* Comp. B V+ terminal Input Select: Channel 4 */\r
1128 #define CBIPSEL_5 (0x0005u) /* Comp. B V+ terminal Input Select: Channel 5 */\r
1129 #define CBIPSEL_6 (0x0006u) /* Comp. B V+ terminal Input Select: Channel 6 */\r
1130 #define CBIPSEL_7 (0x0007u) /* Comp. B V+ terminal Input Select: Channel 7 */\r
1131 #define CBIPSEL_8 (0x0008u) /* Comp. B V+ terminal Input Select: Channel 8 */\r
1132 #define CBIPSEL_9 (0x0009u) /* Comp. B V+ terminal Input Select: Channel 9 */\r
1133 #define CBIPSEL_10 (0x000Au) /* Comp. B V+ terminal Input Select: Channel 10 */\r
1134 #define CBIPSEL_11 (0x000Bu) /* Comp. B V+ terminal Input Select: Channel 11 */\r
1135 #define CBIPSEL_12 (0x000Cu) /* Comp. B V+ terminal Input Select: Channel 12 */\r
1136 #define CBIPSEL_13 (0x000Du) /* Comp. B V+ terminal Input Select: Channel 13 */\r
1137 #define CBIPSEL_14 (0x000Eu) /* Comp. B V+ terminal Input Select: Channel 14 */\r
1138 #define CBIPSEL_15 (0x000Fu) /* Comp. B V+ terminal Input Select: Channel 15 */\r
1139 \r
1140 #define CBIMSEL_0 (0x0000u) /* Comp. B V- Terminal Input Select: Channel 0 */\r
1141 #define CBIMSEL_1 (0x0100u) /* Comp. B V- Terminal Input Select: Channel 1 */\r
1142 #define CBIMSEL_2 (0x0200u) /* Comp. B V- Terminal Input Select: Channel 2 */\r
1143 #define CBIMSEL_3 (0x0300u) /* Comp. B V- Terminal Input Select: Channel 3 */\r
1144 #define CBIMSEL_4 (0x0400u) /* Comp. B V- Terminal Input Select: Channel 4 */\r
1145 #define CBIMSEL_5 (0x0500u) /* Comp. B V- Terminal Input Select: Channel 5 */\r
1146 #define CBIMSEL_6 (0x0600u) /* Comp. B V- Terminal Input Select: Channel 6 */\r
1147 #define CBIMSEL_7 (0x0700u) /* Comp. B V- Terminal Input Select: Channel 7 */\r
1148 #define CBIMSEL_8 (0x0800u) /* Comp. B V- terminal Input Select: Channel 8 */\r
1149 #define CBIMSEL_9 (0x0900u) /* Comp. B V- terminal Input Select: Channel 9 */\r
1150 #define CBIMSEL_10 (0x0A00u) /* Comp. B V- terminal Input Select: Channel 10 */\r
1151 #define CBIMSEL_11 (0x0B00u) /* Comp. B V- terminal Input Select: Channel 11 */\r
1152 #define CBIMSEL_12 (0x0C00u) /* Comp. B V- terminal Input Select: Channel 12 */\r
1153 #define CBIMSEL_13 (0x0D00u) /* Comp. B V- terminal Input Select: Channel 13 */\r
1154 #define CBIMSEL_14 (0x0E00u) /* Comp. B V- terminal Input Select: Channel 14 */\r
1155 #define CBIMSEL_15 (0x0F00u) /* Comp. B V- terminal Input Select: Channel 15 */\r
1156 \r
1157 /* CBCTL1 Control Bits */\r
1158 #define CBOUT (0x0001u) /* Comp. B Output */\r
1159 #define CBOUTPOL (0x0002u) /* Comp. B Output Polarity */\r
1160 #define CBF (0x0004u) /* Comp. B Enable Output Filter */\r
1161 #define CBIES (0x0008u) /* Comp. B Interrupt Edge Select */\r
1162 #define CBSHORT (0x0010u) /* Comp. B Input Short */\r
1163 #define CBEX (0x0020u) /* Comp. B Exchange Inputs */\r
1164 #define CBFDLY0 (0x0040u) /* Comp. B Filter delay Bit 0 */\r
1165 #define CBFDLY1 (0x0080u) /* Comp. B Filter delay Bit 1 */\r
1166 #define CBPWRMD0 (0x0100u) /* Comp. B Power Mode Bit 0 */\r
1167 #define CBPWRMD1 (0x0200u) /* Comp. B Power Mode Bit 1 */\r
1168 #define CBON (0x0400u) /* Comp. B enable */\r
1169 #define CBMRVL (0x0800u) /* Comp. B CBMRV Level */\r
1170 #define CBMRVS (0x1000u) /* Comp. B Output selects between VREF0 or VREF1*/\r
1171 //#define RESERVED (0x2000u) /* Comp. B */\r
1172 //#define RESERVED (0x4000u) /* Comp. B */\r
1173 //#define RESERVED (0x8000u) /* Comp. B */\r
1174 \r
1175 /* CBCTL1 Control Bits */\r
1176 #define CBOUT_L (0x0001u) /* Comp. B Output */\r
1177 #define CBOUTPOL_L (0x0002u) /* Comp. B Output Polarity */\r
1178 #define CBF_L (0x0004u) /* Comp. B Enable Output Filter */\r
1179 #define CBIES_L (0x0008u) /* Comp. B Interrupt Edge Select */\r
1180 #define CBSHORT_L (0x0010u) /* Comp. B Input Short */\r
1181 #define CBEX_L (0x0020u) /* Comp. B Exchange Inputs */\r
1182 #define CBFDLY0_L (0x0040u) /* Comp. B Filter delay Bit 0 */\r
1183 #define CBFDLY1_L (0x0080u) /* Comp. B Filter delay Bit 1 */\r
1184 //#define RESERVED (0x2000u) /* Comp. B */\r
1185 //#define RESERVED (0x4000u) /* Comp. B */\r
1186 //#define RESERVED (0x8000u) /* Comp. B */\r
1187 \r
1188 /* CBCTL1 Control Bits */\r
1189 #define CBPWRMD0_H (0x0001u) /* Comp. B Power Mode Bit 0 */\r
1190 #define CBPWRMD1_H (0x0002u) /* Comp. B Power Mode Bit 1 */\r
1191 #define CBON_H (0x0004u) /* Comp. B enable */\r
1192 #define CBMRVL_H (0x0008u) /* Comp. B CBMRV Level */\r
1193 #define CBMRVS_H (0x0010u) /* Comp. B Output selects between VREF0 or VREF1*/\r
1194 //#define RESERVED (0x2000u) /* Comp. B */\r
1195 //#define RESERVED (0x4000u) /* Comp. B */\r
1196 //#define RESERVED (0x8000u) /* Comp. B */\r
1197 \r
1198 #define CBFDLY_0 (0x0000u) /* Comp. B Filter delay 0 : 450ns */\r
1199 #define CBFDLY_1 (0x0040u) /* Comp. B Filter delay 1 : 900ns */\r
1200 #define CBFDLY_2 (0x0080u) /* Comp. B Filter delay 2 : 1800ns */\r
1201 #define CBFDLY_3 (0x00C0u) /* Comp. B Filter delay 3 : 3600ns */\r
1202 \r
1203 #define CBPWRMD_0 (0x0000u) /* Comp. B Power Mode 0 : High speed */\r
1204 #define CBPWRMD_1 (0x0100u) /* Comp. B Power Mode 1 : Normal */\r
1205 #define CBPWRMD_2 (0x0200u) /* Comp. B Power Mode 2 : Ultra-Low*/\r
1206 #define CBPWRMD_3 (0x0300u) /* Comp. B Power Mode 3 : Reserved */\r
1207 \r
1208 /* CBCTL2 Control Bits */\r
1209 #define CBREF00 (0x0001u) /* Comp. B Reference 0 Resistor Select Bit : 0 */\r
1210 #define CBREF01 (0x0002u) /* Comp. B Reference 0 Resistor Select Bit : 1 */\r
1211 #define CBREF02 (0x0004u) /* Comp. B Reference 0 Resistor Select Bit : 2 */\r
1212 #define CBREF03 (0x0008u) /* Comp. B Reference 0 Resistor Select Bit : 3 */\r
1213 #define CBREF04 (0x0010u) /* Comp. B Reference 0 Resistor Select Bit : 4 */\r
1214 #define CBRSEL (0x0020u) /* Comp. B Reference select */\r
1215 #define CBRS0 (0x0040u) /* Comp. B Reference Source Bit : 0 */\r
1216 #define CBRS1 (0x0080u) /* Comp. B Reference Source Bit : 1 */\r
1217 #define CBREF10 (0x0100u) /* Comp. B Reference 1 Resistor Select Bit : 0 */\r
1218 #define CBREF11 (0x0200u) /* Comp. B Reference 1 Resistor Select Bit : 1 */\r
1219 #define CBREF12 (0x0400u) /* Comp. B Reference 1 Resistor Select Bit : 2 */\r
1220 #define CBREF13 (0x0800u) /* Comp. B Reference 1 Resistor Select Bit : 3 */\r
1221 #define CBREF14 (0x1000u) /* Comp. B Reference 1 Resistor Select Bit : 4 */\r
1222 #define CBREFL0 (0x2000u) /* Comp. B Reference voltage level Bit : 0 */\r
1223 #define CBREFL1 (0x4000u) /* Comp. B Reference voltage level Bit : 1 */\r
1224 #define CBREFACC (0x8000u) /* Comp. B Reference Accuracy */\r
1225 \r
1226 /* CBCTL2 Control Bits */\r
1227 #define CBREF00_L (0x0001u) /* Comp. B Reference 0 Resistor Select Bit : 0 */\r
1228 #define CBREF01_L (0x0002u) /* Comp. B Reference 0 Resistor Select Bit : 1 */\r
1229 #define CBREF02_L (0x0004u) /* Comp. B Reference 0 Resistor Select Bit : 2 */\r
1230 #define CBREF03_L (0x0008u) /* Comp. B Reference 0 Resistor Select Bit : 3 */\r
1231 #define CBREF04_L (0x0010u) /* Comp. B Reference 0 Resistor Select Bit : 4 */\r
1232 #define CBRSEL_L (0x0020u) /* Comp. B Reference select */\r
1233 #define CBRS0_L (0x0040u) /* Comp. B Reference Source Bit : 0 */\r
1234 #define CBRS1_L (0x0080u) /* Comp. B Reference Source Bit : 1 */\r
1235 \r
1236 /* CBCTL2 Control Bits */\r
1237 #define CBREF10_H (0x0001u) /* Comp. B Reference 1 Resistor Select Bit : 0 */\r
1238 #define CBREF11_H (0x0002u) /* Comp. B Reference 1 Resistor Select Bit : 1 */\r
1239 #define CBREF12_H (0x0004u) /* Comp. B Reference 1 Resistor Select Bit : 2 */\r
1240 #define CBREF13_H (0x0008u) /* Comp. B Reference 1 Resistor Select Bit : 3 */\r
1241 #define CBREF14_H (0x0010u) /* Comp. B Reference 1 Resistor Select Bit : 4 */\r
1242 #define CBREFL0_H (0x0020u) /* Comp. B Reference voltage level Bit : 0 */\r
1243 #define CBREFL1_H (0x0040u) /* Comp. B Reference voltage level Bit : 1 */\r
1244 #define CBREFACC_H (0x0080u) /* Comp. B Reference Accuracy */\r
1245 \r
1246 #define CBREF0_0 (0x0000u) /* Comp. B Int. Ref.0 Select 0 : 1/32 */\r
1247 #define CBREF0_1 (0x0001u) /* Comp. B Int. Ref.0 Select 1 : 2/32 */\r
1248 #define CBREF0_2 (0x0002u) /* Comp. B Int. Ref.0 Select 2 : 3/32 */\r
1249 #define CBREF0_3 (0x0003u) /* Comp. B Int. Ref.0 Select 3 : 4/32 */\r
1250 #define CBREF0_4 (0x0004u) /* Comp. B Int. Ref.0 Select 4 : 5/32 */\r
1251 #define CBREF0_5 (0x0005u) /* Comp. B Int. Ref.0 Select 5 : 6/32 */\r
1252 #define CBREF0_6 (0x0006u) /* Comp. B Int. Ref.0 Select 6 : 7/32 */\r
1253 #define CBREF0_7 (0x0007u) /* Comp. B Int. Ref.0 Select 7 : 8/32 */\r
1254 #define CBREF0_8 (0x0008u) /* Comp. B Int. Ref.0 Select 0 : 9/32 */\r
1255 #define CBREF0_9 (0x0009u) /* Comp. B Int. Ref.0 Select 1 : 10/32 */\r
1256 #define CBREF0_10 (0x000Au) /* Comp. B Int. Ref.0 Select 2 : 11/32 */\r
1257 #define CBREF0_11 (0x000Bu) /* Comp. B Int. Ref.0 Select 3 : 12/32 */\r
1258 #define CBREF0_12 (0x000Cu) /* Comp. B Int. Ref.0 Select 4 : 13/32 */\r
1259 #define CBREF0_13 (0x000Du) /* Comp. B Int. Ref.0 Select 5 : 14/32 */\r
1260 #define CBREF0_14 (0x000Eu) /* Comp. B Int. Ref.0 Select 6 : 15/32 */\r
1261 #define CBREF0_15 (0x000Fu) /* Comp. B Int. Ref.0 Select 7 : 16/32 */\r
1262 #define CBREF0_16 (0x0010u) /* Comp. B Int. Ref.0 Select 0 : 17/32 */\r
1263 #define CBREF0_17 (0x0011u) /* Comp. B Int. Ref.0 Select 1 : 18/32 */\r
1264 #define CBREF0_18 (0x0012u) /* Comp. B Int. Ref.0 Select 2 : 19/32 */\r
1265 #define CBREF0_19 (0x0013u) /* Comp. B Int. Ref.0 Select 3 : 20/32 */\r
1266 #define CBREF0_20 (0x0014u) /* Comp. B Int. Ref.0 Select 4 : 21/32 */\r
1267 #define CBREF0_21 (0x0015u) /* Comp. B Int. Ref.0 Select 5 : 22/32 */\r
1268 #define CBREF0_22 (0x0016u) /* Comp. B Int. Ref.0 Select 6 : 23/32 */\r
1269 #define CBREF0_23 (0x0017u) /* Comp. B Int. Ref.0 Select 7 : 24/32 */\r
1270 #define CBREF0_24 (0x0018u) /* Comp. B Int. Ref.0 Select 0 : 25/32 */\r
1271 #define CBREF0_25 (0x0019u) /* Comp. B Int. Ref.0 Select 1 : 26/32 */\r
1272 #define CBREF0_26 (0x001Au) /* Comp. B Int. Ref.0 Select 2 : 27/32 */\r
1273 #define CBREF0_27 (0x001Bu) /* Comp. B Int. Ref.0 Select 3 : 28/32 */\r
1274 #define CBREF0_28 (0x001Cu) /* Comp. B Int. Ref.0 Select 4 : 29/32 */\r
1275 #define CBREF0_29 (0x001Du) /* Comp. B Int. Ref.0 Select 5 : 30/32 */\r
1276 #define CBREF0_30 (0x001Eu) /* Comp. B Int. Ref.0 Select 6 : 31/32 */\r
1277 #define CBREF0_31 (0x001Fu) /* Comp. B Int. Ref.0 Select 7 : 32/32 */\r
1278 \r
1279 #define CBRS_0 (0x0000u) /* Comp. B Reference Source 0 : Off */\r
1280 #define CBRS_1 (0x0040u) /* Comp. B Reference Source 1 : Vcc */\r
1281 #define CBRS_2 (0x0080u) /* Comp. B Reference Source 2 : Shared Ref. */\r
1282 #define CBRS_3 (0x00C0u) /* Comp. B Reference Source 3 : Shared Ref. / Off */\r
1283 \r
1284 #define CBREF1_0 (0x0000u) /* Comp. B Int. Ref.1 Select 0 : 1/32 */\r
1285 #define CBREF1_1 (0x0100u) /* Comp. B Int. Ref.1 Select 1 : 2/32 */\r
1286 #define CBREF1_2 (0x0200u) /* Comp. B Int. Ref.1 Select 2 : 3/32 */\r
1287 #define CBREF1_3 (0x0300u) /* Comp. B Int. Ref.1 Select 3 : 4/32 */\r
1288 #define CBREF1_4 (0x0400u) /* Comp. B Int. Ref.1 Select 4 : 5/32 */\r
1289 #define CBREF1_5 (0x0500u) /* Comp. B Int. Ref.1 Select 5 : 6/32 */\r
1290 #define CBREF1_6 (0x0600u) /* Comp. B Int. Ref.1 Select 6 : 7/32 */\r
1291 #define CBREF1_7 (0x0700u) /* Comp. B Int. Ref.1 Select 7 : 8/32 */\r
1292 #define CBREF1_8 (0x0800u) /* Comp. B Int. Ref.1 Select 0 : 9/32 */\r
1293 #define CBREF1_9 (0x0900u) /* Comp. B Int. Ref.1 Select 1 : 10/32 */\r
1294 #define CBREF1_10 (0x0A00u) /* Comp. B Int. Ref.1 Select 2 : 11/32 */\r
1295 #define CBREF1_11 (0x0B00u) /* Comp. B Int. Ref.1 Select 3 : 12/32 */\r
1296 #define CBREF1_12 (0x0C00u) /* Comp. B Int. Ref.1 Select 4 : 13/32 */\r
1297 #define CBREF1_13 (0x0D00u) /* Comp. B Int. Ref.1 Select 5 : 14/32 */\r
1298 #define CBREF1_14 (0x0E00u) /* Comp. B Int. Ref.1 Select 6 : 15/32 */\r
1299 #define CBREF1_15 (0x0F00u) /* Comp. B Int. Ref.1 Select 7 : 16/32 */\r
1300 #define CBREF1_16 (0x1000u) /* Comp. B Int. Ref.1 Select 0 : 17/32 */\r
1301 #define CBREF1_17 (0x1100u) /* Comp. B Int. Ref.1 Select 1 : 18/32 */\r
1302 #define CBREF1_18 (0x1200u) /* Comp. B Int. Ref.1 Select 2 : 19/32 */\r
1303 #define CBREF1_19 (0x1300u) /* Comp. B Int. Ref.1 Select 3 : 20/32 */\r
1304 #define CBREF1_20 (0x1400u) /* Comp. B Int. Ref.1 Select 4 : 21/32 */\r
1305 #define CBREF1_21 (0x1500u) /* Comp. B Int. Ref.1 Select 5 : 22/32 */\r
1306 #define CBREF1_22 (0x1600u) /* Comp. B Int. Ref.1 Select 6 : 23/32 */\r
1307 #define CBREF1_23 (0x1700u) /* Comp. B Int. Ref.1 Select 7 : 24/32 */\r
1308 #define CBREF1_24 (0x1800u) /* Comp. B Int. Ref.1 Select 0 : 25/32 */\r
1309 #define CBREF1_25 (0x1900u) /* Comp. B Int. Ref.1 Select 1 : 26/32 */\r
1310 #define CBREF1_26 (0x1A00u) /* Comp. B Int. Ref.1 Select 2 : 27/32 */\r
1311 #define CBREF1_27 (0x1B00u) /* Comp. B Int. Ref.1 Select 3 : 28/32 */\r
1312 #define CBREF1_28 (0x1C00u) /* Comp. B Int. Ref.1 Select 4 : 29/32 */\r
1313 #define CBREF1_29 (0x1D00u) /* Comp. B Int. Ref.1 Select 5 : 30/32 */\r
1314 #define CBREF1_30 (0x1E00u) /* Comp. B Int. Ref.1 Select 6 : 31/32 */\r
1315 #define CBREF1_31 (0x1F00u) /* Comp. B Int. Ref.1 Select 7 : 32/32 */\r
1316 \r
1317 #define CBREFL_0 (0x0000u) /* Comp. B Reference voltage level 0 : None */\r
1318 #define CBREFL_1 (0x2000u) /* Comp. B Reference voltage level 1 : 1.5V */\r
1319 #define CBREFL_2 (0x4000u) /* Comp. B Reference voltage level 2 : 2.0V */\r
1320 #define CBREFL_3 (0x6000u) /* Comp. B Reference voltage level 3 : 2.5V */\r
1321 \r
1322 #define CBPD0 (0x0001u) /* Comp. B Disable Input Buffer of Port Register .0 */\r
1323 #define CBPD1 (0x0002u) /* Comp. B Disable Input Buffer of Port Register .1 */\r
1324 #define CBPD2 (0x0004u) /* Comp. B Disable Input Buffer of Port Register .2 */\r
1325 #define CBPD3 (0x0008u) /* Comp. B Disable Input Buffer of Port Register .3 */\r
1326 #define CBPD4 (0x0010u) /* Comp. B Disable Input Buffer of Port Register .4 */\r
1327 #define CBPD5 (0x0020u) /* Comp. B Disable Input Buffer of Port Register .5 */\r
1328 #define CBPD6 (0x0040u) /* Comp. B Disable Input Buffer of Port Register .6 */\r
1329 #define CBPD7 (0x0080u) /* Comp. B Disable Input Buffer of Port Register .7 */\r
1330 #define CBPD8 (0x0100u) /* Comp. B Disable Input Buffer of Port Register .8 */\r
1331 #define CBPD9 (0x0200u) /* Comp. B Disable Input Buffer of Port Register .9 */\r
1332 #define CBPD10 (0x0400u) /* Comp. B Disable Input Buffer of Port Register .10 */\r
1333 #define CBPD11 (0x0800u) /* Comp. B Disable Input Buffer of Port Register .11 */\r
1334 #define CBPD12 (0x1000u) /* Comp. B Disable Input Buffer of Port Register .12 */\r
1335 #define CBPD13 (0x2000u) /* Comp. B Disable Input Buffer of Port Register .13 */\r
1336 #define CBPD14 (0x4000u) /* Comp. B Disable Input Buffer of Port Register .14 */\r
1337 #define CBPD15 (0x8000u) /* Comp. B Disable Input Buffer of Port Register .15 */\r
1338 \r
1339 #define CBPD0_L (0x0001u) /* Comp. B Disable Input Buffer of Port Register .0 */\r
1340 #define CBPD1_L (0x0002u) /* Comp. B Disable Input Buffer of Port Register .1 */\r
1341 #define CBPD2_L (0x0004u) /* Comp. B Disable Input Buffer of Port Register .2 */\r
1342 #define CBPD3_L (0x0008u) /* Comp. B Disable Input Buffer of Port Register .3 */\r
1343 #define CBPD4_L (0x0010u) /* Comp. B Disable Input Buffer of Port Register .4 */\r
1344 #define CBPD5_L (0x0020u) /* Comp. B Disable Input Buffer of Port Register .5 */\r
1345 #define CBPD6_L (0x0040u) /* Comp. B Disable Input Buffer of Port Register .6 */\r
1346 #define CBPD7_L (0x0080u) /* Comp. B Disable Input Buffer of Port Register .7 */\r
1347 \r
1348 #define CBPD8_H (0x0001u) /* Comp. B Disable Input Buffer of Port Register .8 */\r
1349 #define CBPD9_H (0x0002u) /* Comp. B Disable Input Buffer of Port Register .9 */\r
1350 #define CBPD10_H (0x0004u) /* Comp. B Disable Input Buffer of Port Register .10 */\r
1351 #define CBPD11_H (0x0008u) /* Comp. B Disable Input Buffer of Port Register .11 */\r
1352 #define CBPD12_H (0x0010u) /* Comp. B Disable Input Buffer of Port Register .12 */\r
1353 #define CBPD13_H (0x0020u) /* Comp. B Disable Input Buffer of Port Register .13 */\r
1354 #define CBPD14_H (0x0040u) /* Comp. B Disable Input Buffer of Port Register .14 */\r
1355 #define CBPD15_H (0x0080u) /* Comp. B Disable Input Buffer of Port Register .15 */\r
1356 \r
1357 /* CBINT Control Bits */\r
1358 #define CBIFG (0x0001u) /* Comp. B Interrupt Flag */\r
1359 #define CBIIFG (0x0002u) /* Comp. B Interrupt Flag Inverted Polarity */\r
1360 //#define RESERVED (0x0004u) /* Comp. B */\r
1361 //#define RESERVED (0x0008u) /* Comp. B */\r
1362 //#define RESERVED (0x0010u) /* Comp. B */\r
1363 //#define RESERVED (0x0020u) /* Comp. B */\r
1364 //#define RESERVED (0x0040u) /* Comp. B */\r
1365 //#define RESERVED (0x0080u) /* Comp. B */\r
1366 #define CBIE (0x0100u) /* Comp. B Interrupt Enable */\r
1367 #define CBIIE (0x0200u) /* Comp. B Interrupt Enable Inverted Polarity */\r
1368 //#define RESERVED (0x0400u) /* Comp. B */\r
1369 //#define RESERVED (0x0800u) /* Comp. B */\r
1370 //#define RESERVED (0x1000u) /* Comp. B */\r
1371 //#define RESERVED (0x2000u) /* Comp. B */\r
1372 //#define RESERVED (0x4000u) /* Comp. B */\r
1373 //#define RESERVED (0x8000u) /* Comp. B */\r
1374 \r
1375 /* CBINT Control Bits */\r
1376 #define CBIFG_L (0x0001u) /* Comp. B Interrupt Flag */\r
1377 #define CBIIFG_L (0x0002u) /* Comp. B Interrupt Flag Inverted Polarity */\r
1378 //#define RESERVED (0x0004u) /* Comp. B */\r
1379 //#define RESERVED (0x0008u) /* Comp. B */\r
1380 //#define RESERVED (0x0010u) /* Comp. B */\r
1381 //#define RESERVED (0x0020u) /* Comp. B */\r
1382 //#define RESERVED (0x0040u) /* Comp. B */\r
1383 //#define RESERVED (0x0080u) /* Comp. B */\r
1384 //#define RESERVED (0x0400u) /* Comp. B */\r
1385 //#define RESERVED (0x0800u) /* Comp. B */\r
1386 //#define RESERVED (0x1000u) /* Comp. B */\r
1387 //#define RESERVED (0x2000u) /* Comp. B */\r
1388 //#define RESERVED (0x4000u) /* Comp. B */\r
1389 //#define RESERVED (0x8000u) /* Comp. B */\r
1390 \r
1391 /* CBINT Control Bits */\r
1392 //#define RESERVED (0x0004u) /* Comp. B */\r
1393 //#define RESERVED (0x0008u) /* Comp. B */\r
1394 //#define RESERVED (0x0010u) /* Comp. B */\r
1395 //#define RESERVED (0x0020u) /* Comp. B */\r
1396 //#define RESERVED (0x0040u) /* Comp. B */\r
1397 //#define RESERVED (0x0080u) /* Comp. B */\r
1398 #define CBIE_H (0x0001u) /* Comp. B Interrupt Enable */\r
1399 #define CBIIE_H (0x0002u) /* Comp. B Interrupt Enable Inverted Polarity */\r
1400 //#define RESERVED (0x0400u) /* Comp. B */\r
1401 //#define RESERVED (0x0800u) /* Comp. B */\r
1402 //#define RESERVED (0x1000u) /* Comp. B */\r
1403 //#define RESERVED (0x2000u) /* Comp. B */\r
1404 //#define RESERVED (0x4000u) /* Comp. B */\r
1405 //#define RESERVED (0x8000u) /* Comp. B */\r
1406 \r
1407 /* CBIV Definitions */\r
1408 #define CBIV_NONE (0x0000u) /* No Interrupt pending */\r
1409 #define CBIV_CBIFG (0x0002u) /* CBIFG */\r
1410 #define CBIV_CBIIFG (0x0004u) /* CBIIFG */\r
1411 \r
1412 #endif\r
1413 /************************************************************\r
1414 * CC1101 Radio Interface\r
1415 ************************************************************/\r
1416 #ifdef __MSP430_HAS_CC1101__ /* Definition to show that Module is available */\r
1417 \r
1418 #define OFS_RF1AIFCTL0 (0x0000u) /* Radio interface control register 0 */\r
1419 #define OFS_RF1AIFCTL0_L OFS_RF1AIFCTL0\r
1420 #define OFS_RF1AIFCTL0_H OFS_RF1AIFCTL0+1\r
1421 #define OFS_RF1AIFCTL1 (0x0002u) /* Radio interface control register 1 */\r
1422 #define OFS_RF1AIFCTL1_L OFS_RF1AIFCTL1\r
1423 #define OFS_RF1AIFCTL1_H OFS_RF1AIFCTL1+1\r
1424 #define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */\r
1425 #define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */\r
1426 #define OFS_RF1AIFCTL2 (0x0004u) /* (Radio interface control register 2) */\r
1427 #define OFS_RF1AIFCTL2_L OFS_RF1AIFCTL2\r
1428 #define OFS_RF1AIFCTL2_H OFS_RF1AIFCTL2+1\r
1429 #define OFS_RF1AIFERR (0x0006u) /* Radio interface error flag register */\r
1430 #define OFS_RF1AIFERR_L OFS_RF1AIFERR\r
1431 #define OFS_RF1AIFERR_H OFS_RF1AIFERR+1\r
1432 #define OFS_RF1AIFERRV (0x000Cu) /* Radio interface error vector word register */\r
1433 #define OFS_RF1AIFERRV_L OFS_RF1AIFERRV\r
1434 #define OFS_RF1AIFERRV_H OFS_RF1AIFERRV+1\r
1435 #define OFS_RF1AIFIV (0x000Eu) /* Radio interface interrupt vector word register */\r
1436 #define OFS_RF1AIFIV_L OFS_RF1AIFIV\r
1437 #define OFS_RF1AIFIV_H OFS_RF1AIFIV+1\r
1438 #define OFS_RF1AINSTRW (0x0010u) /* Radio instruction word register */\r
1439 #define OFS_RF1AINSTRW_L OFS_RF1AINSTRW\r
1440 #define OFS_RF1AINSTRW_H OFS_RF1AINSTRW+1\r
1441 #define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */\r
1442 #define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */\r
1443 #define OFS_RF1AINSTR1W (0x0012u) /* Radio instruction 1-byte register with autoread */\r
1444 #define OFS_RF1AINSTR1W_L OFS_RF1AINSTR1W\r
1445 #define OFS_RF1AINSTR1W_H OFS_RF1AINSTR1W+1\r
1446 #define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */\r
1447 #define OFS_RF1AINSTR2W (0x0014u) /* Radio instruction 2-byte register with autoread */\r
1448 #define OFS_RF1AINSTR2W_L OFS_RF1AINSTR2W\r
1449 #define OFS_RF1AINSTR2W_H OFS_RF1AINSTR2W+1\r
1450 #define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */\r
1451 #define OFS_RF1ADINW (0x0016u) /* Radio word data in register */\r
1452 #define OFS_RF1ADINW_L OFS_RF1ADINW\r
1453 #define OFS_RF1ADINW_H OFS_RF1ADINW+1\r
1454 \r
1455 #define OFS_RF1ASTAT0W (0x0020u) /* Radio status word register without auto-read */\r
1456 #define OFS_RF1ASTAT0W_L OFS_RF1ASTAT0W\r
1457 #define OFS_RF1ASTAT0W_H OFS_RF1ASTAT0W+1\r
1458 #define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */\r
1459 #define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */\r
1460 #define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */\r
1461 #define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */\r
1462 #define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */\r
1463 #define OFS_RF1ASTAT1W (0x0022u) /* Radio status word register with 1-byte auto-read */\r
1464 #define OFS_RF1ASTAT1W_L OFS_RF1ASTAT1W\r
1465 #define OFS_RF1ASTAT1W_H OFS_RF1ASTAT1W+1\r
1466 #define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */\r
1467 #define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */\r
1468 #define OFS_RF1ASTAT2W (0x0024u) /* Radio status word register with 2-byte auto-read */\r
1469 #define OFS_RF1ASTAT2W_L OFS_RF1ASTAT2W\r
1470 #define OFS_RF1ASTAT2W_H OFS_RF1ASTAT2W+1\r
1471 #define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */\r
1472 #define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */\r
1473 #define OFS_RF1ADOUT0W (0x0028u) /* Radio core word data out register without auto-read */\r
1474 #define OFS_RF1ADOUT0W_L OFS_RF1ADOUT0W\r
1475 #define OFS_RF1ADOUT0W_H OFS_RF1ADOUT0W+1\r
1476 #define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */\r
1477 #define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */\r
1478 #define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */\r
1479 #define OFS_RF1ADOUT1W (0x002Au) /* Radio core word data out register with 1-byte auto-read */\r
1480 #define OFS_RF1ADOUT1W_L OFS_RF1ADOUT1W\r
1481 #define OFS_RF1ADOUT1W_H OFS_RF1ADOUT1W+1\r
1482 #define OFS_RF1ADOUT2W (0x002Cu) /* Radio core word data out register with 2-byte auto-read */\r
1483 #define OFS_RF1ADOUT2W_L OFS_RF1ADOUT2W\r
1484 #define OFS_RF1ADOUT2W_H OFS_RF1ADOUT2W+1\r
1485 #define OFS_RF1AIN (0x0030u) /* Radio core signal input register */\r
1486 #define OFS_RF1AIN_L OFS_RF1AIN\r
1487 #define OFS_RF1AIN_H OFS_RF1AIN+1\r
1488 #define OFS_RF1AIFG (0x0032u) /* Radio core interrupt flag register */\r
1489 #define OFS_RF1AIFG_L OFS_RF1AIFG\r
1490 #define OFS_RF1AIFG_H OFS_RF1AIFG+1\r
1491 #define OFS_RF1AIES (0x0034u) /* Radio core interrupt edge select register */\r
1492 #define OFS_RF1AIES_L OFS_RF1AIES\r
1493 #define OFS_RF1AIES_H OFS_RF1AIES+1\r
1494 #define OFS_RF1AIE (0x0036u) /* Radio core interrupt enable register */\r
1495 #define OFS_RF1AIE_L OFS_RF1AIE\r
1496 #define OFS_RF1AIE_H OFS_RF1AIE+1\r
1497 #define OFS_RF1AIV (0x0038u) /* Radio core interrupt vector word register */\r
1498 #define OFS_RF1AIV_L OFS_RF1AIV\r
1499 #define OFS_RF1AIV_H OFS_RF1AIV+1\r
1500 #define OFS_RF1ARXFIFO (0x003Cu) /* Direct receive FIFO access register */\r
1501 #define OFS_RF1ARXFIFO_L OFS_RF1ARXFIFO\r
1502 #define OFS_RF1ARXFIFO_H OFS_RF1ARXFIFO+1\r
1503 #define OFS_RF1ATXFIFO (0x003Eu) /* Direct transmit FIFO access register */\r
1504 #define OFS_RF1ATXFIFO_L OFS_RF1ATXFIFO\r
1505 #define OFS_RF1ATXFIFO_H OFS_RF1ATXFIFO+1\r
1506 \r
1507 /* RF1AIFCTL0 Control Bits */\r
1508 #define RFFIFOEN (0x0001u) /* CC1101 Direct FIFO access enable */\r
1509 #define RFENDIAN (0x0002u) /* CC1101 Disable endianness conversion */\r
1510 \r
1511 /* RF1AIFCTL0 Control Bits */\r
1512 #define RFFIFOEN_L (0x0001u) /* CC1101 Direct FIFO access enable */\r
1513 #define RFENDIAN_L (0x0002u) /* CC1101 Disable endianness conversion */\r
1514 \r
1515 /* RF1AIFCTL1 Control Bits */\r
1516 #define RFRXIFG (0x0001u) /* Radio interface direct FIFO access receive interrupt flag */\r
1517 #define RFTXIFG (0x0002u) /* Radio interface direct FIFO access transmit interrupt flag */\r
1518 #define RFERRIFG (0x0004u) /* Radio interface error interrupt flag */\r
1519 #define RFINSTRIFG (0x0010u) /* Radio interface instruction interrupt flag */\r
1520 #define RFDINIFG (0x0020u) /* Radio interface data in interrupt flag */\r
1521 #define RFSTATIFG (0x0040u) /* Radio interface status interrupt flag */\r
1522 #define RFDOUTIFG (0x0080u) /* Radio interface data out interrupt flag */\r
1523 #define RFRXIE (0x0100u) /* Radio interface direct FIFO access receive interrupt enable */\r
1524 #define RFTXIE (0x0200u) /* Radio interface direct FIFO access transmit interrupt enable */\r
1525 #define RFERRIE (0x0400u) /* Radio interface error interrupt enable */\r
1526 #define RFINSTRIE (0x1000u) /* Radio interface instruction interrupt enable */\r
1527 #define RFDINIE (0x2000u) /* Radio interface data in interrupt enable */\r
1528 #define RFSTATIE (0x4000u) /* Radio interface status interrupt enable */\r
1529 #define RFDOUTIE (0x8000u) /* Radio interface data out interrupt enable */\r
1530 \r
1531 /* RF1AIFCTL1 Control Bits */\r
1532 #define RFRXIFG_L (0x0001u) /* Radio interface direct FIFO access receive interrupt flag */\r
1533 #define RFTXIFG_L (0x0002u) /* Radio interface direct FIFO access transmit interrupt flag */\r
1534 #define RFERRIFG_L (0x0004u) /* Radio interface error interrupt flag */\r
1535 #define RFINSTRIFG_L (0x0010u) /* Radio interface instruction interrupt flag */\r
1536 #define RFDINIFG_L (0x0020u) /* Radio interface data in interrupt flag */\r
1537 #define RFSTATIFG_L (0x0040u) /* Radio interface status interrupt flag */\r
1538 #define RFDOUTIFG_L (0x0080u) /* Radio interface data out interrupt flag */\r
1539 \r
1540 /* RF1AIFCTL1 Control Bits */\r
1541 #define RFRXIE_H (0x0001u) /* Radio interface direct FIFO access receive interrupt enable */\r
1542 #define RFTXIE_H (0x0002u) /* Radio interface direct FIFO access transmit interrupt enable */\r
1543 #define RFERRIE_H (0x0004u) /* Radio interface error interrupt enable */\r
1544 #define RFINSTRIE_H (0x0010u) /* Radio interface instruction interrupt enable */\r
1545 #define RFDINIE_H (0x0020u) /* Radio interface data in interrupt enable */\r
1546 #define RFSTATIE_H (0x0040u) /* Radio interface status interrupt enable */\r
1547 #define RFDOUTIE_H (0x0080u) /* Radio interface data out interrupt enable */\r
1548 \r
1549 /* RF1AIFERR Control Bits */\r
1550 #define LVERR (0x0001u) /* Low Core Voltage Error Flag */\r
1551 #define OPERR (0x0002u) /* Operand Error Flag */\r
1552 #define OUTERR (0x0004u) /* Output data not available Error Flag */\r
1553 #define OPOVERR (0x0008u) /* Operand Overwrite Error Flag */\r
1554 \r
1555 /* RF1AIFERR Control Bits */\r
1556 #define LVERR_L (0x0001u) /* Low Core Voltage Error Flag */\r
1557 #define OPERR_L (0x0002u) /* Operand Error Flag */\r
1558 #define OUTERR_L (0x0004u) /* Output data not available Error Flag */\r
1559 #define OPOVERR_L (0x0008u) /* Operand Overwrite Error Flag */\r
1560 \r
1561 /* RF1AIFERRV Definitions */\r
1562 #define RF1AIFERRV_NONE (0x0000u) /* No Error pending */\r
1563 #define RF1AIFERRV_LVERR (0x0002u) /* Low core voltage error */\r
1564 #define RF1AIFERRV_OPERR (0x0004u) /* Operand Error */\r
1565 #define RF1AIFERRV_OUTERR (0x0006u) /* Output data not available Error */\r
1566 #define RF1AIFERRV_OPOVERR (0x0008u) /* Operand Overwrite Error */\r
1567 \r
1568 /* RF1AIFIV Definitions */\r
1569 #define RF1AIFIV_NONE (0x0000u) /* No Interrupt pending */\r
1570 #define RF1AIFIV_RFERRIFG (0x0002u) /* Radio interface error */\r
1571 #define RF1AIFIV_RFDOUTIFG (0x0004u) /* Radio i/f data out */\r
1572 #define RF1AIFIV_RFSTATIFG (0x0006u) /* Radio i/f status out */\r
1573 #define RF1AIFIV_RFDINIFG (0x0008u) /* Radio i/f data in */\r
1574 #define RF1AIFIV_RFINSTRIFG (0x000Au) /* Radio i/f instruction in */\r
1575 \r
1576 /* RF1AIV Definitions */\r
1577 #define RF1AIV_NONE (0x0000u) /* No Interrupt pending */\r
1578 #define RF1AIV_RFIFG0 (0x0002u) /* RFIFG0 */\r
1579 #define RF1AIV_RFIFG1 (0x0004u) /* RFIFG1 */\r
1580 #define RF1AIV_RFIFG2 (0x0006u) /* RFIFG2 */\r
1581 #define RF1AIV_RFIFG3 (0x0008u) /* RFIFG3 */\r
1582 #define RF1AIV_RFIFG4 (0x000Au) /* RFIFG4 */\r
1583 #define RF1AIV_RFIFG5 (0x000Cu) /* RFIFG5 */\r
1584 #define RF1AIV_RFIFG6 (0x000Eu) /* RFIFG6 */\r
1585 #define RF1AIV_RFIFG7 (0x0010u) /* RFIFG7 */\r
1586 #define RF1AIV_RFIFG8 (0x0012u) /* RFIFG8 */\r
1587 #define RF1AIV_RFIFG9 (0x0014u) /* RFIFG9 */\r
1588 #define RF1AIV_RFIFG10 (0x0016u) /* RFIFG10 */\r
1589 #define RF1AIV_RFIFG11 (0x0018u) /* RFIFG11 */\r
1590 #define RF1AIV_RFIFG12 (0x001Au) /* RFIFG12 */\r
1591 #define RF1AIV_RFIFG13 (0x001Cu) /* RFIFG13 */\r
1592 #define RF1AIV_RFIFG14 (0x001Eu) /* RFIFG14 */\r
1593 #define RF1AIV_RFIFG15 (0x0020u) /* RFIFG15 */\r
1594 \r
1595 // Radio Core Registers\r
1596 #define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */\r
1597 #define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */\r
1598 #define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */\r
1599 #define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */\r
1600 #define SYNC1 0x04 /* SYNC1 - Sync word, high byte */\r
1601 #define SYNC0 0x05 /* SYNC0 - Sync word, low byte */\r
1602 #define PKTLEN 0x06 /* PKTLEN - Packet length */\r
1603 #define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */\r
1604 #define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */\r
1605 #define ADDR 0x09 /* ADDR - Device address */\r
1606 #define CHANNR 0x0A /* CHANNR - Channel number */\r
1607 #define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */\r
1608 #define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */\r
1609 #define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */\r
1610 #define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */\r
1611 #define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */\r
1612 #define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */\r
1613 #define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */\r
1614 #define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */\r
1615 #define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */\r
1616 #define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */\r
1617 #define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */\r
1618 #define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */\r
1619 #define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */\r
1620 #define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */\r
1621 #define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */\r
1622 #define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */\r
1623 #define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */\r
1624 #define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */\r
1625 #define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */\r
1626 #define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */\r
1627 #define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */\r
1628 #define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */\r
1629 #define FREND1 0x21 /* FREND1 - Front end RX configuration */\r
1630 #define FREND0 0x22 /* FREDN0 - Front end TX configuration */\r
1631 #define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */\r
1632 #define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */\r
1633 #define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */\r
1634 #define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */\r
1635 //#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */\r
1636 //#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */\r
1637 #define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */\r
1638 #define PTEST 0x2A /* PTEST - Production test */\r
1639 #define AGCTEST 0x2B /* AGCTEST - AGC test */\r
1640 #define TEST2 0x2C /* TEST2 - Various test settings */\r
1641 #define TEST1 0x2D /* TEST1 - Various test settings */\r
1642 #define TEST0 0x2E /* TEST0 - Various test settings */\r
1643 \r
1644 /* status registers */\r
1645 #define PARTNUM 0x30 /* PARTNUM - Chip ID */\r
1646 #define VERSION 0x31 /* VERSION - Chip ID */\r
1657 \r
1658 /* burst write registers */\r
1659 #define PATABLE 0x3E /* PATABLE - PA control settings table */\r
1660 #define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */\r
1661 #define RXFIFO 0x3F /* RXFIFO - Receive FIFO */\r
1662 \r
1663 /* Radio Core Instructions */\r
1664 /* command strobes */\r
1665 #define RF_SRES 0x30 /* SRES - Reset chip. */\r
1666 #define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */\r
1667 #define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */\r
1668 #define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */\r
1669 #define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */\r
1670 #define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */\r
1671 #define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */\r
1672 //#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */\r
1673 #define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */\r
1674 #define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */\r
1675 #define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */\r
1676 #define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */\r
1677 #define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */\r
1678 #define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */\r
1679 \r
1680 #define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */\r
1681 #define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */\r
1682 \r
1683 /* other radio instr */\r
1684 #define RF_SNGLREGRD 0x80\r
1685 #define RF_SNGLREGWR 0x00\r
1686 #define RF_REGRD 0xC0\r
1687 #define RF_REGWR 0x40\r
1688 #define RF_STATREGRD 0xC0 /* Read single radio core status register */\r
1689 #define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE)\r
1690 #define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE)\r
1691 #define RF_PATABRD (RF_REGRD+PATABLE)\r
1692 #define RF_PATABWR (RF_REGWR+PATABLE)\r
1693 #define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO)\r
1694 #define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO)\r
1695 #define RF_RXFIFORD (RF_REGRD+RXFIFO)\r
1696 #define RF_TXFIFOWR (RF_REGWR+TXFIFO)\r
1697 \r
1698 #endif\r
1699 /*************************************************************\r
1700 * CRC Module\r
1701 *************************************************************/\r
1702 #ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */\r
1703 \r
1704 #define OFS_CRCDI (0x0000u) /* CRC Data In Register */\r
1705 #define OFS_CRCDI_L OFS_CRCDI\r
1706 #define OFS_CRCDI_H OFS_CRCDI+1\r
1707 #define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */\r
1708 #define OFS_CRCDIRB_L OFS_CRCDIRB\r
1709 #define OFS_CRCDIRB_H OFS_CRCDIRB+1\r
1710 #define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */\r
1711 #define OFS_CRCINIRES_L OFS_CRCINIRES\r
1712 #define OFS_CRCINIRES_H OFS_CRCINIRES+1\r
1713 #define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */\r
1714 #define OFS_CRCRESR_L OFS_CRCRESR\r
1715 #define OFS_CRCRESR_H OFS_CRCRESR+1\r
1716 \r
1717 #endif\r
1718 /************************************************************\r
1719 * DAC12\r
1720 ************************************************************/\r
1721 #ifdef __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */\r
1722 \r
1723 #define OFS_DAC12_0CTL0 (0x0000u) /* DAC12_0 Control Register 0 */\r
1724 #define OFS_DAC12_0CTL1 (0x0002u) /* DAC12_0 Control Register 1 */\r
1725 #define OFS_DAC12_0DAT (0x0004u) /* DAC12_0 Data */\r
1726 #define OFS_DAC12_0CALCTL (0x0006u) /* DAC12_0 Calibration Control Register */\r
1727 #define OFS_DAC12_0CALDAT (0x0008u) /* DAC12_0 Calibration Data Register */\r
1728 #define OFS_DAC12_1CTL0 (0x0010u) /* DAC12_1 Control Register 0 */\r
1729 #define OFS_DAC12_1CTL1 (0x0012u) /* DAC12_1 Control Register 1 */\r
1730 #define OFS_DAC12_1DAT (0x0014u) /* DAC12_1 Data */\r
1731 #define OFS_DAC12_1CALCTL (0x0016u) /* DAC12_1 Calibration Control Register */\r
1732 #define OFS_DAC12_1CALDAT (0x0018u) /* DAC12_1 Calibration Data Register */\r
1733 #define OFS_DAC12_IV (0x001Eu) /* DAC12 Interrupt Vector Word */\r
1734 \r
1735 /* DAC12_xCTL0 Control Bits */\r
1736 #define DAC12GRP (0x0001u) /* DAC12 group */\r
1737 #define DAC12ENC (0x0002u) /* DAC12 enable conversion */\r
1738 #define DAC12IFG (0x0004u) /* DAC12 interrupt flag */\r
1739 #define DAC12IE (0x0008u) /* DAC12 interrupt enable */\r
1740 #define DAC12DF (0x0010u) /* DAC12 data format */\r
1741 #define DAC12AMP0 (0x0020u) /* DAC12 amplifier bit 0 */\r
1742 #define DAC12AMP1 (0x0040u) /* DAC12 amplifier bit 1 */\r
1743 #define DAC12AMP2 (0x0080u) /* DAC12 amplifier bit 2 */\r
1744 #define DAC12IR (0x0100u) /* DAC12 input reference and output range */\r
1745 #define DAC12CALON (0x0200u) /* DAC12 calibration */\r
1746 #define DAC12LSEL0 (0x0400u) /* DAC12 load select bit 0 */\r
1747 #define DAC12LSEL1 (0x0800u) /* DAC12 load select bit 1 */\r
1748 #define DAC12RES (0x1000u) /* DAC12 resolution */\r
1749 #define DAC12SREF0 (0x2000u) /* DAC12 reference bit 0 */\r
1750 #define DAC12SREF1 (0x4000u) /* DAC12 reference bit 1 */\r
1751 #define DAC12OPS (0x8000u) /* DAC12 Operation Amp. */\r
1752 \r
1753 #define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */\r
1754 #define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */\r
1755 #define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */\r
1756 #define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */\r
1757 #define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */\r
1758 #define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */\r
1759 #define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */\r
1760 #define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */\r
1761 \r
1762 #define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */\r
1763 #define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */\r
1764 #define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */\r
1765 #define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */\r
1766 \r
1767 #define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */\r
1768 #define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */\r
1769 #define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */\r
1770 #define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */\r
1771 \r
1772 /* DAC12_xCTL1 Control Bits */\r
1773 #define DAC12DFJ (0x0001u) /* DAC12 Data Format Justification */\r
1774 #define DAC12OG (0x0002u) /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */\r
1775 \r
1776 /* DAC12_xCALCTL Control Bits */\r
1777 #define DAC12LOCK (0x0001u) /* DAC12 Calibration Lock */\r
1778 \r
1779 #define DAC12PW (0xA500u) /* DAC12 Calibration Register write Password */\r
1780 \r
1781 /* DACIV Definitions */\r
1782 #define DACIV_NONE (0x0000u) /* No Interrupt pending */\r
1783 #define DACIV_DAC12IFG_0 (0x0002u) /* DAC12IFG_0 */\r
1784 #define DACIV_DAC12IFG_1 (0x0004u) /* DAC12IFG_1 */\r
1785 \r
1786 #endif\r
1787 /************************************************************\r
1788 * DMA_X\r
1789 ************************************************************/\r
1790 #ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */\r
1791 \r
1792 #define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */\r
1793 #define OFS_DMACTL0_L OFS_DMACTL0\r
1794 #define OFS_DMACTL0_H OFS_DMACTL0+1\r
1795 #define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */\r
1796 #define OFS_DMACTL1_L OFS_DMACTL1\r
1797 #define OFS_DMACTL1_H OFS_DMACTL1+1\r
1798 #define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */\r
1799 #define OFS_DMACTL2_L OFS_DMACTL2\r
1800 #define OFS_DMACTL2_H OFS_DMACTL2+1\r
1801 #define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */\r
1802 #define OFS_DMACTL3_L OFS_DMACTL3\r
1803 #define OFS_DMACTL3_H OFS_DMACTL3+1\r
1804 #define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */\r
1805 #define OFS_DMACTL4_L OFS_DMACTL4\r
1806 #define OFS_DMACTL4_H OFS_DMACTL4+1\r
1807 #define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */\r
1808 #define OFS_DMAIV_L OFS_DMAIV\r
1809 #define OFS_DMAIV_H OFS_DMAIV+1\r
1810 \r
1811 #define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */\r
1812 #define OFS_DMA0CTL_L OFS_DMA0CTL\r
1813 #define OFS_DMA0CTL_H OFS_DMA0CTL+1\r
1814 #define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */\r
1815 #define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */\r
1816 #define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */\r
1817 \r
1818 #define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */\r
1819 #define OFS_DMA1CTL_L OFS_DMA1CTL\r
1820 #define OFS_DMA1CTL_H OFS_DMA1CTL+1\r
1821 #define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */\r
1822 #define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */\r
1823 #define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */\r
1824 \r
1825 #define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */\r
1826 #define OFS_DMA2CTL_L OFS_DMA2CTL\r
1827 #define OFS_DMA2CTL_H OFS_DMA2CTL+1\r
1828 #define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */\r
1829 #define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */\r
1830 #define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */\r
1831 \r
1832 /* DMACTL0 Control Bits */\r
1833 #define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
1834 #define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
1835 #define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
1836 #define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
1837 #define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
1838 #define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */\r
1839 #define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */\r
1840 #define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */\r
1841 #define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */\r
1842 #define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */\r
1843 \r
1844 /* DMACTL0 Control Bits */\r
1845 #define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
1846 #define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
1847 #define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
1848 #define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
1849 #define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
1850 \r
1851 /* DMACTL0 Control Bits */\r
1852 #define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */\r
1853 #define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */\r
1854 #define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */\r
1855 #define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */\r
1856 #define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */\r
1857 \r
1858 /* DMACTL01 Control Bits */\r
1859 #define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
1860 #define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
1861 #define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
1862 #define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
1863 #define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
1864 \r
1865 /* DMACTL01 Control Bits */\r
1866 #define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
1867 #define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
1868 #define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
1869 #define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
1870 #define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
1871 \r
1872 /* DMACTL4 Control Bits */\r
1873 #define ENNMI (0x0001u) /* Enable NMI interruption of DMA */\r
1874 #define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */\r
1875 #define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
1876 \r
1877 /* DMACTL4 Control Bits */\r
1878 #define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */\r
1879 #define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */\r
1880 #define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
1881 \r
1882 /* DMAxCTL Control Bits */\r
1883 #define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
1884 #define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */\r
1885 #define DMAIE (0x0004u) /* DMA interrupt enable */\r
1886 #define DMAIFG (0x0008u) /* DMA interrupt flag */\r
1887 #define DMAEN (0x0010u) /* DMA enable */\r
1888 #define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */\r
1889 #define DMASRCBYTE (0x0040u) /* DMA source byte */\r
1890 #define DMADSTBYTE (0x0080u) /* DMA destination byte */\r
1891 #define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */\r
1892 #define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */\r
1893 #define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */\r
1894 #define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */\r
1895 #define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */\r
1896 #define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */\r
1897 #define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */\r
1898 \r
1899 /* DMAxCTL Control Bits */\r
1900 #define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
1901 #define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */\r
1902 #define DMAIE_L (0x0004u) /* DMA interrupt enable */\r
1903 #define DMAIFG_L (0x0008u) /* DMA interrupt flag */\r
1904 #define DMAEN_L (0x0010u) /* DMA enable */\r
1905 #define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */\r
1906 #define DMASRCBYTE_L (0x0040u) /* DMA source byte */\r
1907 #define DMADSTBYTE_L (0x0080u) /* DMA destination byte */\r
1908 \r
1909 /* DMAxCTL Control Bits */\r
1910 #define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */\r
1911 #define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */\r
1912 #define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */\r
1913 #define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */\r
1914 #define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */\r
1915 #define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */\r
1916 #define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */\r
1917 \r
1918 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */\r
1919 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */\r
1920 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */\r
1921 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */\r
1922 \r
1923 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */\r
1924 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */\r
1925 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */\r
1926 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */\r
1927 \r
1928 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */\r
1929 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */\r
1930 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */\r
1931 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */\r
1932 \r
1933 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */\r
1934 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */\r
1935 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */\r
1936 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */\r
1937 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */\r
1938 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */\r
1939 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */\r
1940 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */\r
1941 \r
1942 /* DMAIV Definitions */\r
1943 #define DMAIV_NONE (0x0000u) /* No Interrupt pending */\r
1944 #define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/\r
1945 #define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/\r
1946 #define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/\r
1947 \r
1948 #endif\r
1949 /************************************************************\r
1950 * DMA_X\r
1951 ************************************************************/\r
1952 #ifdef __MSP430_HAS_DMAX_6__ /* Definition to show that Module is available */\r
1953 \r
1954 #define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */\r
1955 #define OFS_DMACTL0_L OFS_DMACTL0\r
1956 #define OFS_DMACTL0_H OFS_DMACTL0+1\r
1957 #define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */\r
1958 #define OFS_DMACTL1_L OFS_DMACTL1\r
1959 #define OFS_DMACTL1_H OFS_DMACTL1+1\r
1960 #define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */\r
1961 #define OFS_DMACTL2_L OFS_DMACTL2\r
1962 #define OFS_DMACTL2_H OFS_DMACTL2+1\r
1963 #define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */\r
1964 #define OFS_DMACTL3_L OFS_DMACTL3\r
1965 #define OFS_DMACTL3_H OFS_DMACTL3+1\r
1966 #define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */\r
1967 #define OFS_DMACTL4_L OFS_DMACTL4\r
1968 #define OFS_DMACTL4_H OFS_DMACTL4+1\r
1969 #define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */\r
1970 #define OFS_DMAIV_L OFS_DMAIV\r
1971 #define OFS_DMAIV_H OFS_DMAIV+1\r
1972 \r
1973 #define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */\r
1974 #define OFS_DMA0CTL_L OFS_DMA0CTL\r
1975 #define OFS_DMA0CTL_H OFS_DMA0CTL+1\r
1976 #define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */\r
1977 #define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */\r
1978 #define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */\r
1979 \r
1980 #define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */\r
1981 #define OFS_DMA1CTL_L OFS_DMA1CTL\r
1982 #define OFS_DMA1CTL_H OFS_DMA1CTL+1\r
1983 #define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */\r
1984 #define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */\r
1985 #define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */\r
1986 \r
1987 #define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */\r
1988 #define OFS_DMA2CTL_L OFS_DMA2CTL\r
1989 #define OFS_DMA2CTL_H OFS_DMA2CTL+1\r
1990 #define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */\r
1991 #define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */\r
1992 #define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */\r
1993 \r
1994 #define OFS_DMA3CTL (0x0040u) /* DMA Channel 3 Control */\r
1995 #define OFS_DMA3CTL_L OFS_DMA3CTL\r
1996 #define OFS_DMA3CTL_H OFS_DMA3CTL+1\r
1997 #define OFS_DMA3SA (0x0042u) /* DMA Channel 3 Source Address */\r
1998 #define OFS_DMA3DA (0x0046u) /* DMA Channel 3 Destination Address */\r
1999 #define OFS_DMA3SZ (0x004Au) /* DMA Channel 3 Transfer Size */\r
2000 \r
2001 #define OFS_DMA4CTL (0x0050u) /* DMA Channel 4 Control */\r
2002 #define OFS_DMA4CTL_L OFS_DMA4CTL\r
2003 #define OFS_DMA4CTL_H OFS_DMA4CTL+1\r
2004 #define OFS_DMA4SA (0x0052u) /* DMA Channel 4 Source Address */\r
2005 #define OFS_DMA4DA (0x0056u) /* DMA Channel 4 Destination Address */\r
2006 #define OFS_DMA4SZ (0x005Au) /* DMA Channel 4 Transfer Size */\r
2007 \r
2008 #define OFS_DMA5CTL (0x0060u) /* DMA Channel 5 Control */\r
2009 #define OFS_DMA5CTL_L OFS_DMA5CTL\r
2010 #define OFS_DMA5CTL_H OFS_DMA5CTL+1\r
2011 #define OFS_DMA5SA (0x0062u) /* DMA Channel 5 Source Address */\r
2012 #define OFS_DMA5DA (0x0066u) /* DMA Channel 5 Destination Address */\r
2013 #define OFS_DMA5SZ (0x006Au) /* DMA Channel 5 Transfer Size */\r
2014 \r
2015 /* DMACTL0 Control Bits */\r
2016 #define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
2017 #define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
2018 #define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
2019 #define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
2020 #define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
2021 #define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */\r
2022 #define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */\r
2023 #define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */\r
2024 #define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */\r
2025 #define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */\r
2026 \r
2027 /* DMACTL0 Control Bits */\r
2028 #define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
2029 #define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
2030 #define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
2031 #define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
2032 #define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
2033 \r
2034 /* DMACTL0 Control Bits */\r
2035 #define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */\r
2036 #define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */\r
2037 #define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */\r
2038 #define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */\r
2039 #define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */\r
2040 \r
2041 /* DMACTL01 Control Bits */\r
2042 #define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
2043 #define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
2044 #define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
2045 #define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
2046 #define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
2047 #define DMA3TSEL0 (0x0100u) /* DMA channel 3 transfer select bit 0 */\r
2048 #define DMA3TSEL1 (0x0200u) /* DMA channel 3 transfer select bit 1 */\r
2049 #define DMA3TSEL2 (0x0400u) /* DMA channel 3 transfer select bit 2 */\r
2050 #define DMA3TSEL3 (0x0800u) /* DMA channel 3 transfer select bit 3 */\r
2051 #define DMA3TSEL4 (0x1000u) /* DMA channel 3 transfer select bit 4 */\r
2052 \r
2053 /* DMACTL01 Control Bits */\r
2054 #define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
2055 #define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
2056 #define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
2057 #define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
2058 #define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
2059 \r
2060 /* DMACTL01 Control Bits */\r
2061 #define DMA3TSEL0_H (0x0001u) /* DMA channel 3 transfer select bit 0 */\r
2062 #define DMA3TSEL1_H (0x0002u) /* DMA channel 3 transfer select bit 1 */\r
2063 #define DMA3TSEL2_H (0x0004u) /* DMA channel 3 transfer select bit 2 */\r
2064 #define DMA3TSEL3_H (0x0008u) /* DMA channel 3 transfer select bit 3 */\r
2065 #define DMA3TSEL4_H (0x0010u) /* DMA channel 3 transfer select bit 4 */\r
2066 \r
2067 /* DMACTL0 Control Bits */\r
2068 #define DMA4TSEL0 (0x0001u) /* DMA channel 4 transfer select bit 0 */\r
2069 #define DMA4TSEL1 (0x0002u) /* DMA channel 4 transfer select bit 1 */\r
2070 #define DMA4TSEL2 (0x0004u) /* DMA channel 4 transfer select bit 2 */\r
2071 #define DMA4TSEL3 (0x0008u) /* DMA channel 4 transfer select bit 3 */\r
2072 #define DMA4TSEL4 (0x0010u) /* DMA channel 4 transfer select bit 4 */\r
2073 #define DMA5TSEL0 (0x0100u) /* DMA channel 5 transfer select bit 0 */\r
2074 #define DMA5TSEL1 (0x0200u) /* DMA channel 5 transfer select bit 1 */\r
2075 #define DMA5TSEL2 (0x0400u) /* DMA channel 5 transfer select bit 2 */\r
2076 #define DMA5TSEL3 (0x0800u) /* DMA channel 5 transfer select bit 3 */\r
2077 #define DMA5TSEL4 (0x1000u) /* DMA channel 5 transfer select bit 4 */\r
2078 \r
2079 /* DMACTL0 Control Bits */\r
2080 #define DMA4TSEL0_L (0x0001u) /* DMA channel 4 transfer select bit 0 */\r
2081 #define DMA4TSEL1_L (0x0002u) /* DMA channel 4 transfer select bit 1 */\r
2082 #define DMA4TSEL2_L (0x0004u) /* DMA channel 4 transfer select bit 2 */\r
2083 #define DMA4TSEL3_L (0x0008u) /* DMA channel 4 transfer select bit 3 */\r
2084 #define DMA4TSEL4_L (0x0010u) /* DMA channel 4 transfer select bit 4 */\r
2085 \r
2086 /* DMACTL0 Control Bits */\r
2087 #define DMA5TSEL0_H (0x0001u) /* DMA channel 5 transfer select bit 0 */\r
2088 #define DMA5TSEL1_H (0x0002u) /* DMA channel 5 transfer select bit 1 */\r
2089 #define DMA5TSEL2_H (0x0004u) /* DMA channel 5 transfer select bit 2 */\r
2090 #define DMA5TSEL3_H (0x0008u) /* DMA channel 5 transfer select bit 3 */\r
2091 #define DMA5TSEL4_H (0x0010u) /* DMA channel 5 transfer select bit 4 */\r
2092 \r
2093 /* DMACTL4 Control Bits */\r
2094 #define ENNMI (0x0001u) /* Enable NMI interruption of DMA */\r
2095 #define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */\r
2096 #define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
2097 \r
2098 /* DMACTL4 Control Bits */\r
2099 #define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */\r
2100 #define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */\r
2101 #define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
2102 \r
2103 /* DMAxCTL Control Bits */\r
2104 #define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
2105 #define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */\r
2106 #define DMAIE (0x0004u) /* DMA interrupt enable */\r
2107 #define DMAIFG (0x0008u) /* DMA interrupt flag */\r
2108 #define DMAEN (0x0010u) /* DMA enable */\r
2109 #define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */\r
2110 #define DMASRCBYTE (0x0040u) /* DMA source byte */\r
2111 #define DMADSTBYTE (0x0080u) /* DMA destination byte */\r
2112 #define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */\r
2113 #define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */\r
2114 #define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */\r
2115 #define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */\r
2116 #define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */\r
2117 #define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */\r
2118 #define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */\r
2119 \r
2120 /* DMAxCTL Control Bits */\r
2121 #define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
2122 #define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */\r
2123 #define DMAIE_L (0x0004u) /* DMA interrupt enable */\r
2124 #define DMAIFG_L (0x0008u) /* DMA interrupt flag */\r
2125 #define DMAEN_L (0x0010u) /* DMA enable */\r
2126 #define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */\r
2127 #define DMASRCBYTE_L (0x0040u) /* DMA source byte */\r
2128 #define DMADSTBYTE_L (0x0080u) /* DMA destination byte */\r
2129 \r
2130 /* DMAxCTL Control Bits */\r
2131 #define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */\r
2132 #define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */\r
2133 #define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */\r
2134 #define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */\r
2135 #define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */\r
2136 #define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */\r
2137 #define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */\r
2138 \r
2139 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */\r
2140 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */\r
2141 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */\r
2142 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */\r
2143 \r
2144 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */\r
2145 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */\r
2146 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */\r
2147 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */\r
2148 \r
2149 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */\r
2150 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */\r
2151 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */\r
2152 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */\r
2153 \r
2154 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */\r
2155 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */\r
2156 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */\r
2157 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */\r
2158 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */\r
2159 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */\r
2160 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */\r
2161 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */\r
2162 \r
2163 /* DMAIV Definitions */\r
2164 #define DMAIV_NONE (0x0000u) /* No Interrupt pending */\r
2165 #define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/\r
2166 #define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/\r
2167 #define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/\r
2168 #define DMAIV_DMA3IFG (0x0008u) /* DMA3IFG*/\r
2169 #define DMAIV_DMA4IFG (0x000Au) /* DMA4IFG*/\r
2170 #define DMAIV_DMA5IFG (0x000Cu) /* DMA5IFG*/\r
2171 \r
2172 #endif\r
2173 /*************************************************************\r
2174 * Flash Memory\r
2175 *************************************************************/\r
2176 #ifdef __MSP430_HAS_FLASH__ /* Definition to show that Module is available */\r
2177 \r
2178 #define OFS_FCTL1 (0x0000u) /* FLASH Control 1 */\r
2179 #define OFS_FCTL1_L OFS_FCTL1\r
2180 #define OFS_FCTL1_H OFS_FCTL1+1\r
2181 //#define FCTL2_O (0x0002u) /* FLASH Control 2 */\r
2182 #define OFS_FCTL3 (0x0004u) /* FLASH Control 3 */\r
2183 #define OFS_FCTL3_L OFS_FCTL3\r
2184 #define OFS_FCTL3_H OFS_FCTL3+1\r
2185 #define OFS_FCTL4 (0x0006u) /* FLASH Control 4 */\r
2186 #define OFS_FCTL4_L OFS_FCTL4\r
2187 #define OFS_FCTL4_H OFS_FCTL4+1\r
2188 \r
2189 #define FRPW (0x9600u) /* Flash password returned by read */\r
2190 #define FWPW (0xA500u) /* Flash password for write */\r
2191 #define FXPW (0x3300u) /* for use with XOR instruction */\r
2192 #define FRKEY (0x9600u) /* (legacy definition) Flash key returned by read */\r
2193 #define FWKEY (0xA500u) /* (legacy definition) Flash key for write */\r
2194 #define FXKEY (0x3300u) /* (legacy definition) for use with XOR instruction */\r
2195 \r
2196 /* FCTL1 Control Bits */\r
2197 //#define RESERVED (0x0001u) /* Reserved */\r
2198 #define ERASE (0x0002u) /* Enable bit for Flash segment erase */\r
2199 #define MERAS (0x0004u) /* Enable bit for Flash mass erase */\r
2200 //#define RESERVED (0x0008u) /* Reserved */\r
2201 //#define RESERVED (0x0010u) /* Reserved */\r
2202 #define SWRT (0x0020u) /* Smart Write enable */\r
2203 #define WRT (0x0040u) /* Enable bit for Flash write */\r
2204 #define BLKWRT (0x0080u) /* Enable bit for Flash segment write */\r
2205 \r
2206 /* FCTL1 Control Bits */\r
2207 //#define RESERVED (0x0001u) /* Reserved */\r
2208 #define ERASE_L (0x0002u) /* Enable bit for Flash segment erase */\r
2209 #define MERAS_L (0x0004u) /* Enable bit for Flash mass erase */\r
2210 //#define RESERVED (0x0008u) /* Reserved */\r
2211 //#define RESERVED (0x0010u) /* Reserved */\r
2212 #define SWRT_L (0x0020u) /* Smart Write enable */\r
2213 #define WRT_L (0x0040u) /* Enable bit for Flash write */\r
2214 #define BLKWRT_L (0x0080u) /* Enable bit for Flash segment write */\r
2215 \r
2216 /* FCTL3 Control Bits */\r
2217 #define BUSY (0x0001u) /* Flash busy: 1 */\r
2218 #define KEYV (0x0002u) /* Flash Key violation flag */\r
2219 #define ACCVIFG (0x0004u) /* Flash Access violation flag */\r
2220 #define WAIT (0x0008u) /* Wait flag for segment write */\r
2221 #define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */\r
2222 #define EMEX (0x0020u) /* Flash Emergency Exit */\r
2223 #define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */\r
2224 //#define RESERVED (0x0080u) /* Reserved */\r
2225 \r
2226 /* FCTL3 Control Bits */\r
2227 #define BUSY_L (0x0001u) /* Flash busy: 1 */\r
2228 #define KEYV_L (0x0002u) /* Flash Key violation flag */\r
2229 #define ACCVIFG_L (0x0004u) /* Flash Access violation flag */\r
2230 #define WAIT_L (0x0008u) /* Wait flag for segment write */\r
2231 #define LOCK_L (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */\r
2232 #define EMEX_L (0x0020u) /* Flash Emergency Exit */\r
2233 #define LOCKA_L (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */\r
2234 //#define RESERVED (0x0080u) /* Reserved */\r
2235 \r
2236 /* FCTL4 Control Bits */\r
2237 #define VPE (0x0001u) /* Voltage Changed during Program Error Flag */\r
2238 #define MGR0 (0x0010u) /* Marginal read 0 mode. */\r
2239 #define MGR1 (0x0020u) /* Marginal read 1 mode. */\r
2240 #define LOCKINFO (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */\r
2241 \r
2242 /* FCTL4 Control Bits */\r
2243 #define VPE_L (0x0001u) /* Voltage Changed during Program Error Flag */\r
2244 #define MGR0_L (0x0010u) /* Marginal read 0 mode. */\r
2245 #define MGR1_L (0x0020u) /* Marginal read 1 mode. */\r
2246 #define LOCKINFO_L (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */\r
2247 \r
2248 #endif\r
2249 /************************************************************\r
2250 * LCD_B\r
2251 ************************************************************/\r
2252 #ifdef __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */\r
2253 \r
2254 #define OFS_LCDBCTL0 (0x0000u) /* LCD_B Control Register 0 */\r
2255 #define OFS_LCDBCTL0_L OFS_LCDBCTL0\r
2256 #define OFS_LCDBCTL0_H OFS_LCDBCTL0+1\r
2257 #define OFS_LCDBCTL1 (0x0002u) /* LCD_B Control Register 1 */\r
2258 #define OFS_LCDBCTL1_L OFS_LCDBCTL1\r
2259 #define OFS_LCDBCTL1_H OFS_LCDBCTL1+1\r
2260 #define OFS_LCDBBLKCTL (0x0004u) /* LCD_B blinking control register */\r
2261 #define OFS_LCDBBLKCTL_L OFS_LCDBBLKCTL\r
2262 #define OFS_LCDBBLKCTL_H OFS_LCDBBLKCTL+1\r
2263 #define OFS_LCDBMEMCTL (0x0006u) /* LCD_B memory control register */\r
2264 #define OFS_LCDBMEMCTL_L OFS_LCDBMEMCTL\r
2265 #define OFS_LCDBMEMCTL_H OFS_LCDBMEMCTL+1\r
2266 #define OFS_LCDBVCTL (0x0008u) /* LCD_B Voltage Control Register */\r
2267 #define OFS_LCDBVCTL_L OFS_LCDBVCTL\r
2268 #define OFS_LCDBVCTL_H OFS_LCDBVCTL+1\r
2269 #define OFS_LCDBPCTL0 (0x000Au) /* LCD_B Port Control Register 0 */\r
2270 #define OFS_LCDBPCTL0_L OFS_LCDBPCTL0\r
2271 #define OFS_LCDBPCTL0_H OFS_LCDBPCTL0+1\r
2272 #define OFS_LCDBPCTL1 (0x000Cu) /* LCD_B Port Control Register 1 */\r
2273 #define OFS_LCDBPCTL1_L OFS_LCDBPCTL1\r
2274 #define OFS_LCDBPCTL1_H OFS_LCDBPCTL1+1\r
2275 #define OFS_LCDBPCTL2 (0x000Eu) /* LCD_B Port Control Register 2 */\r
2276 #define OFS_LCDBPCTL2_L OFS_LCDBPCTL2\r
2277 #define OFS_LCDBPCTL2_H OFS_LCDBPCTL2+1\r
2278 #define OFS_LCDBPCTL3 (0x0010u) /* LCD_B Port Control Register 3 */\r
2279 #define OFS_LCDBPCTL3_L OFS_LCDBPCTL3\r
2280 #define OFS_LCDBPCTL3_H OFS_LCDBPCTL3+1\r
2281 #define OFS_LCDBCPCTL (0x0012u) /* LCD_B Charge Pump Control Register 3 */\r
2282 #define OFS_LCDBCPCTL_L OFS_LCDBCPCTL\r
2283 #define OFS_LCDBCPCTL_H OFS_LCDBCPCTL+1\r
2284 #define OFS_LCDBIV (0x001Eu) /* LCD_B Interrupt Vector Register */\r
2285 \r
2286 // LCDBCTL0\r
2287 #define LCDON (0x0001u) /* LCD_B LCD On */\r
2288 #define LCDSON (0x0004u) /* LCD_B LCD Segments On */\r
2289 #define LCDMX0 (0x0008u) /* LCD_B Mux Rate Bit: 0 */\r
2290 #define LCDMX1 (0x0010u) /* LCD_B Mux Rate Bit: 1 */\r
2291 //#define RESERVED (0x0020u) /* LCD_B RESERVED */\r
2292 //#define RESERVED (0x0040u) /* LCD_B RESERVED */\r
2293 #define LCDSSEL (0x0080u) /* LCD_B Clock Select */\r
2294 #define LCDPRE0 (0x0100u) /* LCD_B LCD frequency pre-scaler Bit: 0 */\r
2295 #define LCDPRE1 (0x0200u) /* LCD_B LCD frequency pre-scaler Bit: 1 */\r
2296 #define LCDPRE2 (0x0400u) /* LCD_B LCD frequency pre-scaler Bit: 2 */\r
2297 #define LCDDIV0 (0x0800u) /* LCD_B LCD frequency divider Bit: 0 */\r
2298 #define LCDDIV1 (0x1000u) /* LCD_B LCD frequency divider Bit: 1 */\r
2299 #define LCDDIV2 (0x2000u) /* LCD_B LCD frequency divider Bit: 2 */\r
2300 #define LCDDIV3 (0x4000u) /* LCD_B LCD frequency divider Bit: 3 */\r
2301 #define LCDDIV4 (0x8000u) /* LCD_B LCD frequency divider Bit: 4 */\r
2302 \r
2303 // LCDBCTL0\r
2304 #define LCDON_L (0x0001u) /* LCD_B LCD On */\r
2305 #define LCDSON_L (0x0004u) /* LCD_B LCD Segments On */\r
2306 #define LCDMX0_L (0x0008u) /* LCD_B Mux Rate Bit: 0 */\r
2307 #define LCDMX1_L (0x0010u) /* LCD_B Mux Rate Bit: 1 */\r
2308 //#define RESERVED (0x0020u) /* LCD_B RESERVED */\r
2309 //#define RESERVED (0x0040u) /* LCD_B RESERVED */\r
2310 #define LCDSSEL_L (0x0080u) /* LCD_B Clock Select */\r
2311 \r
2312 // LCDBCTL0\r
2313 //#define RESERVED (0x0020u) /* LCD_B RESERVED */\r
2314 //#define RESERVED (0x0040u) /* LCD_B RESERVED */\r
2315 #define LCDPRE0_H (0x0001u) /* LCD_B LCD frequency pre-scaler Bit: 0 */\r
2316 #define LCDPRE1_H (0x0002u) /* LCD_B LCD frequency pre-scaler Bit: 1 */\r
2317 #define LCDPRE2_H (0x0004u) /* LCD_B LCD frequency pre-scaler Bit: 2 */\r
2318 #define LCDDIV0_H (0x0008u) /* LCD_B LCD frequency divider Bit: 0 */\r
2319 #define LCDDIV1_H (0x0010u) /* LCD_B LCD frequency divider Bit: 1 */\r
2320 #define LCDDIV2_H (0x0020u) /* LCD_B LCD frequency divider Bit: 2 */\r
2321 #define LCDDIV3_H (0x0040u) /* LCD_B LCD frequency divider Bit: 3 */\r
2322 #define LCDDIV4_H (0x0080u) /* LCD_B LCD frequency divider Bit: 4 */\r
2323 \r
2324 #define LCDPRE_0 (0x0000u) /* LCD_B LCD frequency pre-scaler: /1 */\r
2325 #define LCDPRE_1 (0x0100u) /* LCD_B LCD frequency pre-scaler: /2 */\r
2326 #define LCDPRE_2 (0x0200u) /* LCD_B LCD frequency pre-scaler: /4 */\r
2327 #define LCDPRE_3 (0x0300u) /* LCD_B LCD frequency pre-scaler: /8 */\r
2328 #define LCDPRE_4 (0x0400u) /* LCD_B LCD frequency pre-scaler: /16 */\r
2329 #define LCDPRE_5 (0x0500u) /* LCD_B LCD frequency pre-scaler: /32 */\r
2330 #define LCDPRE__1 (0x0000u) /* LCD_B LCD frequency pre-scaler: /1 */\r
2331 #define LCDPRE__2 (0x0100u) /* LCD_B LCD frequency pre-scaler: /2 */\r
2332 #define LCDPRE__4 (0x0200u) /* LCD_B LCD frequency pre-scaler: /4 */\r
2333 #define LCDPRE__8 (0x0300u) /* LCD_B LCD frequency pre-scaler: /8 */\r
2334 #define LCDPRE__16 (0x0400u) /* LCD_B LCD frequency pre-scaler: /16 */\r
2335 #define LCDPRE__32 (0x0500u) /* LCD_B LCD frequency pre-scaler: /32 */\r
2336 \r
2337 #define LCDDIV_0 (0x0000u) /* LCD_B LCD frequency divider: /1 */\r
2338 #define LCDDIV_1 (0x0800u) /* LCD_B LCD frequency divider: /2 */\r
2339 #define LCDDIV_2 (0x1000u) /* LCD_B LCD frequency divider: /3 */\r
2340 #define LCDDIV_3 (0x1800u) /* LCD_B LCD frequency divider: /4 */\r
2341 #define LCDDIV_4 (0x2000u) /* LCD_B LCD frequency divider: /5 */\r
2342 #define LCDDIV_5 (0x2800u) /* LCD_B LCD frequency divider: /6 */\r
2343 #define LCDDIV_6 (0x3000u) /* LCD_B LCD frequency divider: /7 */\r
2344 #define LCDDIV_7 (0x3800u) /* LCD_B LCD frequency divider: /8 */\r
2345 #define LCDDIV_8 (0x4000u) /* LCD_B LCD frequency divider: /9 */\r
2346 #define LCDDIV_9 (0x4800u) /* LCD_B LCD frequency divider: /10 */\r
2347 #define LCDDIV_10 (0x5000u) /* LCD_B LCD frequency divider: /11 */\r
2348 #define LCDDIV_11 (0x5800u) /* LCD_B LCD frequency divider: /12 */\r
2349 #define LCDDIV_12 (0x6000u) /* LCD_B LCD frequency divider: /13 */\r
2350 #define LCDDIV_13 (0x6800u) /* LCD_B LCD frequency divider: /14 */\r
2351 #define LCDDIV_14 (0x7000u) /* LCD_B LCD frequency divider: /15 */\r
2352 #define LCDDIV_15 (0x7800u) /* LCD_B LCD frequency divider: /16 */\r
2353 #define LCDDIV_16 (0x8000u) /* LCD_B LCD frequency divider: /17 */\r
2354 #define LCDDIV_17 (0x8800u) /* LCD_B LCD frequency divider: /18 */\r
2355 #define LCDDIV_18 (0x9000u) /* LCD_B LCD frequency divider: /19 */\r
2356 #define LCDDIV_19 (0x9800u) /* LCD_B LCD frequency divider: /20 */\r
2357 #define LCDDIV_20 (0xA000u) /* LCD_B LCD frequency divider: /21 */\r
2358 #define LCDDIV_21 (0xA800u) /* LCD_B LCD frequency divider: /22 */\r
2359 #define LCDDIV_22 (0xB000u) /* LCD_B LCD frequency divider: /23 */\r
2360 #define LCDDIV_23 (0xB800u) /* LCD_B LCD frequency divider: /24 */\r
2361 #define LCDDIV_24 (0xC000u) /* LCD_B LCD frequency divider: /25 */\r
2362 #define LCDDIV_25 (0xC800u) /* LCD_B LCD frequency divider: /26 */\r
2363 #define LCDDIV_26 (0xD000u) /* LCD_B LCD frequency divider: /27 */\r
2364 #define LCDDIV_27 (0xD800u) /* LCD_B LCD frequency divider: /28 */\r
2365 #define LCDDIV_28 (0xE000u) /* LCD_B LCD frequency divider: /29 */\r
2366 #define LCDDIV_29 (0xE800u) /* LCD_B LCD frequency divider: /30 */\r
2367 #define LCDDIV_30 (0xF000u) /* LCD_B LCD frequency divider: /31 */\r
2368 #define LCDDIV_31 (0xF800u) /* LCD_B LCD frequency divider: /32 */\r
2369 #define LCDDIV__1 (0x0000u) /* LCD_B LCD frequency divider: /1 */\r
2370 #define LCDDIV__2 (0x0800u) /* LCD_B LCD frequency divider: /2 */\r
2371 #define LCDDIV__3 (0x1000u) /* LCD_B LCD frequency divider: /3 */\r
2372 #define LCDDIV__4 (0x1800u) /* LCD_B LCD frequency divider: /4 */\r
2373 #define LCDDIV__5 (0x2000u) /* LCD_B LCD frequency divider: /5 */\r
2374 #define LCDDIV__6 (0x2800u) /* LCD_B LCD frequency divider: /6 */\r
2375 #define LCDDIV__7 (0x3000u) /* LCD_B LCD frequency divider: /7 */\r
2376 #define LCDDIV__8 (0x3800u) /* LCD_B LCD frequency divider: /8 */\r
2377 #define LCDDIV__9 (0x4000u) /* LCD_B LCD frequency divider: /9 */\r
2378 #define LCDDIV__10 (0x4800u) /* LCD_B LCD frequency divider: /10 */\r
2379 #define LCDDIV__11 (0x5000u) /* LCD_B LCD frequency divider: /11 */\r
2380 #define LCDDIV__12 (0x5800u) /* LCD_B LCD frequency divider: /12 */\r
2381 #define LCDDIV__13 (0x6000u) /* LCD_B LCD frequency divider: /13 */\r
2382 #define LCDDIV__14 (0x6800u) /* LCD_B LCD frequency divider: /14 */\r
2383 #define LCDDIV__15 (0x7000u) /* LCD_B LCD frequency divider: /15 */\r
2384 #define LCDDIV__16 (0x7800u) /* LCD_B LCD frequency divider: /16 */\r
2385 #define LCDDIV__17 (0x8000u) /* LCD_B LCD frequency divider: /17 */\r
2386 #define LCDDIV__18 (0x8800u) /* LCD_B LCD frequency divider: /18 */\r
2387 #define LCDDIV__19 (0x9000u) /* LCD_B LCD frequency divider: /19 */\r
2388 #define LCDDIV__20 (0x9800u) /* LCD_B LCD frequency divider: /20 */\r
2389 #define LCDDIV__21 (0xA000u) /* LCD_B LCD frequency divider: /21 */\r
2390 #define LCDDIV__22 (0xA800u) /* LCD_B LCD frequency divider: /22 */\r
2391 #define LCDDIV__23 (0xB000u) /* LCD_B LCD frequency divider: /23 */\r
2392 #define LCDDIV__24 (0xB800u) /* LCD_B LCD frequency divider: /24 */\r
2393 #define LCDDIV__25 (0xC000u) /* LCD_B LCD frequency divider: /25 */\r
2394 #define LCDDIV__26 (0xC800u) /* LCD_B LCD frequency divider: /26 */\r
2395 #define LCDDIV__27 (0xD000u) /* LCD_B LCD frequency divider: /27 */\r
2396 #define LCDDIV__28 (0xD800u) /* LCD_B LCD frequency divider: /28 */\r
2397 #define LCDDIV__29 (0xE000u) /* LCD_B LCD frequency divider: /29 */\r
2398 #define LCDDIV__30 (0xE800u) /* LCD_B LCD frequency divider: /30 */\r
2399 #define LCDDIV__31 (0xF000u) /* LCD_B LCD frequency divider: /31 */\r
2400 #define LCDDIV__32 (0xF800u) /* LCD_B LCD frequency divider: /32 */\r
2401 \r
2402 /* Display modes coded with Bits 2-4 */\r
2403 #define LCDSTATIC (LCDSON)\r
2404 #define LCD2MUX (LCDMX0+LCDSON)\r
2405 #define LCD3MUX (LCDMX1+LCDSON)\r
2406 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)\r
2407 \r
2408 // LCDBCTL1\r
2409 #define LCDFRMIFG (0x0001u) /* LCD_B LCD frame interrupt flag */\r
2410 #define LCDBLKOFFIFG (0x0002u) /* LCD_B LCD blinking off interrupt flag, */\r
2411 #define LCDBLKONIFG (0x0004u) /* LCD_B LCD blinking on interrupt flag, */\r
2412 #define LCDNOCAPIFG (0x0008u) /* LCD_B No cpacitance connected interrupt flag */\r
2413 #define LCDFRMIE (0x0100u) /* LCD_B LCD frame interrupt enable */\r
2414 #define LCDBLKOFFIE (0x0200u) /* LCD_B LCD blinking off interrupt flag, */\r
2415 #define LCDBLKONIE (0x0400u) /* LCD_B LCD blinking on interrupt flag, */\r
2416 #define LCDNOCAPIE (0x0800u) /* LCD_B No cpacitance connected interrupt enable */\r
2417 \r
2418 // LCDBCTL1\r
2419 #define LCDFRMIFG_L (0x0001u) /* LCD_B LCD frame interrupt flag */\r
2420 #define LCDBLKOFFIFG_L (0x0002u) /* LCD_B LCD blinking off interrupt flag, */\r
2421 #define LCDBLKONIFG_L (0x0004u) /* LCD_B LCD blinking on interrupt flag, */\r
2422 #define LCDNOCAPIFG_L (0x0008u) /* LCD_B No cpacitance connected interrupt flag */\r
2423 \r
2424 // LCDBCTL1\r
2425 #define LCDFRMIE_H (0x0001u) /* LCD_B LCD frame interrupt enable */\r
2426 #define LCDBLKOFFIE_H (0x0002u) /* LCD_B LCD blinking off interrupt flag, */\r
2427 #define LCDBLKONIE_H (0x0004u) /* LCD_B LCD blinking on interrupt flag, */\r
2428 #define LCDNOCAPIE_H (0x0008u) /* LCD_B No cpacitance connected interrupt enable */\r
2429 \r
2430 // LCDBBLKCTL\r
2431 #define LCDBLKMOD0 (0x0001u) /* LCD_B Blinking mode Bit: 0 */\r
2432 #define LCDBLKMOD1 (0x0002u) /* LCD_B Blinking mode Bit: 1 */\r
2433 #define LCDBLKPRE0 (0x0004u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */\r
2434 #define LCDBLKPRE1 (0x0008u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */\r
2435 #define LCDBLKPRE2 (0x0010u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */\r
2436 #define LCDBLKDIV0 (0x0020u) /* LCD_B Clock divider for blinking frequency Bit: 0 */\r
2437 #define LCDBLKDIV1 (0x0040u) /* LCD_B Clock divider for blinking frequency Bit: 1 */\r
2438 #define LCDBLKDIV2 (0x0080u) /* LCD_B Clock divider for blinking frequency Bit: 2 */\r
2439 \r
2440 // LCDBBLKCTL\r
2441 #define LCDBLKMOD0_L (0x0001u) /* LCD_B Blinking mode Bit: 0 */\r
2442 #define LCDBLKMOD1_L (0x0002u) /* LCD_B Blinking mode Bit: 1 */\r
2443 #define LCDBLKPRE0_L (0x0004u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */\r
2444 #define LCDBLKPRE1_L (0x0008u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */\r
2445 #define LCDBLKPRE2_L (0x0010u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */\r
2446 #define LCDBLKDIV0_L (0x0020u) /* LCD_B Clock divider for blinking frequency Bit: 0 */\r
2447 #define LCDBLKDIV1_L (0x0040u) /* LCD_B Clock divider for blinking frequency Bit: 1 */\r
2448 #define LCDBLKDIV2_L (0x0080u) /* LCD_B Clock divider for blinking frequency Bit: 2 */\r
2449 \r
2450 #define LCDBLKMOD_0 (0x0000u) /* LCD_B Blinking mode: Off */\r
2451 #define LCDBLKMOD_1 (0x0001u) /* LCD_B Blinking mode: Individual */\r
2452 #define LCDBLKMOD_2 (0x0002u) /* LCD_B Blinking mode: All */\r
2453 #define LCDBLKMOD_3 (0x0003u) /* LCD_B Blinking mode: Switching */\r
2454 \r
2455 // LCDBMEMCTL\r
2456 #define LCDDISP (0x0001u) /* LCD_B LCD memory registers for display */\r
2457 #define LCDCLRM (0x0002u) /* LCD_B Clear LCD memory */\r
2458 #define LCDCLRBM (0x0004u) /* LCD_B Clear LCD blinking memory */\r
2459 \r
2460 // LCDBMEMCTL\r
2461 #define LCDDISP_L (0x0001u) /* LCD_B LCD memory registers for display */\r
2462 #define LCDCLRM_L (0x0002u) /* LCD_B Clear LCD memory */\r
2463 #define LCDCLRBM_L (0x0004u) /* LCD_B Clear LCD blinking memory */\r
2464 \r
2465 // LCDBVCTL\r
2466 #define LCD2B (0x0001u) /* Selects 1/2 bias. */\r
2467 #define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
2468 #define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
2469 #define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
2470 #define VLCDEXT (0x0010u) /* Select external source for VLCD. */\r
2471 #define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */\r
2472 #define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */\r
2473 #define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
2474 #define VLCD0 (0x0200u) /* VLCD select: 0 */\r
2475 #define VLCD1 (0x0400u) /* VLCD select: 1 */\r
2476 #define VLCD2 (0x0800u) /* VLCD select: 2 */\r
2477 #define VLCD3 (0x1000u) /* VLCD select: 3 */\r
2478 \r
2479 // LCDBVCTL\r
2480 #define LCD2B_L (0x0001u) /* Selects 1/2 bias. */\r
2481 #define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
2482 #define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
2483 #define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
2484 #define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */\r
2485 #define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */\r
2486 #define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */\r
2487 #define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
2488 \r
2489 // LCDBVCTL\r
2490 #define VLCD0_H (0x0002u) /* VLCD select: 0 */\r
2491 #define VLCD1_H (0x0004u) /* VLCD select: 1 */\r
2492 #define VLCD2_H (0x0008u) /* VLCD select: 2 */\r
2493 #define VLCD3_H (0x0010u) /* VLCD select: 3 */\r
2494 \r
2495 /* Reference voltage source select for the regulated charge pump */\r
2496 #define VLCDREF_0 (0<<1) /* Internal */\r
2497 #define VLCDREF_1 (1<<1) /* External */\r
2498 #define VLCDREF_2 (2<<1) /* Reserved */\r
2499 #define VLCDREF_3 (3<<1) /* Reserved */\r
2500 \r
2501 /* Charge pump voltage selections */\r
2502 #define VLCD_0 (0<<9) /* Charge pump disabled */\r
2503 #define VLCD_1 (1<<9) /* VLCD = 2.60V */\r
2504 #define VLCD_2 (2<<9) /* VLCD = 2.66V */\r
2505 #define VLCD_3 (3<<9) /* VLCD = 2.72V */\r
2506 #define VLCD_4 (4<<9) /* VLCD = 2.78V */\r
2507 #define VLCD_5 (5<<9) /* VLCD = 2.84V */\r
2508 #define VLCD_6 (6<<9) /* VLCD = 2.90V */\r
2509 #define VLCD_7 (7<<9) /* VLCD = 2.96V */\r
2510 #define VLCD_8 (8<<9) /* VLCD = 3.02V */\r
2511 #define VLCD_9 (9<<9) /* VLCD = 3.08V */\r
2512 #define VLCD_10 (10<<9) /* VLCD = 3.14V */\r
2513 #define VLCD_11 (11<<9) /* VLCD = 3.20V */\r
2514 #define VLCD_12 (12<<9) /* VLCD = 3.26V */\r
2515 #define VLCD_13 (13<<9) /* VLCD = 3.32V */\r
2516 #define VLCD_14 (14<<9) /* VLCD = 3.38V */\r
2517 #define VLCD_15 (15<<9) /* VLCD = 3.44V */\r
2518 \r
2519 #define VLCD_DISABLED (0<<9) /* Charge pump disabled */\r
2520 #define VLCD_2_60 (1<<9) /* VLCD = 2.60V */\r
2521 #define VLCD_2_66 (2<<9) /* VLCD = 2.66V */\r
2522 #define VLCD_2_72 (3<<9) /* VLCD = 2.72V */\r
2523 #define VLCD_2_78 (4<<9) /* VLCD = 2.78V */\r
2524 #define VLCD_2_84 (5<<9) /* VLCD = 2.84V */\r
2525 #define VLCD_2_90 (6<<9) /* VLCD = 2.90V */\r
2526 #define VLCD_2_96 (7<<9) /* VLCD = 2.96V */\r
2527 #define VLCD_3_02 (8<<9) /* VLCD = 3.02V */\r
2528 #define VLCD_3_08 (9<<9) /* VLCD = 3.08V */\r
2529 #define VLCD_3_14 (10<<9) /* VLCD = 3.14V */\r
2530 #define VLCD_3_20 (11<<9) /* VLCD = 3.20V */\r
2531 #define VLCD_3_26 (12<<9) /* VLCD = 3.26V */\r
2532 #define VLCD_3_32 (13<<9) /* VLCD = 3.32V */\r
2533 #define VLCD_3_38 (14<<9) /* VLCD = 3.38V */\r
2534 #define VLCD_3_44 (15<<9) /* VLCD = 3.44V */\r
2535 \r
2536 // LCDBPCTL0\r
2537 #define LCDS0 (0x0001u) /* LCD Segment 0 enable. */\r
2538 #define LCDS1 (0x0002u) /* LCD Segment 1 enable. */\r
2539 #define LCDS2 (0x0004u) /* LCD Segment 2 enable. */\r
2540 #define LCDS3 (0x0008u) /* LCD Segment 3 enable. */\r
2541 #define LCDS4 (0x0010u) /* LCD Segment 4 enable. */\r
2542 #define LCDS5 (0x0020u) /* LCD Segment 5 enable. */\r
2543 #define LCDS6 (0x0040u) /* LCD Segment 6 enable. */\r
2544 #define LCDS7 (0x0080u) /* LCD Segment 7 enable. */\r
2545 #define LCDS8 (0x0100u) /* LCD Segment 8 enable. */\r
2546 #define LCDS9 (0x0200u) /* LCD Segment 9 enable. */\r
2547 #define LCDS10 (0x0400u) /* LCD Segment 10 enable. */\r
2548 #define LCDS11 (0x0800u) /* LCD Segment 11 enable. */\r
2549 #define LCDS12 (0x1000u) /* LCD Segment 12 enable. */\r
2550 #define LCDS13 (0x2000u) /* LCD Segment 13 enable. */\r
2551 #define LCDS14 (0x4000u) /* LCD Segment 14 enable. */\r
2552 #define LCDS15 (0x8000u) /* LCD Segment 15 enable. */\r
2553 \r
2554 // LCDBPCTL0\r
2555 #define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */\r
2556 #define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */\r
2557 #define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */\r
2558 #define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */\r
2559 #define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */\r
2560 #define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */\r
2561 #define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */\r
2562 #define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */\r
2563 \r
2564 // LCDBPCTL0\r
2565 #define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */\r
2566 #define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */\r
2567 #define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */\r
2568 #define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */\r
2569 #define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */\r
2570 #define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */\r
2571 #define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */\r
2572 #define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */\r
2573 \r
2574 // LCDBPCTL1\r
2575 #define LCDS16 (0x0001u) /* LCD Segment 16 enable. */\r
2576 #define LCDS17 (0x0002u) /* LCD Segment 17 enable. */\r
2577 #define LCDS18 (0x0004u) /* LCD Segment 18 enable. */\r
2578 #define LCDS19 (0x0008u) /* LCD Segment 19 enable. */\r
2579 #define LCDS20 (0x0010u) /* LCD Segment 20 enable. */\r
2580 #define LCDS21 (0x0020u) /* LCD Segment 21 enable. */\r
2581 #define LCDS22 (0x0040u) /* LCD Segment 22 enable. */\r
2582 #define LCDS23 (0x0080u) /* LCD Segment 23 enable. */\r
2583 #define LCDS24 (0x0100u) /* LCD Segment 24 enable. */\r
2584 #define LCDS25 (0x0200u) /* LCD Segment 25 enable. */\r
2585 #define LCDS26 (0x0400u) /* LCD Segment 26 enable. */\r
2586 #define LCDS27 (0x0800u) /* LCD Segment 27 enable. */\r
2587 #define LCDS28 (0x1000u) /* LCD Segment 28 enable. */\r
2588 #define LCDS29 (0x2000u) /* LCD Segment 29 enable. */\r
2589 #define LCDS30 (0x4000u) /* LCD Segment 30 enable. */\r
2590 #define LCDS31 (0x8000u) /* LCD Segment 31 enable. */\r
2591 \r
2592 // LCDBPCTL1\r
2593 #define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */\r
2594 #define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */\r
2595 #define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */\r
2596 #define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */\r
2597 #define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */\r
2598 #define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */\r
2599 #define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */\r
2600 #define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */\r
2601 \r
2602 // LCDBPCTL1\r
2603 #define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */\r
2604 #define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */\r
2605 #define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */\r
2606 #define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */\r
2607 #define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */\r
2608 #define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */\r
2609 #define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */\r
2610 #define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */\r
2611 \r
2612 // LCDBPCTL2\r
2613 #define LCDS32 (0x0001u) /* LCD Segment 32 enable. */\r
2614 #define LCDS33 (0x0002u) /* LCD Segment 33 enable. */\r
2615 #define LCDS34 (0x0004u) /* LCD Segment 34 enable. */\r
2616 #define LCDS35 (0x0008u) /* LCD Segment 35 enable. */\r
2617 #define LCDS36 (0x0010u) /* LCD Segment 36 enable. */\r
2618 #define LCDS37 (0x0020u) /* LCD Segment 37 enable. */\r
2619 #define LCDS38 (0x0040u) /* LCD Segment 38 enable. */\r
2620 #define LCDS39 (0x0080u) /* LCD Segment 39 enable. */\r
2621 #define LCDS40 (0x0100u) /* LCD Segment 40 enable. */\r
2622 #define LCDS41 (0x0200u) /* LCD Segment 41 enable. */\r
2623 #define LCDS42 (0x0400u) /* LCD Segment 42 enable. */\r
2624 #define LCDS43 (0x0800u) /* LCD Segment 43 enable. */\r
2625 #define LCDS44 (0x1000u) /* LCD Segment 44 enable. */\r
2626 #define LCDS45 (0x2000u) /* LCD Segment 45 enable. */\r
2627 #define LCDS46 (0x4000u) /* LCD Segment 46 enable. */\r
2628 #define LCDS47 (0x8000u) /* LCD Segment 47 enable. */\r
2629 \r
2630 // LCDBPCTL2\r
2631 #define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */\r
2632 #define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */\r
2633 #define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */\r
2634 #define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */\r
2635 #define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */\r
2636 #define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */\r
2637 #define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */\r
2638 #define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */\r
2639 \r
2640 // LCDBPCTL2\r
2641 #define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */\r
2642 #define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */\r
2643 #define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */\r
2644 #define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */\r
2645 #define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */\r
2646 #define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */\r
2647 #define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */\r
2648 #define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */\r
2649 \r
2650 // LCDBPCTL3\r
2651 #define LCDS48 (0x0001u) /* LCD Segment 48 enable. */\r
2652 #define LCDS49 (0x0002u) /* LCD Segment 49 enable. */\r
2653 #define LCDS50 (0x0004u) /* LCD Segment 50 enable. */\r
2654 \r
2655 // LCDBPCTL3\r
2656 #define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */\r
2657 #define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */\r
2658 #define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */\r
2659 \r
2660 // LCDBCPCTL\r
2661 #define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */\r
2662 #define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */\r
2663 #define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */\r
2664 #define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */\r
2665 #define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */\r
2666 #define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */\r
2667 #define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */\r
2668 #define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */\r
2669 #define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */\r
2670 \r
2671 // LCDBCPCTL\r
2672 #define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */\r
2673 #define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */\r
2674 #define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */\r
2675 #define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */\r
2676 #define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */\r
2677 #define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */\r
2678 #define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */\r
2679 #define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */\r
2680 \r
2681 // LCDBCPCTL\r
2682 #define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */\r
2683 \r
2684 #define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */\r
2685 #define LCDMEM_ LCDM1 /* LCD Memory */\r
2686 #ifndef __IAR_SYSTEMS_ICC__\r
2687 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */\r
2688 #else\r
2689 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */\r
2690 #endif\r
2691 #define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */\r
2692 #define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */\r
2693 #define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */\r
2694 #define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */\r
2695 #define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */\r
2696 #define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */\r
2697 #define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */\r
2698 #define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */\r
2699 #define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */\r
2700 #define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */\r
2701 #define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */\r
2702 #define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */\r
2703 #define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */\r
2704 #define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */\r
2705 #define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */\r
2706 #define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */\r
2707 #define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */\r
2708 #define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */\r
2709 #define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */\r
2710 #define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */\r
2711 #define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */\r
2712 #define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */\r
2713 #define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */\r
2714 \r
2715 #define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */\r
2716 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */\r
2717 #ifndef __IAR_SYSTEMS_ICC__\r
2718 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */\r
2719 #else\r
2720 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */\r
2721 #endif\r
2722 #define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */\r
2723 #define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */\r
2724 #define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */\r
2725 #define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */\r
2726 #define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */\r
2727 #define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */\r
2728 #define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */\r
2729 #define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */\r
2730 #define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */\r
2731 #define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */\r
2732 #define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */\r
2733 #define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */\r
2734 #define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */\r
2735 #define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */\r
2736 #define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */\r
2737 #define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */\r
2738 #define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */\r
2739 #define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */\r
2740 #define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */\r
2741 #define OFS_LCDBM21 (0x0054u) /* LCD Blinking Memory 21 */\r
2742 #define OFS_LCDBM22 (0x0055u) /* LCD Blinking Memory 22 */\r
2743 #define OFS_LCDBM23 (0x0056u) /* LCD Blinking Memory 23 */\r
2744 #define OFS_LCDBM24 (0x0057u) /* LCD Blinking Memory 24 */\r
2745 \r
2746 /* LCDBIV Definitions */\r
2747 #define LCDBIV_NONE (0x0000u) /* No Interrupt pending */\r
2748 #define LCDBIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */\r
2749 #define LCDBIV_LCDBLKOFFIFG (0x0004u) /* Blink, segments off */\r
2750 #define LCDBIV_LCDBLKONIFG (0x0006u) /* Blink, segments on */\r
2751 #define LCDBIV_LCDFRMIFG (0x0008u) /* Frame interrupt */\r
2752 \r
2753 #endif\r
2754 /************************************************************\r
2755 * LCD_C\r
2756 ************************************************************/\r
2757 #ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */\r
2758 \r
2759 #define OFS_LCDCCTL0 (0x0000u) /* LCD_C Control Register 0 */\r
2760 #define OFS_LCDCCTL0_L OFS_LCDCCTL0\r
2761 #define OFS_LCDCCTL0_H OFS_LCDCCTL0+1\r
2762 #define OFS_LCDCCTL1 (0x0002u) /* LCD_C Control Register 1 */\r
2763 #define OFS_LCDCCTL1_L OFS_LCDCCTL1\r
2764 #define OFS_LCDCCTL1_H OFS_LCDCCTL1+1\r
2765 #define OFS_LCDCBLKCTL (0x0004u) /* LCD_C blinking control register */\r
2766 #define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL\r
2767 #define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1\r
2768 #define OFS_LCDCMEMCTL (0x0006u) /* LCD_C memory control register */\r
2769 #define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL\r
2770 #define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1\r
2771 #define OFS_LCDCVCTL (0x0008u) /* LCD_C Voltage Control Register */\r
2772 #define OFS_LCDCVCTL_L OFS_LCDCVCTL\r
2773 #define OFS_LCDCVCTL_H OFS_LCDCVCTL+1\r
2774 #define OFS_LCDCPCTL0 (0x000Au) /* LCD_C Port Control Register 0 */\r
2775 #define OFS_LCDCPCTL0_L OFS_LCDCPCTL0\r
2776 #define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1\r
2777 #define OFS_LCDCPCTL1 (0x000Cu) /* LCD_C Port Control Register 1 */\r
2778 #define OFS_LCDCPCTL1_L OFS_LCDCPCTL1\r
2779 #define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1\r
2780 #define OFS_LCDCPCTL2 (0x000Eu) /* LCD_C Port Control Register 2 */\r
2781 #define OFS_LCDCPCTL2_L OFS_LCDCPCTL2\r
2782 #define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1\r
2783 #define OFS_LCDCCPCTL (0x0012u) /* LCD_C Charge Pump Control Register 3 */\r
2784 #define OFS_LCDCCPCTL_L OFS_LCDCCPCTL\r
2785 #define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1\r
2786 #define OFS_LCDCIV (0x001Eu) /* LCD_C Interrupt Vector Register */\r
2787 \r
2788 // LCDCCTL0\r
2789 #define LCDON (0x0001u) /* LCD_C LCD On */\r
2790 #define LCDLP (0x0002u) /* LCD_C Low Power Waveform */\r
2791 #define LCDSON (0x0004u) /* LCD_C LCD Segments On */\r
2792 #define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */\r
2793 #define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */\r
2794 #define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */\r
2795 //#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
2796 #define LCDSSEL (0x0080u) /* LCD_C Clock Select */\r
2797 #define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
2798 #define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
2799 #define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
2800 #define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */\r
2801 #define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */\r
2802 #define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */\r
2803 #define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */\r
2804 #define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */\r
2805 \r
2806 // LCDCCTL0\r
2807 #define LCDON_L (0x0001u) /* LCD_C LCD On */\r
2808 #define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */\r
2809 #define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */\r
2810 #define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */\r
2811 #define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */\r
2812 #define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */\r
2813 //#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
2814 #define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */\r
2815 \r
2816 // LCDCCTL0\r
2817 //#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
2818 #define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
2819 #define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
2820 #define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
2821 #define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */\r
2822 #define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */\r
2823 #define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */\r
2824 #define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */\r
2825 #define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */\r
2826 \r
2827 #define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */\r
2828 #define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */\r
2829 #define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */\r
2830 #define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */\r
2831 #define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */\r
2832 #define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */\r
2833 #define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */\r
2834 #define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */\r
2835 #define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */\r
2836 #define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */\r
2837 #define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */\r
2838 #define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */\r
2839 \r
2840 #define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */\r
2841 #define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */\r
2842 #define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */\r
2843 #define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */\r
2844 #define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */\r
2845 #define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */\r
2846 #define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */\r
2847 #define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */\r
2848 #define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */\r
2849 #define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */\r
2850 #define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */\r
2851 #define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */\r
2852 #define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */\r
2853 #define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */\r
2854 #define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */\r
2855 #define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */\r
2856 #define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */\r
2857 #define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */\r
2858 #define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */\r
2859 #define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */\r
2860 #define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */\r
2861 #define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */\r
2862 #define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */\r
2863 #define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */\r
2864 #define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */\r
2865 #define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */\r
2866 #define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */\r
2867 #define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */\r
2868 #define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */\r
2869 #define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */\r
2870 #define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */\r
2871 #define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */\r
2872 #define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */\r
2873 #define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */\r
2874 #define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */\r
2875 #define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */\r
2876 #define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */\r
2877 #define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */\r
2878 #define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */\r
2879 #define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */\r
2880 #define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */\r
2881 #define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */\r
2882 #define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */\r
2883 #define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */\r
2884 #define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */\r
2885 #define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */\r
2886 #define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */\r
2887 #define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */\r
2888 #define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */\r
2889 #define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */\r
2890 #define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */\r
2891 #define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */\r
2892 #define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */\r
2893 #define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */\r
2894 #define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */\r
2895 #define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */\r
2896 #define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */\r
2897 #define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */\r
2898 #define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */\r
2899 #define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */\r
2900 #define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */\r
2901 #define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */\r
2902 #define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */\r
2903 #define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */\r
2904 \r
2905 /* Display modes coded with Bits 2-4 */\r
2906 #define LCDSTATIC (LCDSON)\r
2907 #define LCD2MUX (LCDMX0+LCDSON)\r
2908 #define LCD3MUX (LCDMX1+LCDSON)\r
2909 #define LCD4MUX (LCDMX1+LCDMX0+LCDSON)\r
2910 #define LCD5MUX (LCDMX2+LCDSON)\r
2911 #define LCD6MUX (LCDMX2+LCDMX0+LCDSON)\r
2912 #define LCD7MUX (LCDMX2+LCDMX1+LCDSON)\r
2913 #define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)\r
2914 \r
2915 // LCDCCTL1\r
2916 #define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */\r
2917 #define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
2918 #define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
2919 #define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */\r
2920 #define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */\r
2921 #define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */\r
2922 #define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */\r
2923 #define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */\r
2924 \r
2925 // LCDCCTL1\r
2926 #define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */\r
2927 #define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
2928 #define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
2929 #define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */\r
2930 \r
2931 // LCDCCTL1\r
2932 #define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */\r
2933 #define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
2934 #define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
2935 #define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */\r
2936 \r
2937 // LCDCBLKCTL\r
2938 #define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */\r
2939 #define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */\r
2940 #define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
2941 #define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
2942 #define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
2943 #define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
2944 #define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
2945 #define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
2946 \r
2947 // LCDCBLKCTL\r
2948 #define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */\r
2949 #define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */\r
2950 #define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
2951 #define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
2952 #define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
2953 #define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
2954 #define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
2955 #define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
2956 \r
2957 #define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */\r
2958 #define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */\r
2959 #define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */\r
2960 #define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */\r
2961 \r
2962 // LCDCMEMCTL\r
2963 #define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */\r
2964 #define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */\r
2965 #define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */\r
2966 \r
2967 // LCDCMEMCTL\r
2968 #define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */\r
2969 #define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */\r
2970 #define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */\r
2971 \r
2972 // LCDCVCTL\r
2973 #define LCD2B (0x0001u) /* Selects 1/2 bias. */\r
2974 #define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
2975 #define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
2976 #define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
2977 #define VLCDEXT (0x0010u) /* Select external source for VLCD. */\r
2978 #define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */\r
2979 #define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */\r
2980 #define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
2981 #define VLCD0 (0x0200u) /* VLCD select: 0 */\r
2982 #define VLCD1 (0x0400u) /* VLCD select: 1 */\r
2983 #define VLCD2 (0x0800u) /* VLCD select: 2 */\r
2984 #define VLCD3 (0x1000u) /* VLCD select: 3 */\r
2985 #define VLCD4 (0x2000u) /* VLCD select: 4 */\r
2986 #define VLCD5 (0x4000u) /* VLCD select: 5 */\r
2987 \r
2988 // LCDCVCTL\r
2989 #define LCD2B_L (0x0001u) /* Selects 1/2 bias. */\r
2990 #define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
2991 #define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
2992 #define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
2993 #define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */\r
2994 #define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */\r
2995 #define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */\r
2996 #define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
2997 \r
2998 // LCDCVCTL\r
2999 #define VLCD0_H (0x0002u) /* VLCD select: 0 */\r
3000 #define VLCD1_H (0x0004u) /* VLCD select: 1 */\r
3001 #define VLCD2_H (0x0008u) /* VLCD select: 2 */\r
3002 #define VLCD3_H (0x0010u) /* VLCD select: 3 */\r
3003 #define VLCD4_H (0x0020u) /* VLCD select: 4 */\r
3004 #define VLCD5_H (0x0040u) /* VLCD select: 5 */\r
3005 \r
3006 /* Reference voltage source select for the regulated charge pump */\r
3007 #define VLCDREF_0 (0x0000u) /* Internal */\r
3008 #define VLCDREF_1 (0x0002u) /* External */\r
3009 #define VLCDREF_2 (0x0004u) /* Reserved */\r
3010 #define VLCDREF_3 (0x0006u) /* Reserved */\r
3011 \r
3012 /* Charge pump voltage selections */\r
3013 #define VLCD_0 (0x0000u) /* Charge pump disabled */\r
3014 #define VLCD_1 (0x0200u) /* VLCD = 2.60V */\r
3015 #define VLCD_2 (0x0400u) /* VLCD = 2.66V */\r
3016 #define VLCD_3 (0x0600u) /* VLCD = 2.72V */\r
3017 #define VLCD_4 (0x0800u) /* VLCD = 2.78V */\r
3018 #define VLCD_5 (0x0A00u) /* VLCD = 2.84V */\r
3019 #define VLCD_6 (0x0C00u) /* VLCD = 2.90V */\r
3020 #define VLCD_7 (0x0E00u) /* VLCD = 2.96V */\r
3021 #define VLCD_8 (0x1000u) /* VLCD = 3.02V */\r
3022 #define VLCD_9 (0x1200u) /* VLCD = 3.08V */\r
3023 #define VLCD_10 (0x1400u) /* VLCD = 3.14V */\r
3024 #define VLCD_11 (0x1600u) /* VLCD = 3.20V */\r
3025 #define VLCD_12 (0x1800u) /* VLCD = 3.26V */\r
3026 #define VLCD_13 (0x1A00u) /* VLCD = 3.32V */\r
3027 #define VLCD_14 (0x1C00u) /* VLCD = 3.38V */\r
3028 #define VLCD_15 (0x1E00u) /* VLCD = 3.44V */\r
3029 \r
3030 #define VLCD_DISABLED (0x0000u) /* Charge pump disabled */\r
3031 #define VLCD_2_60 (0x0200u) /* VLCD = 2.60V */\r
3032 #define VLCD_2_66 (0x0400u) /* VLCD = 2.66V */\r
3033 #define VLCD_2_72 (0x0600u) /* VLCD = 2.72V */\r
3034 #define VLCD_2_78 (0x0800u) /* VLCD = 2.78V */\r
3035 #define VLCD_2_84 (0x0A00u) /* VLCD = 2.84V */\r
3036 #define VLCD_2_90 (0x0C00u) /* VLCD = 2.90V */\r
3037 #define VLCD_2_96 (0x0E00u) /* VLCD = 2.96V */\r
3038 #define VLCD_3_02 (0x1000u) /* VLCD = 3.02V */\r
3039 #define VLCD_3_08 (0x1200u) /* VLCD = 3.08V */\r
3040 #define VLCD_3_14 (0x1400u) /* VLCD = 3.14V */\r
3041 #define VLCD_3_20 (0x1600u) /* VLCD = 3.20V */\r
3042 #define VLCD_3_26 (0x1800u) /* VLCD = 3.26V */\r
3043 #define VLCD_3_32 (0x1A00u) /* VLCD = 3.32V */\r
3044 #define VLCD_3_38 (0x1C00u) /* VLCD = 3.38V */\r
3045 #define VLCD_3_44 (0x1E00u) /* VLCD = 3.44V */\r
3046 \r
3047 // LCDCPCTL0\r
3048 #define LCDS0 (0x0001u) /* LCD Segment 0 enable. */\r
3049 #define LCDS1 (0x0002u) /* LCD Segment 1 enable. */\r
3050 #define LCDS2 (0x0004u) /* LCD Segment 2 enable. */\r
3051 #define LCDS3 (0x0008u) /* LCD Segment 3 enable. */\r
3052 #define LCDS4 (0x0010u) /* LCD Segment 4 enable. */\r
3053 #define LCDS5 (0x0020u) /* LCD Segment 5 enable. */\r
3054 #define LCDS6 (0x0040u) /* LCD Segment 6 enable. */\r
3055 #define LCDS7 (0x0080u) /* LCD Segment 7 enable. */\r
3056 #define LCDS8 (0x0100u) /* LCD Segment 8 enable. */\r
3057 #define LCDS9 (0x0200u) /* LCD Segment 9 enable. */\r
3058 #define LCDS10 (0x0400u) /* LCD Segment 10 enable. */\r
3059 #define LCDS11 (0x0800u) /* LCD Segment 11 enable. */\r
3060 #define LCDS12 (0x1000u) /* LCD Segment 12 enable. */\r
3061 #define LCDS13 (0x2000u) /* LCD Segment 13 enable. */\r
3062 #define LCDS14 (0x4000u) /* LCD Segment 14 enable. */\r
3063 #define LCDS15 (0x8000u) /* LCD Segment 15 enable. */\r
3064 \r
3065 // LCDCPCTL0\r
3066 #define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */\r
3067 #define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */\r
3068 #define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */\r
3069 #define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */\r
3070 #define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */\r
3071 #define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */\r
3072 #define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */\r
3073 #define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */\r
3074 \r
3075 // LCDCPCTL0\r
3076 #define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */\r
3077 #define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */\r
3078 #define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */\r
3079 #define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */\r
3080 #define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */\r
3081 #define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */\r
3082 #define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */\r
3083 #define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */\r
3084 \r
3085 // LCDCPCTL1\r
3086 #define LCDS16 (0x0001u) /* LCD Segment 16 enable. */\r
3087 #define LCDS17 (0x0002u) /* LCD Segment 17 enable. */\r
3088 #define LCDS18 (0x0004u) /* LCD Segment 18 enable. */\r
3089 #define LCDS19 (0x0008u) /* LCD Segment 19 enable. */\r
3090 #define LCDS20 (0x0010u) /* LCD Segment 20 enable. */\r
3091 #define LCDS21 (0x0020u) /* LCD Segment 21 enable. */\r
3092 #define LCDS22 (0x0040u) /* LCD Segment 22 enable. */\r
3093 #define LCDS23 (0x0080u) /* LCD Segment 23 enable. */\r
3094 #define LCDS24 (0x0100u) /* LCD Segment 24 enable. */\r
3095 #define LCDS25 (0x0200u) /* LCD Segment 25 enable. */\r
3096 #define LCDS26 (0x0400u) /* LCD Segment 26 enable. */\r
3097 #define LCDS27 (0x0800u) /* LCD Segment 27 enable. */\r
3098 #define LCDS28 (0x1000u) /* LCD Segment 28 enable. */\r
3099 #define LCDS29 (0x2000u) /* LCD Segment 29 enable. */\r
3100 #define LCDS30 (0x4000u) /* LCD Segment 30 enable. */\r
3101 #define LCDS31 (0x8000u) /* LCD Segment 31 enable. */\r
3102 \r
3103 // LCDCPCTL1\r
3104 #define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */\r
3105 #define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */\r
3106 #define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */\r
3107 #define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */\r
3108 #define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */\r
3109 #define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */\r
3110 #define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */\r
3111 #define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */\r
3112 \r
3113 // LCDCPCTL1\r
3114 #define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */\r
3115 #define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */\r
3116 #define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */\r
3117 #define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */\r
3118 #define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */\r
3119 #define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */\r
3120 #define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */\r
3121 #define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */\r
3122 \r
3123 // LCDCPCTL2\r
3124 #define LCDS32 (0x0001u) /* LCD Segment 32 enable. */\r
3125 #define LCDS33 (0x0002u) /* LCD Segment 33 enable. */\r
3126 #define LCDS34 (0x0004u) /* LCD Segment 34 enable. */\r
3127 #define LCDS35 (0x0008u) /* LCD Segment 35 enable. */\r
3128 #define LCDS36 (0x0010u) /* LCD Segment 36 enable. */\r
3129 #define LCDS37 (0x0020u) /* LCD Segment 37 enable. */\r
3130 #define LCDS38 (0x0040u) /* LCD Segment 38 enable. */\r
3131 #define LCDS39 (0x0080u) /* LCD Segment 39 enable. */\r
3132 #define LCDS40 (0x0100u) /* LCD Segment 40 enable. */\r
3133 #define LCDS41 (0x0200u) /* LCD Segment 41 enable. */\r
3134 #define LCDS42 (0x0400u) /* LCD Segment 42 enable. */\r
3135 #define LCDS43 (0x0800u) /* LCD Segment 43 enable. */\r
3136 #define LCDS44 (0x1000u) /* LCD Segment 44 enable. */\r
3137 #define LCDS45 (0x2000u) /* LCD Segment 45 enable. */\r
3138 #define LCDS46 (0x4000u) /* LCD Segment 46 enable. */\r
3139 #define LCDS47 (0x8000u) /* LCD Segment 47 enable. */\r
3140 \r
3141 // LCDCPCTL2\r
3142 #define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */\r
3143 #define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */\r
3144 #define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */\r
3145 #define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */\r
3146 #define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */\r
3147 #define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */\r
3148 #define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */\r
3149 #define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */\r
3150 \r
3151 // LCDCPCTL2\r
3152 #define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */\r
3153 #define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */\r
3154 #define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */\r
3155 #define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */\r
3156 #define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */\r
3157 #define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */\r
3158 #define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */\r
3159 #define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */\r
3160 \r
3161 // LCDCCPCTL\r
3162 #define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */\r
3163 #define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */\r
3164 #define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */\r
3165 #define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */\r
3166 #define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */\r
3167 #define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */\r
3168 #define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */\r
3169 #define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */\r
3170 #define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */\r
3171 \r
3172 // LCDCCPCTL\r
3173 #define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */\r
3174 #define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */\r
3175 #define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */\r
3176 #define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */\r
3177 #define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */\r
3178 #define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */\r
3179 #define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */\r
3180 #define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */\r
3181 \r
3182 // LCDCCPCTL\r
3183 #define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */\r
3184 \r
3185 #define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */\r
3186 #define LCDMEM_ LCDM1 /* LCD Memory */\r
3187 #ifndef __IAR_SYSTEMS_ICC__\r
3188 #define LCDMEM LCDM1 /* LCD Memory (for assembler) */\r
3189 #else\r
3190 #define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */\r
3191 #endif\r
3192 #define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */\r
3193 #define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */\r
3194 #define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */\r
3195 #define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */\r
3196 #define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */\r
3197 #define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */\r
3198 #define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */\r
3199 #define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */\r
3200 #define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */\r
3201 #define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */\r
3202 #define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */\r
3203 #define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */\r
3204 #define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */\r
3205 #define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */\r
3206 #define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */\r
3207 #define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */\r
3208 #define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */\r
3209 #define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */\r
3210 #define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */\r
3211 #define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */\r
3212 #define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */\r
3213 #define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */\r
3214 #define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */\r
3215 #define OFS_LCDM25 (0x0038u) /* LCD Memory 25 */\r
3216 #define OFS_LCDM26 (0x0039u) /* LCD Memory 26 */\r
3217 #define OFS_LCDM27 (0x003Au) /* LCD Memory 27 */\r
3218 #define OFS_LCDM28 (0x003Bu) /* LCD Memory 28 */\r
3219 #define OFS_LCDM29 (0x003Cu) /* LCD Memory 29 */\r
3220 #define OFS_LCDM30 (0x003Du) /* LCD Memory 30 */\r
3221 #define OFS_LCDM31 (0x003Eu) /* LCD Memory 31 */\r
3222 #define OFS_LCDM32 (0x003Fu) /* LCD Memory 32 */\r
3223 #define OFS_LCDM33 (0x0040u) /* LCD Memory 33 */\r
3224 #define OFS_LCDM34 (0x0041u) /* LCD Memory 34 */\r
3225 #define OFS_LCDM35 (0x0042u) /* LCD Memory 35 */\r
3226 #define OFS_LCDM36 (0x0043u) /* LCD Memory 36 */\r
3227 #define OFS_LCDM37 (0x0044u) /* LCD Memory 37 */\r
3228 #define OFS_LCDM38 (0x0045u) /* LCD Memory 38 */\r
3229 #define OFS_LCDM39 (0x0046u) /* LCD Memory 39 */\r
3230 #define OFS_LCDM40 (0x0047u) /* LCD Memory 40 */\r
3231 \r
3232 #define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */\r
3233 #define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */\r
3234 #ifndef __IAR_SYSTEMS_ICC__\r
3235 #define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */\r
3236 #else\r
3237 #define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */\r
3238 #endif\r
3239 #define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */\r
3240 #define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */\r
3241 #define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */\r
3242 #define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */\r
3243 #define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */\r
3244 #define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */\r
3245 #define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */\r
3246 #define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */\r
3247 #define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */\r
3248 #define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */\r
3249 #define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */\r
3250 #define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */\r
3251 #define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */\r
3252 #define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */\r
3253 #define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */\r
3254 #define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */\r
3255 #define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */\r
3256 #define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */\r
3257 #define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */\r
3258 \r
3259 /* LCDCIV Definitions */\r
3260 #define LCDCIV_NONE (0x0000u) /* No Interrupt pending */\r
3261 #define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */\r
3262 #define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */\r
3263 #define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */\r
3264 #define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */\r
3265 \r
3266 #endif\r
3267 /************************************************************\r
3268 * HARDWARE MULTIPLIER 32Bit\r
3269 ************************************************************/\r
3270 #ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */\r
3271 \r
3272 #define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */\r
3273 #define OFS_MPY_L OFS_MPY\r
3274 #define OFS_MPY_H OFS_MPY+1\r
3275 #define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */\r
3276 #define OFS_MPYS_L OFS_MPYS\r
3277 #define OFS_MPYS_H OFS_MPYS+1\r
3278 #define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */\r
3279 #define OFS_MAC_L OFS_MAC\r
3280 #define OFS_MAC_H OFS_MAC+1\r
3281 #define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */\r
3282 #define OFS_MACS_L OFS_MACS\r
3283 #define OFS_MACS_H OFS_MACS+1\r
3284 #define OFS_OP2 (0x0008u) /* Operand 2 */\r
3285 #define OFS_OP2_L OFS_OP2\r
3286 #define OFS_OP2_H OFS_OP2+1\r
3287 #define OFS_RESLO (0x000Au) /* Result Low Word */\r
3288 #define OFS_RESLO_L OFS_RESLO\r
3289 #define OFS_RESLO_H OFS_RESLO+1\r
3290 #define OFS_RESHI (0x000Cu) /* Result High Word */\r
3291 #define OFS_RESHI_L OFS_RESHI\r
3292 #define OFS_RESHI_H OFS_RESHI+1\r
3293 #define OFS_SUMEXT (0x000Eu) /* Sum Extend */\r
3294 #define OFS_SUMEXT_L OFS_SUMEXT\r
3295 #define OFS_SUMEXT_H OFS_SUMEXT+1\r
3296 #define OFS_MPY32CTL0 (0x002Cu)\r
3297 #define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
3298 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
3299 \r
3300 #define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */\r
3301 #define OFS_MPY32L_L OFS_MPY32L\r
3302 #define OFS_MPY32L_H OFS_MPY32L+1\r
3303 #define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */\r
3304 #define OFS_MPY32H_L OFS_MPY32H\r
3305 #define OFS_MPY32H_H OFS_MPY32H+1\r
3306 #define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */\r
3307 #define OFS_MPYS32L_L OFS_MPYS32L\r
3308 #define OFS_MPYS32L_H OFS_MPYS32L+1\r
3309 #define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */\r
3310 #define OFS_MPYS32H_L OFS_MPYS32H\r
3311 #define OFS_MPYS32H_H OFS_MPYS32H+1\r
3312 #define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */\r
3313 #define OFS_MAC32L_L OFS_MAC32L\r
3314 #define OFS_MAC32L_H OFS_MAC32L+1\r
3315 #define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */\r
3316 #define OFS_MAC32H_L OFS_MAC32H\r
3317 #define OFS_MAC32H_H OFS_MAC32H+1\r
3318 #define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */\r
3319 #define OFS_MACS32L_L OFS_MACS32L\r
3320 #define OFS_MACS32L_H OFS_MACS32L+1\r
3321 #define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */\r
3322 #define OFS_MACS32H_L OFS_MACS32H\r
3323 #define OFS_MACS32H_H OFS_MACS32H+1\r
3324 #define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */\r
3325 #define OFS_OP2L_L OFS_OP2L\r
3326 #define OFS_OP2L_H OFS_OP2L+1\r
3327 #define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */\r
3328 #define OFS_OP2H_L OFS_OP2H\r
3329 #define OFS_OP2H_H OFS_OP2H+1\r
3330 #define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */\r
3331 #define OFS_RES0_L OFS_RES0\r
3332 #define OFS_RES0_H OFS_RES0+1\r
3333 #define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */\r
3334 #define OFS_RES1_L OFS_RES1\r
3335 #define OFS_RES1_H OFS_RES1+1\r
3336 #define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */\r
3337 #define OFS_RES2_L OFS_RES2\r
3338 #define OFS_RES2_H OFS_RES2+1\r
3339 #define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */\r
3340 #define OFS_RES3_L OFS_RES3\r
3341 #define OFS_RES3_H OFS_RES3+1\r
3342 #define OFS_SUMEXT (0x000Eu)\r
3343 #define OFS_SUMEXT_L OFS_SUMEXT\r
3344 #define OFS_SUMEXT_H OFS_SUMEXT+1\r
3345 #define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */\r
3346 #define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
3347 #define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
3348 \r
3349 #define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */\r
3350 #define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */\r
3351 #define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */\r
3352 #define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */\r
3353 #define OP2_B OP2_L /* Operand 2 (Byte Access) */\r
3354 #define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */\r
3355 #define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */\r
3356 #define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */\r
3357 #define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */\r
3358 #define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */\r
3359 #define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */\r
3360 #define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */\r
3361 #define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */\r
3362 #define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */\r
3363 #define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */\r
3364 \r
3365 /* MPY32CTL0 Control Bits */\r
3366 #define MPYC (0x0001u) /* Carry of the multiplier */\r
3367 //#define RESERVED (0x0002u) /* Reserved */\r
3368 #define MPYFRAC (0x0004u) /* Fractional mode */\r
3369 #define MPYSAT (0x0008u) /* Saturation mode */\r
3370 #define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */\r
3371 #define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */\r
3372 #define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
3373 #define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
3374 #define MPYDLYWRTEN (0x0100u) /* Delayed write enable */\r
3375 #define MPYDLY32 (0x0200u) /* Delayed write mode */\r
3376 \r
3377 /* MPY32CTL0 Control Bits */\r
3378 #define MPYC_L (0x0001u) /* Carry of the multiplier */\r
3379 //#define RESERVED (0x0002u) /* Reserved */\r
3380 #define MPYFRAC_L (0x0004u) /* Fractional mode */\r
3381 #define MPYSAT_L (0x0008u) /* Saturation mode */\r
3382 #define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */\r
3383 #define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */\r
3384 #define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
3385 #define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
3386 \r
3387 /* MPY32CTL0 Control Bits */\r
3388 //#define RESERVED (0x0002u) /* Reserved */\r
3389 #define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */\r
3390 #define MPYDLY32_H (0x0002u) /* Delayed write mode */\r
3391 \r
3392 #define MPYM_0 (0x0000u) /* Multiplier mode: MPY */\r
3393 #define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */\r
3394 #define MPYM_2 (0x0020u) /* Multiplier mode: MAC */\r
3395 #define MPYM_3 (0x0030u) /* Multiplier mode: MACS */\r
3396 #define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */\r
3397 #define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */\r
3398 #define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */\r
3399 #define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */\r
3400 \r
3401 #endif\r
3402 /************************************************************\r
3403 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors\r
3404 ************************************************************/\r
3405 #ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */\r
3406 #ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */\r
3407 #ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */\r
3408 \r
3409 #define OFS_PAIN (0x0000u) /* Port A Input */\r
3410 #define OFS_PAIN_L OFS_PAIN\r
3411 #define OFS_PAIN_H OFS_PAIN+1\r
3412 #define OFS_PAOUT (0x0002u) /* Port A Output */\r
3413 #define OFS_PAOUT_L OFS_PAOUT\r
3414 #define OFS_PAOUT_H OFS_PAOUT+1\r
3415 #define OFS_PADIR (0x0004u) /* Port A Direction */\r
3416 #define OFS_PADIR_L OFS_PADIR\r
3417 #define OFS_PADIR_H OFS_PADIR+1\r
3418 #define OFS_PAREN (0x0006u) /* Port A Resistor Enable */\r
3419 #define OFS_PAREN_L OFS_PAREN\r
3420 #define OFS_PAREN_H OFS_PAREN+1\r
3421 #define OFS_PADS (0x0008u) /* Port A Drive Strenght */\r
3422 #define OFS_PADS_L OFS_PADS\r
3423 #define OFS_PADS_H OFS_PADS+1\r
3424 #define OFS_PASEL (0x000Au) /* Port A Selection */\r
3425 #define OFS_PASEL_L OFS_PASEL\r
3426 #define OFS_PASEL_H OFS_PASEL+1\r
3427 #define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */\r
3428 #define OFS_PAIES_L OFS_PAIES\r
3429 #define OFS_PAIES_H OFS_PAIES+1\r
3430 #define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */\r
3431 #define OFS_PAIE_L OFS_PAIE\r
3432 #define OFS_PAIE_H OFS_PAIE+1\r
3433 #define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */\r
3434 #define OFS_PAIFG_L OFS_PAIFG\r
3435 #define OFS_PAIFG_H OFS_PAIFG+1\r
3436 \r
3437 \r
3438 #define OFS_P1IN (0x0000u)\r
3439 #define OFS_P1OUT (0x0002u)\r
3440 #define OFS_P1DIR (0x0004u)\r
3441 #define OFS_P1REN (0x0006u)\r
3442 #define OFS_P1DS (0x0008u)\r
3443 #define OFS_P1SEL (0x000Au)\r
3444 #define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */\r
3445 #define OFS_P1IES (0x0018u)\r
3446 #define OFS_P1IE (0x001Au)\r
3447 #define OFS_P1IFG (0x001Cu)\r
3448 #define OFS_P2IN (0x0001u)\r
3449 #define OFS_P2OUT (0x0003u)\r
3450 #define OFS_P2DIR (0x0005u)\r
3451 #define OFS_P2REN (0x0007u)\r
3452 #define OFS_P2DS (0x0009u)\r
3453 #define OFS_P2SEL (0x000Bu)\r
3454 #define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */\r
3455 #define OFS_P2IES (0x0019u)\r
3456 #define OFS_P2IE (0x001Bu)\r
3457 #define OFS_P2IFG (0x001du)\r
3458 #define P1IN (PAIN_L) /* Port 1 Input */\r
3459 #define P1OUT (PAOUT_L) /* Port 1 Output */\r
3460 #define P1DIR (PADIR_L) /* Port 1 Direction */\r
3461 #define P1REN (PAREN_L) /* Port 1 Resistor Enable */\r
3462 #define P1DS (PADS_L) /* Port 1 Drive Strenght */\r
3463 #define P1SEL (PASEL_L) /* Port 1 Selection */\r
3464 #define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */\r
3465 #define P1IE (PAIE_L) /* Port 1 Interrupt Enable */\r
3466 #define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */\r
3467 \r
3468 //Definitions for P1IV\r
3469 #define P1IV_NONE (0x0000u) /* No Interrupt pending */\r
3470 #define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */\r
3471 #define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */\r
3472 #define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */\r
3473 #define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */\r
3474 #define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */\r
3475 #define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */\r
3476 #define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */\r
3477 #define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */\r
3478 \r
3479 #define P2IN (PAIN_H) /* Port 2 Input */\r
3480 #define P2OUT (PAOUT_H) /* Port 2 Output */\r
3481 #define P2DIR (PADIR_H) /* Port 2 Direction */\r
3482 #define P2REN (PAREN_H) /* Port 2 Resistor Enable */\r
3483 #define P2DS (PADS_H) /* Port 2 Drive Strenght */\r
3484 #define P2SEL (PASEL_H) /* Port 2 Selection */\r
3485 #define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */\r
3486 #define P2IE (PAIE_H) /* Port 2 Interrupt Enable */\r
3487 #define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */\r
3488 \r
3489 //Definitions for P2IV\r
3490 #define P2IV_NONE (0x0000u) /* No Interrupt pending */\r
3491 #define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */\r
3492 #define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */\r
3493 #define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */\r
3494 #define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */\r
3495 #define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */\r
3496 #define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */\r
3497 #define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */\r
3498 #define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */\r
3499 \r
3500 \r
3501 #endif\r
3502 #endif\r
3503 #endif\r
3504 /************************************************************\r
3505 * DIGITAL I/O Port3/4 Pull up / Pull down Resistors\r
3506 ************************************************************/\r
3507 #ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */\r
3508 #ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */\r
3509 #ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */\r
3510 \r
3511 #define OFS_PBIN (0x0000u) /* Port B Input */\r
3512 #define OFS_PBIN_L OFS_PBIN\r
3513 #define OFS_PBIN_H OFS_PBIN+1\r
3514 #define OFS_PBOUT (0x0002u) /* Port B Output */\r
3515 #define OFS_PBOUT_L OFS_PBOUT\r
3516 #define OFS_PBOUT_H OFS_PBOUT+1\r
3517 #define OFS_PBDIR (0x0004u) /* Port B Direction */\r
3518 #define OFS_PBDIR_L OFS_PBDIR\r
3519 #define OFS_PBDIR_H OFS_PBDIR+1\r
3520 #define OFS_PBREN (0x0006u) /* Port B Resistor Enable */\r
3521 #define OFS_PBREN_L OFS_PBREN\r
3522 #define OFS_PBREN_H OFS_PBREN+1\r
3523 #define OFS_PBDS (0x0008u) /* Port B Drive Strenght */\r
3524 #define OFS_PBDS_L OFS_PBDS\r
3525 #define OFS_PBDS_H OFS_PBDS+1\r
3526 #define OFS_PBSEL (0x000Au) /* Port B Selection */\r
3527 #define OFS_PBSEL_L OFS_PBSEL\r
3528 #define OFS_PBSEL_H OFS_PBSEL+1\r
3529 #define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */\r
3530 #define OFS_PBIES_L OFS_PBIES\r
3531 #define OFS_PBIES_H OFS_PBIES+1\r
3532 #define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */\r
3533 #define OFS_PBIE_L OFS_PBIE\r
3534 #define OFS_PBIE_H OFS_PBIE+1\r
3535 #define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */\r
3536 #define OFS_PBIFG_L OFS_PBIFG\r
3537 #define OFS_PBIFG_H OFS_PBIFG+1\r
3538 \r
3539 \r
3540 #define OFS_P3IN (0x0000u)\r
3541 #define OFS_P3OUT (0x0002u)\r
3542 #define OFS_P3DIR (0x0004u)\r
3543 #define OFS_P3REN (0x0006u)\r
3544 #define OFS_P3DS (0x0008u)\r
3545 #define OFS_P3SEL (0x000Au)\r
3546 #define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */\r
3547 #define OFS_P3IES (0x0018u)\r
3548 #define OFS_P3IE (0x001Au)\r
3549 #define OFS_P3IFG (0x001Cu)\r
3550 #define OFS_P4IN (0x0001u)\r
3551 #define OFS_P4OUT (0x0003u)\r
3552 #define OFS_P4DIR (0x0005u)\r
3553 #define OFS_P4REN (0x0007u)\r
3554 #define OFS_P4DS (0x0009u)\r
3555 #define OFS_P4SEL (0x000Bu)\r
3556 #define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */\r
3557 #define OFS_P4IES (0x0019u)\r
3558 #define OFS_P4IE (0x001Bu)\r
3559 #define OFS_P4IFG (0x001du)\r
3560 #define P3IN (PBIN_L) /* Port 3 Input */\r
3561 #define P3OUT (PBOUT_L) /* Port 3 Output */\r
3562 #define P3DIR (PBDIR_L) /* Port 3 Direction */\r
3563 #define P3REN (PBREN_L) /* Port 3 Resistor Enable */\r
3564 #define P3DS (PBDS_L) /* Port 3 Drive Strenght */\r
3565 #define P3SEL (PBSEL_L) /* Port 3 Selection */\r
3566 #define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */\r
3567 #define P3IE (PBIE_L) /* Port 3 Interrupt Enable */\r
3568 #define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */\r
3569 \r
3570 //Definitions for P3IV\r
3571 #define P3IV_NONE (0x0000u) /* No Interrupt pending */\r
3572 #define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */\r
3573 #define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */\r
3574 #define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */\r
3575 #define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */\r
3576 #define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */\r
3577 #define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */\r
3578 #define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */\r
3579 #define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */\r
3580 \r
3581 #define P4IN (PBIN_H) /* Port 4 Input */\r
3582 #define P4OUT (PBOUT_H) /* Port 4 Output */\r
3583 #define P4DIR (PBDIR_H) /* Port 4 Direction */\r
3584 #define P4REN (PBREN_H) /* Port 4 Resistor Enable */\r
3585 #define P4DS (PBDS_H) /* Port 4 Drive Strenght */\r
3586 #define P4SEL (PBSEL_H) /* Port 4 Selection */\r
3587 #define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */\r
3588 #define P4IE (PBIE_H) /* Port 4 Interrupt Enable */\r
3589 #define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */\r
3590 \r
3591 //Definitions for P4IV\r
3592 #define P4IV_NONE (0x0000u) /* No Interrupt pending */\r
3593 #define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */\r
3594 #define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */\r
3595 #define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */\r
3596 #define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */\r
3597 #define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */\r
3598 #define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */\r
3599 #define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */\r
3600 #define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */\r
3601 \r
3602 \r
3603 #endif\r
3604 #endif\r
3605 #endif\r
3606 /************************************************************\r
3607 * DIGITAL I/O Port5/6 Pull up / Pull down Resistors\r
3608 ************************************************************/\r
3609 #ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */\r
3610 #ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */\r
3611 #ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */\r
3612 \r
3613 #define OFS_PCIN (0x0000u) /* Port C Input */\r
3614 #define OFS_PCIN_L OFS_PCIN\r
3615 #define OFS_PCIN_H OFS_PCIN+1\r
3616 #define OFS_PCOUT (0x0002u) /* Port C Output */\r
3617 #define OFS_PCOUT_L OFS_PCOUT\r
3618 #define OFS_PCOUT_H OFS_PCOUT+1\r
3619 #define OFS_PCDIR (0x0004u) /* Port C Direction */\r
3620 #define OFS_PCDIR_L OFS_PCDIR\r
3621 #define OFS_PCDIR_H OFS_PCDIR+1\r
3622 #define OFS_PCREN (0x0006u) /* Port C Resistor Enable */\r
3623 #define OFS_PCREN_L OFS_PCREN\r
3624 #define OFS_PCREN_H OFS_PCREN+1\r
3625 #define OFS_PCDS (0x0008u) /* Port C Drive Strenght */\r
3626 #define OFS_PCDS_L OFS_PCDS\r
3627 #define OFS_PCDS_H OFS_PCDS+1\r
3628 #define OFS_PCSEL (0x000Au) /* Port C Selection */\r
3629 #define OFS_PCSEL_L OFS_PCSEL\r
3630 #define OFS_PCSEL_H OFS_PCSEL+1\r
3631 #define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */\r
3632 #define OFS_PCIES_L OFS_PCIES\r
3633 #define OFS_PCIES_H OFS_PCIES+1\r
3634 #define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */\r
3635 #define OFS_PCIE_L OFS_PCIE\r
3636 #define OFS_PCIE_H OFS_PCIE+1\r
3637 #define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */\r
3638 #define OFS_PCIFG_L OFS_PCIFG\r
3639 #define OFS_PCIFG_H OFS_PCIFG+1\r
3640 \r
3641 \r
3642 #define OFS_P5IN (0x0000u)\r
3643 #define OFS_P5OUT (0x0002u)\r
3644 #define OFS_P5DIR (0x0004u)\r
3645 #define OFS_P5REN (0x0006u)\r
3646 #define OFS_P5DS (0x0008u)\r
3647 #define OFS_P5SEL (0x000Au)\r
3648 #define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */\r
3649 #define OFS_P5IES (0x0018u)\r
3650 #define OFS_P5IE (0x001Au)\r
3651 #define OFS_P5IFG (0x001Cu)\r
3652 #define OFS_P6IN (0x0001u)\r
3653 #define OFS_P6OUT (0x0003u)\r
3654 #define OFS_P6DIR (0x0005u)\r
3655 #define OFS_P6REN (0x0007u)\r
3656 #define OFS_P6DS (0x0009u)\r
3657 #define OFS_P6SEL (0x000Bu)\r
3658 #define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */\r
3659 #define OFS_P6IES (0x0019u)\r
3660 #define OFS_P6IE (0x001Bu)\r
3661 #define OFS_P6IFG (0x001du)\r
3662 #define P5IN (PCIN_L) /* Port 5 Input */\r
3663 #define P5OUT (PCOUT_L) /* Port 5 Output */\r
3664 #define P5DIR (PCDIR_L) /* Port 5 Direction */\r
3665 #define P5REN (PCREN_L) /* Port 5 Resistor Enable */\r
3666 #define P5DS (PCDS_L) /* Port 5 Drive Strenght */\r
3667 #define P5SEL (PCSEL_L) /* Port 5 Selection */\r
3668 #define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */\r
3669 #define P5IE (PCIE_L) /* Port 5 Interrupt Enable */\r
3670 #define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */\r
3671 \r
3672 //Definitions for P5IV\r
3673 #define P5IV_NONE (0x0000u) /* No Interrupt pending */\r
3674 #define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */\r
3675 #define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */\r
3676 #define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */\r
3677 #define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */\r
3678 #define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */\r
3679 #define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */\r
3680 #define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */\r
3681 #define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */\r
3682 \r
3683 #define P6IN (PCIN_H) /* Port 6 Input */\r
3684 #define P6OUT (PCOUT_H) /* Port 6 Output */\r
3685 #define P6DIR (PCDIR_H) /* Port 6 Direction */\r
3686 #define P6REN (PCREN_H) /* Port 6 Resistor Enable */\r
3687 #define P6DS (PCDS_H) /* Port 6 Drive Strenght */\r
3688 #define P6SEL (PCSEL_H) /* Port 6 Selection */\r
3689 #define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */\r
3690 #define P6IE (PCIE_H) /* Port 6 Interrupt Enable */\r
3691 #define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */\r
3692 \r
3693 //Definitions for P6IV\r
3694 #define P6IV_NONE (0x0000u) /* No Interrupt pending */\r
3695 #define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */\r
3696 #define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */\r
3697 #define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */\r
3698 #define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */\r
3699 #define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */\r
3700 #define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */\r
3701 #define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */\r
3702 #define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */\r
3703 \r
3704 \r
3705 #endif\r
3706 #endif\r
3707 #endif\r
3708 /************************************************************\r
3709 * DIGITAL I/O Port7/8 Pull up / Pull down Resistors\r
3710 ************************************************************/\r
3711 #ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */\r
3712 #ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */\r
3713 #ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */\r
3714 \r
3715 #define OFS_PDIN (0x0000u) /* Port D Input */\r
3716 #define OFS_PDIN_L OFS_PDIN\r
3717 #define OFS_PDIN_H OFS_PDIN+1\r
3718 #define OFS_PDOUT (0x0002u) /* Port D Output */\r
3719 #define OFS_PDOUT_L OFS_PDOUT\r
3720 #define OFS_PDOUT_H OFS_PDOUT+1\r
3721 #define OFS_PDDIR (0x0004u) /* Port D Direction */\r
3722 #define OFS_PDDIR_L OFS_PDDIR\r
3723 #define OFS_PDDIR_H OFS_PDDIR+1\r
3724 #define OFS_PDREN (0x0006u) /* Port D Resistor Enable */\r
3725 #define OFS_PDREN_L OFS_PDREN\r
3726 #define OFS_PDREN_H OFS_PDREN+1\r
3727 #define OFS_PDDS (0x0008u) /* Port D Drive Strenght */\r
3728 #define OFS_PDDS_L OFS_PDDS\r
3729 #define OFS_PDDS_H OFS_PDDS+1\r
3730 #define OFS_PDSEL (0x000Au) /* Port D Selection */\r
3731 #define OFS_PDSEL_L OFS_PDSEL\r
3732 #define OFS_PDSEL_H OFS_PDSEL+1\r
3733 #define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */\r
3734 #define OFS_PDIES_L OFS_PDIES\r
3735 #define OFS_PDIES_H OFS_PDIES+1\r
3736 #define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */\r
3737 #define OFS_PDIE_L OFS_PDIE\r
3738 #define OFS_PDIE_H OFS_PDIE+1\r
3739 #define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */\r
3740 #define OFS_PDIFG_L OFS_PDIFG\r
3741 #define OFS_PDIFG_H OFS_PDIFG+1\r
3742 \r
3743 \r
3744 #define OFS_P7IN (0x0000u)\r
3745 #define OFS_P7OUT (0x0002u)\r
3746 #define OFS_P7DIR (0x0004u)\r
3747 #define OFS_P7REN (0x0006u)\r
3748 #define OFS_P7DS (0x0008u)\r
3749 #define OFS_P7SEL (0x000Au)\r
3750 #define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */\r
3751 #define OFS_P7IES (0x0018u)\r
3752 #define OFS_P7IE (0x001Au)\r
3753 #define OFS_P7IFG (0x001Cu)\r
3754 #define OFS_P8IN (0x0001u)\r
3755 #define OFS_P8OUT (0x0003u)\r
3756 #define OFS_P8DIR (0x0005u)\r
3757 #define OFS_P8REN (0x0007u)\r
3758 #define OFS_P8DS (0x0009u)\r
3759 #define OFS_P8SEL (0x000Bu)\r
3760 #define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */\r
3761 #define OFS_P8IES (0x0019u)\r
3762 #define OFS_P8IE (0x001Bu)\r
3763 #define OFS_P8IFG (0x001du)\r
3764 #define P7IN (PDIN_L) /* Port 7 Input */\r
3765 #define P7OUT (PDOUT_L) /* Port 7 Output */\r
3766 #define P7DIR (PDDIR_L) /* Port 7 Direction */\r
3767 #define P7REN (PDREN_L) /* Port 7 Resistor Enable */\r
3768 #define P7DS (PDDS_L) /* Port 7 Drive Strenght */\r
3769 #define P7SEL (PDSEL_L) /* Port 7 Selection */\r
3770 #define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */\r
3771 #define P7IE (PDIE_L) /* Port 7 Interrupt Enable */\r
3772 #define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */\r
3773 \r
3774 //Definitions for P7IV\r
3775 #define P7IV_NONE (0x0000u) /* No Interrupt pending */\r
3776 #define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */\r
3777 #define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */\r
3778 #define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */\r
3779 #define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */\r
3780 #define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */\r
3781 #define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */\r
3782 #define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */\r
3783 #define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */\r
3784 \r
3785 #define P8IN (PDIN_H) /* Port 8 Input */\r
3786 #define P8OUT (PDOUT_H) /* Port 8 Output */\r
3787 #define P8DIR (PDDIR_H) /* Port 8 Direction */\r
3788 #define P8REN (PDREN_H) /* Port 8 Resistor Enable */\r
3789 #define P8DS (PDDS_H) /* Port 8 Drive Strenght */\r
3790 #define P8SEL (PDSEL_H) /* Port 8 Selection */\r
3791 #define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */\r
3792 #define P8IE (PDIE_H) /* Port 8 Interrupt Enable */\r
3793 #define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */\r
3794 \r
3795 //Definitions for P8IV\r
3796 #define P8IV_NONE (0x0000u) /* No Interrupt pending */\r
3797 #define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */\r
3798 #define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */\r
3799 #define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */\r
3800 #define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */\r
3801 #define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */\r
3802 #define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */\r
3803 #define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */\r
3804 #define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */\r
3805 \r
3806 \r
3807 #endif\r
3808 #endif\r
3809 #endif\r
3810 /************************************************************\r
3811 * DIGITAL I/O Port9/10 Pull up / Pull down Resistors\r
3812 ************************************************************/\r
3813 #ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */\r
3814 #ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */\r
3815 #ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */\r
3816 \r
3817 #define OFS_PEIN (0x0000u) /* Port E Input */\r
3818 #define OFS_PEIN_L OFS_PEIN\r
3819 #define OFS_PEIN_H OFS_PEIN+1\r
3820 #define OFS_PEOUT (0x0002u) /* Port E Output */\r
3821 #define OFS_PEOUT_L OFS_PEOUT\r
3822 #define OFS_PEOUT_H OFS_PEOUT+1\r
3823 #define OFS_PEDIR (0x0004u) /* Port E Direction */\r
3824 #define OFS_PEDIR_L OFS_PEDIR\r
3825 #define OFS_PEDIR_H OFS_PEDIR+1\r
3826 #define OFS_PEREN (0x0006u) /* Port E Resistor Enable */\r
3827 #define OFS_PEREN_L OFS_PEREN\r
3828 #define OFS_PEREN_H OFS_PEREN+1\r
3829 #define OFS_PEDS (0x0008u) /* Port E Drive Strenght */\r
3830 #define OFS_PEDS_L OFS_PEDS\r
3831 #define OFS_PEDS_H OFS_PEDS+1\r
3832 #define OFS_PESEL (0x000Au) /* Port E Selection */\r
3833 #define OFS_PESEL_L OFS_PESEL\r
3834 #define OFS_PESEL_H OFS_PESEL+1\r
3835 #define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */\r
3836 #define OFS_PEIES_L OFS_PEIES\r
3837 #define OFS_PEIES_H OFS_PEIES+1\r
3838 #define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */\r
3839 #define OFS_PEIE_L OFS_PEIE\r
3840 #define OFS_PEIE_H OFS_PEIE+1\r
3841 #define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */\r
3842 #define OFS_PEIFG_L OFS_PEIFG\r
3843 #define OFS_PEIFG_H OFS_PEIFG+1\r
3844 \r
3845 \r
3846 #define OFS_P9IN (0x0000u)\r
3847 #define OFS_P9OUT (0x0002u)\r
3848 #define OFS_P9DIR (0x0004u)\r
3849 #define OFS_P9REN (0x0006u)\r
3850 #define OFS_P9DS (0x0008u)\r
3851 #define OFS_P9SEL (0x000Au)\r
3852 #define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */\r
3853 #define OFS_P9IES (0x0018u)\r
3854 #define OFS_P9IE (0x001Au)\r
3855 #define OFS_P9IFG (0x001Cu)\r
3856 #define OFS_P10IN (0x0001u)\r
3857 #define OFS_P10OUT (0x0003u)\r
3858 #define OFS_P10DIR (0x0005u)\r
3859 #define OFS_P10REN (0x0007u)\r
3860 #define OFS_P10DS (0x0009u)\r
3861 #define OFS_P10SEL (0x000Bu)\r
3862 #define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */\r
3863 #define OFS_P10IES (0x0019u)\r
3864 #define OFS_P10IE (0x001Bu)\r
3865 #define OFS_P10IFG (0x001du)\r
3866 #define P9IN (PEIN_L) /* Port 9 Input */\r
3867 #define P9OUT (PEOUT_L) /* Port 9 Output */\r
3868 #define P9DIR (PEDIR_L) /* Port 9 Direction */\r
3869 #define P9REN (PEREN_L) /* Port 9 Resistor Enable */\r
3870 #define P9DS (PEDS_L) /* Port 9 Drive Strenght */\r
3871 #define P9SEL (PESEL_L) /* Port 9 Selection */\r
3872 #define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */\r
3873 #define P9IE (PEIE_L) /* Port 9 Interrupt Enable */\r
3874 #define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */\r
3875 \r
3876 //Definitions for P9IV\r
3877 #define P9IV_NONE (0x0000u) /* No Interrupt pending */\r
3878 #define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */\r
3879 #define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */\r
3880 #define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */\r
3881 #define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */\r
3882 #define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */\r
3883 #define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */\r
3884 #define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */\r
3885 #define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */\r
3886 \r
3887 #define P10IN (PEIN_H) /* Port 10 Input */\r
3888 #define P10OUT (PEOUT_H) /* Port 10 Output */\r
3889 #define P10DIR (PEDIR_H) /* Port 10 Direction */\r
3890 #define P10REN (PEREN_H) /* Port 10 Resistor Enable */\r
3891 #define P10DS (PEDS_H) /* Port 10 Drive Strenght */\r
3892 #define P10SEL (PESEL_H) /* Port 10 Selection */\r
3893 #define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */\r
3894 #define P10IE (PEIE_H) /* Port 10 Interrupt Enable */\r
3895 #define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */\r
3896 \r
3897 //Definitions for P10IV\r
3898 #define P10IV_NONE (0x0000u) /* No Interrupt pending */\r
3899 #define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */\r
3900 #define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */\r
3901 #define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */\r
3902 #define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */\r
3903 #define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */\r
3904 #define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */\r
3905 #define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */\r
3906 #define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */\r
3907 \r
3908 \r
3909 #endif\r
3910 #endif\r
3911 #endif\r
3912 /************************************************************\r
3913 * DIGITAL I/O Port11 Pull up / Pull down Resistors\r
3914 ************************************************************/\r
3915 #ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */\r
3916 #ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */\r
3917 \r
3918 #define OFS_PFIN (0x0000u) /* Port F Input */\r
3919 #define OFS_PFIN_L OFS_PFIN\r
3920 #define OFS_PFIN_H OFS_PFIN+1\r
3921 #define OFS_PFOUT (0x0002u) /* Port F Output */\r
3922 #define OFS_PFOUT_L OFS_PFOUT\r
3923 #define OFS_PFOUT_H OFS_PFOUT+1\r
3924 #define OFS_PFDIR (0x0004u) /* Port F Direction */\r
3925 #define OFS_PFDIR_L OFS_PFDIR\r
3926 #define OFS_PFDIR_H OFS_PFDIR+1\r
3927 #define OFS_PFREN (0x0006u) /* Port F Resistor Enable */\r
3928 #define OFS_PFREN_L OFS_PFREN\r
3929 #define OFS_PFREN_H OFS_PFREN+1\r
3930 #define OFS_PFDS (0x0008u) /* Port F Drive Strenght */\r
3931 #define OFS_PFDS_L OFS_PFDS\r
3932 #define OFS_PFDS_H OFS_PFDS+1\r
3933 #define OFS_PFSEL (0x000Au) /* Port F Selection */\r
3934 #define OFS_PFSEL_L OFS_PFSEL\r
3935 #define OFS_PFSEL_H OFS_PFSEL+1\r
3936 #define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */\r
3937 #define OFS_PFIES_L OFS_PFIES\r
3938 #define OFS_PFIES_H OFS_PFIES+1\r
3939 #define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */\r
3940 #define OFS_PFIE_L OFS_PFIE\r
3941 #define OFS_PFIE_H OFS_PFIE+1\r
3942 #define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */\r
3943 #define OFS_PFIFG_L OFS_PFIFG\r
3944 #define OFS_PFIFG_H OFS_PFIFG+1\r
3945 \r
3946 \r
3947 #define OFS_P11IN (0x0000u)\r
3948 #define OFS_P11OUT (0x0002u)\r
3949 #define OFS_P11DIR (0x0004u)\r
3950 #define OFS_P11REN (0x0006u)\r
3951 #define OFS_P11DS (0x0008u)\r
3952 #define OFS_P11SEL (0x000Au)\r
3953 #define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */\r
3954 #define OFS_P11IES (0x0018u)\r
3955 #define OFS_P11IE (0x001Au)\r
3956 #define OFS_P11IFG (0x001Cu)\r
3957 #define P11IN (PFIN_L) /* Port 11 Input */\r
3958 #define P11OUT (PFOUT_L) /* Port 11 Output */\r
3959 #define P11DIR (PFDIR_L) /* Port 11 Direction */\r
3960 #define P11REN (PFREN_L) /* Port 11 Resistor Enable */\r
3961 #define P11DS (PFDS_L) /* Port 11 Drive Strenght */\r
3962 #define P11SEL (PFSEL_L) /* Port 11 Selection */\r
3963 \r
3964 #define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */\r
3965 #define P11IE (PFIE_L) /* Port 11 Interrupt Enable */\r
3966 #define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */\r
3967 \r
3968 //Definitions for P11IV\r
3969 #define P11IV_NONE (0x0000u) /* No Interrupt pending */\r
3970 #define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */\r
3971 #define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */\r
3972 #define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */\r
3973 #define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */\r
3974 #define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */\r
3975 #define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */\r
3976 #define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */\r
3977 #define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */\r
3978 \r
3979 \r
3980 #endif\r
3981 #endif\r
3982 /************************************************************\r
3983 * DIGITAL I/O PortJ Pull up / Pull down Resistors\r
3984 ************************************************************/\r
3985 #ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */\r
3986 \r
3987 #define OFS_PJIN (0x0000u) /* Port J Input */\r
3988 #define OFS_PJIN_L OFS_PJIN\r
3989 #define OFS_PJIN_H OFS_PJIN+1\r
3990 #define OFS_PJOUT (0x0002u) /* Port J Output */\r
3991 #define OFS_PJOUT_L OFS_PJOUT\r
3992 #define OFS_PJOUT_H OFS_PJOUT+1\r
3993 #define OFS_PJDIR (0x0004u) /* Port J Direction */\r
3994 #define OFS_PJDIR_L OFS_PJDIR\r
3995 #define OFS_PJDIR_H OFS_PJDIR+1\r
3996 #define OFS_PJREN (0x0006u) /* Port J Resistor Enable */\r
3997 #define OFS_PJREN_L OFS_PJREN\r
3998 #define OFS_PJREN_H OFS_PJREN+1\r
3999 #define OFS_PJDS (0x0008u) /* Port J Drive Strenght */\r
4000 #define OFS_PJDS_L OFS_PJDS\r
4001 #define OFS_PJDS_H OFS_PJDS+1\r
4002 #define OFS_PJSEL (0x000Au) /* Port J Selection */\r
4003 #define OFS_PJSEL_L OFS_PJSEL\r
4004 #define OFS_PJSEL_H OFS_PJSEL+1\r
4005 \r
4006 #endif\r
4007 /************************************************************\r
4008 * PORT MAPPING CONTROLLER\r
4009 ************************************************************/\r
4010 #ifdef __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */\r
4011 \r
4012 #define OFS_PMAPKEYID (0x0000u) /* Port Mapping Key register */\r
4013 #define OFS_PMAPKEYID_L OFS_PMAPKEYID\r
4014 #define OFS_PMAPKEYID_H OFS_PMAPKEYID+1\r
4015 #define OFS_PMAPCTL (0x0002u) /* Port Mapping control register */\r
4016 #define OFS_PMAPCTL_L OFS_PMAPCTL\r
4017 #define OFS_PMAPCTL_H OFS_PMAPCTL+1\r
4018 \r
4019 #define PMAPKEY (0x2D52u) /* Port Mapping Key */\r
4020 #define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */\r
4021 #define PMAPPW (0x2D52u) /* Legacy Definition: Port Mapping Password */\r
4022 \r
4023 /* PMAPCTL Control Bits */\r
4024 #define PMAPLOCKED (0x0001u) /* Port Mapping Lock bit. Read only */\r
4025 #define PMAPRECFG (0x0002u) /* Port Mapping re-configuration control bit */\r
4026 \r
4027 /* PMAPCTL Control Bits */\r
4028 #define PMAPLOCKED_L (0x0001u) /* Port Mapping Lock bit. Read only */\r
4029 #define PMAPRECFG_L (0x0002u) /* Port Mapping re-configuration control bit */\r
4030 \r
4031 #endif\r
4032 /************************************************************\r
4033 * PORT 2 MAPPING CONTROLLER\r
4034 ************************************************************/\r
4035 #ifdef __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */\r
4036 \r
4037 #define OFS_P2MAP01 (0x0000u) /* Port P2.0/1 mapping register */\r
4038 #define OFS_P2MAP01_L OFS_P2MAP01\r
4039 #define OFS_P2MAP01_H OFS_P2MAP01+1\r
4040 #define OFS_P2MAP23 (0x0002u) /* Port P2.2/3 mapping register */\r
4041 #define OFS_P2MAP23_L OFS_P2MAP23\r
4042 #define OFS_P2MAP23_H OFS_P2MAP23+1\r
4043 #define OFS_P2MAP45 (0x0004u) /* Port P2.4/5 mapping register */\r
4044 #define OFS_P2MAP45_L OFS_P2MAP45\r
4045 #define OFS_P2MAP45_H OFS_P2MAP45+1\r
4046 #define OFS_P2MAP67 (0x0006u) /* Port P2.6/7 mapping register */\r
4047 #define OFS_P2MAP67_L OFS_P2MAP67\r
4048 #define OFS_P2MAP67_H OFS_P2MAP67+1\r
4049 #define OFS_P2MAP0 (0x0000u)\r
4050 #define OFS_P2MAP1 (0x0001u)\r
4051 #define OFS_P2MAP2 (0x0002u)\r
4052 #define OFS_P2MAP3 (0x0003u)\r
4053 #define OFS_P2MAP4 (0x0004u)\r
4054 #define OFS_P2MAP5 (0x0005u)\r
4055 #define OFS_P2MAP6 (0x0006u)\r
4056 #define OFS_P2MAP7 (0x0007u)\r
4057 \r
4058 #define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */\r
4059 #define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */\r
4060 #define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */\r
4061 #define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */\r
4062 #define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */\r
4063 #define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */\r
4064 #define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */\r
4065 #define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */\r
4066 \r
4067 #endif\r
4068 /************************************************************\r
4069 * PMM - Power Management System\r
4070 ************************************************************/\r
4071 #ifdef __MSP430_HAS_PMM__ /* Definition to show that Module is available */\r
4072 \r
4073 #define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */\r
4074 #define OFS_PMMCTL0_L OFS_PMMCTL0\r
4075 #define OFS_PMMCTL0_H OFS_PMMCTL0+1\r
4076 #define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */\r
4077 #define OFS_PMMCTL1_L OFS_PMMCTL1\r
4078 #define OFS_PMMCTL1_H OFS_PMMCTL1+1\r
4079 #define OFS_SVSMHCTL (0x0004u) /* SVS and SVM high side control register */\r
4080 #define OFS_SVSMHCTL_L OFS_SVSMHCTL\r
4081 #define OFS_SVSMHCTL_H OFS_SVSMHCTL+1\r
4082 #define OFS_SVSMLCTL (0x0006u) /* SVS and SVM low side control register */\r
4083 #define OFS_SVSMLCTL_L OFS_SVSMLCTL\r
4084 #define OFS_SVSMLCTL_H OFS_SVSMLCTL+1\r
4085 #define OFS_SVSMIO (0x0008u) /* SVSIN and SVSOUT control register */\r
4086 #define OFS_SVSMIO_L OFS_SVSMIO\r
4087 #define OFS_SVSMIO_H OFS_SVSMIO+1\r
4088 #define OFS_PMMIFG (0x000Cu) /* PMM Interrupt Flag */\r
4089 #define OFS_PMMIFG_L OFS_PMMIFG\r
4090 #define OFS_PMMIFG_H OFS_PMMIFG+1\r
4091 #define OFS_PMMRIE (0x000Eu) /* PMM and RESET Interrupt Enable */\r
4092 #define OFS_PMMRIE_L OFS_PMMRIE\r
4093 #define OFS_PMMRIE_H OFS_PMMRIE+1\r
4094 \r
4095 #define PMMPW (0xA500u) /* PMM Register Write Password */\r
4096 #define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */\r
4097 \r
4098 /* PMMCTL0 Control Bits */\r
4099 #define PMMCOREV0 (0x0001u) /* PMM Core Voltage Bit: 0 */\r
4100 #define PMMCOREV1 (0x0002u) /* PMM Core Voltage Bit: 1 */\r
4101 #define PMMSWBOR (0x0004u) /* PMM Software BOR */\r
4102 #define PMMSWPOR (0x0008u) /* PMM Software POR */\r
4103 #define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */\r
4104 #define PMMHPMRE (0x0080u) /* PMM Global High Power Module Request Enable */\r
4105 \r
4106 /* PMMCTL0 Control Bits */\r
4107 #define PMMCOREV0_L (0x0001u) /* PMM Core Voltage Bit: 0 */\r
4108 #define PMMCOREV1_L (0x0002u) /* PMM Core Voltage Bit: 1 */\r
4109 #define PMMSWBOR_L (0x0004u) /* PMM Software BOR */\r
4110 #define PMMSWPOR_L (0x0008u) /* PMM Software POR */\r
4111 #define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */\r
4112 #define PMMHPMRE_L (0x0080u) /* PMM Global High Power Module Request Enable */\r
4113 \r
4114 #define PMMCOREV_0 (0x0000u) /* PMM Core Voltage 0 (1.35V) */\r
4115 #define PMMCOREV_1 (0x0001u) /* PMM Core Voltage 1 (1.55V) */\r
4116 #define PMMCOREV_2 (0x0002u) /* PMM Core Voltage 2 (1.75V) */\r
4117 #define PMMCOREV_3 (0x0003u) /* PMM Core Voltage 3 (1.85V) */\r
4118 \r
4119 /* PMMCTL1 Control Bits */\r
4120 #define PMMREFMD (0x0001u) /* PMM Reference Mode */\r
4121 #define PMMCMD0 (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */\r
4122 #define PMMCMD1 (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */\r
4123 \r
4124 /* PMMCTL1 Control Bits */\r
4125 #define PMMREFMD_L (0x0001u) /* PMM Reference Mode */\r
4126 #define PMMCMD0_L (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */\r
4127 #define PMMCMD1_L (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */\r
4128 \r
4129 /* SVSMHCTL Control Bits */\r
4130 #define SVSMHRRL0 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */\r
4131 #define SVSMHRRL1 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */\r
4132 #define SVSMHRRL2 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */\r
4133 #define SVSMHDLYST (0x0008u) /* SVS and SVM high side delay status */\r
4134 #define SVSHMD (0x0010u) /* SVS high side mode */\r
4135 #define SVSMHEVM (0x0040u) /* SVS and SVM high side event mask */\r
4136 #define SVSMHACE (0x0080u) /* SVS and SVM high side auto control enable */\r
4137 #define SVSHRVL0 (0x0100u) /* SVS high side reset voltage level Bit: 0 */\r
4138 #define SVSHRVL1 (0x0200u) /* SVS high side reset voltage level Bit: 1 */\r
4139 #define SVSHE (0x0400u) /* SVS high side enable */\r
4140 #define SVSHFP (0x0800u) /* SVS high side full performace mode */\r
4141 #define SVMHOVPE (0x1000u) /* SVM high side over-voltage enable */\r
4142 #define SVMHE (0x4000u) /* SVM high side enable */\r
4143 #define SVMHFP (0x8000u) /* SVM high side full performace mode */\r
4144 \r
4145 /* SVSMHCTL Control Bits */\r
4146 #define SVSMHRRL0_L (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */\r
4147 #define SVSMHRRL1_L (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */\r
4148 #define SVSMHRRL2_L (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */\r
4149 #define SVSMHDLYST_L (0x0008u) /* SVS and SVM high side delay status */\r
4150 #define SVSHMD_L (0x0010u) /* SVS high side mode */\r
4151 #define SVSMHEVM_L (0x0040u) /* SVS and SVM high side event mask */\r
4152 #define SVSMHACE_L (0x0080u) /* SVS and SVM high side auto control enable */\r
4153 \r
4154 /* SVSMHCTL Control Bits */\r
4155 #define SVSHRVL0_H (0x0001u) /* SVS high side reset voltage level Bit: 0 */\r
4156 #define SVSHRVL1_H (0x0002u) /* SVS high side reset voltage level Bit: 1 */\r
4157 #define SVSHE_H (0x0004u) /* SVS high side enable */\r
4158 #define SVSHFP_H (0x0008u) /* SVS high side full performace mode */\r
4159 #define SVMHOVPE_H (0x0010u) /* SVM high side over-voltage enable */\r
4160 #define SVMHE_H (0x0040u) /* SVM high side enable */\r
4161 #define SVMHFP_H (0x0080u) /* SVM high side full performace mode */\r
4162 \r
4163 #define SVSMHRRL_0 (0x0000u) /* SVS and SVM high side Reset Release Voltage Level 0 */\r
4164 #define SVSMHRRL_1 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level 1 */\r
4165 #define SVSMHRRL_2 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level 2 */\r
4166 #define SVSMHRRL_3 (0x0003u) /* SVS and SVM high side Reset Release Voltage Level 3 */\r
4167 #define SVSMHRRL_4 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level 4 */\r
4168 #define SVSMHRRL_5 (0x0005u) /* SVS and SVM high side Reset Release Voltage Level 5 */\r
4169 #define SVSMHRRL_6 (0x0006u) /* SVS and SVM high side Reset Release Voltage Level 6 */\r
4170 #define SVSMHRRL_7 (0x0007u) /* SVS and SVM high side Reset Release Voltage Level 7 */\r
4171 \r
4172 #define SVSHRVL_0 (0x0000u) /* SVS high side Reset Release Voltage Level 0 */\r
4173 #define SVSHRVL_1 (0x0100u) /* SVS high side Reset Release Voltage Level 1 */\r
4174 #define SVSHRVL_2 (0x0200u) /* SVS high side Reset Release Voltage Level 2 */\r
4175 #define SVSHRVL_3 (0x0300u) /* SVS high side Reset Release Voltage Level 3 */\r
4176 \r
4177 /* SVSMLCTL Control Bits */\r
4178 #define SVSMLRRL0 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */\r
4179 #define SVSMLRRL1 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */\r
4180 #define SVSMLRRL2 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */\r
4181 #define SVSMLDLYST (0x0008u) /* SVS and SVM low side delay status */\r
4182 #define SVSLMD (0x0010u) /* SVS low side mode */\r
4183 #define SVSMLEVM (0x0040u) /* SVS and SVM low side event mask */\r
4184 #define SVSMLACE (0x0080u) /* SVS and SVM low side auto control enable */\r
4185 #define SVSLRVL0 (0x0100u) /* SVS low side reset voltage level Bit: 0 */\r
4186 #define SVSLRVL1 (0x0200u) /* SVS low side reset voltage level Bit: 1 */\r
4187 #define SVSLE (0x0400u) /* SVS low side enable */\r
4188 #define SVSLFP (0x0800u) /* SVS low side full performace mode */\r
4189 #define SVMLOVPE (0x1000u) /* SVM low side over-voltage enable */\r
4190 #define SVMLE (0x4000u) /* SVM low side enable */\r
4191 #define SVMLFP (0x8000u) /* SVM low side full performace mode */\r
4192 \r
4193 /* SVSMLCTL Control Bits */\r
4194 #define SVSMLRRL0_L (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */\r
4195 #define SVSMLRRL1_L (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */\r
4196 #define SVSMLRRL2_L (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */\r
4197 #define SVSMLDLYST_L (0x0008u) /* SVS and SVM low side delay status */\r
4198 #define SVSLMD_L (0x0010u) /* SVS low side mode */\r
4199 #define SVSMLEVM_L (0x0040u) /* SVS and SVM low side event mask */\r
4200 #define SVSMLACE_L (0x0080u) /* SVS and SVM low side auto control enable */\r
4201 \r
4202 /* SVSMLCTL Control Bits */\r
4203 #define SVSLRVL0_H (0x0001u) /* SVS low side reset voltage level Bit: 0 */\r
4204 #define SVSLRVL1_H (0x0002u) /* SVS low side reset voltage level Bit: 1 */\r
4205 #define SVSLE_H (0x0004u) /* SVS low side enable */\r
4206 #define SVSLFP_H (0x0008u) /* SVS low side full performace mode */\r
4207 #define SVMLOVPE_H (0x0010u) /* SVM low side over-voltage enable */\r
4208 #define SVMLE_H (0x0040u) /* SVM low side enable */\r
4209 #define SVMLFP_H (0x0080u) /* SVM low side full performace mode */\r
4210 \r
4211 #define SVSMLRRL_0 (0x0000u) /* SVS and SVM low side Reset Release Voltage Level 0 */\r
4212 #define SVSMLRRL_1 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level 1 */\r
4213 #define SVSMLRRL_2 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level 2 */\r
4214 #define SVSMLRRL_3 (0x0003u) /* SVS and SVM low side Reset Release Voltage Level 3 */\r
4215 #define SVSMLRRL_4 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level 4 */\r
4216 #define SVSMLRRL_5 (0x0005u) /* SVS and SVM low side Reset Release Voltage Level 5 */\r
4217 #define SVSMLRRL_6 (0x0006u) /* SVS and SVM low side Reset Release Voltage Level 6 */\r
4218 #define SVSMLRRL_7 (0x0007u) /* SVS and SVM low side Reset Release Voltage Level 7 */\r
4219 \r
4220 #define SVSLRVL_0 (0x0000u) /* SVS low side Reset Release Voltage Level 0 */\r
4221 #define SVSLRVL_1 (0x0100u) /* SVS low side Reset Release Voltage Level 1 */\r
4222 #define SVSLRVL_2 (0x0200u) /* SVS low side Reset Release Voltage Level 2 */\r
4223 #define SVSLRVL_3 (0x0300u) /* SVS low side Reset Release Voltage Level 3 */\r
4224 \r
4225 /* SVSMIO Control Bits */\r
4226 #define SVMLOE (0x0008u) /* SVM low side output enable */\r
4227 #define SVMLVLROE (0x0010u) /* SVM low side voltage level reached output enable */\r
4228 #define SVMOUTPOL (0x0020u) /* SVMOUT pin polarity */\r
4229 #define SVMHOE (0x0800u) /* SVM high side output enable */\r
4230 #define SVMHVLROE (0x1000u) /* SVM high side voltage level reached output enable */\r
4231 \r
4232 /* SVSMIO Control Bits */\r
4233 #define SVMLOE_L (0x0008u) /* SVM low side output enable */\r
4234 #define SVMLVLROE_L (0x0010u) /* SVM low side voltage level reached output enable */\r
4235 #define SVMOUTPOL_L (0x0020u) /* SVMOUT pin polarity */\r
4236 \r
4237 /* SVSMIO Control Bits */\r
4238 #define SVMHOE_H (0x0008u) /* SVM high side output enable */\r
4239 #define SVMHVLROE_H (0x0010u) /* SVM high side voltage level reached output enable */\r
4240 \r
4241 /* PMMIFG Control Bits */\r
4242 #define SVSMLDLYIFG (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */\r
4243 #define SVMLIFG (0x0002u) /* SVM low side interrupt flag */\r
4244 #define SVMLVLRIFG (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */\r
4245 #define SVSMHDLYIFG (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */\r
4246 #define SVMHIFG (0x0020u) /* SVM high side interrupt flag */\r
4247 #define SVMHVLRIFG (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */\r
4248 #define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */\r
4249 #define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */\r
4250 #define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */\r
4251 #define SVSHIFG (0x1000u) /* SVS low side interrupt flag */\r
4252 #define SVSLIFG (0x2000u) /* SVS high side interrupt flag */\r
4253 #define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */\r
4254 \r
4255 /* PMMIFG Control Bits */\r
4256 #define SVSMLDLYIFG_L (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */\r
4257 #define SVMLIFG_L (0x0002u) /* SVM low side interrupt flag */\r
4258 #define SVMLVLRIFG_L (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */\r
4259 #define SVSMHDLYIFG_L (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */\r
4260 #define SVMHIFG_L (0x0020u) /* SVM high side interrupt flag */\r
4261 #define SVMHVLRIFG_L (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */\r
4262 \r
4263 /* PMMIFG Control Bits */\r
4264 #define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */\r
4265 #define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */\r
4266 #define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */\r
4267 #define SVSHIFG_H (0x0010u) /* SVS low side interrupt flag */\r
4268 #define SVSLIFG_H (0x0020u) /* SVS high side interrupt flag */\r
4269 #define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */\r
4270 \r
4271 #define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */\r
4272 \r
4273 /* PMMIE and RESET Control Bits */\r
4274 #define SVSMLDLYIE (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */\r
4275 #define SVMLIE (0x0002u) /* SVM low side interrupt enable */\r
4276 #define SVMLVLRIE (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */\r
4277 #define SVSMHDLYIE (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */\r
4278 #define SVMHIE (0x0020u) /* SVM high side interrupt enable */\r
4279 #define SVMHVLRIE (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */\r
4280 #define SVSLPE (0x0100u) /* SVS low side POR enable */\r
4281 #define SVMLVLRPE (0x0200u) /* SVM low side Voltage Level reached POR enable */\r
4282 #define SVSHPE (0x1000u) /* SVS high side POR enable */\r
4283 #define SVMHVLRPE (0x2000u) /* SVM high side Voltage Level reached POR enable */\r
4284 \r
4285 /* PMMIE and RESET Control Bits */\r
4286 #define SVSMLDLYIE_L (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */\r
4287 #define SVMLIE_L (0x0002u) /* SVM low side interrupt enable */\r
4288 #define SVMLVLRIE_L (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */\r
4289 #define SVSMHDLYIE_L (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */\r
4290 #define SVMHIE_L (0x0020u) /* SVM high side interrupt enable */\r
4291 #define SVMHVLRIE_L (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */\r
4292 \r
4293 /* PMMIE and RESET Control Bits */\r
4294 #define SVSLPE_H (0x0001u) /* SVS low side POR enable */\r
4295 #define SVMLVLRPE_H (0x0002u) /* SVM low side Voltage Level reached POR enable */\r
4296 #define SVSHPE_H (0x0010u) /* SVS high side POR enable */\r
4297 #define SVMHVLRPE_H (0x0020u) /* SVM high side Voltage Level reached POR enable */\r
4298 \r
4299 #endif\r
4300 /************************************************************\r
4301 * Port U\r
4302 ************************************************************/\r
4303 #ifdef __MSP430_HAS_PU__ /* Definition to show that Module is available */\r
4304 \r
4305 /* ========================================================================= */\r
4306 /* Port U and LDO Control Registers */\r
4307 /* ========================================================================= */\r
4308 #define OFS_LDOKEYPID (0x0000u) /* LDO Controller peripheral ID and key register */\r
4309 #define OFS_LDOKEYPID_L OFS_LDOKEYPID\r
4310 #define OFS_LDOKEYPID_H OFS_LDOKEYPID+1\r
4311 #define OFS_PUCTL (0x0004u) /* PU Control register */\r
4312 #define OFS_PUCTL_L OFS_PUCTL\r
4313 #define OFS_PUCTL_H OFS_PUCTL+1\r
4314 #define OFS_LDOPWRCTL (0x0008u) /* LDO Power control register */\r
4315 #define OFS_LDOPWRCTL_L OFS_LDOPWRCTL\r
4316 #define OFS_LDOPWRCTL_H OFS_LDOPWRCTL+1\r
4317 \r
4318 #define LDOKEY (0x9628u) /* LDO Control Register key */\r
4319 #define LDOKEYID LDOKEYPID /* Legacy Definiton */\r
4320 \r
4321 /* PUCTL Control Bits */\r
4322 #define PUOUT0 (0x0001u) /* PU - PU Output Signal Bit 0 */\r
4323 #define PUOUT1 (0x0002u) /* PU - PU Output Signal Bit 1 */\r
4324 #define PUIN0 (0x0004u) /* PU - PU0/DP Input Data */\r
4325 #define PUIN1 (0x0008u) /* PU - PU1/DM Input Data */\r
4326 #define PUOPE (0x0020u) /* PU - Port Output Enable */\r
4327 #define PUIPE (0x0100u) /* PU - PHY Single Ended Input enable */\r
4328 \r
4329 /* PUCTL Control Bits */\r
4330 #define PUOUT0_L (0x0001u) /* PU - PU Output Signal Bit 0 */\r
4331 #define PUOUT1_L (0x0002u) /* PU - PU Output Signal Bit 1 */\r
4332 #define PUIN0_L (0x0004u) /* PU - PU0/DP Input Data */\r
4333 #define PUIN1_L (0x0008u) /* PU - PU1/DM Input Data */\r
4334 #define PUOPE_L (0x0020u) /* PU - Port Output Enable */\r
4335 \r
4336 /* PUCTL Control Bits */\r
4337 #define PUIPE_H (0x0001u) /* PU - PHY Single Ended Input enable */\r
4338 \r
4339 #define PUDIR (0x0020u) /* Legacy Definiton */\r
4340 #define PSEIEN (0x0100u) /* Legacy Definiton */\r
4341 \r
4342 /* LDOPWRCTL Control Bits */\r
4343 #define LDOOVLIFG (0x0001u) /* PU - LDOO Overload Interrupt Flag */\r
4344 #define LDOONIFG (0x0002u) /* PU - LDOI "Coming ON" Interrupt Flag */\r
4345 #define LDOOFFIFG (0x0004u) /* PU - LDOI "Going OFF" Interrupt Flag */\r
4346 #define LDOBGVBV (0x0008u) /* PU - LDO Bandgap and LDOI valid */\r
4347 #define OVLAOFF (0x0020u) /* PU - LDO overload auto off enable */\r
4348 #define LDOOVLIE (0x0100u) /* PU - Overload indication Interrupt Enable */\r
4349 #define LDOONIE (0x0200u) /* PU - LDOI "Coming ON" Interrupt Enable */\r
4350 #define LDOOFFIE (0x0400u) /* PU - LDOI "Going OFF" Interrupt Enable */\r
4351 #define LDOEN (0x0800u) /* PU - LDO Enable (3.3V) */\r
4352 \r
4353 /* LDOPWRCTL Control Bits */\r
4354 #define LDOOVLIFG_L (0x0001u) /* PU - LDOO Overload Interrupt Flag */\r
4355 #define LDOONIFG_L (0x0002u) /* PU - LDOI "Coming ON" Interrupt Flag */\r
4356 #define LDOOFFIFG_L (0x0004u) /* PU - LDOI "Going OFF" Interrupt Flag */\r
4357 #define LDOBGVBV_L (0x0008u) /* PU - LDO Bandgap and LDOI valid */\r
4358 #define OVLAOFF_L (0x0020u) /* PU - LDO overload auto off enable */\r
4359 \r
4360 /* LDOPWRCTL Control Bits */\r
4361 #define LDOOVLIE_H (0x0001u) /* PU - Overload indication Interrupt Enable */\r
4362 #define LDOONIE_H (0x0002u) /* PU - LDOI "Coming ON" Interrupt Enable */\r
4363 #define LDOOFFIE_H (0x0004u) /* PU - LDOI "Going OFF" Interrupt Enable */\r
4364 #define LDOEN_H (0x0008u) /* PU - LDO Enable (3.3V) */\r
4365 #define LDOOEN LDOEN /* Deprecated support for LDO Enable (3.3V) */\r
4366 #define LDOOEN_H LDOEN_H /* Deprecated support for LDO Enable (3.3V) */\r
4367 \r
4368 #define VUOVLIFG (0x0001u) /* PU - Legacy Definiton: LDOO Overload Interrupt Flag */\r
4369 #define VBONIFG (0x0002u) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Flag */\r
4370 #define VBOFFIFG (0x0004u) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Flag */\r
4371 #define VUOVLIE (0x0100u) /* PU - Legacy Definiton: Overload indication Interrupt Enable */\r
4372 #define VBONIE (0x0200u) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Enable */\r
4373 #define VBOFFIE (0x0400u) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Enable */\r
4374 \r
4375 \r
4376 #endif\r
4377 /*************************************************************\r
4378 * RAM Control Module\r
4379 *************************************************************/\r
4380 #ifdef __MSP430_HAS_RC__ /* Definition to show that Module is available */\r
4381 \r
4382 #define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */\r
4383 #define OFS_RCCTL0_L OFS_RCCTL0\r
4384 #define OFS_RCCTL0_H OFS_RCCTL0+1\r
4385 \r
4386 /* RCCTL0 Control Bits */\r
4387 #define RCRS0OFF (0x0001u) /* RAM Controller RAM Sector 0 Off */\r
4388 #define RCRS1OFF (0x0002u) /* RAM Controller RAM Sector 1 Off */\r
4389 #define RCRS2OFF (0x0004u) /* RAM Controller RAM Sector 2 Off */\r
4390 #define RCRS3OFF (0x0008u) /* RAM Controller RAM Sector 3 Off */\r
4391 #define RCRS4OFF (0x0010u) /* RAM Controller RAM Sector 4 Off */\r
4392 #define RCRS5OFF (0x0020u) /* RAM Controller RAM Sector 5 Off */\r
4393 #define RCRS6OFF (0x0040u) /* RAM Controller RAM Sector 6 Off */\r
4394 #define RCRS7OFF (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off */\r
4395 \r
4396 /* RCCTL0 Control Bits */\r
4397 #define RCRS0OFF_L (0x0001u) /* RAM Controller RAM Sector 0 Off */\r
4398 #define RCRS1OFF_L (0x0002u) /* RAM Controller RAM Sector 1 Off */\r
4399 #define RCRS2OFF_L (0x0004u) /* RAM Controller RAM Sector 2 Off */\r
4400 #define RCRS3OFF_L (0x0008u) /* RAM Controller RAM Sector 3 Off */\r
4401 #define RCRS4OFF_L (0x0010u) /* RAM Controller RAM Sector 4 Off */\r
4402 #define RCRS5OFF_L (0x0020u) /* RAM Controller RAM Sector 5 Off */\r
4403 #define RCRS6OFF_L (0x0040u) /* RAM Controller RAM Sector 6 Off */\r
4404 #define RCRS7OFF_L (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off */\r
4405 \r
4406 #define RCKEY (0x5A00u)\r
4407 \r
4408 #endif\r
4409 /************************************************************\r
4410 * Shared Reference\r
4411 ************************************************************/\r
4412 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */\r
4413 \r
4414 #define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */\r
4415 #define OFS_REFCTL0_L OFS_REFCTL0\r
4416 #define OFS_REFCTL0_H OFS_REFCTL0+1\r
4417 \r
4418 /* REFCTL0 Control Bits */\r
4419 #define REFON (0x0001u) /* REF Reference On */\r
4420 #define REFOUT (0x0002u) /* REF Reference output Buffer On */\r
4421 //#define RESERVED (0x0004u) /* Reserved */\r
4422 #define REFTCOFF (0x0008u) /* REF Temp.Sensor off */\r
4423 #define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
4424 #define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
4425 //#define RESERVED (0x0040u) /* Reserved */\r
4426 #define REFMSTR (0x0080u) /* REF Master Control */\r
4427 #define REFGENACT (0x0100u) /* REF Reference generator active */\r
4428 #define REFBGACT (0x0200u) /* REF Reference bandgap active */\r
4429 #define REFGENBUSY (0x0400u) /* REF Reference generator busy */\r
4430 #define BGMODE (0x0800u) /* REF Bandgap mode */\r
4431 //#define RESERVED (0x1000u) /* Reserved */\r
4432 //#define RESERVED (0x2000u) /* Reserved */\r
4433 //#define RESERVED (0x4000u) /* Reserved */\r
4434 //#define RESERVED (0x8000u) /* Reserved */\r
4435 \r
4436 /* REFCTL0 Control Bits */\r
4437 #define REFON_L (0x0001u) /* REF Reference On */\r
4438 #define REFOUT_L (0x0002u) /* REF Reference output Buffer On */\r
4439 //#define RESERVED (0x0004u) /* Reserved */\r
4440 #define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */\r
4441 #define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
4442 #define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
4443 //#define RESERVED (0x0040u) /* Reserved */\r
4444 #define REFMSTR_L (0x0080u) /* REF Master Control */\r
4445 //#define RESERVED (0x1000u) /* Reserved */\r
4446 //#define RESERVED (0x2000u) /* Reserved */\r
4447 //#define RESERVED (0x4000u) /* Reserved */\r
4448 //#define RESERVED (0x8000u) /* Reserved */\r
4449 \r
4450 /* REFCTL0 Control Bits */\r
4451 //#define RESERVED (0x0004u) /* Reserved */\r
4452 //#define RESERVED (0x0040u) /* Reserved */\r
4453 #define REFGENACT_H (0x0001u) /* REF Reference generator active */\r
4454 #define REFBGACT_H (0x0002u) /* REF Reference bandgap active */\r
4455 #define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */\r
4456 #define BGMODE_H (0x0008u) /* REF Bandgap mode */\r
4457 //#define RESERVED (0x1000u) /* Reserved */\r
4458 //#define RESERVED (0x2000u) /* Reserved */\r
4459 //#define RESERVED (0x4000u) /* Reserved */\r
4460 //#define RESERVED (0x8000u) /* Reserved */\r
4461 \r
4462 #define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */\r
4463 #define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */\r
4464 #define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */\r
4465 #define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */\r
4466 \r
4467 #endif\r
4468 /************************************************************\r
4469 * Shared Reference\r
4470 ************************************************************/\r
4471 #ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */\r
4472 \r
4473 #define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */\r
4474 #define OFS_REFCTL0_L OFS_REFCTL0\r
4475 #define OFS_REFCTL0_H OFS_REFCTL0+1\r
4476 \r
4477 /* REFCTL0 Control Bits */\r
4478 #define REFON (0x0001u) /* REF Reference On */\r
4479 //#define RESERVED (0x0002u) /* Reserved */\r
4480 //#define RESERVED (0x0004u) /* Reserved */\r
4481 #define REFTCOFF (0x0008u) /* REF Temp.Sensor off */\r
4482 #define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
4483 #define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
4484 //#define RESERVED (0x0040u) /* Reserved */\r
4485 //#define RESERVED (0x0080u) /* Reserved */\r
4486 #define REFGENACT (0x0100u) /* REF Reference generator active */\r
4487 #define REFBGACT (0x0200u) /* REF Reference bandgap active */\r
4488 #define REFGENBUSY (0x0400u) /* REF Reference generator busy */\r
4489 #define BGMODE (0x0800u) /* REF Bandgap mode */\r
4490 //#define RESERVED (0x1000u) /* Reserved */\r
4491 //#define RESERVED (0x2000u) /* Reserved */\r
4492 //#define RESERVED (0x4000u) /* Reserved */\r
4493 //#define RESERVED (0x8000u) /* Reserved */\r
4494 \r
4495 /* REFCTL0 Control Bits */\r
4496 #define REFON_L (0x0001u) /* REF Reference On */\r
4497 //#define RESERVED (0x0002u) /* Reserved */\r
4498 //#define RESERVED (0x0004u) /* Reserved */\r
4499 #define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */\r
4500 #define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
4501 #define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
4502 //#define RESERVED (0x0040u) /* Reserved */\r
4503 //#define RESERVED (0x0080u) /* Reserved */\r
4504 //#define RESERVED (0x1000u) /* Reserved */\r
4505 //#define RESERVED (0x2000u) /* Reserved */\r
4506 //#define RESERVED (0x4000u) /* Reserved */\r
4507 //#define RESERVED (0x8000u) /* Reserved */\r
4508 \r
4509 /* REFCTL0 Control Bits */\r
4510 //#define RESERVED (0x0002u) /* Reserved */\r
4511 //#define RESERVED (0x0004u) /* Reserved */\r
4512 //#define RESERVED (0x0040u) /* Reserved */\r
4513 //#define RESERVED (0x0080u) /* Reserved */\r
4514 #define REFGENACT_H (0x0001u) /* REF Reference generator active */\r
4515 #define REFBGACT_H (0x0002u) /* REF Reference bandgap active */\r
4516 #define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */\r
4517 #define BGMODE_H (0x0008u) /* REF Bandgap mode */\r
4518 //#define RESERVED (0x1000u) /* Reserved */\r
4519 //#define RESERVED (0x2000u) /* Reserved */\r
4520 //#define RESERVED (0x4000u) /* Reserved */\r
4521 //#define RESERVED (0x8000u) /* Reserved */\r
4522 \r
4523 #define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */\r
4524 #define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */\r
4525 #define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */\r
4526 #define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */\r
4527 \r
4528 #endif\r
4529 /************************************************************\r
4530 * Real Time Clock\r
4531 ************************************************************/\r
4532 #ifdef __MSP430_HAS_RTC__ /* Definition to show that Module is available */\r
4533 \r
4534 #define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */\r
4535 #define OFS_RTCCTL01_L OFS_RTCCTL01\r
4536 #define OFS_RTCCTL01_H OFS_RTCCTL01+1\r
4537 #define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */\r
4538 #define OFS_RTCCTL23_L OFS_RTCCTL23\r
4539 #define OFS_RTCCTL23_H OFS_RTCCTL23+1\r
4540 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
4541 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
4542 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
4543 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
4544 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
4545 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
4546 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
4547 #define OFS_RTCPS_L OFS_RTCPS\r
4548 #define OFS_RTCPS_H OFS_RTCPS+1\r
4549 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
4550 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
4551 #define OFS_RTCTIM0_L OFS_RTCTIM0\r
4552 #define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
4553 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
4554 #define OFS_RTCTIM1_L OFS_RTCTIM1\r
4555 #define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
4556 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
4557 #define OFS_RTCDATE_L OFS_RTCDATE\r
4558 #define OFS_RTCDATE_H OFS_RTCDATE+1\r
4559 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
4560 #define OFS_RTCYEAR_L OFS_RTCYEAR\r
4561 #define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
4562 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
4563 #define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
4564 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
4565 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
4566 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
4567 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
4568 #define OFS_RTCSEC (0x0010u)\r
4569 #define OFS_RTCMIN (0x0011u)\r
4570 #define OFS_RTCHOUR (0x0012u)\r
4571 #define OFS_RTCDOW (0x0013u)\r
4572 #define OFS_RTCDAY (0x0014u)\r
4573 #define OFS_RTCMON (0x0015u)\r
4574 #define OFS_RTCAMIN (0x0018u)\r
4575 #define OFS_RTCAHOUR (0x0019u)\r
4576 #define OFS_RTCADOW (0x001Au)\r
4577 #define OFS_RTCADAY (0x001Bu)\r
4578 \r
4579 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */\r
4580 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */\r
4581 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */\r
4582 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */\r
4583 #define RTCNT12 RTCTIM0\r
4584 #define RTCNT34 RTCTIM1\r
4585 #define RTCNT1 RTCTIM0_L\r
4586 #define RTCNT2 RTCTIM0_H\r
4587 #define RTCNT3 RTCTIM1_L\r
4588 #define RTCNT4 RTCTIM1_H\r
4589 #define RTCSEC RTCTIM0_L\r
4590 #define RTCMIN RTCTIM0_H\r
4591 #define RTCHOUR RTCTIM1_L\r
4592 #define RTCDOW RTCTIM1_H\r
4593 #define RTCDAY RTCDATE_L\r
4594 #define RTCMON RTCDATE_H\r
4595 #define RTCYEARL RTCYEAR_L\r
4596 #define RTCYEARH RTCYEAR_H\r
4597 #define RT0PS RTCPS_L\r
4598 #define RT1PS RTCPS_H\r
4599 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
4600 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
4601 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
4602 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
4603 \r
4604 /* RTCCTL01 Control Bits */\r
4605 #define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */\r
4606 #define RTCHOLD (0x4000u) /* RTC Hold */\r
4607 #define RTCMODE (0x2000u) /* RTC Mode 0:Counter / 1: Calendar */\r
4608 #define RTCRDY (0x1000u) /* RTC Ready */\r
4609 #define RTCSSEL1 (0x0800u) /* RTC Source Select 1 */\r
4610 #define RTCSSEL0 (0x0400u) /* RTC Source Select 0 */\r
4611 #define RTCTEV1 (0x0200u) /* RTC Time Event 1 */\r
4612 #define RTCTEV0 (0x0100u) /* RTC Time Event 0 */\r
4613 //#define Reserved (0x0080u)\r
4614 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
4615 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
4616 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
4617 //#define Reserved (0x0008u)\r
4618 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
4619 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
4620 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
4621 \r
4622 /* RTCCTL01 Control Bits */\r
4623 //#define Reserved (0x0080u)\r
4624 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
4625 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
4626 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
4627 //#define Reserved (0x0008u)\r
4628 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
4629 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
4630 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
4631 \r
4632 /* RTCCTL01 Control Bits */\r
4633 #define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
4634 #define RTCHOLD_H (0x0040u) /* RTC Hold */\r
4635 #define RTCMODE_H (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
4636 #define RTCRDY_H (0x0010u) /* RTC Ready */\r
4637 #define RTCSSEL1_H (0x0008u) /* RTC Source Select 1 */\r
4638 #define RTCSSEL0_H (0x0004u) /* RTC Source Select 0 */\r
4639 #define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */\r
4640 #define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */\r
4641 //#define Reserved (0x0080u)\r
4642 //#define Reserved (0x0008u)\r
4643 \r
4644 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */\r
4645 #define RTCSSEL_1 (0x0400u) /* RTC Source Select SMCLK */\r
4646 #define RTCSSEL_2 (0x0800u) /* RTC Source Select RT1PS */\r
4647 #define RTCSSEL_3 (0x0C00u) /* RTC Source Select RT1PS */\r
4648 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */\r
4649 #define RTCSSEL__SMCLK (0x0400u) /* RTC Source Select SMCLK */\r
4650 #define RTCSSEL__RT1PS (0x0800u) /* RTC Source Select RT1PS */\r
4651 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
4652 #define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
4653 #define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */\r
4654 #define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */\r
4655 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
4656 #define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
4657 #define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */\r
4658 #define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */\r
4659 \r
4660 /* RTCCTL23 Control Bits */\r
4661 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
4662 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
4663 #define RTCCALS (0x0080u) /* RTC Calibration Sign */\r
4664 //#define Reserved (0x0040u)\r
4665 #define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */\r
4666 #define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */\r
4667 #define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */\r
4668 #define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */\r
4669 #define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */\r
4670 #define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */\r
4671 \r
4672 /* RTCCTL23 Control Bits */\r
4673 #define RTCCALS_L (0x0080u) /* RTC Calibration Sign */\r
4674 //#define Reserved (0x0040u)\r
4675 #define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */\r
4676 #define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */\r
4677 #define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */\r
4678 #define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */\r
4679 #define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */\r
4680 #define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */\r
4681 \r
4682 /* RTCCTL23 Control Bits */\r
4683 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
4684 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
4685 //#define Reserved (0x0040u)\r
4686 \r
4687 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
4688 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
4689 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
4690 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
4691 \r
4692 #define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
4693 \r
4694 /* RTCPS0CTL Control Bits */\r
4695 //#define Reserved (0x8000u)\r
4696 #define RT0SSEL (0x4000u) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */\r
4697 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
4698 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
4699 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
4700 //#define Reserved (0x0400u)\r
4701 //#define Reserved (0x0200u)\r
4702 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */\r
4703 //#define Reserved (0x0080u)\r
4704 //#define Reserved (0x0040u)\r
4705 //#define Reserved (0x0020u)\r
4706 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
4707 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
4708 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
4709 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
4710 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
4711 \r
4712 /* RTCPS0CTL Control Bits */\r
4713 //#define Reserved (0x8000u)\r
4714 //#define Reserved (0x0400u)\r
4715 //#define Reserved (0x0200u)\r
4716 //#define Reserved (0x0080u)\r
4717 //#define Reserved (0x0040u)\r
4718 //#define Reserved (0x0020u)\r
4719 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
4720 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
4721 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
4722 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
4723 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
4724 \r
4725 /* RTCPS0CTL Control Bits */\r
4726 //#define Reserved (0x8000u)\r
4727 #define RT0SSEL_H (0x0040u) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */\r
4728 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
4729 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
4730 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
4731 //#define Reserved (0x0400u)\r
4732 //#define Reserved (0x0200u)\r
4733 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */\r
4734 //#define Reserved (0x0080u)\r
4735 //#define Reserved (0x0040u)\r
4736 //#define Reserved (0x0020u)\r
4737 \r
4738 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
4739 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
4740 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
4741 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
4742 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
4743 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
4744 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
4745 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
4746 \r
4747 #define RT0PSDIV_0 (0x0000u) /* RTC Prescale Timer 0 Clock Divide /2 */\r
4748 #define RT0PSDIV_1 (0x0800u) /* RTC Prescale Timer 0 Clock Divide /4 */\r
4749 #define RT0PSDIV_2 (0x1000u) /* RTC Prescale Timer 0 Clock Divide /8 */\r
4750 #define RT0PSDIV_3 (0x1800u) /* RTC Prescale Timer 0 Clock Divide /16 */\r
4751 #define RT0PSDIV_4 (0x2000u) /* RTC Prescale Timer 0 Clock Divide /32 */\r
4752 #define RT0PSDIV_5 (0x2800u) /* RTC Prescale Timer 0 Clock Divide /64 */\r
4753 #define RT0PSDIV_6 (0x3000u) /* RTC Prescale Timer 0 Clock Divide /128 */\r
4754 #define RT0PSDIV_7 (0x3800u) /* RTC Prescale Timer 0 Clock Divide /256 */\r
4755 \r
4756 /* RTCPS1CTL Control Bits */\r
4757 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
4758 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
4759 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
4760 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
4761 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
4762 //#define Reserved (0x0400u)\r
4763 //#define Reserved (0x0200u)\r
4764 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */\r
4765 //#define Reserved (0x0080u)\r
4766 //#define Reserved (0x0040u)\r
4767 //#define Reserved (0x0020u)\r
4768 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
4769 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
4770 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
4771 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
4772 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
4773 \r
4774 /* RTCPS1CTL Control Bits */\r
4775 //#define Reserved (0x0400u)\r
4776 //#define Reserved (0x0200u)\r
4777 //#define Reserved (0x0080u)\r
4778 //#define Reserved (0x0040u)\r
4779 //#define Reserved (0x0020u)\r
4780 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
4781 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
4782 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
4783 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
4784 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
4785 \r
4786 /* RTCPS1CTL Control Bits */\r
4787 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
4788 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
4789 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
4790 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
4791 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
4792 //#define Reserved (0x0400u)\r
4793 //#define Reserved (0x0200u)\r
4794 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */\r
4795 //#define Reserved (0x0080u)\r
4796 //#define Reserved (0x0040u)\r
4797 //#define Reserved (0x0020u)\r
4798 \r
4799 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
4800 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
4801 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
4802 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
4803 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
4804 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
4805 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
4806 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
4807 \r
4808 #define RT1PSDIV_0 (0x0000u) /* RTC Prescale Timer 1 Clock Divide /2 */\r
4809 #define RT1PSDIV_1 (0x0800u) /* RTC Prescale Timer 1 Clock Divide /4 */\r
4810 #define RT1PSDIV_2 (0x1000u) /* RTC Prescale Timer 1 Clock Divide /8 */\r
4811 #define RT1PSDIV_3 (0x1800u) /* RTC Prescale Timer 1 Clock Divide /16 */\r
4812 #define RT1PSDIV_4 (0x2000u) /* RTC Prescale Timer 1 Clock Divide /32 */\r
4813 #define RT1PSDIV_5 (0x2800u) /* RTC Prescale Timer 1 Clock Divide /64 */\r
4814 #define RT1PSDIV_6 (0x3000u) /* RTC Prescale Timer 1 Clock Divide /128 */\r
4815 #define RT1PSDIV_7 (0x3800u) /* RTC Prescale Timer 1 Clock Divide /256 */\r
4816 \r
4817 #define RT1SSEL_0 (0x0000u) /* RTC Prescale Timer Source Select ACLK */\r
4818 #define RT1SSEL_1 (0x4000u) /* RTC Prescale Timer Source Select SMCLK */\r
4819 #define RT1SSEL_2 (0x8000u) /* RTC Prescale Timer Source Select RT0PS */\r
4820 #define RT1SSEL_3 (0xC000u) /* RTC Prescale Timer Source Select RT0PS */\r
4821 \r
4822 /* RTC Definitions */\r
4823 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
4824 #define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
4825 #define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
4826 #define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
4827 #define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
4828 #define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
4829 \r
4830 /* Legacy Definitions */\r
4831 #define RTC_NONE (0x0000u) /* No Interrupt pending */\r
4832 #define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
4833 #define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
4834 #define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
4835 #define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
4836 #define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
4837 \r
4838 #endif\r
4839 /************************************************************\r
4840 * Real Time Clock\r
4841 ************************************************************/\r
4842 #ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */\r
4843 \r
4844 #define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */\r
4845 #define OFS_RTCCTL01_L OFS_RTCCTL01\r
4846 #define OFS_RTCCTL01_H OFS_RTCCTL01+1\r
4847 #define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */\r
4848 #define OFS_RTCCTL23_L OFS_RTCCTL23\r
4849 #define OFS_RTCCTL23_H OFS_RTCCTL23+1\r
4850 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
4851 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
4852 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
4853 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
4854 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
4855 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
4856 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
4857 #define OFS_RTCPS_L OFS_RTCPS\r
4858 #define OFS_RTCPS_H OFS_RTCPS+1\r
4859 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
4860 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
4861 #define OFS_RTCTIM0_L OFS_RTCTIM0\r
4862 #define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
4863 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
4864 #define OFS_RTCTIM1_L OFS_RTCTIM1\r
4865 #define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
4866 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
4867 #define OFS_RTCDATE_L OFS_RTCDATE\r
4868 #define OFS_RTCDATE_H OFS_RTCDATE+1\r
4869 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
4870 #define OFS_RTCYEAR_L OFS_RTCYEAR\r
4871 #define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
4872 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
4873 #define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
4874 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
4875 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
4876 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
4877 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
4878 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
4879 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
4880 #define OFS_RTCSEC (0x0010u)\r
4881 #define OFS_RTCMIN (0x0011u)\r
4882 #define OFS_RTCHOUR (0x0012u)\r
4883 #define OFS_RTCDOW (0x0013u)\r
4884 #define OFS_RTCDAY (0x0014u)\r
4885 #define OFS_RTCMON (0x0015u)\r
4886 #define OFS_RTCAMIN (0x0018u)\r
4887 #define OFS_RTCAHOUR (0x0019u)\r
4888 #define OFS_RTCADOW (0x001Au)\r
4889 #define OFS_RTCADAY (0x001Bu)\r
4890 \r
4891 #define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */\r
4892 #define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */\r
4893 #define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */\r
4894 #define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */\r
4895 #define RTCNT12 RTCTIM0\r
4896 #define RTCNT34 RTCTIM1\r
4897 #define RTCNT1 RTCTIM0_L\r
4898 #define RTCNT2 RTCTIM0_H\r
4899 #define RTCNT3 RTCTIM1_L\r
4900 #define RTCNT4 RTCTIM1_H\r
4901 #define RTCSEC RTCTIM0_L\r
4902 #define RTCMIN RTCTIM0_H\r
4903 #define RTCHOUR RTCTIM1_L\r
4904 #define RTCDOW RTCTIM1_H\r
4905 #define RTCDAY RTCDATE_L\r
4906 #define RTCMON RTCDATE_H\r
4907 #define RTCYEARL RTCYEAR_L\r
4908 #define RTCYEARH RTCYEAR_H\r
4909 #define RT0PS RTCPS_L\r
4910 #define RT1PS RTCPS_H\r
4911 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
4912 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
4913 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
4914 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
4915 \r
4916 /* RTCCTL01 Control Bits */\r
4917 #define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */\r
4918 #define RTCHOLD (0x4000u) /* RTC Hold */\r
4919 //#define RESERVED (0x2000u) /* RESERVED */\r
4920 #define RTCRDY (0x1000u) /* RTC Ready */\r
4921 //#define RESERVED (0x0800u) /* RESERVED */\r
4922 //#define RESERVED (0x0400u) /* RESERVED */\r
4923 #define RTCTEV1 (0x0200u) /* RTC Time Event 1 */\r
4924 #define RTCTEV0 (0x0100u) /* RTC Time Event 0 */\r
4925 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
4926 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
4927 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
4928 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
4929 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
4930 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
4931 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
4932 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
4933 \r
4934 /* RTCCTL01 Control Bits */\r
4935 //#define RESERVED (0x2000u) /* RESERVED */\r
4936 //#define RESERVED (0x0800u) /* RESERVED */\r
4937 //#define RESERVED (0x0400u) /* RESERVED */\r
4938 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
4939 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
4940 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
4941 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
4942 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
4943 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
4944 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
4945 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
4946 \r
4947 /* RTCCTL01 Control Bits */\r
4948 #define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
4949 #define RTCHOLD_H (0x0040u) /* RTC Hold */\r
4950 //#define RESERVED (0x2000u) /* RESERVED */\r
4951 #define RTCRDY_H (0x0010u) /* RTC Ready */\r
4952 //#define RESERVED (0x0800u) /* RESERVED */\r
4953 //#define RESERVED (0x0400u) /* RESERVED */\r
4954 #define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */\r
4955 #define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */\r
4956 \r
4957 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
4958 #define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
4959 #define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */\r
4960 #define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */\r
4961 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
4962 #define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
4963 #define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */\r
4964 #define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */\r
4965 \r
4966 /* RTCCTL23 Control Bits */\r
4967 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
4968 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
4969 #define RTCCALS (0x0080u) /* RTC Calibration Sign */\r
4970 //#define Reserved (0x0040u)\r
4971 #define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */\r
4972 #define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */\r
4973 #define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */\r
4974 #define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */\r
4975 #define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */\r
4976 #define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */\r
4977 \r
4978 /* RTCCTL23 Control Bits */\r
4979 #define RTCCALS_L (0x0080u) /* RTC Calibration Sign */\r
4980 //#define Reserved (0x0040u)\r
4981 #define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */\r
4982 #define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */\r
4983 #define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */\r
4984 #define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */\r
4985 #define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */\r
4986 #define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */\r
4987 \r
4988 /* RTCCTL23 Control Bits */\r
4989 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
4990 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
4991 //#define Reserved (0x0040u)\r
4992 \r
4993 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
4994 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
4995 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
4996 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
4997 \r
4998 #define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
4999 \r
5000 /* RTCPS0CTL Control Bits */\r
5001 //#define Reserved (0x0080u)\r
5002 //#define Reserved (0x0040u)\r
5003 //#define Reserved (0x0020u)\r
5004 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
5005 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
5006 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
5007 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
5008 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
5009 \r
5010 /* RTCPS0CTL Control Bits */\r
5011 //#define Reserved (0x0080u)\r
5012 //#define Reserved (0x0040u)\r
5013 //#define Reserved (0x0020u)\r
5014 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
5015 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
5016 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
5017 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
5018 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
5019 \r
5020 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
5021 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
5022 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
5023 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
5024 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
5025 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
5026 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
5027 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
5028 \r
5029 #define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
5030 #define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
5031 #define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
5032 #define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
5033 #define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
5034 #define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
5035 #define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
5036 #define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
5037 \r
5038 /* RTCPS1CTL Control Bits */\r
5039 //#define Reserved (0x0080u)\r
5040 //#define Reserved (0x0040u)\r
5041 //#define Reserved (0x0020u)\r
5042 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
5043 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
5044 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
5045 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
5046 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
5047 \r
5048 /* RTCPS1CTL Control Bits */\r
5049 //#define Reserved (0x0080u)\r
5050 //#define Reserved (0x0040u)\r
5051 //#define Reserved (0x0020u)\r
5052 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
5053 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
5054 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
5055 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
5056 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
5057 \r
5058 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
5059 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
5060 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
5061 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
5062 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
5063 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
5064 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
5065 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
5066 \r
5067 #define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
5068 #define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
5069 #define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
5070 #define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
5071 #define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
5072 #define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
5073 #define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
5074 #define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
5075 \r
5076 /* RTC Definitions */\r
5077 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
5078 #define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
5079 #define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
5080 #define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
5081 #define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
5082 #define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
5083 #define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */\r
5084 \r
5085 /* Legacy Definitions */\r
5086 #define RTC_NONE (0x0000u) /* No Interrupt pending */\r
5087 #define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
5088 #define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
5089 #define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
5090 #define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
5091 #define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
5092 #define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */\r
5093 \r
5094 #endif\r
5095 /************************************************************\r
5096 * Real Time Clock\r
5097 ************************************************************/\r
5098 #ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */\r
5099 \r
5100 #define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */\r
5101 #define OFS_RTCCTL0_L OFS_RTCCTL0\r
5102 #define OFS_RTCCTL0_H OFS_RTCCTL0+1\r
5103 #define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */\r
5104 #define OFS_RTCCTL13_L OFS_RTCCTL13\r
5105 #define OFS_RTCCTL13_H OFS_RTCCTL13+1\r
5106 #define RTCCTL1 RTCCTL13_L\r
5107 #define RTCCTL3 RTCCTL13_H\r
5108 #define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */\r
5109 #define OFS_RTCOCAL_L OFS_RTCOCAL\r
5110 #define OFS_RTCOCAL_H OFS_RTCOCAL+1\r
5111 #define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */\r
5112 #define OFS_RTCTCMP_L OFS_RTCTCMP\r
5113 #define OFS_RTCTCMP_H OFS_RTCTCMP+1\r
5114 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
5115 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
5116 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
5117 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
5118 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
5119 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
5120 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
5121 #define OFS_RTCPS_L OFS_RTCPS\r
5122 #define OFS_RTCPS_H OFS_RTCPS+1\r
5123 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
5124 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
5125 #define OFS_RTCTIM0_L OFS_RTCTIM0\r
5126 #define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
5127 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
5128 #define OFS_RTCTIM1_L OFS_RTCTIM1\r
5129 #define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
5130 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
5131 #define OFS_RTCDATE_L OFS_RTCDATE\r
5132 #define OFS_RTCDATE_H OFS_RTCDATE+1\r
5133 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
5134 #define OFS_RTCYEAR_L OFS_RTCYEAR\r
5135 #define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
5136 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
5137 #define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
5138 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
5139 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
5140 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
5141 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
5142 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
5143 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
5144 #define OFS_RTCSEC (0x0010u)\r
5145 #define OFS_RTCMIN (0x0011u)\r
5146 #define OFS_RTCHOUR (0x0012u)\r
5147 #define OFS_RTCDOW (0x0013u)\r
5148 #define OFS_RTCDAY (0x0014u)\r
5149 #define OFS_RTCMON (0x0015u)\r
5150 #define OFS_RTCAMIN (0x0018u)\r
5151 #define OFS_RTCAHOUR (0x0019u)\r
5152 #define OFS_RTCADOW (0x001Au)\r
5153 #define OFS_RTCADAY (0x001Bu)\r
5154 \r
5155 #define RTCSEC RTCTIM0_L\r
5156 #define RTCMIN RTCTIM0_H\r
5157 #define RTCHOUR RTCTIM1_L\r
5158 #define RTCDOW RTCTIM1_H\r
5159 #define RTCDAY RTCDATE_L\r
5160 #define RTCMON RTCDATE_H\r
5161 #define RTCYEARL RTCYEAR_L\r
5162 #define RT0PS RTCPS_L\r
5163 #define RT1PS RTCPS_H\r
5164 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
5165 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
5166 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
5167 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
5168 \r
5169 /* RTCCTL0 Control Bits */\r
5170 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
5171 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
5172 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
5173 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
5174 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
5175 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
5176 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
5177 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
5178 \r
5179 /* RTCCTL0 Control Bits */\r
5180 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
5181 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
5182 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
5183 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
5184 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
5185 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
5186 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
5187 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
5188 \r
5189 #define RTCKEY (0xA500u) /* RTC Key for RTC write access */\r
5190 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */\r
5191 \r
5192 /* RTCCTL13 Control Bits */\r
5193 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
5194 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
5195 #define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
5196 #define RTCHOLD (0x0040u) /* RTC Hold */\r
5197 #define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
5198 #define RTCRDY (0x0010u) /* RTC Ready */\r
5199 #define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */\r
5200 #define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */\r
5201 #define RTCTEV1 (0x0002u) /* RTC Time Event 1 */\r
5202 #define RTCTEV0 (0x0001u) /* RTC Time Event 0 */\r
5203 \r
5204 /* RTCCTL13 Control Bits */\r
5205 #define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
5206 #define RTCHOLD_L (0x0040u) /* RTC Hold */\r
5207 #define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
5208 #define RTCRDY_L (0x0010u) /* RTC Ready */\r
5209 #define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */\r
5210 #define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */\r
5211 #define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */\r
5212 #define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */\r
5213 \r
5214 /* RTCCTL13 Control Bits */\r
5215 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
5216 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
5217 \r
5218 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */\r
5219 #define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */\r
5220 #define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */\r
5221 #define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */\r
5222 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */\r
5223 #define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */\r
5224 #define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */\r
5225 \r
5226 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
5227 #define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
5228 #define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */\r
5229 #define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */\r
5230 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
5231 #define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
5232 #define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */\r
5233 #define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */\r
5234 \r
5235 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
5236 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
5237 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
5238 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
5239 \r
5240 /* RTCOCAL Control Bits */\r
5241 #define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */\r
5242 #define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */\r
5243 #define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */\r
5244 #define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */\r
5245 #define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */\r
5246 #define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */\r
5247 #define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */\r
5248 #define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */\r
5249 #define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */\r
5250 \r
5251 /* RTCOCAL Control Bits */\r
5252 #define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */\r
5253 #define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */\r
5254 #define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */\r
5255 #define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */\r
5256 #define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */\r
5257 #define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */\r
5258 #define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */\r
5259 #define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */\r
5260 \r
5261 /* RTCOCAL Control Bits */\r
5262 #define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */\r
5263 \r
5264 /* RTCTCMP Control Bits */\r
5265 #define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */\r
5266 #define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */\r
5267 #define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */\r
5268 #define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
5269 #define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
5270 #define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
5271 #define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
5272 #define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
5273 #define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
5274 #define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
5275 #define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
5276 \r
5277 /* RTCTCMP Control Bits */\r
5278 #define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
5279 #define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
5280 #define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
5281 #define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
5282 #define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
5283 #define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
5284 #define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
5285 #define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
5286 \r
5287 /* RTCTCMP Control Bits */\r
5288 #define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */\r
5289 #define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */\r
5290 #define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */\r
5291 \r
5292 #define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
5293 \r
5294 /* RTCPS0CTL Control Bits */\r
5295 //#define Reserved (0x8000u)\r
5296 //#define Reserved (0x4000u)\r
5297 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
5298 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
5299 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
5300 //#define Reserved (0x0400u)\r
5301 //#define Reserved (0x0200u)\r
5302 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */\r
5303 //#define Reserved (0x0080u)\r
5304 //#define Reserved (0x0040u)\r
5305 //#define Reserved (0x0020u)\r
5306 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
5307 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
5308 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
5309 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
5310 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
5311 \r
5312 /* RTCPS0CTL Control Bits */\r
5313 //#define Reserved (0x8000u)\r
5314 //#define Reserved (0x4000u)\r
5315 //#define Reserved (0x0400u)\r
5316 //#define Reserved (0x0200u)\r
5317 //#define Reserved (0x0080u)\r
5318 //#define Reserved (0x0040u)\r
5319 //#define Reserved (0x0020u)\r
5320 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
5321 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
5322 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
5323 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
5324 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
5325 \r
5326 /* RTCPS0CTL Control Bits */\r
5327 //#define Reserved (0x8000u)\r
5328 //#define Reserved (0x4000u)\r
5329 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
5330 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
5331 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
5332 //#define Reserved (0x0400u)\r
5333 //#define Reserved (0x0200u)\r
5334 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */\r
5335 //#define Reserved (0x0080u)\r
5336 //#define Reserved (0x0040u)\r
5337 //#define Reserved (0x0020u)\r
5338 \r
5339 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
5340 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
5341 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
5342 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
5343 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
5344 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
5345 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
5346 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
5347 \r
5348 /* RTCPS1CTL Control Bits */\r
5349 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
5350 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
5351 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
5352 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
5353 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
5354 //#define Reserved (0x0400u)\r
5355 //#define Reserved (0x0200u)\r
5356 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */\r
5357 //#define Reserved (0x0080u)\r
5358 //#define Reserved (0x0040u)\r
5359 //#define Reserved (0x0020u)\r
5360 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
5361 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
5362 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
5363 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
5364 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
5365 \r
5366 /* RTCPS1CTL Control Bits */\r
5367 //#define Reserved (0x0400u)\r
5368 //#define Reserved (0x0200u)\r
5369 //#define Reserved (0x0080u)\r
5370 //#define Reserved (0x0040u)\r
5371 //#define Reserved (0x0020u)\r
5372 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
5373 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
5374 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
5375 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
5376 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
5377 \r
5378 /* RTCPS1CTL Control Bits */\r
5379 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
5380 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
5381 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
5382 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
5383 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
5384 //#define Reserved (0x0400u)\r
5385 //#define Reserved (0x0200u)\r
5386 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */\r
5387 //#define Reserved (0x0080u)\r
5388 //#define Reserved (0x0040u)\r
5389 //#define Reserved (0x0020u)\r
5390 \r
5391 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
5392 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
5393 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
5394 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
5395 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
5396 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
5397 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
5398 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
5399 \r
5400 /* RTC Definitions */\r
5401 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
5402 #define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
5403 #define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */\r
5404 #define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */\r
5405 #define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */\r
5406 #define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */\r
5407 #define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */\r
5408 \r
5409 /* Legacy Definitions */\r
5410 #define RTC_NONE (0x0000u) /* No Interrupt pending */\r
5411 #define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
5412 #define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */\r
5413 #define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */\r
5414 #define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */\r
5415 #define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */\r
5416 #define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */\r
5417 \r
5418 #endif\r
5419 /************************************************************\r
5420 * Real Time Clock\r
5421 ************************************************************/\r
5422 #ifdef __MSP430_HAS_RTC_CE__ /* Definition to show that Module is available */\r
5423 \r
5424 #define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */\r
5425 #define OFS_RTCCTL0_L OFS_RTCCTL0\r
5426 #define OFS_RTCCTL0_H OFS_RTCCTL0+1\r
5427 #define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */\r
5428 #define OFS_RTCCTL13_L OFS_RTCCTL13\r
5429 #define OFS_RTCCTL13_H OFS_RTCCTL13+1\r
5430 #define RTCCTL1 RTCCTL13_L\r
5431 #define RTCCTL3 RTCCTL13_H\r
5432 #define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */\r
5433 #define OFS_RTCOCAL_L OFS_RTCOCAL\r
5434 #define OFS_RTCOCAL_H OFS_RTCOCAL+1\r
5435 #define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */\r
5436 #define OFS_RTCTCMP_L OFS_RTCTCMP\r
5437 #define OFS_RTCTCMP_H OFS_RTCTCMP+1\r
5438 #define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
5439 #define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
5440 #define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
5441 #define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
5442 #define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
5443 #define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
5444 #define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
5445 #define OFS_RTCPS_L OFS_RTCPS\r
5446 #define OFS_RTCPS_H OFS_RTCPS+1\r
5447 #define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
5448 #define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
5449 #define OFS_RTCTIM0_L OFS_RTCTIM0\r
5450 #define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
5451 #define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
5452 #define OFS_RTCTIM1_L OFS_RTCTIM1\r
5453 #define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
5454 #define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
5455 #define OFS_RTCDATE_L OFS_RTCDATE\r
5456 #define OFS_RTCDATE_H OFS_RTCDATE+1\r
5457 #define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
5458 #define OFS_RTCYEAR_L OFS_RTCYEAR\r
5459 #define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
5460 #define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
5461 #define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
5462 #define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
5463 #define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
5464 #define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
5465 #define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
5466 #define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
5467 #define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
5468 #define OFS_RTCSEC (0x0010u)\r
5469 #define OFS_RTCMIN (0x0011u)\r
5470 #define OFS_RTCHOUR (0x0012u)\r
5471 #define OFS_RTCDOW (0x0013u)\r
5472 #define OFS_RTCDAY (0x0014u)\r
5473 #define OFS_RTCMON (0x0015u)\r
5474 #define OFS_RTCAMIN (0x0018u)\r
5475 #define OFS_RTCAHOUR (0x0019u)\r
5476 #define OFS_RTCADOW (0x001Au)\r
5477 #define OFS_RTCADAY (0x001Bu)\r
5478 \r
5479 #define OFS_RTCTCCTL0 (0x0020u) /* Real-Time Clock Time Capture Control Register 0 */\r
5480 #define OFS_RTCTCCTL1 (0x0021u) /* Real-Time Clock Time Capture Control Register 1 */\r
5481 #define OFS_RTCCAP0CTL (0x0022u) /* Tamper Detect Pin 0 Control Register */\r
5482 #define OFS_RTCCAP1CTL (0x0023u) /* Tamper Detect Pin 1 Control Register */\r
5483 #define OFS_RTCSECBAK0 (0x0030u) /* Real-Time Clock Seconds Backup Register 0 */\r
5484 #define OFS_RTCMINBAK0 (0x0031u) /* Real-Time Clock Minutes Backup Register 0 */\r
5485 #define OFS_RTCHOURBAK0 (0x0032u) /* Real-Time Clock Hours Backup Register 0 */\r
5486 #define OFS_RTCDAYBAK0 (0x0033u) /* Real-Time Clock Days Backup Register 0 */\r
5487 #define OFS_RTCMONBAK0 (0x0034u) /* Real-Time Clock Months Backup Register 0 */\r
5488 #define OFS_RTCYEARBAK0 (0x0036u) /* Real-Time Clock year Backup Register 0 */\r
5489 #define OFS_RTCSECBAK1 (0x0038u) /* Real-Time Clock Seconds Backup Register 1 */\r
5490 #define OFS_RTCMINBAK1 (0x0039u) /* Real-Time Clock Minutes Backup Register 1 */\r
5491 #define OFS_RTCHOURBAK1 (0x003Au) /* Real-Time Clock Hours Backup Register 1 */\r
5492 #define OFS_RTCDAYBAK1 (0x003Bu) /* Real-Time Clock Days Backup Register 1 */\r
5493 #define OFS_RTCMONBAK1 (0x003Cu) /* Real-Time Clock Months Backup Register 1 */\r
5494 #define OFS_RTCYEARBAK1 (0x003Eu) /* Real-Time Clock Year Backup Register 1 */\r
5495 \r
5496 #define RTCSEC RTCTIM0_L\r
5497 #define RTCMIN RTCTIM0_H\r
5498 #define RTCHOUR RTCTIM1_L\r
5499 #define RTCDOW RTCTIM1_H\r
5500 #define RTCDAY RTCDATE_L\r
5501 #define RTCMON RTCDATE_H\r
5502 #define RTCYEARL RTCYEAR_L\r
5503 #define RT0PS RTCPS_L\r
5504 #define RT1PS RTCPS_H\r
5505 #define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
5506 #define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
5507 #define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
5508 #define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
5509 \r
5510 /* RTCCTL0 Control Bits */\r
5511 #define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
5512 #define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
5513 #define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
5514 #define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
5515 #define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
5516 #define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
5517 #define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
5518 #define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
5519 \r
5520 /* RTCCTL0 Control Bits */\r
5521 #define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
5522 #define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
5523 #define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
5524 #define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
5525 #define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
5526 #define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
5527 #define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
5528 #define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
5529 \r
5530 #define RTCKEY (0xA500u) /* RTC Key for RTC write access */\r
5531 #define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */\r
5532 \r
5533 /* RTCCTL13 Control Bits */\r
5534 #define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
5535 #define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
5536 #define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
5537 #define RTCHOLD (0x0040u) /* RTC Hold */\r
5538 #define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
5539 #define RTCRDY (0x0010u) /* RTC Ready */\r
5540 #define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */\r
5541 #define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */\r
5542 #define RTCTEV1 (0x0002u) /* RTC Time Event 1 */\r
5543 #define RTCTEV0 (0x0001u) /* RTC Time Event 0 */\r
5544 \r
5545 /* RTCCTL13 Control Bits */\r
5546 #define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
5547 #define RTCHOLD_L (0x0040u) /* RTC Hold */\r
5548 #define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
5549 #define RTCRDY_L (0x0010u) /* RTC Ready */\r
5550 #define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */\r
5551 #define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */\r
5552 #define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */\r
5553 #define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */\r
5554 \r
5555 /* RTCCTL13 Control Bits */\r
5556 #define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
5557 #define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
5558 \r
5559 #define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */\r
5560 #define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */\r
5561 #define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */\r
5562 #define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */\r
5563 #define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */\r
5564 #define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */\r
5565 #define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */\r
5566 \r
5567 #define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
5568 #define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
5569 #define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */\r
5570 #define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */\r
5571 #define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
5572 #define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
5573 #define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */\r
5574 #define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */\r
5575 \r
5576 #define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
5577 #define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
5578 #define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
5579 #define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
5580 \r
5581 /* RTCOCAL Control Bits */\r
5582 #define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */\r
5583 #define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */\r
5584 #define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */\r
5585 #define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */\r
5586 #define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */\r
5587 #define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */\r
5588 #define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */\r
5589 #define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */\r
5590 #define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */\r
5591 \r
5592 /* RTCOCAL Control Bits */\r
5593 #define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */\r
5594 #define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */\r
5595 #define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */\r
5596 #define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */\r
5597 #define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */\r
5598 #define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */\r
5599 #define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */\r
5600 #define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */\r
5601 \r
5602 /* RTCOCAL Control Bits */\r
5603 #define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */\r
5604 \r
5605 /* RTCTCMP Control Bits */\r
5606 #define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */\r
5607 #define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */\r
5608 #define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */\r
5609 #define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
5610 #define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
5611 #define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
5612 #define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
5613 #define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
5614 #define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
5615 #define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
5616 #define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
5617 \r
5618 /* RTCTCMP Control Bits */\r
5619 #define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
5620 #define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
5621 #define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
5622 #define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
5623 #define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
5624 #define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
5625 #define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
5626 #define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
5627 \r
5628 /* RTCTCMP Control Bits */\r
5629 #define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */\r
5630 #define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */\r
5631 #define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */\r
5632 \r
5633 #define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
5634 \r
5635 /* RTCPS0CTL Control Bits */\r
5636 //#define Reserved (0x8000u)\r
5637 //#define Reserved (0x4000u)\r
5638 #define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
5639 #define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
5640 #define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
5641 //#define Reserved (0x0400u)\r
5642 //#define Reserved (0x0200u)\r
5643 #define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */\r
5644 //#define Reserved (0x0080u)\r
5645 //#define Reserved (0x0040u)\r
5646 //#define Reserved (0x0020u)\r
5647 #define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
5648 #define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
5649 #define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
5650 #define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
5651 #define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
5652 \r
5653 /* RTCPS0CTL Control Bits */\r
5654 //#define Reserved (0x8000u)\r
5655 //#define Reserved (0x4000u)\r
5656 //#define Reserved (0x0400u)\r
5657 //#define Reserved (0x0200u)\r
5658 //#define Reserved (0x0080u)\r
5659 //#define Reserved (0x0040u)\r
5660 //#define Reserved (0x0020u)\r
5661 #define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
5662 #define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
5663 #define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
5664 #define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
5665 #define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
5666 \r
5667 /* RTCPS0CTL Control Bits */\r
5668 //#define Reserved (0x8000u)\r
5669 //#define Reserved (0x4000u)\r
5670 #define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
5671 #define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
5672 #define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
5673 //#define Reserved (0x0400u)\r
5674 //#define Reserved (0x0200u)\r
5675 #define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */\r
5676 //#define Reserved (0x0080u)\r
5677 //#define Reserved (0x0040u)\r
5678 //#define Reserved (0x0020u)\r
5679 \r
5680 #define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
5681 #define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
5682 #define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
5683 #define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
5684 #define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
5685 #define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
5686 #define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
5687 #define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
5688 \r
5689 /* RTCPS1CTL Control Bits */\r
5690 #define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
5691 #define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
5692 #define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
5693 #define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
5694 #define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
5695 //#define Reserved (0x0400u)\r
5696 //#define Reserved (0x0200u)\r
5697 #define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */\r
5698 //#define Reserved (0x0080u)\r
5699 //#define Reserved (0x0040u)\r
5700 //#define Reserved (0x0020u)\r
5701 #define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
5702 #define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
5703 #define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
5704 #define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
5705 #define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
5706 \r
5707 /* RTCPS1CTL Control Bits */\r
5708 //#define Reserved (0x0400u)\r
5709 //#define Reserved (0x0200u)\r
5710 //#define Reserved (0x0080u)\r
5711 //#define Reserved (0x0040u)\r
5712 //#define Reserved (0x0020u)\r
5713 #define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
5714 #define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
5715 #define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
5716 #define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
5717 #define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
5718 \r
5719 /* RTCPS1CTL Control Bits */\r
5720 #define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
5721 #define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
5722 #define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
5723 #define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
5724 #define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
5725 //#define Reserved (0x0400u)\r
5726 //#define Reserved (0x0200u)\r
5727 #define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */\r
5728 //#define Reserved (0x0080u)\r
5729 //#define Reserved (0x0040u)\r
5730 //#define Reserved (0x0020u)\r
5731 \r
5732 #define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
5733 #define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
5734 #define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
5735 #define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
5736 #define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
5737 #define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
5738 #define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
5739 #define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
5740 \r
5741 /* RTCTCCTL0 Control Bits */\r
5742 #define TCEN (0x0001u) /* RTC Enable for RTC Tamper Detection with Time Stamp */\r
5743 #define AUX3RST (0x0002u) /* RTC Indication of power cycle on AUXVCC3 */\r
5744 \r
5745 /* RTCTCCTL1 Control Bits */\r
5746 #define RTCCAPIFG (0x0001u) /* RTC Tamper Event Interrupt Flag */\r
5747 #define RTCCAPIE (0x0002u) /* RTC Tamper Event Interrupt Enable */\r
5748 \r
5749 /* RTCCAPxCTL Control Bits */\r
5750 #define CAPEV (0x0001u) /* RTC Tamper Event Flag */\r
5751 #define CAPES (0x0004u) /* RTC Event Edge Select */\r
5752 #define RTCREN (0x0008u) /* RTC RTCCAPx pin pullup/pulldown resistor enable */\r
5753 #define RTCCAPIN (0x0010u) /* RTC RTCCAPx input */\r
5754 #define RTCCAPDIR (0x0020u) /* RTC RTCCAPx Pin direction */\r
5755 #define RTCCAPOUT (0x0040u) /* RTC RTCCAPx Output */\r
5756 \r
5757 /* RTCIV Definitions */\r
5758 #define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
5759 #define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
5760 #define RTCIV_RTCCAPIFG (0x0004u) /* RTC RTC Tamper Event: RTCCAPIFG */\r
5761 #define RTCIV_RTCRDYIFG (0x0006u) /* RTC ready: RTCRDYIFG */\r
5762 #define RTCIV_RTCTEVIFG (0x0008u) /* RTC interval timer: RTCTEVIFG */\r
5763 #define RTCIV_RTCAIFG (0x000Au) /* RTC user alarm: RTCAIFG */\r
5764 #define RTCIV_RT0PSIFG (0x000Cu) /* RTC prescaler 0: RT0PSIFG */\r
5765 #define RTCIV_RT1PSIFG (0x000Eu) /* RTC prescaler 1: RT1PSIFG */\r
5766 \r
5767 /* Legacy RTCIV Definitions */\r
5768 #define RTC_NONE (0x0000u) /* No Interrupt pending */\r
5769 #define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
5770 #define RTC_RTCRDYIFG (0x0006u) /* RTC ready: RTCRDYIFG */\r
5771 #define RTC_RTCTEVIFG (0x0008u) /* RTC interval timer: RTCTEVIFG */\r
5772 #define RTC_RTCAIFG (0x000Au) /* RTC user alarm: RTCAIFG */\r
5773 #define RTC_RT0PSIFG (0x000Cu) /* RTC prescaler 0: RT0PSIFG */\r
5774 #define RTC_RT1PSIFG (0x000Eu) /* RTC prescaler 1: RT1PSIFG */\r
5775 \r
5776 #endif\r
5777 /************************************************************\r
5778 * SD24_B - Sigma Delta 24 Bit\r
5779 ************************************************************/\r
5780 #ifdef __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */\r
5781 \r
5782 #define OFS_SD24BCTL0 (0x0000u) /* SD24B Control Register 0 */\r
5783 #define OFS_SD24BCTL0_L OFS_SD24BCTL0\r
5784 #define OFS_SD24BCTL0_H OFS_SD24BCTL0+1\r
5785 #define OFS_SD24BCTL1 (0x0002u) /* SD24B Control Register 1 */\r
5786 #define OFS_SD24BCTL1_L OFS_SD24BCTL1\r
5787 #define OFS_SD24BCTL1_H OFS_SD24BCTL1+1\r
5788 #define OFS_SD24BTRGCTL (0x0004u) /* SD24B Trigger Control Register */\r
5789 #define OFS_SD24BTRGCTL_L OFS_SD24BTRGCTL\r
5790 #define OFS_SD24BTRGCTL_H OFS_SD24BTRGCTL+1\r
5791 #define OFS_SD24BTRGOSR (0x0006u) /* SD24B Trigger OSR Control Register */\r
5792 #define OFS_SD24BTRGOSR_L OFS_SD24BTRGOSR\r
5793 #define OFS_SD24BTRGOSR_H OFS_SD24BTRGOSR+1\r
5794 #define OFS_SD24BTRGPRE (0x0008u) /* SD24B Trigger Preload Register */\r
5795 #define OFS_SD24BTRGPRE_L OFS_SD24BTRGPRE\r
5796 #define OFS_SD24BTRGPRE_H OFS_SD24BTRGPRE+1\r
5797 #define OFS_SD24BIFG (0x000Au) /* SD24B Interrupt Flag Register */\r
5798 #define OFS_SD24BIFG_L OFS_SD24BIFG\r
5799 #define OFS_SD24BIFG_H OFS_SD24BIFG+1\r
5800 #define OFS_SD24BIE (0x000Cu) /* SD24B Interrupt Enable Register */\r
5801 #define OFS_SD24BIE_L OFS_SD24BIE\r
5802 #define OFS_SD24BIE_H OFS_SD24BIE+1\r
5803 #define OFS_SD24BIV (0x000Eu) /* SD24B Interrupt Vector Register */\r
5804 #define OFS_SD24BIV_L OFS_SD24BIV\r
5805 #define OFS_SD24BIV_H OFS_SD24BIV+1\r
5806 \r
5807 #define OFS_SD24BCCTL0 (0x0010u) /* SD24B Channel 0 Control Register */\r
5808 #define OFS_SD24BCCTL0_L OFS_SD24BCCTL0\r
5809 #define OFS_SD24BCCTL0_H OFS_SD24BCCTL0+1\r
5810 #define OFS_SD24BINCTL0 (0x0012u) /* SD24B Channel 0 Input Control Register */\r
5811 #define OFS_SD24BINCTL0_L OFS_SD24BINCTL0\r
5812 #define OFS_SD24BINCTL0_H OFS_SD24BINCTL0+1\r
5813 #define OFS_SD24BOSR0 (0x0014u) /* SD24B Channel 0 OSR Control Register */\r
5814 #define OFS_SD24BOSR0_L OFS_SD24BOSR0\r
5815 #define OFS_SD24BOSR0_H OFS_SD24BOSR0+1\r
5816 #define OFS_SD24BPRE0 (0x0016u) /* SD24B Channel 0 Preload Register */\r
5817 #define OFS_SD24BPRE0_L OFS_SD24BPRE0\r
5818 #define OFS_SD24BPRE0_H OFS_SD24BPRE0+1\r
5819 \r
5820 #define OFS_SD24BMEML0 (0x0050u) /* SD24B Channel 0 Conversion Memory Low word */\r
5821 #define OFS_SD24BMEML0_L OFS_SD24BMEML0\r
5822 #define OFS_SD24BMEML0_H OFS_SD24BMEML0+1\r
5823 #define OFS_SD24BMEMH0 (0x0052u) /* SD24B Channel 0 Conversion Memory High Word */\r
5824 #define OFS_SD24BMEMH0_L OFS_SD24BMEMH0\r
5825 #define OFS_SD24BMEMH0_H OFS_SD24BMEMH0+1\r
5826 \r
5827 /* SD24BCTL0 */\r
5828 #define SD24OV32 (0x0002u) /* SD24B Overflow Control */\r
5829 #define SD24REFS (0x0004u) /* SD24B Reference Select */\r
5830 #define SD24SSEL0 (0x0010u) /* SD24B Clock Source Select 0 */\r
5831 #define SD24SSEL1 (0x0020u) /* SD24B Clock Source Select 1 */\r
5832 #define SD24M4 (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */\r
5833 #define SD24CLKOS (0x0080u) /* SD24B Clock Output Select */\r
5834 #define SD24PDIV0 (0x0100u) /* SD24B Frequency pre-scaler Bit 0 */\r
5835 #define SD24PDIV1 (0x0200u) /* SD24B Frequency pre-scaler Bit 1 */\r
5836 #define SD24PDIV2 (0x0400u) /* SD24B Frequency pre-scaler Bit 2 */\r
5837 #define SD24DIV0 (0x0800u) /* SD24B Frequency Divider Bit 0 */\r
5838 #define SD24DIV1 (0x1000u) /* SD24B Frequency Divider Bit 1 */\r
5839 #define SD24DIV2 (0x2000u) /* SD24B Frequency Divider Bit 2 */\r
5840 #define SD24DIV3 (0x4000u) /* SD24B Frequency Divider Bit 3 */\r
5841 #define SD24DIV4 (0x8000u) /* SD24B Frequency Divider Bit 4 */\r
5842 \r
5843 #define SD24OV32_L (0x0002u) /* SD24B Overflow Control */\r
5844 #define SD24REFS_L (0x0004u) /* SD24B Reference Select */\r
5845 #define SD24SSEL0_L (0x0010u) /* SD24B Clock Source Select 0 */\r
5846 #define SD24SSEL1_L (0x0020u) /* SD24B Clock Source Select 1 */\r
5847 #define SD24M4_L (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */\r
5848 #define SD24CLKOS_L (0x0080u) /* SD24B Clock Output Select */\r
5849 \r
5850 #define SD24PDIV0_H (0x0001u) /* SD24B Frequency pre-scaler Bit 0 */\r
5851 #define SD24PDIV1_H (0x0002u) /* SD24B Frequency pre-scaler Bit 1 */\r
5852 #define SD24PDIV2_H (0x0004u) /* SD24B Frequency pre-scaler Bit 2 */\r
5853 #define SD24DIV0_H (0x0008u) /* SD24B Frequency Divider Bit 0 */\r
5854 #define SD24DIV1_H (0x0010u) /* SD24B Frequency Divider Bit 1 */\r
5855 #define SD24DIV2_H (0x0020u) /* SD24B Frequency Divider Bit 2 */\r
5856 #define SD24DIV3_H (0x0040u) /* SD24B Frequency Divider Bit 3 */\r
5857 #define SD24DIV4_H (0x0080u) /* SD24B Frequency Divider Bit 4 */\r
5858 \r
5859 #define SD24SSEL_0 (0x0000u) /* SD24B Clock Source Select MCLK */\r
5860 #define SD24SSEL_1 (0x0010u) /* SD24B Clock Source Select SMCLK */\r
5861 #define SD24SSEL_2 (0x0020u) /* SD24B Clock Source Select ACLK */\r
5862 #define SD24SSEL_3 (0x0030u) /* SD24B Clock Source Select TACLK */\r
5863 #define SD24SSEL__MCLK (0x0000u) /* SD24B Clock Source Select MCLK */\r
5864 #define SD24SSEL__SMCLK (0x0010u) /* SD24B Clock Source Select SMCLK */\r
5865 #define SD24SSEL__ACLK (0x0020u) /* SD24B Clock Source Select ACLK */\r
5866 #define SD24SSEL__SD24CLK (0x0030u) /* SD24B Clock Source Select SD24CLK */\r
5867 \r
5868 #define SD24PDIV_0 (0x0000u) /* SD24B Frequency pre-scaler /1 */\r
5869 #define SD24PDIV_1 (0x0100u) /* SD24B Frequency pre-scaler /2 */\r
5870 #define SD24PDIV_2 (0x0200u) /* SD24B Frequency pre-scaler /4 */\r
5871 #define SD24PDIV_3 (0x0300u) /* SD24B Frequency pre-scaler /8 */\r
5872 #define SD24PDIV_4 (0x0400u) /* SD24B Frequency pre-scaler /16 */\r
5873 #define SD24PDIV_5 (0x0500u) /* SD24B Frequency pre-scaler /32 */\r
5874 #define SD24PDIV_6 (0x0600u) /* SD24B Frequency pre-scaler /64 */\r
5875 #define SD24PDIV_7 (0x0700u) /* SD24B Frequency pre-scaler /128 */\r
5876 \r
5877 /* SD24BCTL1 */\r
5878 #define SD24GRP0SC (0x0001u) /* SD24B Group 0 Start Conversion */\r
5879 #define SD24GRP1SC (0x0002u) /* SD24B Group 1 Start Conversion */\r
5880 #define SD24GRP2SC (0x0004u) /* SD24B Group 2 Start Conversion */\r
5881 #define SD24GRP3SC (0x0008u) /* SD24B Group 3 Start Conversion */\r
5882 #define SD24DMA0 (0x0100u) /* SD24B DMA Trigger Select Bit 0 */\r
5883 #define SD24DMA1 (0x0200u) /* SD24B DMA Trigger Select Bit 1 */\r
5884 #define SD24DMA2 (0x0400u) /* SD24B DMA Trigger Select Bit 2 */\r
5885 #define SD24DMA3 (0x0800u) /* SD24B DMA Trigger Select Bit 3 */\r
5886 \r
5887 #define SD24GRP0SC_L (0x0001u) /* SD24B Group 0 Start Conversion */\r
5888 #define SD24GRP1SC_L (0x0002u) /* SD24B Group 1 Start Conversion */\r
5889 #define SD24GRP2SC_L (0x0004u) /* SD24B Group 2 Start Conversion */\r
5890 #define SD24GRP3SC_L (0x0008u) /* SD24B Group 3 Start Conversion */\r
5891 \r
5892 #define SD24DMA0_H (0x0001u) /* SD24B DMA Trigger Select Bit 0 */\r
5893 #define SD24DMA1_H (0x0002u) /* SD24B DMA Trigger Select Bit 1 */\r
5894 #define SD24DMA2_H (0x0004u) /* SD24B DMA Trigger Select Bit 2 */\r
5895 #define SD24DMA3_H (0x0008u) /* SD24B DMA Trigger Select Bit 3 */\r
5896 \r
5897 #define SD24DMA_0 (0x0000u) /* SD24B DMA Trigger: 0 */\r
5898 #define SD24DMA_1 (0x0100u) /* SD24B DMA Trigger: 1 */\r
5899 #define SD24DMA_2 (0x0200u) /* SD24B DMA Trigger: 2 */\r
5900 #define SD24DMA_3 (0x0300u) /* SD24B DMA Trigger: 3 */\r
5901 #define SD24DMA_4 (0x0400u) /* SD24B DMA Trigger: 4 */\r
5902 #define SD24DMA_5 (0x0500u) /* SD24B DMA Trigger: 5 */\r
5903 #define SD24DMA_6 (0x0600u) /* SD24B DMA Trigger: 6 */\r
5904 #define SD24DMA_7 (0x0700u) /* SD24B DMA Trigger: 7 */\r
5905 #define SD24DMA_8 (0x0800u) /* SD24B DMA Trigger: 8 */\r
5906 \r
5907 /* SD24BTRGCTL */\r
5908 #define SD24SC (0x0001u) /* SD24B Start Conversion */\r
5909 #define SD24SCS0 (0x0002u) /* SD24B Start Conversion Select Bit 0 */\r
5910 #define SD24SCS1 (0x0004u) /* SD24B Start Conversion Select Bit 1 */\r
5911 #define SD24SCS2 (0x0008u) /* SD24B Start Conversion Select Bit 2 */\r
5912 #define SD24SNGL (0x0100u) /* SD24B Single Trigger Mode */\r
5913 #define SD24TRGIFG (0x0400u) /* SD24B Trigger Interrupt Flag */\r
5914 #define SD24TRGIE (0x0800u) /* SD24B Trigger Interrupt Enable */\r
5915 \r
5916 #define SD24SC_L (0x0001u) /* SD24B Start Conversion */\r
5917 #define SD24SCS0_L (0x0002u) /* SD24B Start Conversion Select Bit 0 */\r
5918 #define SD24SCS1_L (0x0004u) /* SD24B Start Conversion Select Bit 1 */\r
5919 #define SD24SCS2_L (0x0008u) /* SD24B Start Conversion Select Bit 2 */\r
5920 \r
5921 #define SD24SNGL_H (0x0001u) /* SD24B Single Trigger Mode */\r
5922 #define SD24TRGIFG_H (0x0004u) /* SD24B Trigger Interrupt Flag */\r
5923 #define SD24TRGIE_H (0x0008u) /* SD24B Trigger Interrupt Enable */\r
5924 \r
5925 #define SD24SCS_0 (0x0000u) /* SD24B Start Conversion Select: 0 */\r
5926 #define SD24SCS_1 (0x0002u) /* SD24B Start Conversion Select: 1 */\r
5927 #define SD24SCS_2 (0x0004u) /* SD24B Start Conversion Select: 2 */\r
5928 #define SD24SCS_3 (0x0006u) /* SD24B Start Conversion Select: 3 */\r
5929 #define SD24SCS_4 (0x0008u) /* SD24B Start Conversion Select: 4 */\r
5930 #define SD24SCS_5 (0x000Au) /* SD24B Start Conversion Select: 5 */\r
5931 #define SD24SCS_6 (0x000Cu) /* SD24B Start Conversion Select: 6 */\r
5932 #define SD24SCS_7 (0x000Eu) /* SD24B Start Conversion Select: 7 */\r
5933 #define SD24SCS__SD24SC (0x0000u) /* SD24B Start Conversion Select: SD24SC */\r
5934 #define SD24SCS__EXT1 (0x0002u) /* SD24B Start Conversion Select: EXT1 */\r
5935 #define SD24SCS__EXT2 (0x0004u) /* SD24B Start Conversion Select: EXT2 */\r
5936 #define SD24SCS__EXT3 (0x0006u) /* SD24B Start Conversion Select: EXT3 */\r
5937 #define SD24SCS__GROUP0 (0x0008u) /* SD24B Start Conversion Select: GROUP0 */\r
5938 #define SD24SCS__GROUP1 (0x000Au) /* SD24B Start Conversion Select: GROUP1 */\r
5939 #define SD24SCS__GROUP2 (0x000Cu) /* SD24B Start Conversion Select: GROUP2 */\r
5940 #define SD24SCS__GROUP3 (0x000Eu) /* SD24B Start Conversion Select: GROUP3 */\r
5941 \r
5942 /* SD24BIFG */\r
5943 #define SD24IFG0 (0x0001u) /* SD24B Channel 0 Interrupt Flag */\r
5944 #define SD24OVIFG0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Flag */\r
5945 \r
5946 #define SD24IFG0_L (0x0001u) /* SD24B Channel 0 Interrupt Flag */\r
5947 \r
5948 #define SD24OVIFG0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Flag */\r
5949 \r
5950 /* SD24BIE */\r
5951 #define SD24IE0 (0x0001u) /* SD24B Channel 0 Interrupt Enable */\r
5952 #define SD24OVIE0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Enable */\r
5953 \r
5954 #define SD24IE0_L (0x0001u) /* SD24B Channel 0 Interrupt Enable */\r
5955 \r
5956 #define SD24OVIE0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Enable */\r
5957 \r
5958 /* SD24BIV Definitions */\r
5959 #define SD24BIV_NONE (0x0000u) /* No Interrupt pending */\r
5960 #define SD24BIV_SD24OVIFG (0x0002u) /* SD24OVIFG */\r
5961 #define SD24BIV_SD24TRGIFG (0x0004u) /* SD24TRGIFG */\r
5962 #define SD24BIV_SD24IFG0 (0x0006u) /* SD24IFG0 */\r
5963 \r
5964 /* SD24BCCTLx */\r
5965 #define SD24DF0 (0x0010u) /* SD24B Data Format Bit: 0 */\r
5966 #define SD24DF1 (0x0020u) /* SD24B Data Format Bit: 1 */\r
5967 #define SD24ALGN (0x0040u) /* SD24B Data Alignment */\r
5968 #define SD24CAL (0x0200u) /* SD24B Calibration */\r
5969 #define SD24DFS0 (0x0400u) /* SD24B Digital Filter Bit: 0 */\r
5970 #define SD24DFS1 (0x0800u) /* SD24B Digital Filter Bit: 1 */\r
5971 #define SD24DI (0x1000u) /* SD24B Digital Bitstream Input */\r
5972 #define SD24MC0 (0x2000u) /* SD24B Manchaster Encoding Bit: 0 */\r
5973 #define SD24MC1 (0x4000u) /* SD24B Manchaster Encoding Bit: 1 */\r
5974 \r
5975 #define SD24DF0_L (0x0010u) /* SD24B Data Format Bit: 0 */\r
5976 #define SD24DF1_L (0x0020u) /* SD24B Data Format Bit: 1 */\r
5977 #define SD24ALGN_L (0x0040u) /* SD24B Data Alignment */\r
5978 \r
5979 #define SD24CAL_H (0x0002u) /* SD24B Calibration */\r
5980 #define SD24DFS0_H (0x0004u) /* SD24B Digital Filter Bit: 0 */\r
5981 #define SD24DFS1_H (0x0008u) /* SD24B Digital Filter Bit: 1 */\r
5982 #define SD24DI_H (0x0010u) /* SD24B Digital Bitstream Input */\r
5983 #define SD24MC0_H (0x0020u) /* SD24B Manchaster Encoding Bit: 0 */\r
5984 #define SD24MC1_H (0x0040u) /* SD24B Manchaster Encoding Bit: 1 */\r
5985 \r
5986 #define SD24DF_0 (0x0000u) /* SD24B Data Format: Offset Binary */\r
5987 #define SD24DF_1 (0x0010u) /* SD24B Data Format: 2's complement */\r
5988 \r
5989 #define SD24DFS_0 (0x0000u) /* SD24B Digital Filter 0 */\r
5990 #define SD24DFS_1 (0x0400u) /* SD24B Digital Filter 1 */\r
5991 #define SD24DFS_2 (0x0800u) /* SD24B Digital Filter 2 */\r
5992 #define SD24DFS_3 (0x0C00u) /* SD24B Digital Filter 3 */\r
5993 \r
5994 #define SD24MC_0 (0x0000u) /* SD24B Manchaster Encoding 0 */\r
5995 #define SD24MC_1 (0x2000u) /* SD24B Manchaster Encoding 1 */\r
5996 #define SD24MC_2 (0x4000u) /* SD24B Manchaster Encoding 2 */\r
5997 #define SD24MC_3 (0x6000u) /* SD24B Manchaster Encoding 3 */\r
5998 \r
5999 /* SD24BINCTLx */\r
6000 #define SD24GAIN0 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */\r
6001 #define SD24GAIN1 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */\r
6002 #define SD24GAIN2 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */\r
6003 #define SD24INTDLY0 (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */\r
6004 #define SD24INTDLY1 (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */\r
6005 \r
6006 #define SD24GAIN0_L (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */\r
6007 #define SD24GAIN1_L (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */\r
6008 #define SD24GAIN2_L (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */\r
6009 #define SD24INTDLY0_L (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */\r
6010 #define SD24INTDLY1_L (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */\r
6011 \r
6012 #define SD24GAIN_1 (0x0000u) /* SD24B Input Pre-Amplifier Gain Select *1 */\r
6013 #define SD24GAIN_2 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select *2 */\r
6014 #define SD24GAIN_4 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select *4 */\r
6015 #define SD24GAIN_8 (0x0018u) /* SD24B Input Pre-Amplifier Gain Select *8 */\r
6016 #define SD24GAIN_16 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select *16 */\r
6017 #define SD24GAIN_32 (0x0028u) /* SD24B Input Pre-Amplifier Gain Select *32 */\r
6018 #define SD24GAIN_64 (0x0030u) /* SD24B Input Pre-Amplifier Gain Select *64 */\r
6019 #define SD24GAIN_128 (0x0038u) /* SD24B Input Pre-Amplifier Gain Select *128 */\r
6020 \r
6021 #define SD24INTDLY_0 (0x0000u) /* SD24B Interrupt Delay: Int. after 4.Conversion */\r
6022 #define SD24INTDLY_1 (0x0040u) /* SD24B Interrupt Delay: Int. after 3.Conversion */\r
6023 #define SD24INTDLY_2 (0x0080u) /* SD24B Interrupt Delay: Int. after 2.Conversion */\r
6024 #define SD24INTDLY_3 (0x00C0u) /* SD24B Interrupt Delay: Int. after 1.Conversion */\r
6025 \r
6026 /* SD24BOSRx */\r
6027 #define OSR0 (0x0001u) /* SD24B Oversampling Rate Bit: 0 */\r
6028 #define OSR1 (0x0002u) /* SD24B Oversampling Rate Bit: 1 */\r
6029 #define OSR2 (0x0004u) /* SD24B Oversampling Rate Bit: 2 */\r
6030 #define OSR3 (0x0008u) /* SD24B Oversampling Rate Bit: 3 */\r
6031 #define OSR4 (0x0010u) /* SD24B Oversampling Rate Bit: 4 */\r
6032 #define OSR5 (0x0020u) /* SD24B Oversampling Rate Bit: 5 */\r
6033 #define OSR6 (0x0040u) /* SD24B Oversampling Rate Bit: 6 */\r
6034 #define OSR7 (0x0080u) /* SD24B Oversampling Rate Bit: 7 */\r
6035 #define OSR8 (0x0100u) /* SD24B Oversampling Rate Bit: 8 */\r
6036 #define OSR9 (0x0200u) /* SD24B Oversampling Rate Bit: 9 */\r
6037 #define OSR10 (0x0400u) /* SD24B Oversampling Rate Bit: 10 */\r
6038 \r
6039 #define OSR0_L (0x0001u) /* SD24B Oversampling Rate Bit: 0 */\r
6040 #define OSR1_L (0x0002u) /* SD24B Oversampling Rate Bit: 1 */\r
6041 #define OSR2_L (0x0004u) /* SD24B Oversampling Rate Bit: 2 */\r
6042 #define OSR3_L (0x0008u) /* SD24B Oversampling Rate Bit: 3 */\r
6043 #define OSR4_L (0x0010u) /* SD24B Oversampling Rate Bit: 4 */\r
6044 #define OSR5_L (0x0020u) /* SD24B Oversampling Rate Bit: 5 */\r
6045 #define OSR6_L (0x0040u) /* SD24B Oversampling Rate Bit: 6 */\r
6046 #define OSR7_L (0x0080u) /* SD24B Oversampling Rate Bit: 7 */\r
6047 \r
6048 #define OSR8_H (0x0001u) /* SD24B Oversampling Rate Bit: 8 */\r
6049 #define OSR9_H (0x0002u) /* SD24B Oversampling Rate Bit: 9 */\r
6050 #define OSR10_H (0x0004u) /* SD24B Oversampling Rate Bit: 10 */\r
6051 \r
6052 /* SD24BTRGOSR */\r
6053 \r
6054 #define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */\r
6055 #define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */\r
6056 #define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */\r
6057 #define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */\r
6058 #define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */\r
6059 #define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */\r
6060 \r
6061 \r
6062 #endif\r
6063 /************************************************************\r
6064 * SFR - Special Function Register Module\r
6065 ************************************************************/\r
6066 #ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */\r
6067 \r
6068 #define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */\r
6069 #define OFS_SFRIE1_L OFS_SFRIE1\r
6070 #define OFS_SFRIE1_H OFS_SFRIE1+1\r
6071 \r
6072 /* SFRIE1 Control Bits */\r
6073 #define WDTIE (0x0001u) /* WDT Interrupt Enable */\r
6074 #define OFIE (0x0002u) /* Osc Fault Enable */\r
6075 //#define Reserved (0x0004u)\r
6076 #define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */\r
6077 #define NMIIE (0x0010u) /* NMI Interrupt Enable */\r
6078 #ifndef ACCVIE\r
6079 #define ACCVIE (0x0020u) /* Flash Access Violation Interrupt Enable */\r
6080 #endif\r
6081 #define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */\r
6082 #define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */\r
6083 \r
6084 #define WDTIE_L (0x0001u) /* WDT Interrupt Enable */\r
6085 #define OFIE_L (0x0002u) /* Osc Fault Enable */\r
6086 //#define Reserved (0x0004u)\r
6087 #define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */\r
6088 #define NMIIE_L (0x0010u) /* NMI Interrupt Enable */\r
6089 #ifndef ACCVIE\r
6090 #define ACCVIE_L (0x0020u) /* Flash Access Violation Interrupt Enable */\r
6091 #endif\r
6092 #define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */\r
6093 #define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */\r
6094 \r
6095 #define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */\r
6096 #define OFS_SFRIFG1_L OFS_SFRIFG1\r
6097 #define OFS_SFRIFG1_H OFS_SFRIFG1+1\r
6098 /* SFRIFG1 Control Bits */\r
6099 #define WDTIFG (0x0001u) /* WDT Interrupt Flag */\r
6100 #define OFIFG (0x0002u) /* Osc Fault Flag */\r
6101 //#define Reserved (0x0004u)\r
6102 #define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */\r
6103 #define NMIIFG (0x0010u) /* NMI Interrupt Flag */\r
6104 //#define Reserved (0x0020u)\r
6105 #define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */\r
6106 #define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */\r
6107 \r
6108 #define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */\r
6109 #define OFIFG_L (0x0002u) /* Osc Fault Flag */\r
6110 //#define Reserved (0x0004u)\r
6111 #define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */\r
6112 #define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */\r
6113 //#define Reserved (0x0020u)\r
6114 #define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */\r
6115 #define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */\r
6116 \r
6117 #define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */\r
6118 #define OFS_SFRRPCR_L OFS_SFRRPCR\r
6119 #define OFS_SFRRPCR_H OFS_SFRRPCR+1\r
6120 /* SFRRPCR Control Bits */\r
6121 #define SYSNMI (0x0001u) /* NMI select */\r
6122 #define SYSNMIIES (0x0002u) /* NMI edge select */\r
6123 #define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */\r
6124 #define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */\r
6125 \r
6126 #define SYSNMI_L (0x0001u) /* NMI select */\r
6127 #define SYSNMIIES_L (0x0002u) /* NMI edge select */\r
6128 #define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */\r
6129 #define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */\r
6130 \r
6131 #endif\r
6132 /************************************************************\r
6133 * SYS - System Module\r
6134 ************************************************************/\r
6135 #ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */\r
6136 \r
6137 #define OFS_SYSCTL (0x0000u) /* System control */\r
6138 #define OFS_SYSCTL_L OFS_SYSCTL\r
6139 #define OFS_SYSCTL_H OFS_SYSCTL+1\r
6140 #define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */\r
6141 #define OFS_SYSBSLC_L OFS_SYSBSLC\r
6142 #define OFS_SYSBSLC_H OFS_SYSBSLC+1\r
6143 #define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */\r
6144 #define OFS_SYSJMBC_L OFS_SYSJMBC\r
6145 #define OFS_SYSJMBC_H OFS_SYSJMBC+1\r
6146 #define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */\r
6147 #define OFS_SYSJMBI0_L OFS_SYSJMBI0\r
6148 #define OFS_SYSJMBI0_H OFS_SYSJMBI0+1\r
6149 #define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */\r
6150 #define OFS_SYSJMBI1_L OFS_SYSJMBI1\r
6151 #define OFS_SYSJMBI1_H OFS_SYSJMBI1+1\r
6152 #define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */\r
6153 #define OFS_SYSJMBO0_L OFS_SYSJMBO0\r
6154 #define OFS_SYSJMBO0_H OFS_SYSJMBO0+1\r
6155 #define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */\r
6156 #define OFS_SYSJMBO1_L OFS_SYSJMBO1\r
6157 #define OFS_SYSJMBO1_H OFS_SYSJMBO1+1\r
6158 \r
6159 #define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */\r
6160 #define OFS_SYSBERRIV_L OFS_SYSBERRIV\r
6161 #define OFS_SYSBERRIV_H OFS_SYSBERRIV+1\r
6162 #define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */\r
6163 #define OFS_SYSUNIV_L OFS_SYSUNIV\r
6164 #define OFS_SYSUNIV_H OFS_SYSUNIV+1\r
6165 #define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */\r
6166 #define OFS_SYSSNIV_L OFS_SYSSNIV\r
6167 #define OFS_SYSSNIV_H OFS_SYSSNIV+1\r
6168 #define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */\r
6169 #define OFS_SYSRSTIV_L OFS_SYSRSTIV\r
6170 #define OFS_SYSRSTIV_H OFS_SYSRSTIV+1\r
6171 \r
6172 /* SYSCTL Control Bits */\r
6173 #define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */\r
6174 //#define RESERVED (0x0002u) /* SYS - Reserved */\r
6175 #define SYSPMMPE (0x0004u) /* SYS - PMM access protect */\r
6176 //#define RESERVED (0x0008u) /* SYS - Reserved */\r
6177 #define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */\r
6178 #define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */\r
6179 //#define RESERVED (0x0040u) /* SYS - Reserved */\r
6180 //#define RESERVED (0x0080u) /* SYS - Reserved */\r
6181 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6182 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6183 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6184 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6185 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6186 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6187 //#define RESERVED (0x4000u) /* SYS - Reserved */\r
6188 //#define RESERVED (0x8000u) /* SYS - Reserved */\r
6189 \r
6190 /* SYSCTL Control Bits */\r
6191 #define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */\r
6192 //#define RESERVED (0x0002u) /* SYS - Reserved */\r
6193 #define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */\r
6194 //#define RESERVED (0x0008u) /* SYS - Reserved */\r
6195 #define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */\r
6196 #define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */\r
6197 //#define RESERVED (0x0040u) /* SYS - Reserved */\r
6198 //#define RESERVED (0x0080u) /* SYS - Reserved */\r
6199 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6200 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6201 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6202 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6203 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6204 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6205 //#define RESERVED (0x4000u) /* SYS - Reserved */\r
6206 //#define RESERVED (0x8000u) /* SYS - Reserved */\r
6207 \r
6208 /* SYSBSLC Control Bits */\r
6209 #define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */\r
6210 #define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */\r
6211 #define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */\r
6212 //#define RESERVED (0x0008u) /* SYS - Reserved */\r
6213 //#define RESERVED (0x0010u) /* SYS - Reserved */\r
6214 //#define RESERVED (0x0020u) /* SYS - Reserved */\r
6215 //#define RESERVED (0x0040u) /* SYS - Reserved */\r
6216 //#define RESERVED (0x0080u) /* SYS - Reserved */\r
6217 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6218 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6219 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6220 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6221 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6222 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6223 #define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */\r
6224 #define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */\r
6225 \r
6226 /* SYSBSLC Control Bits */\r
6227 #define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */\r
6228 #define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */\r
6229 #define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */\r
6230 //#define RESERVED (0x0008u) /* SYS - Reserved */\r
6231 //#define RESERVED (0x0010u) /* SYS - Reserved */\r
6232 //#define RESERVED (0x0020u) /* SYS - Reserved */\r
6233 //#define RESERVED (0x0040u) /* SYS - Reserved */\r
6234 //#define RESERVED (0x0080u) /* SYS - Reserved */\r
6235 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6236 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6237 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6238 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6239 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6240 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6241 \r
6242 /* SYSBSLC Control Bits */\r
6243 //#define RESERVED (0x0008u) /* SYS - Reserved */\r
6244 //#define RESERVED (0x0010u) /* SYS - Reserved */\r
6245 //#define RESERVED (0x0020u) /* SYS - Reserved */\r
6246 //#define RESERVED (0x0040u) /* SYS - Reserved */\r
6247 //#define RESERVED (0x0080u) /* SYS - Reserved */\r
6248 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6249 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6250 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6251 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6252 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6253 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6254 #define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */\r
6255 #define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */\r
6256 \r
6257 /* SYSJMBC Control Bits */\r
6258 #define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
6259 #define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
6260 #define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
6261 #define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
6262 #define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */\r
6263 //#define RESERVED (0x0020u) /* SYS - Reserved */\r
6264 #define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
6265 #define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
6266 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6267 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6268 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6269 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6270 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6271 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6272 //#define RESERVED (0x4000u) /* SYS - Reserved */\r
6273 //#define RESERVED (0x8000u) /* SYS - Reserved */\r
6274 \r
6275 /* SYSJMBC Control Bits */\r
6276 #define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
6277 #define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
6278 #define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
6279 #define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
6280 #define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */\r
6281 //#define RESERVED (0x0020u) /* SYS - Reserved */\r
6282 #define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
6283 #define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
6284 //#define RESERVED (0x0100u) /* SYS - Reserved */\r
6285 //#define RESERVED (0x0200u) /* SYS - Reserved */\r
6286 //#define RESERVED (0x0400u) /* SYS - Reserved */\r
6287 //#define RESERVED (0x0800u) /* SYS - Reserved */\r
6288 //#define RESERVED (0x1000u) /* SYS - Reserved */\r
6289 //#define RESERVED (0x2000u) /* SYS - Reserved */\r
6290 //#define RESERVED (0x4000u) /* SYS - Reserved */\r
6291 //#define RESERVED (0x8000u) /* SYS - Reserved */\r
6292 \r
6293 \r
6294 #endif\r
6295 /************************************************************\r
6296 * Timerx_A7\r
6297 ************************************************************/\r
6298 #ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */\r
6299 \r
6300 #define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */\r
6301 #define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */\r
6302 #define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */\r
6303 #define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */\r
6304 #define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */\r
6305 #define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */\r
6306 #define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */\r
6307 #define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */\r
6308 #define OFS_TAxR (0x0010u) /* Timerx_A7 */\r
6309 #define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */\r
6310 #define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */\r
6311 #define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */\r
6312 #define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */\r
6313 #define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */\r
6314 #define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */\r
6315 #define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */\r
6316 #define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */\r
6317 #define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */\r
6318 \r
6319 /* Bits are already defined within the Timer0_Ax */\r
6320 \r
6321 /* TAxIV Definitions */\r
6322 #define TAxIV_NONE (0x0000u) /* No Interrupt pending */\r
6323 #define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */\r
6324 #define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */\r
6325 #define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */\r
6326 #define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */\r
6327 #define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */\r
6328 #define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */\r
6329 #define TAxIV_TAIFG (0x000Eu) /* TAxIFG */\r
6330 \r
6331 /* Legacy Defines */\r
6332 #define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */\r
6333 #define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */\r
6334 #define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */\r
6335 #define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */\r
6336 #define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */\r
6337 #define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */\r
6338 #define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */\r
6339 \r
6340 /* TAxCTL Control Bits */\r
6341 #define TASSEL1 (0x0200u) /* Timer A clock source select 1 */\r
6342 #define TASSEL0 (0x0100u) /* Timer A clock source select 0 */\r
6343 #define ID1 (0x0080u) /* Timer A clock input divider 1 */\r
6344 #define ID0 (0x0040u) /* Timer A clock input divider 0 */\r
6345 #define MC1 (0x0020u) /* Timer A mode control 1 */\r
6346 #define MC0 (0x0010u) /* Timer A mode control 0 */\r
6347 #define TACLR (0x0004u) /* Timer A counter clear */\r
6348 #define TAIE (0x0002u) /* Timer A counter interrupt enable */\r
6349 #define TAIFG (0x0001u) /* Timer A counter interrupt flag */\r
6350 \r
6351 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */\r
6352 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
6353 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
6354 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
6355 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
6356 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
6357 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
6358 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
6359 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
6360 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
6361 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
6362 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
6363 #define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */\r
6364 #define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
6365 #define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
6366 #define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
6367 #define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
6368 #define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
6369 #define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
6370 #define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
6371 #define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
6372 #define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
6373 #define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
6374 #define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
6375 #define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
6376 \r
6377 /* TAxCCTLx Control Bits */\r
6378 #define CM1 (0x8000u) /* Capture mode 1 */\r
6379 #define CM0 (0x4000u) /* Capture mode 0 */\r
6380 #define CCIS1 (0x2000u) /* Capture input select 1 */\r
6381 #define CCIS0 (0x1000u) /* Capture input select 0 */\r
6382 #define SCS (0x0800u) /* Capture sychronize */\r
6383 #define SCCI (0x0400u) /* Latched capture signal (read) */\r
6384 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
6385 #define OUTMOD2 (0x0080u) /* Output mode 2 */\r
6386 #define OUTMOD1 (0x0040u) /* Output mode 1 */\r
6387 #define OUTMOD0 (0x0020u) /* Output mode 0 */\r
6388 #define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
6389 #define CCI (0x0008u) /* Capture input signal (read) */\r
6390 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
6391 #define COV (0x0002u) /* Capture/compare overflow flag */\r
6392 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
6393 \r
6394 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
6395 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
6396 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
6397 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
6398 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
6399 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
6400 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
6401 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
6402 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */\r
6403 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */\r
6404 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */\r
6405 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */\r
6406 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
6407 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
6408 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
6409 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
6410 \r
6411 /* TAxEX0 Control Bits */\r
6412 #define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */\r
6413 #define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */\r
6414 #define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */\r
6415 \r
6416 #define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */\r
6417 #define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */\r
6418 #define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */\r
6419 #define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */\r
6420 #define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */\r
6421 #define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */\r
6422 #define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */\r
6423 #define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */\r
6424 \r
6425 #endif\r
6426 /************************************************************\r
6427 * Timerx_B7\r
6428 ************************************************************/\r
6429 #ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */\r
6430 \r
6431 #define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */\r
6432 #define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */\r
6433 #define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */\r
6434 #define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */\r
6435 #define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */\r
6436 #define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */\r
6437 #define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */\r
6438 #define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */\r
6439 #define OFS_TBxR (0x0010u) /* Timerx_B7 */\r
6440 #define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */\r
6441 #define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */\r
6442 #define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */\r
6443 #define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */\r
6444 #define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */\r
6445 #define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */\r
6446 #define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */\r
6447 #define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */\r
6448 #define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */\r
6449 \r
6450 /* Bits are already defined within the Timer0_Ax */\r
6451 \r
6452 /* TBxIV Definitions */\r
6453 #define TBxIV_NONE (0x0000u) /* No Interrupt pending */\r
6454 #define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */\r
6455 #define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */\r
6456 #define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */\r
6457 #define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */\r
6458 #define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */\r
6459 #define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */\r
6460 #define TBxIV_TBIFG (0x000Eu) /* TBxIFG */\r
6461 \r
6462 /* Legacy Defines */\r
6463 #define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */\r
6464 #define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */\r
6465 #define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */\r
6466 #define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */\r
6467 #define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */\r
6468 #define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */\r
6469 #define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */\r
6470 \r
6471 /* TBxCTL Control Bits */\r
6472 #define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */\r
6473 #define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */\r
6474 #define CNTL1 (0x1000u) /* Counter lenght 1 */\r
6475 #define CNTL0 (0x0800u) /* Counter lenght 0 */\r
6476 #define TBSSEL1 (0x0200u) /* Clock source 1 */\r
6477 #define TBSSEL0 (0x0100u) /* Clock source 0 */\r
6478 #define TBCLR (0x0004u) /* Timer_B7 counter clear */\r
6479 #define TBIE (0x0002u) /* Timer_B7 interrupt enable */\r
6480 #define TBIFG (0x0001u) /* Timer_B7 interrupt flag */\r
6481 \r
6482 #define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */\r
6483 #define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */\r
6484 \r
6485 #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */\r
6486 #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */\r
6487 #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */\r
6488 #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */\r
6489 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */\r
6490 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */\r
6491 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */\r
6492 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */\r
6493 #define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
6494 #define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
6495 #define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
6496 #define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
6497 #define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
6498 #define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
6499 #define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
6500 #define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
6501 #define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */\r
6502 #define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */\r
6503 #define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */\r
6504 #define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */\r
6505 #define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */\r
6506 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */\r
6507 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */\r
6508 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */\r
6509 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */\r
6510 \r
6511 /* Additional Timer B Control Register bits are defined in Timer A */\r
6512 /* TBxCCTLx Control Bits */\r
6513 #define CLLD1 (0x0400u) /* Compare latch load source 1 */\r
6514 #define CLLD0 (0x0200u) /* Compare latch load source 0 */\r
6515 \r
6516 #define SLSHR1 (0x0400u) /* Compare latch load source 1 */\r
6517 #define SLSHR0 (0x0200u) /* Compare latch load source 0 */\r
6518 \r
6519 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
6520 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
6521 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
6522 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
6523 \r
6524 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
6525 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
6526 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
6527 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
6528 \r
6529 /* TBxEX0 Control Bits */\r
6530 #define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */\r
6531 #define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */\r
6532 #define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */\r
6533 \r
6534 #define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
6535 #define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
6536 #define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
6537 #define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
6538 #define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
6539 #define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
6540 #define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
6541 #define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
6542 #define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
6543 #define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
6544 #define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
6545 #define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
6546 #define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
6547 #define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
6548 #define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
6549 #define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
6550 \r
6551 \r
6552 #define ID1 (0x0080u) /* Timer B clock input divider 1 */\r
6553 #define ID0 (0x0040u) /* Timer B clock input divider 0 */\r
6554 #define MC1 (0x0020u) /* Timer B mode control 1 */\r
6555 #define MC0 (0x0010u) /* Timer B mode control 0 */\r
6556 #define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */\r
6557 #define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
6558 #define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
6559 #define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
6560 #define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
6561 #define CM1 (0x8000u) /* Capture mode 1 */\r
6562 #define CM0 (0x4000u) /* Capture mode 0 */\r
6563 #define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */\r
6564 #define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
6565 #define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
6566 #define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
6567 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
6568 #define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
6569 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
6570 #define CCIS_0 (0*0x1000u)\r
6571 #define CCIS_1 (1*0x1000u)\r
6572 #define CCIS_2 (2*0x1000u)\r
6573 #define CCIS_3 (3*0x1000u)\r
6574 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
6575 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
6576 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
6577 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
6578 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
6579 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
6580 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
6581 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
6582 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
6583 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
6584 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
6585 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
6586 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
6587 #define SCCI (0x0400u) /* Latched capture signal (read) */\r
6588 #define SCS (0x0800u) /* Capture sychronize */\r
6589 #define CCI (0x0008u) /* Capture input signal (read) */\r
6590 #define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
6591 #define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
6592 #define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
6593 #define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
6594 #define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
6595 #define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
6596 #define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
6597 #define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
6598 \r
6599 #endif\r
6600 /************************************************************\r
6601 * Timerx_D7\r
6602 ************************************************************/\r
6603 #ifdef __MSP430_HAS_TxD7__ /* Definition to show that Module is available */\r
6604 \r
6605 #define OFS_TDxCTL0 (0x0000u) /* Timerx_D7 Control 0 */\r
6606 #define OFS_TDxCTL1 (0x0002u) /* Timerx_D7 Control 1 */\r
6607 #define OFS_TDxCTL2 (0x0004u) /* Timerx_D7 Control 2 */\r
6608 #define OFS_TDxR (0x0006u) /* Timerx_D7 Counter */\r
6609 #define OFS_TDxCCTL0 (0x0008u) /* Timerx_D7 Capture/Compare Control 0 */\r
6610 #define OFS_TDxCCR0 (0x000Au) /* Timerx_D7 Capture/Compare 0 */\r
6611 #define OFS_TDxCL0 (0x000Cu) /* Timerx_D7 Capture/Compare Latch 0 */\r
6612 #define OFS_TDxCCTL1 (0x000Eu) /* Timerx_D7 Capture/Compare Control 1 */\r
6613 #define OFS_TDxCCR1 (0x0010u) /* Timerx_D7 Capture/Compare 1 */\r
6614 #define OFS_TDxCL1 (0x0012u) /* Timerx_D7 Capture/Compare Latch 1 */\r
6615 #define OFS_TDxCCTL2 (0x0014u) /* Timerx_D7 Capture/Compare Control 2 */\r
6616 #define OFS_TDxCCR2 (0x0016u) /* Timerx_D7 Capture/Compare 2 */\r
6617 #define OFS_TDxCL2 (0x0018u) /* Timerx_D7 Capture/Compare Latch 2 */\r
6618 #define OFS_TDxCCTL3 (0x001Au) /* Timerx_D7 Capture/Compare Control 3 */\r
6619 #define OFS_TDxCCR3 (0x001Cu) /* Timerx_D7 Capture/Compare 3 */\r
6620 #define OFS_TDxCL3 (0x001Eu) /* Timerx_D7 Capture/Compare Latch 3 */\r
6621 #define OFS_TDxCCTL4 (0x0020u) /* Timerx_D7 Capture/Compare Control 4 */\r
6622 #define OFS_TDxCCR4 (0x0022u) /* Timerx_D7 Capture/Compare 4 */\r
6623 #define OFS_TDxCL4 (0x0024u) /* Timerx_D7 Capture/Compare Latch 4 */\r
6624 #define OFS_TDxCCTL5 (0x0026u) /* Timerx_D7 Capture/Compare Control 5 */\r
6625 #define OFS_TDxCCR5 (0x0028u) /* Timerx_D7 Capture/Compare 5 */\r
6626 #define OFS_TDxCL5 (0x002Au) /* Timerx_D7 Capture/Compare Latch 5 */\r
6627 #define OFS_TDxCCTL6 (0x002Cu) /* Timerx_D7 Capture/Compare Control 6 */\r
6628 #define OFS_TDxCCR6 (0x002Eu) /* Timerx_D7 Capture/Compare 6 */\r
6629 #define OFS_TDxCL6 (0x0030u) /* Timerx_D7 Capture/Compare Latch 6 */\r
6630 #define OFS_TDxHCTL0 (0x0038u) /* Timerx_D7 High-resolution Control Register 0 */\r
6631 #define OFS_TDxHCTL1 (0x003Au) /* Timerx_D7 High-resolution Control Register 1 */\r
6632 #define OFS_TDxHINT (0x003Cu) /* Timerx_D7 High-resolution Interrupt Register */\r
6633 #define OFS_TDxIV (0x003Eu) /* Timerx_D7 Interrupt Vector Word */\r
6634 \r
6635 /* Bits are already defined within the Timer0_Dx */\r
6636 \r
6637 /* TDxIV Definitions */\r
6638 #define TDxIV_NONE (0x0000u) /* No Interrupt pending */\r
6639 #define TDxIV_TDCCR1 (0x0002u) /* TDxCCR1_CCIFG */\r
6640 #define TDxIV_TDCCR2 (0x0004u) /* TDxCCR2_CCIFG */\r
6641 #define TDxIV_TDCCR3 (0x0006u) /* TDxCCR3_CCIFG */\r
6642 #define TDxIV_TDCCR4 (0x0008u) /* TDxCCR4_CCIFG */\r
6643 #define TDxIV_TDCCR5 (0x000Au) /* TDxCCR5_CCIFG */\r
6644 #define TDxIV_TDCCR6 (0x000Cu) /* TDxCCR6_CCIFG */\r
6645 #define TDxIV_RES_14 (0x000Eu) /* Reserverd */\r
6646 #define TDxIV_TDIFG (0x0010u) /* TDxIFG */\r
6647 #define TDxIV_TDHFLIFG (0x0012u) /* TDHFLIFG Clock fail low */\r
6648 #define TDxIV_TDHFHIFG (0x0014u) /* TDHFLIFG Clock fail high */\r
6649 #define TDxIV_TDHLKIFG (0x0016u) /* TDHLKIE Clock lock*/\r
6650 #define TDxIV_TDHUNLKIFG (0x0018u) /* TDHUNLKIE Clock unlock */\r
6651 \r
6652 /* Legacy Defines */\r
6653 #define TDxIV_TDxCCR1 (0x0002u) /* TDxCCR1_CCIFG */\r
6654 #define TDxIV_TDxCCR2 (0x0004u) /* TDxCCR2_CCIFG */\r
6655 #define TDxIV_TDxCCR3 (0x0006u) /* TDxCCR3_CCIFG */\r
6656 #define TDxIV_TDxCCR4 (0x0008u) /* TDxCCR4_CCIFG */\r
6657 #define TDxIV_TDxCCR5 (0x000Au) /* TDxCCR5_CCIFG */\r
6658 #define TDxIV_TDxCCR6 (0x000Cu) /* TDxCCR6_CCIFG */\r
6659 #define TDxIV_TDxIFG (0x0010u) /* TDxIFG */\r
6660 \r
6661 /* TDxCTL0 Control Bits */\r
6662 #define TDCLGRP1 (0x4000u) /* Timer_D7 Compare latch load group 1 */\r
6663 #define TDCLGRP0 (0x2000u) /* Timer_D7 Compare latch load group 0 */\r
6664 #define CNTL1 (0x1000u) /* Counter lenght 1 */\r
6665 #define CNTL0 (0x0800u) /* Counter lenght 0 */\r
6666 #define TDSSEL1 (0x0200u) /* Clock source 1 */\r
6667 #define TDSSEL0 (0x0100u) /* Clock source 0 */\r
6668 #define TDCLR (0x0004u) /* Timer_D7 counter clear */\r
6669 #define TDIE (0x0002u) /* Timer_D7 interrupt enable */\r
6670 #define TDIFG (0x0001u) /* Timer_D7 interrupt flag */\r
6671 \r
6672 #define SHR1 (0x4000u) /* Timer_D7 Compare latch load group 1 */\r
6673 #define SHR0 (0x2000u) /* Timer_D7 Compare latch load group 0 */\r
6674 \r
6675 #define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */\r
6676 #define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */\r
6677 #define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */\r
6678 #define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */\r
6679 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */\r
6680 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */\r
6681 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */\r
6682 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */\r
6683 #define SHR_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */\r
6684 #define SHR_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
6685 #define SHR_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/\r
6686 #define SHR_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */\r
6687 #define TDCLGRP_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */\r
6688 #define TDCLGRP_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
6689 #define TDCLGRP_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/\r
6690 #define TDCLGRP_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */\r
6691 #define TDSSEL__TACLK (0*0x0100u) /* Timer_D7 clock source select: 0 - TACLK */\r
6692 #define TDSSEL__ACLK (1*0x0100u) /* Timer_D7 clock source select: 1 - ACLK */\r
6693 #define TDSSEL__SMCLK (2*0x0100u) /* Timer_D7 clock source select: 2 - SMCLK */\r
6694 #define TDSSEL__INCLK (3*0x0100u) /* Timer_D7 clock source select: 3 - INCLK */\r
6695 #define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */\r
6696 #define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */\r
6697 #define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */\r
6698 #define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */\r
6699 \r
6700 /* Additional Timer B Control Register bits are defined in Timer A */\r
6701 \r
6702 /* TDxCTL1 Control Bits */\r
6703 #define TDCLKM0 (0x0001u) /* Timer_D7 Clocking Mode Bit: 0 */\r
6704 #define TDCLKM1 (0x0002u) /* Timer_D7 Clocking Mode Bit: 1 */\r
6705 #define TD2CMB (0x0010u) /* Timer_D7 TD0CCR Combination in TD2 */\r
6706 #define TD4CMB (0x0020u) /* Timer_D7 TD0CCR Combination in TD4 */\r
6707 #define TD6CMB (0x0040u) /* Timer_D7 TD0CCR Combination in TD6 */\r
6708 #define TDIDEX0 (0x0100u) /* Timer_D7 Input divider expansion Bit: 0 */\r
6709 #define TDIDEX1 (0x0200u) /* Timer_D7 Input divider expansion Bit: 1 */\r
6710 #define TDIDEX2 (0x0400u) /* Timer_D7 Input divider expansion Bit: 2 */\r
6711 \r
6712 #define TDCLKM_0 (0x0000u) /* Timer_D7 Clocking Mode: External */\r
6713 #define TDCLKM_1 (0x0001u) /* Timer_D7 Clocking Mode: High-Res. local clock */\r
6714 #define TDCLKM_2 (0x0002u) /* Timer_D7 Clocking Mode: Aux Clock */\r
6715 #define TDCLKM__EXT (0x0000u) /* Timer_D7 Clocking Mode: External */\r
6716 #define TDCLKM__HIGHRES (0x0001u) /* Timer_D7 Clocking Mode: High-Res. local clock */\r
6717 #define TDCLKM__AUX (0x0002u) /* Timer_D7 Clocking Mode: Aux Clock */\r
6718 \r
6719 #define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */\r
6720 #define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */\r
6721 #define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */\r
6722 #define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */\r
6723 #define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */\r
6724 #define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */\r
6725 #define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */\r
6726 #define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */\r
6727 #define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */\r
6728 #define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */\r
6729 #define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */\r
6730 #define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */\r
6731 #define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */\r
6732 #define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */\r
6733 #define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */\r
6734 #define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */\r
6735 \r
6736 /* TDxCTL2 Control Bits */\r
6737 #define TDCAPM0 (0x0001u) /* Timer_D7 Capture Mode of Channel 0 */\r
6738 #define TDCAPM1 (0x0002u) /* Timer_D7 Capture Mode of Channel 1 */\r
6739 #define TDCAPM2 (0x0004u) /* Timer_D7 Capture Mode of Channel 2 */\r
6740 #define TDCAPM3 (0x0008u) /* Timer_D7 Capture Mode of Channel 3 */\r
6741 #define TDCAPM4 (0x0010u) /* Timer_D7 Capture Mode of Channel 4 */\r
6742 #define TDCAPM5 (0x0020u) /* Timer_D7 Capture Mode of Channel 5 */\r
6743 #define TDCAPM6 (0x0040u) /* Timer_D7 Capture Mode of Channel 6 */\r
6744 \r
6745 /* TDxCCTLx Control Bits */\r
6746 #define CLLD1 (0x0400u) /* Compare latch load source 1 */\r
6747 #define CLLD0 (0x0200u) /* Compare latch load source 0 */\r
6748 \r
6749 #define SLSHR1 (0x0400u) /* Compare latch load source 1 */\r
6750 #define SLSHR0 (0x0200u) /* Compare latch load source 0 */\r
6751 \r
6752 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
6753 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */\r
6754 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
6755 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */\r
6756 \r
6757 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
6758 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */\r
6759 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
6760 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */\r
6761 \r
6762 /* TDxHCTL0 Control Bits */\r
6763 #define TDHEN (0x0001u) /* Timer_D7 High-Resolution Enable */\r
6764 #define TDHREGEN (0x0002u) /* Timer_D7 High-Resolution Regulatied Mode */\r
6765 #define TDHEAEN (0x0004u) /* Timer_D7 High-Resolution clock error accum. enable */\r
6766 #define TDHRON (0x0008u) /* Timer_D7 High-Resolution Generator forced on*/\r
6767 #define TDHM0 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 0 */\r
6768 #define TDHM1 (0x0020u) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 1 */\r
6769 #define TDHD0 (0x0040u) /* Timer_D7 High-Resolution clock divider Bit: 0 */\r
6770 #define TDHD1 (0x0080u) /* Timer_D7 High-Resolution clock divider Bit: 1 */\r
6771 #define TDHFW (0x0100u) /* Timer_D7 High-resolution generator fast wakeup enable */\r
6772 \r
6773 #define TDHCALEN TDHREGEN /* Timer_D7 Lagacy Definition */\r
6774 \r
6775 #define TDHM_0 (0x0000u) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */\r
6776 #define TDHM_1 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */\r
6777 #define TDHM__8 (0x0000u) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */\r
6778 #define TDHM__16 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */\r
6779 #define TDHD_0 (0x0000u) /* Timer_D7 High-Resolution clock divider: /1 */\r
6780 #define TDHD_1 (0x0040u) /* Timer_D7 High-Resolution clock divider: /2 */\r
6781 #define TDHD_2 (0x0080u) /* Timer_D7 High-Resolution clock divider: /4 */\r
6782 #define TDHD_3 (0x00C0u) /* Timer_D7 High-Resolution clock divider: /8 */\r
6783 #define TDHD__1 (0x0000u) /* Timer_D7 High-Resolution clock divider: /1 */\r
6784 #define TDHD__2 (0x0040u) /* Timer_D7 High-Resolution clock divider: /2 */\r
6785 #define TDHD__4 (0x0080u) /* Timer_D7 High-Resolution clock divider: /4 */\r
6786 #define TDHD__8 (0x00C0u) /* Timer_D7 High-Resolution clock divider: /8 */\r
6787 \r
6788 /* TDxHCTL1 Control Bits */\r
6789 #define TDHCLKTRIM0 (0x0002u) /* Timer_D7 High-Resolution Clock Trim Bit: 0 */\r
6790 #define TDHCLKTRIM1 (0x0004u) /* Timer_D7 High-Resolution Clock Trim Bit: 1 */\r
6791 #define TDHCLKTRIM2 (0x0008u) /* Timer_D7 High-Resolution Clock Trim Bit: 2 */\r
6792 #define TDHCLKTRIM3 (0x0010u) /* Timer_D7 High-Resolution Clock Trim Bit: 3 */\r
6793 #define TDHCLKTRIM4 (0x0020u) /* Timer_D7 High-Resolution Clock Trim Bit: 4 */\r
6794 #define TDHCLKTRIM5 (0x0040u) /* Timer_D7 High-Resolution Clock Trim Bit: 5 */\r
6795 #define TDHCLKTRIM6 (0x0080u) /* Timer_D7 High-Resolution Clock Trim Bit: 6 */\r
6796 #define TDHCLKSR0 (0x0100u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 0 */\r
6797 #define TDHCLKSR1 (0x0200u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 1 */\r
6798 #define TDHCLKSR2 (0x0400u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 2 */\r
6799 #define TDHCLKSR3 (0x0800u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 3 */\r
6800 #define TDHCLKSR4 (0x1000u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 4 */\r
6801 #define TDHCLKR0 (0x2000u) /* Timer_D7 High-Resolution Clock Range Bit: 0 */\r
6802 #define TDHCLKR1 (0x4000u) /* Timer_D7 High-Resolution Clock Range Bit: 1 */\r
6803 #define TDHCLKCR (0x8000u) /* Timer_D7 High-Resolution Coarse Clock Range */\r
6804 \r
6805 /* TDxHINT Control Bits */\r
6806 #define TDHFLIFG (0x0001u) /* Timer_D7 High-Res. fail low Interrupt Flag */\r
6807 #define TDHFHIFG (0x0002u) /* Timer_D7 High-Res. fail high Interrupt Flag */\r
6808 #define TDHLKIFG (0x0004u) /* Timer_D7 High-Res. frequency lock Interrupt Flag */\r
6809 #define TDHUNLKIFG (0x0008u) /* Timer_D7 High-Res. frequency unlock Interrupt Flag */\r
6810 #define TDHFLIE (0x0100u) /* Timer_D7 High-Res. fail low Interrupt Enable */\r
6811 #define TDHFHIE (0x0200u) /* Timer_D7 High-Res. fail high Interrupt Enable */\r
6812 #define TDHLKIE (0x0400u) /* Timer_D7 High-Res. frequency lock Interrupt Enable */\r
6813 #define TDHUNLKIE (0x0800u) /* Timer_D7 High-Res. frequency unlock Interrupt Enable */\r
6814 \r
6815 #define ID1 (0x0080u) /* Timer D clock input divider 1 */\r
6816 #define ID0 (0x0040u) /* Timer D clock input divider 0 */\r
6817 #define MC1 (0x0020u) /* Timer D mode control 1 */\r
6818 #define MC0 (0x0010u) /* Timer D mode control 0 */\r
6819 #define MC__STOP (0*0x10u) /* Timer D mode control: 0 - Stop */\r
6820 #define MC__UP (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */\r
6821 #define MC__CONTINUOUS (2*0x10u) /* Timer D mode control: 2 - Continuous up */\r
6822 #define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
6823 #define MC__UPDOWN (3*0x10u) /* Timer D mode control: 3 - Up/Down */\r
6824 #define CM1 (0x8000u) /* Capture mode 1 */\r
6825 #define CM0 (0x4000u) /* Capture mode 0 */\r
6826 #define MC_0 (0*0x10u) /* Timer D mode control: 0 - Stop */\r
6827 #define MC_1 (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */\r
6828 #define MC_2 (2*0x10u) /* Timer D mode control: 2 - Continuous up */\r
6829 #define MC_3 (3*0x10u) /* Timer D mode control: 3 - Up/Down */\r
6830 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
6831 #define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
6832 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
6833 #define CCIS_0 (0*0x1000u)\r
6834 #define CCIS_1 (1*0x1000u)\r
6835 #define CCIS_2 (2*0x1000u)\r
6836 #define CCIS_3 (3*0x1000u)\r
6837 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
6838 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
6839 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
6840 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
6841 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
6842 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
6843 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
6844 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
6845 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
6846 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
6847 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
6848 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
6849 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
6850 #define SCCI (0x0400u) /* Latched capture signal (read) */\r
6851 #define SCS (0x0800u) /* Capture sychronize */\r
6852 #define CCI (0x0008u) /* Capture input signal (read) */\r
6853 #define ID__1 (0*0x40u) /* Timer D input divider: 0 - /1 */\r
6854 #define ID__2 (1*0x40u) /* Timer D input divider: 1 - /2 */\r
6855 #define ID__4 (2*0x40u) /* Timer D input divider: 2 - /4 */\r
6856 #define ID__8 (3*0x40u) /* Timer D input divider: 3 - /8 */\r
6857 #define ID_0 (0*0x40u) /* Timer D input divider: 0 - /1 */\r
6858 #define ID_1 (1*0x40u) /* Timer D input divider: 1 - /2 */\r
6859 #define ID_2 (2*0x40u) /* Timer D input divider: 2 - /4 */\r
6860 #define ID_3 (3*0x40u) /* Timer D input divider: 3 - /8 */\r
6861 \r
6862 #endif\r
6863 /************************************************************\r
6864 * Timer Event Control 0\r
6865 ************************************************************/\r
6866 #ifdef __MSP430_HAS_TEV0__ /* Definition to show that Module is available */\r
6867 \r
6868 #define OFS_TEC0XCTL0 (0x0000u) /* Timer Event Control 0 External Control 0 */\r
6869 #define OFS_TEC0XCTL0_L OFS_TEC0XCTL0\r
6870 #define OFS_TEC0XCTL0_H OFS_TEC0XCTL0+1\r
6871 #define OFS_TEC0XCTL1 (0x0002u) /* Timer Event Control 0 External Control 1 */\r
6872 #define OFS_TEC0XCTL1_L OFS_TEC0XCTL1\r
6873 #define OFS_TEC0XCTL1_H OFS_TEC0XCTL1+1\r
6874 #define OFS_TEC0XCTL2 (0x0004u) /* Timer Event Control 0 External Control 2 */\r
6875 #define OFS_TEC0XCTL2_L OFS_TEC0XCTL2\r
6876 #define OFS_TEC0XCTL2_H OFS_TEC0XCTL2+1\r
6877 #define OFS_TEC0STA (0x0006u) /* Timer Event Control 0 Status */\r
6878 #define OFS_TEC0STA_L OFS_TEC0STA\r
6879 #define OFS_TEC0STA_H OFS_TEC0STA+1\r
6880 #define OFS_TEC0XINT (0x0008u) /* Timer Event Control 0 External Interrupt */\r
6881 #define OFS_TEC0XINT_L OFS_TEC0XINT\r
6882 #define OFS_TEC0XINT_H OFS_TEC0XINT+1\r
6883 #define OFS_TEC0IV (0x000Au) /* Timer Event Control 0 Interrupt Vector */\r
6884 #define OFS_TEC0IV_L OFS_TEC0IV\r
6885 #define OFS_TEC0IV_H OFS_TEC0IV+1\r
6886 \r
6887 /* TECxXCTL0 Control Bits */\r
6888 #define TECXFLTHLD0 (0x0001u) /* TEV Ext. fault signal hold for CE0 */\r
6889 #define TECXFLTHLD1 (0x0002u) /* TEV Ext. fault signal hold for CE1 */\r
6890 #define TECXFLTHLD2 (0x0004u) /* TEV Ext. fault signal hold for CE2 */\r
6891 #define TECXFLTHLD3 (0x0008u) /* TEV Ext. fault signal hold for CE3 */\r
6892 #define TECXFLTHLD4 (0x0010u) /* TEV Ext. fault signal hold for CE4 */\r
6893 #define TECXFLTHLD5 (0x0020u) /* TEV Ext. fault signal hold for CE5 */\r
6894 #define TECXFLTHLD6 (0x0040u) /* TEV Ext. fault signal hold for CE6 */\r
6895 #define TECXFLTEN0 (0x0100u) /* TEV Ext. fault signal enable for CE0 */\r
6896 #define TECXFLTEN1 (0x0200u) /* TEV Ext. fault signal enable for CE1 */\r
6897 #define TECXFLTEN2 (0x0400u) /* TEV Ext. fault signal enable for CE2 */\r
6898 #define TECXFLTEN3 (0x0800u) /* TEV Ext. fault signal enable for CE3 */\r
6899 #define TECXFLTEN4 (0x1000u) /* TEV Ext. fault signal enable for CE4 */\r
6900 #define TECXFLTEN5 (0x2000u) /* TEV Ext. fault signal enable for CE5 */\r
6901 #define TECXFLTEN6 (0x4000u) /* TEV Ext. fault signal enable for CE6 */\r
6902 \r
6903 /* TECxXCTL0 Control Bits */\r
6904 #define TECXFLTHLD0_L (0x0001u) /* TEV Ext. fault signal hold for CE0 */\r
6905 #define TECXFLTHLD1_L (0x0002u) /* TEV Ext. fault signal hold for CE1 */\r
6906 #define TECXFLTHLD2_L (0x0004u) /* TEV Ext. fault signal hold for CE2 */\r
6907 #define TECXFLTHLD3_L (0x0008u) /* TEV Ext. fault signal hold for CE3 */\r
6908 #define TECXFLTHLD4_L (0x0010u) /* TEV Ext. fault signal hold for CE4 */\r
6909 #define TECXFLTHLD5_L (0x0020u) /* TEV Ext. fault signal hold for CE5 */\r
6910 #define TECXFLTHLD6_L (0x0040u) /* TEV Ext. fault signal hold for CE6 */\r
6911 \r
6912 /* TECxXCTL0 Control Bits */\r
6913 #define TECXFLTEN0_H (0x0001u) /* TEV Ext. fault signal enable for CE0 */\r
6914 #define TECXFLTEN1_H (0x0002u) /* TEV Ext. fault signal enable for CE1 */\r
6915 #define TECXFLTEN2_H (0x0004u) /* TEV Ext. fault signal enable for CE2 */\r
6916 #define TECXFLTEN3_H (0x0008u) /* TEV Ext. fault signal enable for CE3 */\r
6917 #define TECXFLTEN4_H (0x0010u) /* TEV Ext. fault signal enable for CE4 */\r
6918 #define TECXFLTEN5_H (0x0020u) /* TEV Ext. fault signal enable for CE5 */\r
6919 #define TECXFLTEN6_H (0x0040u) /* TEV Ext. fault signal enable for CE6 */\r
6920 \r
6921 /* TECxXCTL1 Control Bits */\r
6922 #define TECXFLTPOL0 (0x0001u) /* TEV Polarity Bit of ext. fault 0 */\r
6923 #define TECXFLTPOL1 (0x0002u) /* TEV Polarity Bit of ext. fault 1 */\r
6924 #define TECXFLTPOL2 (0x0004u) /* TEV Polarity Bit of ext. fault 2 */\r
6925 #define TECXFLTPOL3 (0x0008u) /* TEV Polarity Bit of ext. fault 3 */\r
6926 #define TECXFLTPOL4 (0x0010u) /* TEV Polarity Bit of ext. fault 4 */\r
6927 #define TECXFLTPOL5 (0x0020u) /* TEV Polarity Bit of ext. fault 5 */\r
6928 #define TECXFLTPOL6 (0x0040u) /* TEV Polarity Bit of ext. fault 6 */\r
6929 #define TECXFLTLVS0 (0x0100u) /* TEV Signal Type of Ext. fault 0 */\r
6930 #define TECXFLTLVS1 (0x0200u) /* TEV Signal Type of Ext. fault 1 */\r
6931 #define TECXFLTLVS2 (0x0400u) /* TEV Signal Type of Ext. fault 2 */\r
6932 #define TECXFLTLVS3 (0x0800u) /* TEV Signal Type of Ext. fault 3 */\r
6933 #define TECXFLTLVS4 (0x1000u) /* TEV Signal Type of Ext. fault 4 */\r
6934 #define TECXFLTLVS5 (0x2000u) /* TEV Signal Type of Ext. fault 5 */\r
6935 #define TECXFLTLVS6 (0x4000u) /* TEV Signal Type of Ext. fault 6 */\r
6936 \r
6937 /* TECxXCTL1 Control Bits */\r
6938 #define TECXFLTPOL0_L (0x0001u) /* TEV Polarity Bit of ext. fault 0 */\r
6939 #define TECXFLTPOL1_L (0x0002u) /* TEV Polarity Bit of ext. fault 1 */\r
6940 #define TECXFLTPOL2_L (0x0004u) /* TEV Polarity Bit of ext. fault 2 */\r
6941 #define TECXFLTPOL3_L (0x0008u) /* TEV Polarity Bit of ext. fault 3 */\r
6942 #define TECXFLTPOL4_L (0x0010u) /* TEV Polarity Bit of ext. fault 4 */\r
6943 #define TECXFLTPOL5_L (0x0020u) /* TEV Polarity Bit of ext. fault 5 */\r
6944 #define TECXFLTPOL6_L (0x0040u) /* TEV Polarity Bit of ext. fault 6 */\r
6945 \r
6946 /* TECxXCTL1 Control Bits */\r
6947 #define TECXFLTLVS0_H (0x0001u) /* TEV Signal Type of Ext. fault 0 */\r
6948 #define TECXFLTLVS1_H (0x0002u) /* TEV Signal Type of Ext. fault 1 */\r
6949 #define TECXFLTLVS2_H (0x0004u) /* TEV Signal Type of Ext. fault 2 */\r
6950 #define TECXFLTLVS3_H (0x0008u) /* TEV Signal Type of Ext. fault 3 */\r
6951 #define TECXFLTLVS4_H (0x0010u) /* TEV Signal Type of Ext. fault 4 */\r
6952 #define TECXFLTLVS5_H (0x0020u) /* TEV Signal Type of Ext. fault 5 */\r
6953 #define TECXFLTLVS6_H (0x0040u) /* TEV Signal Type of Ext. fault 6 */\r
6954 \r
6955 /* TECxXCTL2 Control Bits */\r
6956 #define TECCLKSEL0 (0x0001u) /* TEV Aux. Clock Select Bit: 0 */\r
6957 #define TECCLKSEL1 (0x0002u) /* TEV Aux. Clock Select Bit: 1 */\r
6958 #define TECAXCLREN (0x0004u) /* TEV Auxilary clear signal control */\r
6959 #define TECEXCLREN (0x0008u) /* TEV Ext. clear signal control */\r
6960 #define TECEXCLRHLD (0x0010u) /* TEV External clear signal hold bit */\r
6961 #define TECEXCLRPOL (0x0020u) /* TEV Polarity Bit of ext. clear */\r
6962 #define TECEXCLRLVS (0x0040u) /* TEV Signal Type of Ext. clear */\r
6963 \r
6964 /* TECxXCTL2 Control Bits */\r
6965 #define TECCLKSEL0_L (0x0001u) /* TEV Aux. Clock Select Bit: 0 */\r
6966 #define TECCLKSEL1_L (0x0002u) /* TEV Aux. Clock Select Bit: 1 */\r
6967 #define TECAXCLREN_L (0x0004u) /* TEV Auxilary clear signal control */\r
6968 #define TECEXCLREN_L (0x0008u) /* TEV Ext. clear signal control */\r
6969 #define TECEXCLRHLD_L (0x0010u) /* TEV External clear signal hold bit */\r
6970 #define TECEXCLRPOL_L (0x0020u) /* TEV Polarity Bit of ext. clear */\r
6971 #define TECEXCLRLVS_L (0x0040u) /* TEV Signal Type of Ext. clear */\r
6972 \r
6973 #define TECCLKSEL_0 (0x0000u) /* TEV Aux. Clock Select: CLK0 */\r
6974 #define TECCLKSEL_1 (0x0001u) /* TEV Aux. Clock Select: CLK1 */\r
6975 #define TECCLKSEL_2 (0x0002u) /* TEV Aux. Clock Select: CLK2 */\r
6976 #define TECCLKSEL_3 (0x0003u) /* TEV Aux. Clock Select: CLK3 */\r
6977 \r
6978 /* TECxSTA Control Bits */\r
6979 #define TECXFLT0STA (0x0001u) /* TEV External fault status flag for CE0 */\r
6980 #define TECXFLT1STA (0x0002u) /* TEV External fault status flag for CE1 */\r
6981 #define TECXFLT2STA (0x0004u) /* TEV External fault status flag for CE2 */\r
6982 #define TECXFLT3STA (0x0008u) /* TEV External fault status flag for CE3 */\r
6983 #define TECXFLT4STA (0x0010u) /* TEV External fault status flag for CE4 */\r
6984 #define TECXFLT5STA (0x0020u) /* TEV External fault status flag for CE5 */\r
6985 #define TECXFLT6STA (0x0040u) /* TEV External fault status flag for CE6 */\r
6986 #define TECXCLRSTA (0x0100u) /* TEC External clear status flag */\r
6987 \r
6988 /* TECxSTA Control Bits */\r
6989 #define TECXFLT0STA_L (0x0001u) /* TEV External fault status flag for CE0 */\r
6990 #define TECXFLT1STA_L (0x0002u) /* TEV External fault status flag for CE1 */\r
6991 #define TECXFLT2STA_L (0x0004u) /* TEV External fault status flag for CE2 */\r
6992 #define TECXFLT3STA_L (0x0008u) /* TEV External fault status flag for CE3 */\r
6993 #define TECXFLT4STA_L (0x0010u) /* TEV External fault status flag for CE4 */\r
6994 #define TECXFLT5STA_L (0x0020u) /* TEV External fault status flag for CE5 */\r
6995 #define TECXFLT6STA_L (0x0040u) /* TEV External fault status flag for CE6 */\r
6996 \r
6997 /* TECxSTA Control Bits */\r
6998 #define TECXCLRSTA_H (0x0001u) /* TEC External clear status flag */\r
6999 \r
7000 /* TECxXINT Control Bits */\r
7001 #define TECAXCLRIFG (0x0001u) /* TEC Aux. Clear Interrupt Flag */\r
7002 #define TECEXCLRIFG (0x0002u) /* TEC External Clear Interrupt Flag */\r
7003 #define TECXFLTIFG (0x0004u) /* TEC External Fault Interrupt Flag */\r
7004 #define TECAXCLRIE (0x0100u) /* TEC Aux. Clear Interrupt Enable */\r
7005 #define TECEXCLRIE (0x0200u) /* TEC External Clear Interrupt Enable */\r
7006 #define TECXFLTIE (0x0400u) /* TEC External Fault Interrupt Enable */\r
7007 \r
7008 /* TECxXINT Control Bits */\r
7009 #define TECAXCLRIFG_L (0x0001u) /* TEC Aux. Clear Interrupt Flag */\r
7010 #define TECEXCLRIFG_L (0x0002u) /* TEC External Clear Interrupt Flag */\r
7011 #define TECXFLTIFG_L (0x0004u) /* TEC External Fault Interrupt Flag */\r
7012 \r
7013 /* TECxXINT Control Bits */\r
7014 #define TECAXCLRIE_H (0x0001u) /* TEC Aux. Clear Interrupt Enable */\r
7015 #define TECEXCLRIE_H (0x0002u) /* TEC External Clear Interrupt Enable */\r
7016 #define TECXFLTIE_H (0x0004u) /* TEC External Fault Interrupt Enable */\r
7017 \r
7018 /* TEC0IV Definitions */\r
7019 #define TEC0IV_NONE (0x0000u) /* No Interrupt pending */\r
7020 #define TEC0IV_TECXFLTIFG (0x0002u) /* TEC0XFLTIFG */\r
7021 #define TEC0IV_TECEXCLRIFG (0x0004u) /* TEC0EXCLRIFG */\r
7022 #define TEC0IV_TECAXCLRIFG (0x0006u) /* TEC0AXCLRIFG */\r
7023 \r
7024 #endif\r
7025 /************************************************************\r
7026 * Timer Event Control x\r
7027 ************************************************************/\r
7028 #ifdef __MSP430_HAS_TEVx__ /* Definition to show that Module is available */\r
7029 \r
7030 #define OFS_TECxXCTL0 (0x0000u) /* Timer Event Control x External Control 0 */\r
7031 #define OFS_TECxXCTL0_L OFS_TECxXCTL0\r
7032 #define OFS_TECxXCTL0_H OFS_TECxXCTL0+1\r
7033 #define OFS_TECxXCTL1 (0x0002u) /* Timer Event Control x External Control 1 */\r
7034 #define OFS_TECxXCTL1_L OFS_TECxXCTL1\r
7035 #define OFS_TECxXCTL1_H OFS_TECxXCTL1+1\r
7036 #define OFS_TECxXCTL2 (0x0004u) /* Timer Event Control x External Control 2 */\r
7037 #define OFS_TECxXCTL2_L OFS_TECxXCTL2\r
7038 #define OFS_TECxXCTL2_H OFS_TECxXCTL2+1\r
7039 #define OFS_TECxSTA (0x0006u) /* Timer Event Control x Status */\r
7040 #define OFS_TECxSTA_L OFS_TECxSTA\r
7041 #define OFS_TECxSTA_H OFS_TECxSTA+1\r
7042 #define OFS_TECxXINT (0x0008u) /* Timer Event Control x External Interrupt */\r
7043 #define OFS_TECxXINT_L OFS_TECxXINT\r
7044 #define OFS_TECxXINT_H OFS_TECxXINT+1\r
7045 #define OFS_TECxIV (0x000Au) /* Timer Event Control x Interrupt Vector */\r
7046 #define OFS_TECxIV_L OFS_TECxIV\r
7047 #define OFS_TECxIV_H OFS_TECxIV+1\r
7048 \r
7049 /* TECIV Definitions */\r
7050 #define TECxIV_NONE (0x0000u) /* No Interrupt pending */\r
7051 #define TECxIV_TECXFLTIFG (0x0002u) /* TECxXFLTIFG */\r
7052 #define TECxIV_TECEXCLRIFG (0x0004u) /* TECxEXCLRIFG */\r
7053 #define TECxIV_TECAXCLRIFG (0x0006u) /* TECxAXCLRIFG */\r
7054 \r
7055 \r
7056 #endif\r
7057 \r
7058 /************************************************************\r
7059 * UNIFIED CLOCK SYSTEM\r
7060 ************************************************************/\r
7061 #ifdef __MSP430_HAS_UCS__ /* Definition to show that Module is available */\r
7062 \r
7063 #define OFS_UCSCTL0 (0x0000u) /* UCS Control Register 0 */\r
7064 #define OFS_UCSCTL0_L OFS_UCSCTL0\r
7065 #define OFS_UCSCTL0_H OFS_UCSCTL0+1\r
7066 #define OFS_UCSCTL1 (0x0002u) /* UCS Control Register 1 */\r
7067 #define OFS_UCSCTL1_L OFS_UCSCTL1\r
7068 #define OFS_UCSCTL1_H OFS_UCSCTL1+1\r
7069 #define OFS_UCSCTL2 (0x0004u) /* UCS Control Register 2 */\r
7070 #define OFS_UCSCTL2_L OFS_UCSCTL2\r
7071 #define OFS_UCSCTL2_H OFS_UCSCTL2+1\r
7072 #define OFS_UCSCTL3 (0x0006u) /* UCS Control Register 3 */\r
7073 #define OFS_UCSCTL3_L OFS_UCSCTL3\r
7074 #define OFS_UCSCTL3_H OFS_UCSCTL3+1\r
7075 #define OFS_UCSCTL4 (0x0008u) /* UCS Control Register 4 */\r
7076 #define OFS_UCSCTL4_L OFS_UCSCTL4\r
7077 #define OFS_UCSCTL4_H OFS_UCSCTL4+1\r
7078 #define OFS_UCSCTL5 (0x000Au) /* UCS Control Register 5 */\r
7079 #define OFS_UCSCTL5_L OFS_UCSCTL5\r
7080 #define OFS_UCSCTL5_H OFS_UCSCTL5+1\r
7081 #define OFS_UCSCTL6 (0x000Cu) /* UCS Control Register 6 */\r
7082 #define OFS_UCSCTL6_L OFS_UCSCTL6\r
7083 #define OFS_UCSCTL6_H OFS_UCSCTL6+1\r
7084 #define OFS_UCSCTL7 (0x000Eu) /* UCS Control Register 7 */\r
7085 #define OFS_UCSCTL7_L OFS_UCSCTL7\r
7086 #define OFS_UCSCTL7_H OFS_UCSCTL7+1\r
7087 #define OFS_UCSCTL8 (0x0010u) /* UCS Control Register 8 */\r
7088 #define OFS_UCSCTL8_L OFS_UCSCTL8\r
7089 #define OFS_UCSCTL8_H OFS_UCSCTL8+1\r
7090 \r
7091 /* UCSCTL0 Control Bits */\r
7092 //#define RESERVED (0x0001u) /* RESERVED */\r
7093 //#define RESERVED (0x0002u) /* RESERVED */\r
7094 //#define RESERVED (0x0004u) /* RESERVED */\r
7095 #define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */\r
7096 #define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */\r
7097 #define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */\r
7098 #define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */\r
7099 #define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */\r
7100 #define DCO0 (0x0100u) /* DCO TAP Bit : 0 */\r
7101 #define DCO1 (0x0200u) /* DCO TAP Bit : 1 */\r
7102 #define DCO2 (0x0400u) /* DCO TAP Bit : 2 */\r
7103 #define DCO3 (0x0800u) /* DCO TAP Bit : 3 */\r
7104 #define DCO4 (0x1000u) /* DCO TAP Bit : 4 */\r
7105 //#define RESERVED (0x2000u) /* RESERVED */\r
7106 //#define RESERVED (0x4000u) /* RESERVED */\r
7107 //#define RESERVED (0x8000u) /* RESERVED */\r
7108 \r
7109 /* UCSCTL0 Control Bits */\r
7110 //#define RESERVED (0x0001u) /* RESERVED */\r
7111 //#define RESERVED (0x0002u) /* RESERVED */\r
7112 //#define RESERVED (0x0004u) /* RESERVED */\r
7113 #define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */\r
7114 #define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */\r
7115 #define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */\r
7116 #define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */\r
7117 #define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */\r
7118 //#define RESERVED (0x2000u) /* RESERVED */\r
7119 //#define RESERVED (0x4000u) /* RESERVED */\r
7120 //#define RESERVED (0x8000u) /* RESERVED */\r
7121 \r
7122 /* UCSCTL0 Control Bits */\r
7123 //#define RESERVED (0x0001u) /* RESERVED */\r
7124 //#define RESERVED (0x0002u) /* RESERVED */\r
7125 //#define RESERVED (0x0004u) /* RESERVED */\r
7126 #define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */\r
7127 #define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */\r
7128 #define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */\r
7129 #define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */\r
7130 #define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */\r
7131 //#define RESERVED (0x2000u) /* RESERVED */\r
7132 //#define RESERVED (0x4000u) /* RESERVED */\r
7133 //#define RESERVED (0x8000u) /* RESERVED */\r
7134 \r
7135 /* UCSCTL1 Control Bits */\r
7136 #define DISMOD (0x0001u) /* Disable Modulation */\r
7137 //#define RESERVED (0x0002u) /* RESERVED */\r
7138 //#define RESERVED (0x0004u) /* RESERVED */\r
7139 //#define RESERVED (0x0008u) /* RESERVED */\r
7140 #define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */\r
7141 #define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */\r
7142 #define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */\r
7143 //#define RESERVED (0x0080u) /* RESERVED */\r
7144 //#define RESERVED (0x0100u) /* RESERVED */\r
7145 //#define RESERVED (0x0200u) /* RESERVED */\r
7146 //#define RESERVED (0x0400u) /* RESERVED */\r
7147 //#define RESERVED (0x0800u) /* RESERVED */\r
7148 //#define RESERVED (0x1000u) /* RESERVED */\r
7149 //#define RESERVED (0x2000u) /* RESERVED */\r
7150 //#define RESERVED (0x4000u) /* RESERVED */\r
7151 //#define RESERVED (0x8000u) /* RESERVED */\r
7152 \r
7153 /* UCSCTL1 Control Bits */\r
7154 #define DISMOD_L (0x0001u) /* Disable Modulation */\r
7155 //#define RESERVED (0x0002u) /* RESERVED */\r
7156 //#define RESERVED (0x0004u) /* RESERVED */\r
7157 //#define RESERVED (0x0008u) /* RESERVED */\r
7158 #define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */\r
7159 #define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */\r
7160 #define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */\r
7161 //#define RESERVED (0x0080u) /* RESERVED */\r
7162 //#define RESERVED (0x0100u) /* RESERVED */\r
7163 //#define RESERVED (0x0200u) /* RESERVED */\r
7164 //#define RESERVED (0x0400u) /* RESERVED */\r
7165 //#define RESERVED (0x0800u) /* RESERVED */\r
7166 //#define RESERVED (0x1000u) /* RESERVED */\r
7167 //#define RESERVED (0x2000u) /* RESERVED */\r
7168 //#define RESERVED (0x4000u) /* RESERVED */\r
7169 //#define RESERVED (0x8000u) /* RESERVED */\r
7170 \r
7171 #define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */\r
7172 #define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */\r
7173 #define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */\r
7174 #define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */\r
7175 #define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */\r
7176 #define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */\r
7177 #define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */\r
7178 #define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */\r
7179 \r
7180 /* UCSCTL2 Control Bits */\r
7181 #define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */\r
7182 #define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */\r
7183 #define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */\r
7184 #define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */\r
7185 #define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */\r
7186 #define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */\r
7187 #define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */\r
7188 #define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */\r
7189 #define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */\r
7190 #define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */\r
7191 //#define RESERVED (0x0400u) /* RESERVED */\r
7192 //#define RESERVED (0x0800u) /* RESERVED */\r
7193 #define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */\r
7194 #define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */\r
7195 #define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */\r
7196 //#define RESERVED (0x8000u) /* RESERVED */\r
7197 \r
7198 /* UCSCTL2 Control Bits */\r
7199 #define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */\r
7200 #define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */\r
7201 #define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */\r
7202 #define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */\r
7203 #define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */\r
7204 #define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */\r
7205 #define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */\r
7206 #define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */\r
7207 //#define RESERVED (0x0400u) /* RESERVED */\r
7208 //#define RESERVED (0x0800u) /* RESERVED */\r
7209 //#define RESERVED (0x8000u) /* RESERVED */\r
7210 \r
7211 /* UCSCTL2 Control Bits */\r
7212 #define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */\r
7213 #define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */\r
7214 //#define RESERVED (0x0400u) /* RESERVED */\r
7215 //#define RESERVED (0x0800u) /* RESERVED */\r
7216 #define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */\r
7217 #define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */\r
7218 #define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */\r
7219 //#define RESERVED (0x8000u) /* RESERVED */\r
7220 \r
7221 #define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */\r
7222 #define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */\r
7223 #define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */\r
7224 #define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */\r
7225 #define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */\r
7226 #define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */\r
7227 #define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */\r
7228 #define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */\r
7229 #define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */\r
7230 #define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */\r
7231 #define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */\r
7232 #define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */\r
7233 #define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */\r
7234 #define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */\r
7235 \r
7236 /* UCSCTL3 Control Bits */\r
7237 #define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */\r
7238 #define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */\r
7239 #define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */\r
7240 //#define RESERVED (0x0008u) /* RESERVED */\r
7241 #define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */\r
7242 #define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */\r
7243 #define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */\r
7244 //#define RESERVED (0x0080u) /* RESERVED */\r
7245 //#define RESERVED (0x0100u) /* RESERVED */\r
7246 //#define RESERVED (0x0200u) /* RESERVED */\r
7247 //#define RESERVED (0x0400u) /* RESERVED */\r
7248 //#define RESERVED (0x0800u) /* RESERVED */\r
7249 //#define RESERVED (0x1000u) /* RESERVED */\r
7250 //#define RESERVED (0x2000u) /* RESERVED */\r
7251 //#define RESERVED (0x4000u) /* RESERVED */\r
7252 //#define RESERVED (0x8000u) /* RESERVED */\r
7253 \r
7254 /* UCSCTL3 Control Bits */\r
7255 #define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */\r
7256 #define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */\r
7257 #define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */\r
7258 //#define RESERVED (0x0008u) /* RESERVED */\r
7259 #define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */\r
7260 #define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */\r
7261 #define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */\r
7262 //#define RESERVED (0x0080u) /* RESERVED */\r
7263 //#define RESERVED (0x0100u) /* RESERVED */\r
7264 //#define RESERVED (0x0200u) /* RESERVED */\r
7265 //#define RESERVED (0x0400u) /* RESERVED */\r
7266 //#define RESERVED (0x0800u) /* RESERVED */\r
7267 //#define RESERVED (0x1000u) /* RESERVED */\r
7268 //#define RESERVED (0x2000u) /* RESERVED */\r
7269 //#define RESERVED (0x4000u) /* RESERVED */\r
7270 //#define RESERVED (0x8000u) /* RESERVED */\r
7271 \r
7272 #define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */\r
7273 #define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */\r
7274 #define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */\r
7275 #define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */\r
7276 #define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */\r
7277 #define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */\r
7278 #define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */\r
7279 #define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */\r
7280 #define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */\r
7281 #define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */\r
7282 #define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */\r
7283 #define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */\r
7284 #define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */\r
7285 #define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */\r
7286 #define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */\r
7287 #define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */\r
7288 #define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */\r
7289 #define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */\r
7290 #define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */\r
7291 #define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */\r
7292 #define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */\r
7293 #define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */\r
7294 #define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */\r
7295 #define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */\r
7296 #define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */\r
7297 \r
7298 /* UCSCTL4 Control Bits */\r
7299 #define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */\r
7300 #define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */\r
7301 #define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */\r
7302 //#define RESERVED (0x0008u) /* RESERVED */\r
7303 #define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */\r
7304 #define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */\r
7305 #define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */\r
7306 //#define RESERVED (0x0080u) /* RESERVED */\r
7307 #define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */\r
7308 #define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */\r
7309 #define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */\r
7310 //#define RESERVED (0x0800u) /* RESERVED */\r
7311 //#define RESERVED (0x1000u) /* RESERVED */\r
7312 //#define RESERVED (0x2000u) /* RESERVED */\r
7313 //#define RESERVED (0x4000u) /* RESERVED */\r
7314 //#define RESERVED (0x8000u) /* RESERVED */\r
7315 \r
7316 /* UCSCTL4 Control Bits */\r
7317 #define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */\r
7318 #define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */\r
7319 #define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */\r
7320 //#define RESERVED (0x0008u) /* RESERVED */\r
7321 #define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */\r
7322 #define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */\r
7323 #define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */\r
7324 //#define RESERVED (0x0080u) /* RESERVED */\r
7325 //#define RESERVED (0x0800u) /* RESERVED */\r
7326 //#define RESERVED (0x1000u) /* RESERVED */\r
7327 //#define RESERVED (0x2000u) /* RESERVED */\r
7328 //#define RESERVED (0x4000u) /* RESERVED */\r
7329 //#define RESERVED (0x8000u) /* RESERVED */\r
7330 \r
7331 /* UCSCTL4 Control Bits */\r
7332 //#define RESERVED (0x0008u) /* RESERVED */\r
7333 //#define RESERVED (0x0080u) /* RESERVED */\r
7334 #define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */\r
7335 #define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */\r
7336 #define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */\r
7337 //#define RESERVED (0x0800u) /* RESERVED */\r
7338 //#define RESERVED (0x1000u) /* RESERVED */\r
7339 //#define RESERVED (0x2000u) /* RESERVED */\r
7340 //#define RESERVED (0x4000u) /* RESERVED */\r
7341 //#define RESERVED (0x8000u) /* RESERVED */\r
7342 \r
7343 #define SELM_0 (0x0000u) /* MCLK Source Select 0 */\r
7344 #define SELM_1 (0x0001u) /* MCLK Source Select 1 */\r
7345 #define SELM_2 (0x0002u) /* MCLK Source Select 2 */\r
7346 #define SELM_3 (0x0003u) /* MCLK Source Select 3 */\r
7347 #define SELM_4 (0x0004u) /* MCLK Source Select 4 */\r
7348 #define SELM_5 (0x0005u) /* MCLK Source Select 5 */\r
7349 #define SELM_6 (0x0006u) /* MCLK Source Select 6 */\r
7350 #define SELM_7 (0x0007u) /* MCLK Source Select 7 */\r
7351 #define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */\r
7352 #define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */\r
7353 #define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */\r
7354 #define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */\r
7355 #define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */\r
7356 #define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */\r
7357 \r
7358 #define SELS_0 (0x0000u) /* SMCLK Source Select 0 */\r
7359 #define SELS_1 (0x0010u) /* SMCLK Source Select 1 */\r
7360 #define SELS_2 (0x0020u) /* SMCLK Source Select 2 */\r
7361 #define SELS_3 (0x0030u) /* SMCLK Source Select 3 */\r
7362 #define SELS_4 (0x0040u) /* SMCLK Source Select 4 */\r
7363 #define SELS_5 (0x0050u) /* SMCLK Source Select 5 */\r
7364 #define SELS_6 (0x0060u) /* SMCLK Source Select 6 */\r
7365 #define SELS_7 (0x0070u) /* SMCLK Source Select 7 */\r
7366 #define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */\r
7367 #define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */\r
7368 #define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */\r
7369 #define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */\r
7370 #define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */\r
7371 #define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */\r
7372 \r
7373 #define SELA_0 (0x0000u) /* ACLK Source Select 0 */\r
7374 #define SELA_1 (0x0100u) /* ACLK Source Select 1 */\r
7375 #define SELA_2 (0x0200u) /* ACLK Source Select 2 */\r
7376 #define SELA_3 (0x0300u) /* ACLK Source Select 3 */\r
7377 #define SELA_4 (0x0400u) /* ACLK Source Select 4 */\r
7378 #define SELA_5 (0x0500u) /* ACLK Source Select 5 */\r
7379 #define SELA_6 (0x0600u) /* ACLK Source Select 6 */\r
7380 #define SELA_7 (0x0700u) /* ACLK Source Select 7 */\r
7381 #define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */\r
7382 #define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */\r
7383 #define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */\r
7384 #define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */\r
7385 #define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */\r
7386 #define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */\r
7387 \r
7388 /* UCSCTL5 Control Bits */\r
7389 #define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */\r
7390 #define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */\r
7391 #define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */\r
7392 //#define RESERVED (0x0008u) /* RESERVED */\r
7393 #define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */\r
7394 #define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */\r
7395 #define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */\r
7396 //#define RESERVED (0x0080u) /* RESERVED */\r
7397 #define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */\r
7398 #define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */\r
7399 #define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */\r
7400 //#define RESERVED (0x0800u) /* RESERVED */\r
7401 #define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */\r
7402 #define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */\r
7403 #define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */\r
7404 //#define RESERVED (0x8000u) /* RESERVED */\r
7405 \r
7406 /* UCSCTL5 Control Bits */\r
7407 #define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */\r
7408 #define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */\r
7409 #define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */\r
7410 //#define RESERVED (0x0008u) /* RESERVED */\r
7411 #define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */\r
7412 #define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */\r
7413 #define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */\r
7414 //#define RESERVED (0x0080u) /* RESERVED */\r
7415 //#define RESERVED (0x0800u) /* RESERVED */\r
7416 //#define RESERVED (0x8000u) /* RESERVED */\r
7417 \r
7418 /* UCSCTL5 Control Bits */\r
7419 //#define RESERVED (0x0008u) /* RESERVED */\r
7420 //#define RESERVED (0x0080u) /* RESERVED */\r
7421 #define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */\r
7422 #define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */\r
7423 #define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */\r
7424 //#define RESERVED (0x0800u) /* RESERVED */\r
7425 #define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */\r
7426 #define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */\r
7427 #define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */\r
7428 //#define RESERVED (0x8000u) /* RESERVED */\r
7429 \r
7430 #define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */\r
7431 #define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */\r
7432 #define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */\r
7433 #define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */\r
7434 #define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */\r
7435 #define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */\r
7436 #define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */\r
7437 #define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */\r
7438 #define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */\r
7439 #define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */\r
7440 #define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */\r
7441 #define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */\r
7442 #define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */\r
7443 #define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */\r
7444 \r
7445 #define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */\r
7446 #define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */\r
7447 #define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */\r
7448 #define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */\r
7449 #define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */\r
7450 #define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */\r
7451 #define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */\r
7452 #define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */\r
7453 #define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */\r
7454 #define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */\r
7455 #define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */\r
7456 #define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */\r
7457 #define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */\r
7458 #define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */\r
7459 \r
7460 #define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */\r
7461 #define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */\r
7462 #define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */\r
7463 #define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */\r
7464 #define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */\r
7465 #define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */\r
7466 #define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */\r
7467 #define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */\r
7468 #define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */\r
7469 #define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */\r
7470 #define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */\r
7471 #define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */\r
7472 #define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */\r
7473 #define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */\r
7474 \r
7475 #define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */\r
7476 #define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */\r
7477 #define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */\r
7478 #define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */\r
7479 #define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */\r
7480 #define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */\r
7481 #define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */\r
7482 #define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */\r
7483 #define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */\r
7484 #define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */\r
7485 #define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */\r
7486 #define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */\r
7487 #define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */\r
7488 #define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */\r
7489 \r
7490 /* UCSCTL6 Control Bits */\r
7491 #define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
7492 #define SMCLKOFF (0x0002u) /* SMCLK Off */\r
7493 #define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */\r
7494 #define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */\r
7495 #define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */\r
7496 #define XTS (0x0020u) /* 1: Selects high-freq. oscillator */\r
7497 #define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */\r
7498 #define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */\r
7499 #define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */\r
7500 //#define RESERVED (0x0200u) /* RESERVED */\r
7501 //#define RESERVED (0x0400u) /* RESERVED */\r
7502 //#define RESERVED (0x0800u) /* RESERVED */\r
7503 #define XT2BYPASS (0x1000u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */\r
7504 //#define RESERVED (0x2000u) /* RESERVED */\r
7505 #define XT2DRIVE0 (0x4000u) /* XT2 Drive Level mode Bit 0 */\r
7506 #define XT2DRIVE1 (0x8000u) /* XT2 Drive Level mode Bit 1 */\r
7507 \r
7508 /* UCSCTL6 Control Bits */\r
7509 #define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
7510 #define SMCLKOFF_L (0x0002u) /* SMCLK Off */\r
7511 #define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */\r
7512 #define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */\r
7513 #define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */\r
7514 #define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */\r
7515 #define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */\r
7516 #define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */\r
7517 //#define RESERVED (0x0200u) /* RESERVED */\r
7518 //#define RESERVED (0x0400u) /* RESERVED */\r
7519 //#define RESERVED (0x0800u) /* RESERVED */\r
7520 //#define RESERVED (0x2000u) /* RESERVED */\r
7521 \r
7522 /* UCSCTL6 Control Bits */\r
7523 #define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */\r
7524 //#define RESERVED (0x0200u) /* RESERVED */\r
7525 //#define RESERVED (0x0400u) /* RESERVED */\r
7526 //#define RESERVED (0x0800u) /* RESERVED */\r
7527 #define XT2BYPASS_H (0x0010u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */\r
7528 //#define RESERVED (0x2000u) /* RESERVED */\r
7529 #define XT2DRIVE0_H (0x0040u) /* XT2 Drive Level mode Bit 0 */\r
7530 #define XT2DRIVE1_H (0x0080u) /* XT2 Drive Level mode Bit 1 */\r
7531 \r
7532 #define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */\r
7533 #define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */\r
7534 #define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */\r
7535 #define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */\r
7536 #define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */\r
7537 #define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */\r
7538 #define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */\r
7539 #define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */\r
7540 #define XT2DRIVE_0 (0x0000u) /* XT2 Drive Level mode: 0 */\r
7541 #define XT2DRIVE_1 (0x4000u) /* XT2 Drive Level mode: 1 */\r
7542 #define XT2DRIVE_2 (0x8000u) /* XT2 Drive Level mode: 2 */\r
7543 #define XT2DRIVE_3 (0xC000u) /* XT2 Drive Level mode: 3 */\r
7544 \r
7545 /* UCSCTL7 Control Bits */\r
7546 #define DCOFFG (0x0001u) /* DCO Fault Flag */\r
7547 #define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */\r
7548 #define XT1HFOFFG (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */\r
7549 #define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */\r
7550 //#define RESERVED (0x0010u) /* RESERVED */\r
7551 //#define RESERVED (0x0020u) /* RESERVED */\r
7552 //#define RESERVED (0x0040u) /* RESERVED */\r
7553 //#define RESERVED (0x0080u) /* RESERVED */\r
7554 //#define RESERVED (0x0100u) /* RESERVED */\r
7555 //#define RESERVED (0x0200u) /* RESERVED */\r
7556 //#define RESERVED (0x0400u) /* RESERVED */\r
7557 //#define RESERVED (0x0800u) /* RESERVED */\r
7558 //#define RESERVED (0x1000u) /* RESERVED */\r
7559 //#define RESERVED (0x2000u) /* RESERVED */\r
7560 //#define RESERVED (0x4000u) /* RESERVED */\r
7561 //#define RESERVED (0x8000u) /* RESERVED */\r
7562 \r
7563 /* UCSCTL7 Control Bits */\r
7564 #define DCOFFG_L (0x0001u) /* DCO Fault Flag */\r
7565 #define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */\r
7566 #define XT1HFOFFG_L (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */\r
7567 #define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */\r
7568 //#define RESERVED (0x0010u) /* RESERVED */\r
7569 //#define RESERVED (0x0020u) /* RESERVED */\r
7570 //#define RESERVED (0x0040u) /* RESERVED */\r
7571 //#define RESERVED (0x0080u) /* RESERVED */\r
7572 //#define RESERVED (0x0100u) /* RESERVED */\r
7573 //#define RESERVED (0x0200u) /* RESERVED */\r
7574 //#define RESERVED (0x0400u) /* RESERVED */\r
7575 //#define RESERVED (0x0800u) /* RESERVED */\r
7576 //#define RESERVED (0x1000u) /* RESERVED */\r
7577 //#define RESERVED (0x2000u) /* RESERVED */\r
7578 //#define RESERVED (0x4000u) /* RESERVED */\r
7579 //#define RESERVED (0x8000u) /* RESERVED */\r
7580 \r
7581 /* UCSCTL8 Control Bits */\r
7582 #define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */\r
7583 #define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */\r
7584 #define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */\r
7585 #define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */\r
7586 //#define RESERVED (0x0010u) /* RESERVED */\r
7587 //#define RESERVED (0x0020u) /* RESERVED */\r
7588 //#define RESERVED (0x0040u) /* RESERVED */\r
7589 //#define RESERVED (0x0080u) /* RESERVED */\r
7590 //#define RESERVED (0x0100u) /* RESERVED */\r
7591 //#define RESERVED (0x0200u) /* RESERVED */\r
7592 //#define RESERVED (0x0400u) /* RESERVED */\r
7593 //#define RESERVED (0x0800u) /* RESERVED */\r
7594 //#define RESERVED (0x1000u) /* RESERVED */\r
7595 //#define RESERVED (0x2000u) /* RESERVED */\r
7596 //#define RESERVED (0x4000u) /* RESERVED */\r
7597 //#define RESERVED (0x8000u) /* RESERVED */\r
7598 \r
7599 /* UCSCTL8 Control Bits */\r
7600 #define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */\r
7601 #define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */\r
7602 #define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */\r
7603 #define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */\r
7604 //#define RESERVED (0x0010u) /* RESERVED */\r
7605 //#define RESERVED (0x0020u) /* RESERVED */\r
7606 //#define RESERVED (0x0040u) /* RESERVED */\r
7607 //#define RESERVED (0x0080u) /* RESERVED */\r
7608 //#define RESERVED (0x0100u) /* RESERVED */\r
7609 //#define RESERVED (0x0200u) /* RESERVED */\r
7610 //#define RESERVED (0x0400u) /* RESERVED */\r
7611 //#define RESERVED (0x0800u) /* RESERVED */\r
7612 //#define RESERVED (0x1000u) /* RESERVED */\r
7613 //#define RESERVED (0x2000u) /* RESERVED */\r
7614 //#define RESERVED (0x4000u) /* RESERVED */\r
7615 //#define RESERVED (0x8000u) /* RESERVED */\r
7616 \r
7617 #endif\r
7618 /************************************************************\r
7619 * UNIFIED CLOCK SYSTEM FOR Radio Devices\r
7620 ************************************************************/\r
7621 #ifdef __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */\r
7622 \r
7623 #define OFS_UCSCTL0 (0x0000u) /* UCS Control Register 0 */\r
7624 #define OFS_UCSCTL0_L OFS_UCSCTL0\r
7625 #define OFS_UCSCTL0_H OFS_UCSCTL0+1\r
7626 #define OFS_UCSCTL1 (0x0002u) /* UCS Control Register 1 */\r
7627 #define OFS_UCSCTL1_L OFS_UCSCTL1\r
7628 #define OFS_UCSCTL1_H OFS_UCSCTL1+1\r
7629 #define OFS_UCSCTL2 (0x0004u) /* UCS Control Register 2 */\r
7630 #define OFS_UCSCTL2_L OFS_UCSCTL2\r
7631 #define OFS_UCSCTL2_H OFS_UCSCTL2+1\r
7632 #define OFS_UCSCTL3 (0x0006u) /* UCS Control Register 3 */\r
7633 #define OFS_UCSCTL3_L OFS_UCSCTL3\r
7634 #define OFS_UCSCTL3_H OFS_UCSCTL3+1\r
7635 #define OFS_UCSCTL4 (0x0008u) /* UCS Control Register 4 */\r
7636 #define OFS_UCSCTL4_L OFS_UCSCTL4\r
7637 #define OFS_UCSCTL4_H OFS_UCSCTL4+1\r
7638 #define OFS_UCSCTL5 (0x000Au) /* UCS Control Register 5 */\r
7639 #define OFS_UCSCTL5_L OFS_UCSCTL5\r
7640 #define OFS_UCSCTL5_H OFS_UCSCTL5+1\r
7641 #define OFS_UCSCTL6 (0x000Cu) /* UCS Control Register 6 */\r
7642 #define OFS_UCSCTL6_L OFS_UCSCTL6\r
7643 #define OFS_UCSCTL6_H OFS_UCSCTL6+1\r
7644 #define OFS_UCSCTL7 (0x000Eu) /* UCS Control Register 7 */\r
7645 #define OFS_UCSCTL7_L OFS_UCSCTL7\r
7646 #define OFS_UCSCTL7_H OFS_UCSCTL7+1\r
7647 #define OFS_UCSCTL8 (0x0010u) /* UCS Control Register 8 */\r
7648 #define OFS_UCSCTL8_L OFS_UCSCTL8\r
7649 #define OFS_UCSCTL8_H OFS_UCSCTL8+1\r
7650 \r
7651 /* UCSCTL0 Control Bits */\r
7652 //#define RESERVED (0x0001u) /* RESERVED */\r
7653 //#define RESERVED (0x0002u) /* RESERVED */\r
7654 //#define RESERVED (0x0004u) /* RESERVED */\r
7655 #define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */\r
7656 #define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */\r
7657 #define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */\r
7658 #define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */\r
7659 #define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */\r
7660 #define DCO0 (0x0100u) /* DCO TAP Bit : 0 */\r
7661 #define DCO1 (0x0200u) /* DCO TAP Bit : 1 */\r
7662 #define DCO2 (0x0400u) /* DCO TAP Bit : 2 */\r
7663 #define DCO3 (0x0800u) /* DCO TAP Bit : 3 */\r
7664 #define DCO4 (0x1000u) /* DCO TAP Bit : 4 */\r
7665 //#define RESERVED (0x2000u) /* RESERVED */\r
7666 //#define RESERVED (0x4000u) /* RESERVED */\r
7667 //#define RESERVED (0x8000u) /* RESERVED */\r
7668 \r
7669 /* UCSCTL0 Control Bits */\r
7670 //#define RESERVED (0x0001u) /* RESERVED */\r
7671 //#define RESERVED (0x0002u) /* RESERVED */\r
7672 //#define RESERVED (0x0004u) /* RESERVED */\r
7673 #define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */\r
7674 #define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */\r
7675 #define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */\r
7676 #define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */\r
7677 #define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */\r
7678 //#define RESERVED (0x2000u) /* RESERVED */\r
7679 //#define RESERVED (0x4000u) /* RESERVED */\r
7680 //#define RESERVED (0x8000u) /* RESERVED */\r
7681 \r
7682 /* UCSCTL0 Control Bits */\r
7683 //#define RESERVED (0x0001u) /* RESERVED */\r
7684 //#define RESERVED (0x0002u) /* RESERVED */\r
7685 //#define RESERVED (0x0004u) /* RESERVED */\r
7686 #define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */\r
7687 #define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */\r
7688 #define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */\r
7689 #define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */\r
7690 #define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */\r
7691 //#define RESERVED (0x2000u) /* RESERVED */\r
7692 //#define RESERVED (0x4000u) /* RESERVED */\r
7693 //#define RESERVED (0x8000u) /* RESERVED */\r
7694 \r
7695 /* UCSCTL1 Control Bits */\r
7696 #define DISMOD (0x0001u) /* Disable Modulation */\r
7697 //#define RESERVED (0x0002u) /* RESERVED */\r
7698 //#define RESERVED (0x0004u) /* RESERVED */\r
7699 //#define RESERVED (0x0008u) /* RESERVED */\r
7700 #define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */\r
7701 #define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */\r
7702 #define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */\r
7703 //#define RESERVED (0x0080u) /* RESERVED */\r
7704 //#define RESERVED (0x0100u) /* RESERVED */\r
7705 //#define RESERVED (0x0200u) /* RESERVED */\r
7706 //#define RESERVED (0x0400u) /* RESERVED */\r
7707 //#define RESERVED (0x0800u) /* RESERVED */\r
7708 //#define RESERVED (0x1000u) /* RESERVED */\r
7709 //#define RESERVED (0x2000u) /* RESERVED */\r
7710 //#define RESERVED (0x4000u) /* RESERVED */\r
7711 //#define RESERVED (0x8000u) /* RESERVED */\r
7712 \r
7713 /* UCSCTL1 Control Bits */\r
7714 #define DISMOD_L (0x0001u) /* Disable Modulation */\r
7715 //#define RESERVED (0x0002u) /* RESERVED */\r
7716 //#define RESERVED (0x0004u) /* RESERVED */\r
7717 //#define RESERVED (0x0008u) /* RESERVED */\r
7718 #define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */\r
7719 #define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */\r
7720 #define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */\r
7721 //#define RESERVED (0x0080u) /* RESERVED */\r
7722 //#define RESERVED (0x0100u) /* RESERVED */\r
7723 //#define RESERVED (0x0200u) /* RESERVED */\r
7724 //#define RESERVED (0x0400u) /* RESERVED */\r
7725 //#define RESERVED (0x0800u) /* RESERVED */\r
7726 //#define RESERVED (0x1000u) /* RESERVED */\r
7727 //#define RESERVED (0x2000u) /* RESERVED */\r
7728 //#define RESERVED (0x4000u) /* RESERVED */\r
7729 //#define RESERVED (0x8000u) /* RESERVED */\r
7730 \r
7731 #define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */\r
7732 #define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */\r
7733 #define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */\r
7734 #define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */\r
7735 #define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */\r
7736 #define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */\r
7737 #define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */\r
7738 #define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */\r
7739 \r
7740 /* UCSCTL2 Control Bits */\r
7741 #define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */\r
7742 #define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */\r
7743 #define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */\r
7744 #define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */\r
7745 #define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */\r
7746 #define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */\r
7747 #define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */\r
7748 #define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */\r
7749 #define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */\r
7750 #define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */\r
7751 //#define RESERVED (0x0400u) /* RESERVED */\r
7752 //#define RESERVED (0x0800u) /* RESERVED */\r
7753 #define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */\r
7754 #define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */\r
7755 #define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */\r
7756 //#define RESERVED (0x8000u) /* RESERVED */\r
7757 \r
7758 /* UCSCTL2 Control Bits */\r
7759 #define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */\r
7760 #define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */\r
7761 #define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */\r
7762 #define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */\r
7763 #define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */\r
7764 #define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */\r
7765 #define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */\r
7766 #define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */\r
7767 //#define RESERVED (0x0400u) /* RESERVED */\r
7768 //#define RESERVED (0x0800u) /* RESERVED */\r
7769 //#define RESERVED (0x8000u) /* RESERVED */\r
7770 \r
7771 /* UCSCTL2 Control Bits */\r
7772 #define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */\r
7773 #define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */\r
7774 //#define RESERVED (0x0400u) /* RESERVED */\r
7775 //#define RESERVED (0x0800u) /* RESERVED */\r
7776 #define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */\r
7777 #define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */\r
7778 #define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */\r
7779 //#define RESERVED (0x8000u) /* RESERVED */\r
7780 \r
7781 #define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */\r
7782 #define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */\r
7783 #define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */\r
7784 #define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */\r
7785 #define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */\r
7786 #define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */\r
7787 #define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */\r
7788 #define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */\r
7789 #define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */\r
7790 #define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */\r
7791 #define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */\r
7792 #define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */\r
7793 #define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */\r
7794 #define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */\r
7795 \r
7796 /* UCSCTL3 Control Bits */\r
7797 #define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */\r
7798 #define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */\r
7799 #define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */\r
7800 //#define RESERVED (0x0008u) /* RESERVED */\r
7801 #define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */\r
7802 #define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */\r
7803 #define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */\r
7804 //#define RESERVED (0x0080u) /* RESERVED */\r
7805 //#define RESERVED (0x0100u) /* RESERVED */\r
7806 //#define RESERVED (0x0200u) /* RESERVED */\r
7807 //#define RESERVED (0x0400u) /* RESERVED */\r
7808 //#define RESERVED (0x0800u) /* RESERVED */\r
7809 //#define RESERVED (0x1000u) /* RESERVED */\r
7810 //#define RESERVED (0x2000u) /* RESERVED */\r
7811 //#define RESERVED (0x4000u) /* RESERVED */\r
7812 //#define RESERVED (0x8000u) /* RESERVED */\r
7813 \r
7814 /* UCSCTL3 Control Bits */\r
7815 #define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */\r
7816 #define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */\r
7817 #define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */\r
7818 //#define RESERVED (0x0008u) /* RESERVED */\r
7819 #define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */\r
7820 #define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */\r
7821 #define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */\r
7822 //#define RESERVED (0x0080u) /* RESERVED */\r
7823 //#define RESERVED (0x0100u) /* RESERVED */\r
7824 //#define RESERVED (0x0200u) /* RESERVED */\r
7825 //#define RESERVED (0x0400u) /* RESERVED */\r
7826 //#define RESERVED (0x0800u) /* RESERVED */\r
7827 //#define RESERVED (0x1000u) /* RESERVED */\r
7828 //#define RESERVED (0x2000u) /* RESERVED */\r
7829 //#define RESERVED (0x4000u) /* RESERVED */\r
7830 //#define RESERVED (0x8000u) /* RESERVED */\r
7831 \r
7832 #define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */\r
7833 #define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */\r
7834 #define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */\r
7835 #define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */\r
7836 #define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */\r
7837 #define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */\r
7838 #define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */\r
7839 #define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */\r
7840 #define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */\r
7841 #define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */\r
7842 #define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */\r
7843 #define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */\r
7844 #define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */\r
7845 #define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */\r
7846 #define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */\r
7847 #define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */\r
7848 #define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */\r
7849 #define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */\r
7850 #define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */\r
7851 #define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */\r
7852 #define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */\r
7853 #define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */\r
7854 #define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */\r
7855 #define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */\r
7856 #define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */\r
7857 \r
7858 /* UCSCTL4 Control Bits */\r
7859 #define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */\r
7860 #define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */\r
7861 #define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */\r
7862 //#define RESERVED (0x0008u) /* RESERVED */\r
7863 #define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */\r
7864 #define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */\r
7865 #define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */\r
7866 //#define RESERVED (0x0080u) /* RESERVED */\r
7867 #define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */\r
7868 #define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */\r
7869 #define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */\r
7870 //#define RESERVED (0x0800u) /* RESERVED */\r
7871 //#define RESERVED (0x1000u) /* RESERVED */\r
7872 //#define RESERVED (0x2000u) /* RESERVED */\r
7873 //#define RESERVED (0x4000u) /* RESERVED */\r
7874 //#define RESERVED (0x8000u) /* RESERVED */\r
7875 \r
7876 /* UCSCTL4 Control Bits */\r
7877 #define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */\r
7878 #define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */\r
7879 #define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */\r
7880 //#define RESERVED (0x0008u) /* RESERVED */\r
7881 #define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */\r
7882 #define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */\r
7883 #define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */\r
7884 //#define RESERVED (0x0080u) /* RESERVED */\r
7885 //#define RESERVED (0x0800u) /* RESERVED */\r
7886 //#define RESERVED (0x1000u) /* RESERVED */\r
7887 //#define RESERVED (0x2000u) /* RESERVED */\r
7888 //#define RESERVED (0x4000u) /* RESERVED */\r
7889 //#define RESERVED (0x8000u) /* RESERVED */\r
7890 \r
7891 /* UCSCTL4 Control Bits */\r
7892 //#define RESERVED (0x0008u) /* RESERVED */\r
7893 //#define RESERVED (0x0080u) /* RESERVED */\r
7894 #define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */\r
7895 #define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */\r
7896 #define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */\r
7897 //#define RESERVED (0x0800u) /* RESERVED */\r
7898 //#define RESERVED (0x1000u) /* RESERVED */\r
7899 //#define RESERVED (0x2000u) /* RESERVED */\r
7900 //#define RESERVED (0x4000u) /* RESERVED */\r
7901 //#define RESERVED (0x8000u) /* RESERVED */\r
7902 \r
7903 #define SELM_0 (0x0000u) /* MCLK Source Select 0 */\r
7904 #define SELM_1 (0x0001u) /* MCLK Source Select 1 */\r
7905 #define SELM_2 (0x0002u) /* MCLK Source Select 2 */\r
7906 #define SELM_3 (0x0003u) /* MCLK Source Select 3 */\r
7907 #define SELM_4 (0x0004u) /* MCLK Source Select 4 */\r
7908 #define SELM_5 (0x0005u) /* MCLK Source Select 5 */\r
7909 #define SELM_6 (0x0006u) /* MCLK Source Select 6 */\r
7910 #define SELM_7 (0x0007u) /* MCLK Source Select 7 */\r
7911 #define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */\r
7912 #define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */\r
7913 #define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */\r
7914 #define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */\r
7915 #define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */\r
7916 #define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */\r
7917 \r
7918 #define SELS_0 (0x0000u) /* SMCLK Source Select 0 */\r
7919 #define SELS_1 (0x0010u) /* SMCLK Source Select 1 */\r
7920 #define SELS_2 (0x0020u) /* SMCLK Source Select 2 */\r
7921 #define SELS_3 (0x0030u) /* SMCLK Source Select 3 */\r
7922 #define SELS_4 (0x0040u) /* SMCLK Source Select 4 */\r
7923 #define SELS_5 (0x0050u) /* SMCLK Source Select 5 */\r
7924 #define SELS_6 (0x0060u) /* SMCLK Source Select 6 */\r
7925 #define SELS_7 (0x0070u) /* SMCLK Source Select 7 */\r
7926 #define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */\r
7927 #define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */\r
7928 #define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */\r
7929 #define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */\r
7930 #define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */\r
7931 #define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */\r
7932 \r
7933 #define SELA_0 (0x0000u) /* ACLK Source Select 0 */\r
7934 #define SELA_1 (0x0100u) /* ACLK Source Select 1 */\r
7935 #define SELA_2 (0x0200u) /* ACLK Source Select 2 */\r
7936 #define SELA_3 (0x0300u) /* ACLK Source Select 3 */\r
7937 #define SELA_4 (0x0400u) /* ACLK Source Select 4 */\r
7938 #define SELA_5 (0x0500u) /* ACLK Source Select 5 */\r
7939 #define SELA_6 (0x0600u) /* ACLK Source Select 6 */\r
7940 #define SELA_7 (0x0700u) /* ACLK Source Select 7 */\r
7941 #define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */\r
7942 #define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */\r
7943 #define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */\r
7944 #define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */\r
7945 #define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */\r
7946 #define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */\r
7947 \r
7948 /* UCSCTL5 Control Bits */\r
7949 #define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */\r
7950 #define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */\r
7951 #define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */\r
7952 //#define RESERVED (0x0008u) /* RESERVED */\r
7953 #define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */\r
7954 #define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */\r
7955 #define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */\r
7956 //#define RESERVED (0x0080u) /* RESERVED */\r
7957 #define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */\r
7958 #define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */\r
7959 #define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */\r
7960 //#define RESERVED (0x0800u) /* RESERVED */\r
7961 #define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */\r
7962 #define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */\r
7963 #define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */\r
7964 //#define RESERVED (0x8000u) /* RESERVED */\r
7965 \r
7966 /* UCSCTL5 Control Bits */\r
7967 #define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */\r
7968 #define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */\r
7969 #define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */\r
7970 //#define RESERVED (0x0008u) /* RESERVED */\r
7971 #define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */\r
7972 #define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */\r
7973 #define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */\r
7974 //#define RESERVED (0x0080u) /* RESERVED */\r
7975 //#define RESERVED (0x0800u) /* RESERVED */\r
7976 //#define RESERVED (0x8000u) /* RESERVED */\r
7977 \r
7978 /* UCSCTL5 Control Bits */\r
7979 //#define RESERVED (0x0008u) /* RESERVED */\r
7980 //#define RESERVED (0x0080u) /* RESERVED */\r
7981 #define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */\r
7982 #define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */\r
7983 #define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */\r
7984 //#define RESERVED (0x0800u) /* RESERVED */\r
7985 #define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */\r
7986 #define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */\r
7987 #define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */\r
7988 //#define RESERVED (0x8000u) /* RESERVED */\r
7989 \r
7990 #define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */\r
7991 #define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */\r
7992 #define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */\r
7993 #define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */\r
7994 #define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */\r
7995 #define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */\r
7996 #define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */\r
7997 #define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */\r
7998 #define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */\r
7999 #define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */\r
8000 #define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */\r
8001 #define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */\r
8002 #define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */\r
8003 #define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */\r
8004 \r
8005 #define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */\r
8006 #define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */\r
8007 #define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */\r
8008 #define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */\r
8009 #define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */\r
8010 #define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */\r
8011 #define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */\r
8012 #define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */\r
8013 #define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */\r
8014 #define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */\r
8015 #define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */\r
8016 #define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */\r
8017 #define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */\r
8018 #define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */\r
8019 \r
8020 #define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */\r
8021 #define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */\r
8022 #define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */\r
8023 #define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */\r
8024 #define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */\r
8025 #define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */\r
8026 #define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */\r
8027 #define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */\r
8028 #define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */\r
8029 #define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */\r
8030 #define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */\r
8031 #define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */\r
8032 #define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */\r
8033 #define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */\r
8034 \r
8035 #define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */\r
8036 #define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */\r
8037 #define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */\r
8038 #define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */\r
8039 #define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */\r
8040 #define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */\r
8041 #define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */\r
8042 #define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */\r
8043 #define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */\r
8044 #define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */\r
8045 #define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */\r
8046 #define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */\r
8047 #define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */\r
8048 #define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */\r
8049 \r
8050 /* UCSCTL6 Control Bits */\r
8051 #define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
8052 #define SMCLKOFF (0x0002u) /* SMCLK Off */\r
8053 #define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */\r
8054 #define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */\r
8055 #define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */\r
8056 #define XTS (0x0020u) /* 1: Selects high-freq. oscillator */\r
8057 #define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */\r
8058 #define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */\r
8059 #define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */\r
8060 //#define RESERVED (0x0200u) /* RESERVED */\r
8061 //#define RESERVED (0x0400u) /* RESERVED */\r
8062 //#define RESERVED (0x0800u) /* RESERVED */\r
8063 //#define RESERVED (0x1000u) /* RESERVED */\r
8064 //#define RESERVED (0x2000u) /* RESERVED */\r
8065 //#define RESERVED (0x4000u) /* RESERVED */\r
8066 //#define RESERVED (0x8000u) /* RESERVED */\r
8067 \r
8068 /* UCSCTL6 Control Bits */\r
8069 #define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
8070 #define SMCLKOFF_L (0x0002u) /* SMCLK Off */\r
8071 #define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */\r
8072 #define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */\r
8073 #define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */\r
8074 #define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */\r
8075 #define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */\r
8076 #define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */\r
8077 //#define RESERVED (0x0200u) /* RESERVED */\r
8078 //#define RESERVED (0x0400u) /* RESERVED */\r
8079 //#define RESERVED (0x0800u) /* RESERVED */\r
8080 //#define RESERVED (0x1000u) /* RESERVED */\r
8081 //#define RESERVED (0x2000u) /* RESERVED */\r
8082 //#define RESERVED (0x4000u) /* RESERVED */\r
8083 //#define RESERVED (0x8000u) /* RESERVED */\r
8084 \r
8085 /* UCSCTL6 Control Bits */\r
8086 #define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */\r
8087 //#define RESERVED (0x0200u) /* RESERVED */\r
8088 //#define RESERVED (0x0400u) /* RESERVED */\r
8089 //#define RESERVED (0x0800u) /* RESERVED */\r
8090 //#define RESERVED (0x1000u) /* RESERVED */\r
8091 //#define RESERVED (0x2000u) /* RESERVED */\r
8092 //#define RESERVED (0x4000u) /* RESERVED */\r
8093 //#define RESERVED (0x8000u) /* RESERVED */\r
8094 \r
8095 #define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */\r
8096 #define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */\r
8097 #define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */\r
8098 #define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */\r
8099 #define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */\r
8100 #define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */\r
8101 #define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */\r
8102 #define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */\r
8103 \r
8104 /* UCSCTL7 Control Bits */\r
8105 #define DCOFFG (0x0001u) /* DCO Fault Flag */\r
8106 #define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */\r
8107 #define XT1HFOFFG (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */\r
8108 #define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */\r
8109 //#define RESERVED (0x0010u) /* RESERVED */\r
8110 //#define RESERVED (0x0020u) /* RESERVED */\r
8111 //#define RESERVED (0x0040u) /* RESERVED */\r
8112 //#define RESERVED (0x0080u) /* RESERVED */\r
8113 //#define RESERVED (0x0100u) /* RESERVED */\r
8114 //#define RESERVED (0x0200u) /* RESERVED */\r
8115 //#define RESERVED (0x0400u) /* RESERVED */\r
8116 //#define RESERVED (0x0800u) /* RESERVED */\r
8117 //#define RESERVED (0x1000u) /* RESERVED */\r
8118 //#define RESERVED (0x2000u) /* RESERVED */\r
8119 //#define RESERVED (0x4000u) /* RESERVED */\r
8120 //#define RESERVED (0x8000u) /* RESERVED */\r
8121 \r
8122 /* UCSCTL7 Control Bits */\r
8123 #define DCOFFG_L (0x0001u) /* DCO Fault Flag */\r
8124 #define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */\r
8125 #define XT1HFOFFG_L (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */\r
8126 #define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */\r
8127 //#define RESERVED (0x0010u) /* RESERVED */\r
8128 //#define RESERVED (0x0020u) /* RESERVED */\r
8129 //#define RESERVED (0x0040u) /* RESERVED */\r
8130 //#define RESERVED (0x0080u) /* RESERVED */\r
8131 //#define RESERVED (0x0100u) /* RESERVED */\r
8132 //#define RESERVED (0x0200u) /* RESERVED */\r
8133 //#define RESERVED (0x0400u) /* RESERVED */\r
8134 //#define RESERVED (0x0800u) /* RESERVED */\r
8135 //#define RESERVED (0x1000u) /* RESERVED */\r
8136 //#define RESERVED (0x2000u) /* RESERVED */\r
8137 //#define RESERVED (0x4000u) /* RESERVED */\r
8138 //#define RESERVED (0x8000u) /* RESERVED */\r
8139 \r
8140 /* UCSCTL8 Control Bits */\r
8141 #define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */\r
8142 #define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */\r
8143 #define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */\r
8144 #define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */\r
8145 //#define RESERVED (0x0010u) /* RESERVED */\r
8146 //#define RESERVED (0x0020u) /* RESERVED */\r
8147 //#define RESERVED (0x0040u) /* RESERVED */\r
8148 //#define RESERVED (0x0080u) /* RESERVED */\r
8149 //#define RESERVED (0x0100u) /* RESERVED */\r
8150 //#define RESERVED (0x0200u) /* RESERVED */\r
8151 //#define RESERVED (0x0400u) /* RESERVED */\r
8152 //#define RESERVED (0x0800u) /* RESERVED */\r
8153 //#define RESERVED (0x1000u) /* RESERVED */\r
8154 //#define RESERVED (0x2000u) /* RESERVED */\r
8155 //#define RESERVED (0x4000u) /* RESERVED */\r
8156 //#define RESERVED (0x8000u) /* RESERVED */\r
8157 \r
8158 /* UCSCTL8 Control Bits */\r
8159 #define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */\r
8160 #define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */\r
8161 #define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */\r
8162 #define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */\r
8163 //#define RESERVED (0x0010u) /* RESERVED */\r
8164 //#define RESERVED (0x0020u) /* RESERVED */\r
8165 //#define RESERVED (0x0040u) /* RESERVED */\r
8166 //#define RESERVED (0x0080u) /* RESERVED */\r
8167 //#define RESERVED (0x0100u) /* RESERVED */\r
8168 //#define RESERVED (0x0200u) /* RESERVED */\r
8169 //#define RESERVED (0x0400u) /* RESERVED */\r
8170 //#define RESERVED (0x0800u) /* RESERVED */\r
8171 //#define RESERVED (0x1000u) /* RESERVED */\r
8172 //#define RESERVED (0x2000u) /* RESERVED */\r
8173 //#define RESERVED (0x4000u) /* RESERVED */\r
8174 //#define RESERVED (0x8000u) /* RESERVED */\r
8175 \r
8176 #endif\r
8177 /************************************************************\r
8178 * USB\r
8179 ************************************************************/\r
8180 #ifdef __MSP430_HAS_USB__ /* Definition to show that Module is available */\r
8181 \r
8182 /* ========================================================================= */\r
8183 /* USB Configuration Registers */\r
8184 /* ========================================================================= */\r
8185 #define OFS_USBKEYID (0x0000u) /* USB Controller key register */\r
8186 #define OFS_USBKEYID_L OFS_USBKEYID\r
8187 #define OFS_USBKEYID_H OFS_USBKEYID+1\r
8188 #define OFS_USBCNF (0x0002u) /* USB Module configuration register */\r
8189 #define OFS_USBCNF_L OFS_USBCNF\r
8190 #define OFS_USBCNF_H OFS_USBCNF+1\r
8191 #define OFS_USBPHYCTL (0x0004u) /* USB PHY control register */\r
8192 #define OFS_USBPHYCTL_L OFS_USBPHYCTL\r
8193 #define OFS_USBPHYCTL_H OFS_USBPHYCTL+1\r
8194 #define OFS_USBPWRCTL (0x0008u) /* USB Power control register */\r
8195 #define OFS_USBPWRCTL_L OFS_USBPWRCTL\r
8196 #define OFS_USBPWRCTL_H OFS_USBPWRCTL+1\r
8197 #define OFS_USBPLLCTL (0x0010u) /* USB PLL control register */\r
8198 #define OFS_USBPLLCTL_L OFS_USBPLLCTL\r
8199 #define OFS_USBPLLCTL_H OFS_USBPLLCTL+1\r
8200 #define OFS_USBPLLDIVB (0x0012u) /* USB PLL Clock Divider Buffer control register */\r
8201 #define OFS_USBPLLDIVB_L OFS_USBPLLDIVB\r
8202 #define OFS_USBPLLDIVB_H OFS_USBPLLDIVB+1\r
8203 #define OFS_USBPLLIR (0x0014u) /* USB PLL Interrupt control register */\r
8204 #define OFS_USBPLLIR_L OFS_USBPLLIR\r
8205 #define OFS_USBPLLIR_H OFS_USBPLLIR+1\r
8206 \r
8207 #define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */\r
8208 #define USBKEY (0x9628u) /* USB Control Register key */\r
8209 \r
8210 /* USBCNF Control Bits */\r
8211 #define USB_EN (0x0001u) /* USB - Module enable */\r
8212 #define PUR_EN (0x0002u) /* USB - PUR pin enable */\r
8213 #define PUR_IN (0x0004u) /* USB - PUR pin input value */\r
8214 #define BLKRDY (0x0008u) /* USB - Block ready signal for DMA */\r
8215 #define FNTEN (0x0010u) /* USB - Frame Number receive Trigger enable for DMA */\r
8216 //#define RESERVED (0x0020u) /* USB - */\r
8217 //#define RESERVED (0x0040u) /* USB - */\r
8218 //#define RESERVED (0x0080u) /* USB - */\r
8219 //#define RESERVED (0x0100u) /* USB - */\r
8220 //#define RESERVED (0x0200u) /* USB - */\r
8221 //#define RESERVED (0x0400u) /* USB - */\r
8222 //#define RESERVED (0x0800u) /* USB - */\r
8223 //#define RESERVED (0x1000u) /* USB - */\r
8224 //#define RESERVED (0x2000u) /* USB - */\r
8225 //#define RESERVED (0x4000u) /* USB - */\r
8226 //#define RESERVED (0x8000u) /* USB - */\r
8227 \r
8228 /* USBCNF Control Bits */\r
8229 #define USB_EN_L (0x0001u) /* USB - Module enable */\r
8230 #define PUR_EN_L (0x0002u) /* USB - PUR pin enable */\r
8231 #define PUR_IN_L (0x0004u) /* USB - PUR pin input value */\r
8232 #define BLKRDY_L (0x0008u) /* USB - Block ready signal for DMA */\r
8233 #define FNTEN_L (0x0010u) /* USB - Frame Number receive Trigger enable for DMA */\r
8234 //#define RESERVED (0x0020u) /* USB - */\r
8235 //#define RESERVED (0x0040u) /* USB - */\r
8236 //#define RESERVED (0x0080u) /* USB - */\r
8237 //#define RESERVED (0x0100u) /* USB - */\r
8238 //#define RESERVED (0x0200u) /* USB - */\r
8239 //#define RESERVED (0x0400u) /* USB - */\r
8240 //#define RESERVED (0x0800u) /* USB - */\r
8241 //#define RESERVED (0x1000u) /* USB - */\r
8242 //#define RESERVED (0x2000u) /* USB - */\r
8243 //#define RESERVED (0x4000u) /* USB - */\r
8244 //#define RESERVED (0x8000u) /* USB - */\r
8245 \r
8246 /* USBPHYCTL Control Bits */\r
8247 #define PUOUT0 (0x0001u) /* USB - USB Port Output Signal Bit 0 */\r
8248 #define PUOUT1 (0x0002u) /* USB - USB Port Output Signal Bit 1 */\r
8249 #define PUIN0 (0x0004u) /* USB - PU0/DP Input Data */\r
8250 #define PUIN1 (0x0008u) /* USB - PU1/DM Input Data */\r
8251 //#define RESERVED (0x0010u) /* USB - */\r
8252 #define PUOPE (0x0020u) /* USB - USB Port Output Enable */\r
8253 //#define RESERVED (0x0040u) /* USB - */\r
8254 #define PUSEL (0x0080u) /* USB - USB Port Function Select */\r
8255 #define PUIPE (0x0100u) /* USB - PHY Single Ended Input enable */\r
8256 //#define RESERVED (0x0200u) /* USB - */\r
8257 //#define RESERVED (0x0100u) /* USB - */\r
8258 //#define RESERVED (0x0200u) /* USB - */\r
8259 //#define RESERVED (0x0400u) /* USB - */\r
8260 //#define RESERVED (0x0800u) /* USB - */\r
8261 //#define RESERVED (0x1000u) /* USB - */\r
8262 //#define RESERVED (0x2000u) /* USB - */\r
8263 //#define RESERVED (0x4000u) /* USB - */\r
8264 //#define RESERVED (0x8000u) /* USB - */\r
8265 \r
8266 /* USBPHYCTL Control Bits */\r
8267 #define PUOUT0_L (0x0001u) /* USB - USB Port Output Signal Bit 0 */\r
8268 #define PUOUT1_L (0x0002u) /* USB - USB Port Output Signal Bit 1 */\r
8269 #define PUIN0_L (0x0004u) /* USB - PU0/DP Input Data */\r
8270 #define PUIN1_L (0x0008u) /* USB - PU1/DM Input Data */\r
8271 //#define RESERVED (0x0010u) /* USB - */\r
8272 #define PUOPE_L (0x0020u) /* USB - USB Port Output Enable */\r
8273 //#define RESERVED (0x0040u) /* USB - */\r
8274 #define PUSEL_L (0x0080u) /* USB - USB Port Function Select */\r
8275 //#define RESERVED (0x0200u) /* USB - */\r
8276 //#define RESERVED (0x0100u) /* USB - */\r
8277 //#define RESERVED (0x0200u) /* USB - */\r
8278 //#define RESERVED (0x0400u) /* USB - */\r
8279 //#define RESERVED (0x0800u) /* USB - */\r
8280 //#define RESERVED (0x1000u) /* USB - */\r
8281 //#define RESERVED (0x2000u) /* USB - */\r
8282 //#define RESERVED (0x4000u) /* USB - */\r
8283 //#define RESERVED (0x8000u) /* USB - */\r
8284 \r
8285 /* USBPHYCTL Control Bits */\r
8286 //#define RESERVED (0x0010u) /* USB - */\r
8287 //#define RESERVED (0x0040u) /* USB - */\r
8288 #define PUIPE_H (0x0001u) /* USB - PHY Single Ended Input enable */\r
8289 //#define RESERVED (0x0200u) /* USB - */\r
8290 //#define RESERVED (0x0100u) /* USB - */\r
8291 //#define RESERVED (0x0200u) /* USB - */\r
8292 //#define RESERVED (0x0400u) /* USB - */\r
8293 //#define RESERVED (0x0800u) /* USB - */\r
8294 //#define RESERVED (0x1000u) /* USB - */\r
8295 //#define RESERVED (0x2000u) /* USB - */\r
8296 //#define RESERVED (0x4000u) /* USB - */\r
8297 //#define RESERVED (0x8000u) /* USB - */\r
8298 \r
8299 #define PUDIR (0x0020u) /* USB - Legacy Definition: USB Port Output Enable */\r
8300 #define PSEIEN (0x0100u) /* USB - Legacy Definition: PHY Single Ended Input enable */\r
8301 \r
8302 /* USBPWRCTL Control Bits */\r
8303 #define VUOVLIFG (0x0001u) /* USB - VUSB Overload Interrupt Flag */\r
8304 #define VBONIFG (0x0002u) /* USB - VBUS "Coming ON" Interrupt Flag */\r
8305 #define VBOFFIFG (0x0004u) /* USB - VBUS "Going OFF" Interrupt Flag */\r
8306 #define USBBGVBV (0x0008u) /* USB - USB Bandgap and VBUS valid */\r
8307 #define USBDETEN (0x0010u) /* USB - VBUS on/off events enable */\r
8308 #define OVLAOFF (0x0020u) /* USB - LDO overload auto off enable */\r
8309 #define SLDOAON (0x0040u) /* USB - Secondary LDO auto on enable */\r
8310 //#define RESERVED (0x0080u) /* USB - */\r
8311 #define VUOVLIE (0x0100u) /* USB - Overload indication Interrupt Enable */\r
8312 #define VBONIE (0x0200u) /* USB - VBUS "Coming ON" Interrupt Enable */\r
8313 #define VBOFFIE (0x0400u) /* USB - VBUS "Going OFF" Interrupt Enable */\r
8314 #define VUSBEN (0x0800u) /* USB - LDO Enable (3.3V) */\r
8315 #define SLDOEN (0x1000u) /* USB - Secondary LDO Enable (1.8V) */\r
8316 //#define RESERVED (0x2000u) /* USB - */\r
8317 //#define RESERVED (0x4000u) /* USB - */\r
8318 //#define RESERVED (0x8000u) /* USB - */\r
8319 \r
8320 /* USBPWRCTL Control Bits */\r
8321 #define VUOVLIFG_L (0x0001u) /* USB - VUSB Overload Interrupt Flag */\r
8322 #define VBONIFG_L (0x0002u) /* USB - VBUS "Coming ON" Interrupt Flag */\r
8323 #define VBOFFIFG_L (0x0004u) /* USB - VBUS "Going OFF" Interrupt Flag */\r
8324 #define USBBGVBV_L (0x0008u) /* USB - USB Bandgap and VBUS valid */\r
8325 #define USBDETEN_L (0x0010u) /* USB - VBUS on/off events enable */\r
8326 #define OVLAOFF_L (0x0020u) /* USB - LDO overload auto off enable */\r
8327 #define SLDOAON_L (0x0040u) /* USB - Secondary LDO auto on enable */\r
8328 //#define RESERVED (0x0080u) /* USB - */\r
8329 //#define RESERVED (0x2000u) /* USB - */\r
8330 //#define RESERVED (0x4000u) /* USB - */\r
8331 //#define RESERVED (0x8000u) /* USB - */\r
8332 \r
8333 /* USBPWRCTL Control Bits */\r
8334 //#define RESERVED (0x0080u) /* USB - */\r
8335 #define VUOVLIE_H (0x0001u) /* USB - Overload indication Interrupt Enable */\r
8336 #define VBONIE_H (0x0002u) /* USB - VBUS "Coming ON" Interrupt Enable */\r
8337 #define VBOFFIE_H (0x0004u) /* USB - VBUS "Going OFF" Interrupt Enable */\r
8338 #define VUSBEN_H (0x0008u) /* USB - LDO Enable (3.3V) */\r
8339 #define SLDOEN_H (0x0010u) /* USB - Secondary LDO Enable (1.8V) */\r
8340 //#define RESERVED (0x2000u) /* USB - */\r
8341 //#define RESERVED (0x4000u) /* USB - */\r
8342 //#define RESERVED (0x8000u) /* USB - */\r
8343 \r
8344 /* USBPLLCTL Control Bits */\r
8345 //#define RESERVED (0x0001u) /* USB - */\r
8346 //#define RESERVED (0x0002u) /* USB - */\r
8347 //#define RESERVED (0x0004u) /* USB - */\r
8348 //#define RESERVED (0x0008u) /* USB - */\r
8349 //#define RESERVED (0x0010u) /* USB - */\r
8350 //#define RESERVED (0x0020u) /* USB - */\r
8351 #define UCLKSEL0 (0x0040u) /* USB - Module Clock Select Bit 0 */\r
8352 #define UCLKSEL1 (0x0080u) /* USB - Module Clock Select Bit 1 */\r
8353 #define UPLLEN (0x0100u) /* USB - PLL enable */\r
8354 #define UPFDEN (0x0200u) /* USB - Phase Freq. Discriminator enable */\r
8355 //#define RESERVED (0x0400u) /* USB - */\r
8356 //#define RESERVED (0x0800u) /* USB - */\r
8357 //#define RESERVED (0x1000u) /* USB - */\r
8358 //#define RESERVED (0x2000u) /* USB - */\r
8359 //#define RESERVED (0x4000u) /* USB - */\r
8360 //#define RESERVED (0x8000u) /* USB - */\r
8361 \r
8362 /* USBPLLCTL Control Bits */\r
8363 //#define RESERVED (0x0001u) /* USB - */\r
8364 //#define RESERVED (0x0002u) /* USB - */\r
8365 //#define RESERVED (0x0004u) /* USB - */\r
8366 //#define RESERVED (0x0008u) /* USB - */\r
8367 //#define RESERVED (0x0010u) /* USB - */\r
8368 //#define RESERVED (0x0020u) /* USB - */\r
8369 #define UCLKSEL0_L (0x0040u) /* USB - Module Clock Select Bit 0 */\r
8370 #define UCLKSEL1_L (0x0080u) /* USB - Module Clock Select Bit 1 */\r
8371 //#define RESERVED (0x0400u) /* USB - */\r
8372 //#define RESERVED (0x0800u) /* USB - */\r
8373 //#define RESERVED (0x1000u) /* USB - */\r
8374 //#define RESERVED (0x2000u) /* USB - */\r
8375 //#define RESERVED (0x4000u) /* USB - */\r
8376 //#define RESERVED (0x8000u) /* USB - */\r
8377 \r
8378 /* USBPLLCTL Control Bits */\r
8379 //#define RESERVED (0x0001u) /* USB - */\r
8380 //#define RESERVED (0x0002u) /* USB - */\r
8381 //#define RESERVED (0x0004u) /* USB - */\r
8382 //#define RESERVED (0x0008u) /* USB - */\r
8383 //#define RESERVED (0x0010u) /* USB - */\r
8384 //#define RESERVED (0x0020u) /* USB - */\r
8385 #define UPLLEN_H (0x0001u) /* USB - PLL enable */\r
8386 #define UPFDEN_H (0x0002u) /* USB - Phase Freq. Discriminator enable */\r
8387 //#define RESERVED (0x0400u) /* USB - */\r
8388 //#define RESERVED (0x0800u) /* USB - */\r
8389 //#define RESERVED (0x1000u) /* USB - */\r
8390 //#define RESERVED (0x2000u) /* USB - */\r
8391 //#define RESERVED (0x4000u) /* USB - */\r
8392 //#define RESERVED (0x8000u) /* USB - */\r
8393 \r
8394 #define UCLKSEL_0 (0x0000u) /* USB - Module Clock Select: 0 */\r
8395 #define UCLKSEL_1 (0x0040u) /* USB - Module Clock Select: 1 */\r
8396 #define UCLKSEL_2 (0x0080u) /* USB - Module Clock Select: 2 */\r
8397 #define UCLKSEL_3 (0x00C0u) /* USB - Module Clock Select: 3 (Reserved) */\r
8398 \r
8399 #define UCLKSEL__PLLCLK (0x0000u) /* USB - Module Clock Select: PLLCLK */\r
8400 #define UCLKSEL__XT1CLK (0x0040u) /* USB - Module Clock Select: XT1CLK */\r
8401 #define UCLKSEL__XT2CLK (0x0080u) /* USB - Module Clock Select: XT2CLK */\r
8402 \r
8403 /* USBPLLDIVB Control Bits */\r
8404 #define UPMB0 (0x0001u) /* USB - PLL feedback divider buffer Bit 0 */\r
8405 #define UPMB1 (0x0002u) /* USB - PLL feedback divider buffer Bit 1 */\r
8406 #define UPMB2 (0x0004u) /* USB - PLL feedback divider buffer Bit 2 */\r
8407 #define UPMB3 (0x0008u) /* USB - PLL feedback divider buffer Bit 3 */\r
8408 #define UPMB4 (0x0010u) /* USB - PLL feedback divider buffer Bit 4 */\r
8409 #define UPMB5 (0x0020u) /* USB - PLL feedback divider buffer Bit 5 */\r
8410 //#define RESERVED (0x0040u) /* USB - */\r
8411 //#define RESERVED (0x0080u) /* USB - */\r
8412 #define UPQB0 (0x0100u) /* USB - PLL prescale divider buffer Bit 0 */\r
8413 #define UPQB1 (0x0200u) /* USB - PLL prescale divider buffer Bit 1 */\r
8414 #define UPQB2 (0x0400u) /* USB - PLL prescale divider buffer Bit 2 */\r
8415 //#define RESERVED (0x0800u) /* USB - */\r
8416 //#define RESERVED (0x1000u) /* USB - */\r
8417 //#define RESERVED (0x2000u) /* USB - */\r
8418 //#define RESERVED (0x4000u) /* USB - */\r
8419 //#define RESERVED (0x8000u) /* USB - */\r
8420 \r
8421 /* USBPLLDIVB Control Bits */\r
8422 #define UPMB0_L (0x0001u) /* USB - PLL feedback divider buffer Bit 0 */\r
8423 #define UPMB1_L (0x0002u) /* USB - PLL feedback divider buffer Bit 1 */\r
8424 #define UPMB2_L (0x0004u) /* USB - PLL feedback divider buffer Bit 2 */\r
8425 #define UPMB3_L (0x0008u) /* USB - PLL feedback divider buffer Bit 3 */\r
8426 #define UPMB4_L (0x0010u) /* USB - PLL feedback divider buffer Bit 4 */\r
8427 #define UPMB5_L (0x0020u) /* USB - PLL feedback divider buffer Bit 5 */\r
8428 //#define RESERVED (0x0040u) /* USB - */\r
8429 //#define RESERVED (0x0080u) /* USB - */\r
8430 //#define RESERVED (0x0800u) /* USB - */\r
8431 //#define RESERVED (0x1000u) /* USB - */\r
8432 //#define RESERVED (0x2000u) /* USB - */\r
8433 //#define RESERVED (0x4000u) /* USB - */\r
8434 //#define RESERVED (0x8000u) /* USB - */\r
8435 \r
8436 /* USBPLLDIVB Control Bits */\r
8437 //#define RESERVED (0x0040u) /* USB - */\r
8438 //#define RESERVED (0x0080u) /* USB - */\r
8439 #define UPQB0_H (0x0001u) /* USB - PLL prescale divider buffer Bit 0 */\r
8440 #define UPQB1_H (0x0002u) /* USB - PLL prescale divider buffer Bit 1 */\r
8441 #define UPQB2_H (0x0004u) /* USB - PLL prescale divider buffer Bit 2 */\r
8442 //#define RESERVED (0x0800u) /* USB - */\r
8443 //#define RESERVED (0x1000u) /* USB - */\r
8444 //#define RESERVED (0x2000u) /* USB - */\r
8445 //#define RESERVED (0x4000u) /* USB - */\r
8446 //#define RESERVED (0x8000u) /* USB - */\r
8447 \r
8448 #define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */\r
8449 #define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */\r
8450 #define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */\r
8451 #define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */\r
8452 #define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */\r
8453 #define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */\r
8454 #define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */\r
8455 #define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */\r
8456 #define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */\r
8457 #define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */\r
8458 #define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */\r
8459 #define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */\r
8460 #define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */\r
8461 #define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */\r
8462 #define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */\r
8463 #define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */\r
8464 #define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */\r
8465 #define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */\r
8466 #define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */\r
8467 #define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */\r
8468 #define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */\r
8469 #define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */\r
8470 #define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */\r
8471 #define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */\r
8472 #define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */\r
8473 #define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */\r
8474 #define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */\r
8475 #define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */\r
8476 #define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */\r
8477 #define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */\r
8478 #define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */\r
8479 #define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */\r
8480 #define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */\r
8481 #define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */\r
8482 #define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */\r
8483 #define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */\r
8484 #define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */\r
8485 #define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */\r
8486 #define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */\r
8487 #define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */\r
8488 #define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */\r
8489 #define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */\r
8490 #define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */\r
8491 \r
8492 /* USBPLLIR Control Bits */\r
8493 #define USBOOLIFG (0x0001u) /* USB - PLL out of lock Interrupt Flag */\r
8494 #define USBLOSIFG (0x0002u) /* USB - PLL loss of signal Interrupt Flag */\r
8495 #define USBOORIFG (0x0004u) /* USB - PLL out of range Interrupt Flag */\r
8496 //#define RESERVED (0x0008u) /* USB - */\r
8497 //#define RESERVED (0x0010u) /* USB - */\r
8498 //#define RESERVED (0x0020u) /* USB - */\r
8499 //#define RESERVED (0x0040u) /* USB - */\r
8500 //#define RESERVED (0x0080u) /* USB - */\r
8501 #define USBOOLIE (0x0100u) /* USB - PLL out of lock Interrupt enable */\r
8502 #define USBLOSIE (0x0200u) /* USB - PLL loss of signal Interrupt enable */\r
8503 #define USBOORIE (0x0400u) /* USB - PLL out of range Interrupt enable */\r
8504 //#define RESERVED (0x0800u) /* USB - */\r
8505 //#define RESERVED (0x1000u) /* USB - */\r
8506 //#define RESERVED (0x2000u) /* USB - */\r
8507 //#define RESERVED (0x4000u) /* USB - */\r
8508 //#define RESERVED (0x8000u) /* USB - */\r
8509 \r
8510 /* USBPLLIR Control Bits */\r
8511 #define USBOOLIFG_L (0x0001u) /* USB - PLL out of lock Interrupt Flag */\r
8512 #define USBLOSIFG_L (0x0002u) /* USB - PLL loss of signal Interrupt Flag */\r
8513 #define USBOORIFG_L (0x0004u) /* USB - PLL out of range Interrupt Flag */\r
8514 //#define RESERVED (0x0008u) /* USB - */\r
8515 //#define RESERVED (0x0010u) /* USB - */\r
8516 //#define RESERVED (0x0020u) /* USB - */\r
8517 //#define RESERVED (0x0040u) /* USB - */\r
8518 //#define RESERVED (0x0080u) /* USB - */\r
8519 //#define RESERVED (0x0800u) /* USB - */\r
8520 //#define RESERVED (0x1000u) /* USB - */\r
8521 //#define RESERVED (0x2000u) /* USB - */\r
8522 //#define RESERVED (0x4000u) /* USB - */\r
8523 //#define RESERVED (0x8000u) /* USB - */\r
8524 \r
8525 /* USBPLLIR Control Bits */\r
8526 //#define RESERVED (0x0008u) /* USB - */\r
8527 //#define RESERVED (0x0010u) /* USB - */\r
8528 //#define RESERVED (0x0020u) /* USB - */\r
8529 //#define RESERVED (0x0040u) /* USB - */\r
8530 //#define RESERVED (0x0080u) /* USB - */\r
8531 #define USBOOLIE_H (0x0001u) /* USB - PLL out of lock Interrupt enable */\r
8532 #define USBLOSIE_H (0x0002u) /* USB - PLL loss of signal Interrupt enable */\r
8533 #define USBOORIE_H (0x0004u) /* USB - PLL out of range Interrupt enable */\r
8534 //#define RESERVED (0x0800u) /* USB - */\r
8535 //#define RESERVED (0x1000u) /* USB - */\r
8536 //#define RESERVED (0x2000u) /* USB - */\r
8537 //#define RESERVED (0x4000u) /* USB - */\r
8538 //#define RESERVED (0x8000u) /* USB - */\r
8539 \r
8540 /* ========================================================================= */\r
8541 /* USB Control Registers */\r
8542 /* ========================================================================= */\r
8543 #define OFS_USBIEPCNF_0 (0x0020u) /* USB Input endpoint_0: Configuration */\r
8544 #define OFS_USBIEPCNT_0 (0x0021u) /* USB Input endpoint_0: Byte Count */\r
8545 #define OFS_USBOEPCNF_0 (0x0022u) /* USB Output endpoint_0: Configuration */\r
8546 #define OFS_USBOEPCNT_0 (0x0023u) /* USB Output endpoint_0: byte count */\r
8547 #define OFS_USBIEPIE (0x002Eu) /* USB Input endpoint interrupt enable flags */\r
8548 #define OFS_USBOEPIE (0x002Fu) /* USB Output endpoint interrupt enable flags */\r
8549 #define OFS_USBIEPIFG (0x0030u) /* USB Input endpoint interrupt flags */\r
8550 #define OFS_USBOEPIFG (0x0031u) /* USB Output endpoint interrupt flags */\r
8551 #define OFS_USBVECINT (0x0032u) /* USB Vector interrupt register */\r
8552 #define OFS_USBVECINT_L OFS_USBVECINT\r
8553 #define OFS_USBVECINT_H OFS_USBVECINT+1\r
8554 #define OFS_USBMAINT (0x0036u) /* USB maintenance register */\r
8555 #define OFS_USBMAINT_L OFS_USBMAINT\r
8556 #define OFS_USBMAINT_H OFS_USBMAINT+1\r
8557 #define OFS_USBTSREG (0x0038u) /* USB Time Stamp register */\r
8558 #define OFS_USBTSREG_L OFS_USBTSREG\r
8559 #define OFS_USBTSREG_H OFS_USBTSREG+1\r
8560 #define OFS_USBFN (0x003Au) /* USB Frame number */\r
8561 #define OFS_USBFN_L OFS_USBFN\r
8562 #define OFS_USBFN_H OFS_USBFN+1\r
8563 #define OFS_USBCTL (0x003Cu) /* USB control register */\r
8564 #define OFS_USBIE (0x003Du) /* USB interrupt enable register */\r
8565 #define OFS_USBIFG (0x003Eu) /* USB interrupt flag register */\r
8566 #define OFS_USBFUNADR (0x003Fu) /* USB Function address register */\r
8567 \r
8568 #define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */\r
8569 \r
8570 /* USBIEPCNF_0 Control Bits */\r
8571 /* USBOEPCNF_0 Control Bits */\r
8572 //#define RESERVED (0x0001u) /* USB - */\r
8573 //#define RESERVED (0x0001u) /* USB - */\r
8574 #define USBIIE (0x0004u) /* USB - Transaction Interrupt indication enable */\r
8575 #define STALL (0x0008u) /* USB - Stall Condition */\r
8576 //#define RESERVED (0x0010u) /* USB - */\r
8577 #define TOGGLE (0x0020u) /* USB - Toggle Bit */\r
8578 //#define RESERVED (0x0040u) /* USB - */\r
8579 #define UBME (0x0080u) /* USB - UBM In-Endpoint Enable */\r
8580 \r
8581 /* USBIEPBCNT_0 Control Bits */\r
8582 /* USBOEPBCNT_0 Control Bits */\r
8583 #define CNT0 (0x0001u) /* USB - Byte Count Bit 0 */\r
8584 #define CNT1 (0x0001u) /* USB - Byte Count Bit 1 */\r
8585 #define CNT2 (0x0004u) /* USB - Byte Count Bit 2 */\r
8586 #define CNT3 (0x0008u) /* USB - Byte Count Bit 3 */\r
8587 //#define RESERVED (0x0010u) /* USB - */\r
8588 //#define RESERVED (0x0020u) /* USB - */\r
8589 //#define RESERVED (0x0040u) /* USB - */\r
8590 #define NAK (0x0080u) /* USB - No Acknowledge Status Bit */\r
8591 \r
8592 /* USBMAINT Control Bits */\r
8593 #define UTIFG (0x0001u) /* USB - Timer Interrupt Flag */\r
8594 #define UTIE (0x0002u) /* USB - Timer Interrupt Enable */\r
8595 //#define RESERVED (0x0004u) /* USB - */\r
8596 //#define RESERVED (0x0008u) /* USB - */\r
8597 //#define RESERVED (0x0010u) /* USB - */\r
8598 //#define RESERVED (0x0020u) /* USB - */\r
8599 //#define RESERVED (0x0040u) /* USB - */\r
8600 //#define RESERVED (0x0080u) /* USB - */\r
8601 #define TSGEN (0x0100u) /* USB - Time Stamp Generator Enable */\r
8602 #define TSESEL0 (0x0200u) /* USB - Time Stamp Event Select Bit 0 */\r
8603 #define TSESEL1 (0x0400u) /* USB - Time Stamp Event Select Bit 1 */\r
8604 #define TSE3 (0x0800u) /* USB - Time Stamp Event #3 Bit */\r
8605 //#define RESERVED (0x1000u) /* USB - */\r
8606 #define UTSEL0 (0x2000u) /* USB - Timer Select Bit 0 */\r
8607 #define UTSEL1 (0x4000u) /* USB - Timer Select Bit 1 */\r
8608 #define UTSEL2 (0x8000u) /* USB - Timer Select Bit 2 */\r
8609 \r
8610 /* USBMAINT Control Bits */\r
8611 #define UTIFG_L (0x0001u) /* USB - Timer Interrupt Flag */\r
8612 #define UTIE_L (0x0002u) /* USB - Timer Interrupt Enable */\r
8613 //#define RESERVED (0x0004u) /* USB - */\r
8614 //#define RESERVED (0x0008u) /* USB - */\r
8615 //#define RESERVED (0x0010u) /* USB - */\r
8616 //#define RESERVED (0x0020u) /* USB - */\r
8617 //#define RESERVED (0x0040u) /* USB - */\r
8618 //#define RESERVED (0x0080u) /* USB - */\r
8619 //#define RESERVED (0x1000u) /* USB - */\r
8620 \r
8621 /* USBMAINT Control Bits */\r
8622 //#define RESERVED (0x0004u) /* USB - */\r
8623 //#define RESERVED (0x0008u) /* USB - */\r
8624 //#define RESERVED (0x0010u) /* USB - */\r
8625 //#define RESERVED (0x0020u) /* USB - */\r
8626 //#define RESERVED (0x0040u) /* USB - */\r
8627 //#define RESERVED (0x0080u) /* USB - */\r
8628 #define TSGEN_H (0x0001u) /* USB - Time Stamp Generator Enable */\r
8629 #define TSESEL0_H (0x0002u) /* USB - Time Stamp Event Select Bit 0 */\r
8630 #define TSESEL1_H (0x0004u) /* USB - Time Stamp Event Select Bit 1 */\r
8631 #define TSE3_H (0x0008u) /* USB - Time Stamp Event #3 Bit */\r
8632 //#define RESERVED (0x1000u) /* USB - */\r
8633 #define UTSEL0_H (0x0020u) /* USB - Timer Select Bit 0 */\r
8634 #define UTSEL1_H (0x0040u) /* USB - Timer Select Bit 1 */\r
8635 #define UTSEL2_H (0x0080u) /* USB - Timer Select Bit 2 */\r
8636 \r
8637 #define TSESEL_0 (0x0000u) /* USB - Time Stamp Event Select: 0 */\r
8638 #define TSESEL_1 (0x0200u) /* USB - Time Stamp Event Select: 1 */\r
8639 #define TSESEL_2 (0x0400u) /* USB - Time Stamp Event Select: 2 */\r
8640 #define TSESEL_3 (0x0600u) /* USB - Time Stamp Event Select: 3 */\r
8641 \r
8642 #define UTSEL_0 (0x0000u) /* USB - Timer Select: 0 */\r
8643 #define UTSEL_1 (0x2000u) /* USB - Timer Select: 1 */\r
8644 #define UTSEL_2 (0x4000u) /* USB - Timer Select: 2 */\r
8645 #define UTSEL_3 (0x6000u) /* USB - Timer Select: 3 */\r
8646 #define UTSEL_4 (0x8000u) /* USB - Timer Select: 4 */\r
8647 #define UTSEL_5 (0xA000u) /* USB - Timer Select: 5 */\r
8648 #define UTSEL_6 (0xC000u) /* USB - Timer Select: 6 */\r
8649 #define UTSEL_7 (0xE000u) /* USB - Timer Select: 7 */\r
8650 \r
8651 /* USBCTL Control Bits */\r
8652 #define DIR (0x0001u) /* USB - Data Response Bit */\r
8653 //#define RESERVED (0x0002u) /* USB - */\r
8654 //#define RESERVED (0x0004u) /* USB - */\r
8655 //#define RESERVED (0x0008u) /* USB - */\r
8656 #define FRSTE (0x0010u) /* USB - Function Reset Connection Enable */\r
8657 #define RWUP (0x0020u) /* USB - Device Remote Wakeup Request */\r
8658 #define FEN (0x0040u) /* USB - Function Enable Bit */\r
8659 //#define RESERVED (0x0080u) /* USB - */\r
8660 \r
8661 /* USBIE Control Bits */\r
8662 #define STPOWIE (0x0001u) /* USB - Setup Overwrite Interrupt Enable */\r
8663 //#define RESERVED (0x0002u) /* USB - */\r
8664 #define SETUPIE (0x0004u) /* USB - Setup Interrupt Enable */\r
8665 //#define RESERVED (0x0008u) /* USB - */\r
8666 //#define RESERVED (0x0010u) /* USB - */\r
8667 #define RESRIE (0x0020u) /* USB - Function Resume Request Interrupt Enable */\r
8668 #define SUSRIE (0x0040u) /* USB - Function Suspend Request Interrupt Enable */\r
8669 #define RSTRIE (0x0080u) /* USB - Function Reset Request Interrupt Enable */\r
8670 \r
8671 /* USBIFG Control Bits */\r
8672 #define STPOWIFG (0x0001u) /* USB - Setup Overwrite Interrupt Flag */\r
8673 //#define RESERVED (0x0002u) /* USB - */\r
8674 #define SETUPIFG (0x0004u) /* USB - Setup Interrupt Flag */\r
8675 //#define RESERVED (0x0008u) /* USB - */\r
8676 //#define RESERVED (0x0010u) /* USB - */\r
8677 #define RESRIFG (0x0020u) /* USB - Function Resume Request Interrupt Flag */\r
8678 #define SUSRIFG (0x0040u) /* USB - Function Suspend Request Interrupt Flag */\r
8679 #define RSTRIFG (0x0080u) /* USB - Function Reset Request Interrupt Flag */\r
8680 \r
8681 //values of USBVECINT when USB-interrupt occured\r
8682 #define USBVECINT_NONE 0x00\r
8683 #define USBVECINT_PWR_DROP 0x02\r
8684 #define USBVECINT_PLL_LOCK 0x04\r
8685 #define USBVECINT_PLL_SIGNAL 0x06\r
8686 #define USBVECINT_PLL_RANGE 0x08\r
8687 #define USBVECINT_PWR_VBUSOn 0x0A\r
8688 #define USBVECINT_PWR_VBUSOff 0x0C\r
8689 #define USBVECINT_USB_TIMESTAMP 0x10\r
8690 #define USBVECINT_INPUT_ENDPOINT0 0x12\r
8691 #define USBVECINT_OUTPUT_ENDPOINT0 0x14\r
8692 #define USBVECINT_RSTR 0x16\r
8693 #define USBVECINT_SUSR 0x18\r
8694 #define USBVECINT_RESR 0x1A\r
8695 #define USBVECINT_SETUP_PACKET_RECEIVED 0x20\r
8696 #define USBVECINT_STPOW_PACKET_RECEIVED 0x22\r
8697 #define USBVECINT_INPUT_ENDPOINT1 0x24\r
8698 #define USBVECINT_INPUT_ENDPOINT2 0x26\r
8699 #define USBVECINT_INPUT_ENDPOINT3 0x28\r
8700 #define USBVECINT_INPUT_ENDPOINT4 0x2A\r
8701 #define USBVECINT_INPUT_ENDPOINT5 0x2C\r
8702 #define USBVECINT_INPUT_ENDPOINT6 0x2E\r
8703 #define USBVECINT_INPUT_ENDPOINT7 0x30\r
8704 #define USBVECINT_OUTPUT_ENDPOINT1 0x32\r
8705 #define USBVECINT_OUTPUT_ENDPOINT2 0x34\r
8706 #define USBVECINT_OUTPUT_ENDPOINT3 0x36\r
8707 #define USBVECINT_OUTPUT_ENDPOINT4 0x38\r
8708 #define USBVECINT_OUTPUT_ENDPOINT5 0x3A\r
8709 #define USBVECINT_OUTPUT_ENDPOINT6 0x3C\r
8710 #define USBVECINT_OUTPUT_ENDPOINT7 0x3E\r
8711 \r
8712 \r
8713 /* ========================================================================= */\r
8714 /* USB Operation Registers */\r
8715 /* ========================================================================= */\r
8716 \r
8717 #define OFS_USBIEPSIZXY_7 (0x23FFu) /* Input Endpoint_7: X/Y-buffer size */\r
8718 #define OFS_USBIEPBCTY_7 (0x23FEu) /* Input Endpoint_7: Y-byte count */\r
8719 #define OFS_USBIEPBBAY_7 (0x23FDu) /* Input Endpoint_7: Y-buffer base addr. */\r
8720 //#define Spare_O (0x23FCu) /* Not used */\r
8721 //#define Spare_O (0x23FBu) /* Not used */\r
8722 #define OFS_USBIEPBCTX_7 (0x23FAu) /* Input Endpoint_7: X-byte count */\r
8723 #define OFS_USBIEPBBAX_7 (0x23F9u) /* Input Endpoint_7: X-buffer base addr. */\r
8724 #define OFS_USBIEPCNF_7 (0x23F8u) /* Input Endpoint_7: Configuration */\r
8725 #define OFS_USBIEPSIZXY_6 (0x23F7u) /* Input Endpoint_6: X/Y-buffer size */\r
8726 #define OFS_USBIEPBCTY_6 (0x23F6u) /* Input Endpoint_6: Y-byte count */\r
8727 #define OFS_USBIEPBBAY_6 (0x23F5u) /* Input Endpoint_6: Y-buffer base addr. */\r
8728 //#define Spare_O (0x23F4u) /* Not used */\r
8729 //#define Spare_O (0x23F3u) /* Not used */\r
8730 #define OFS_USBIEPBCTX_6 (0x23F2u) /* Input Endpoint_6: X-byte count */\r
8731 #define OFS_USBIEPBBAX_6 (0x23F1u) /* Input Endpoint_6: X-buffer base addr. */\r
8732 #define OFS_USBIEPCNF_6 (0x23F0u) /* Input Endpoint_6: Configuration */\r
8733 #define OFS_USBIEPSIZXY_5 (0x23EFu) /* Input Endpoint_5: X/Y-buffer size */\r
8734 #define OFS_USBIEPBCTY_5 (0x23EEu) /* Input Endpoint_5: Y-byte count */\r
8735 #define OFS_USBIEPBBAY_5 (0x23EDu) /* Input Endpoint_5: Y-buffer base addr. */\r
8736 //#define Spare_O (0x23ECu) /* Not used */\r
8737 //#define Spare_O (0x23EBu) /* Not used */\r
8738 #define OFS_USBIEPBCTX_5 (0x23EAu) /* Input Endpoint_5: X-byte count */\r
8739 #define OFS_USBIEPBBAX_5 (0x23E9u) /* Input Endpoint_5: X-buffer base addr. */\r
8740 #define OFS_USBIEPCNF_5 (0x23E8u) /* Input Endpoint_5: Configuration */\r
8741 #define OFS_USBIEPSIZXY_4 (0x23E7u) /* Input Endpoint_4: X/Y-buffer size */\r
8742 #define OFS_USBIEPBCTY_4 (0x23E6u) /* Input Endpoint_4: Y-byte count */\r
8743 #define OFS_USBIEPBBAY_4 (0x23E5u) /* Input Endpoint_4: Y-buffer base addr. */\r
8744 //#define Spare_O (0x23E4u) /* Not used */\r
8745 //#define Spare_O (0x23E3u) /* Not used */\r
8746 #define OFS_USBIEPBCTX_4 (0x23E2u) /* Input Endpoint_4: X-byte count */\r
8747 #define OFS_USBIEPBBAX_4 (0x23E1u) /* Input Endpoint_4: X-buffer base addr. */\r
8748 #define OFS_USBIEPCNF_4 (0x23E0u) /* Input Endpoint_4: Configuration */\r
8749 #define OFS_USBIEPSIZXY_3 (0x23DFu) /* Input Endpoint_3: X/Y-buffer size */\r
8750 #define OFS_USBIEPBCTY_3 (0x23DEu) /* Input Endpoint_3: Y-byte count */\r
8751 #define OFS_USBIEPBBAY_3 (0x23DDu) /* Input Endpoint_3: Y-buffer base addr. */\r
8752 //#define Spare_O (0x23DCu) /* Not used */\r
8753 //#define Spare_O (0x23DBu) /* Not used */\r
8754 #define OFS_USBIEPBCTX_3 (0x23DAu) /* Input Endpoint_3: X-byte count */\r
8755 #define OFS_USBIEPBBAX_3 (0x23D9u) /* Input Endpoint_3: X-buffer base addr. */\r
8756 #define OFS_USBIEPCNF_3 (0x23D8u) /* Input Endpoint_3: Configuration */\r
8757 #define OFS_USBIEPSIZXY_2 (0x23D7u) /* Input Endpoint_2: X/Y-buffer size */\r
8758 #define OFS_USBIEPBCTY_2 (0x23D6u) /* Input Endpoint_2: Y-byte count */\r
8759 #define OFS_USBIEPBBAY_2 (0x23D5u) /* Input Endpoint_2: Y-buffer base addr. */\r
8760 //#define Spare_O (0x23D4u) /* Not used */\r
8761 //#define Spare_O (0x23D3u) /* Not used */\r
8762 #define OFS_USBIEPBCTX_2 (0x23D2u) /* Input Endpoint_2: X-byte count */\r
8763 #define OFS_USBIEPBBAX_2 (0x23D1u) /* Input Endpoint_2: X-buffer base addr. */\r
8764 #define OFS_USBIEPCNF_2 (0x23D0u) /* Input Endpoint_2: Configuration */\r
8765 #define OFS_USBIEPSIZXY_1 (0x23CFu) /* Input Endpoint_1: X/Y-buffer size */\r
8766 #define OFS_USBIEPBCTY_1 (0x23CEu) /* Input Endpoint_1: Y-byte count */\r
8767 #define OFS_USBIEPBBAY_1 (0x23CDu) /* Input Endpoint_1: Y-buffer base addr. */\r
8768 //#define Spare_O (0x23CCu) /* Not used */\r
8769 //#define Spare_O (0x23CBu) /* Not used */\r
8770 #define OFS_USBIEPBCTX_1 (0x23CAu) /* Input Endpoint_1: X-byte count */\r
8771 #define OFS_USBIEPBBAX_1 (0x23C9u) /* Input Endpoint_1: X-buffer base addr. */\r
8772 #define OFS_USBIEPCNF_1 (0x23C8u) /* Input Endpoint_1: Configuration */\r
8773 //#define (0x23C7)_O /* */\r
8774 //#define RESERVED_O (0x1C00u) /* */\r
8775 //#define (0x23C0)_O /* */\r
8776 #define OFS_USBOEPSIZXY_7 (0x23BFu) /* Output Endpoint_7: X/Y-buffer size */\r
8777 #define OFS_USBOEPBCTY_7 (0x23BEu) /* Output Endpoint_7: Y-byte count */\r
8778 #define OFS_USBOEPBBAY_7 (0x23BDu) /* Output Endpoint_7: Y-buffer base addr. */\r
8779 //#define Spare_O (0x23BCu) /* Not used */\r
8780 //#define Spare_O (0x23BBu) /* Not used */\r
8781 #define OFS_USBOEPBCTX_7 (0x23BAu) /* Output Endpoint_7: X-byte count */\r
8782 #define OFS_USBOEPBBAX_7 (0x23B9u) /* Output Endpoint_7: X-buffer base addr. */\r
8783 #define OFS_USBOEPCNF_7 (0x23B8u) /* Output Endpoint_7: Configuration */\r
8784 #define OFS_USBOEPSIZXY_6 (0x23B7u) /* Output Endpoint_6: X/Y-buffer size */\r
8785 #define OFS_USBOEPBCTY_6 (0x23B6u) /* Output Endpoint_6: Y-byte count */\r
8786 #define OFS_USBOEPBBAY_6 (0x23B5u) /* Output Endpoint_6: Y-buffer base addr. */\r
8787 //#define Spare_O (0x23B4u) /* Not used */\r
8788 //#define Spare_O (0x23B3u) /* Not used */\r
8789 #define OFS_USBOEPBCTX_6 (0x23B2u) /* Output Endpoint_6: X-byte count */\r
8790 #define OFS_USBOEPBBAX_6 (0x23B1u) /* Output Endpoint_6: X-buffer base addr. */\r
8791 #define OFS_USBOEPCNF_6 (0x23B0u) /* Output Endpoint_6: Configuration */\r
8792 #define OFS_USBOEPSIZXY_5 (0x23AFu) /* Output Endpoint_5: X/Y-buffer size */\r
8793 #define OFS_USBOEPBCTY_5 (0x23AEu) /* Output Endpoint_5: Y-byte count */\r
8794 #define OFS_USBOEPBBAY_5 (0x23ADu) /* Output Endpoint_5: Y-buffer base addr. */\r
8795 //#define Spare_O (0x23ACu) /* Not used */\r
8796 //#define Spare_O (0x23ABu) /* Not used */\r
8797 #define OFS_USBOEPBCTX_5 (0x23AAu) /* Output Endpoint_5: X-byte count */\r
8798 #define OFS_USBOEPBBAX_5 (0x23A9u) /* Output Endpoint_5: X-buffer base addr. */\r
8799 #define OFS_USBOEPCNF_5 (0x23A8u) /* Output Endpoint_5: Configuration */\r
8800 #define OFS_USBOEPSIZXY_4 (0x23A7u) /* Output Endpoint_4: X/Y-buffer size */\r
8801 #define OFS_USBOEPBCTY_4 (0x23A6u) /* Output Endpoint_4: Y-byte count */\r
8802 #define OFS_USBOEPBBAY_4 (0x23A5u) /* Output Endpoint_4: Y-buffer base addr. */\r
8803 //#define Spare_O (0x23A4u) /* Not used */\r
8804 //#define Spare_O (0x23A3u) /* Not used */\r
8805 #define OFS_USBOEPBCTX_4 (0x23A2u) /* Output Endpoint_4: X-byte count */\r
8806 #define OFS_USBOEPBBAX_4 (0x23A1u) /* Output Endpoint_4: X-buffer base addr. */\r
8807 #define OFS_USBOEPCNF_4 (0x23A0u) /* Output Endpoint_4: Configuration */\r
8808 #define OFS_USBOEPSIZXY_3 (0x239Fu) /* Output Endpoint_3: X/Y-buffer size */\r
8809 #define OFS_USBOEPBCTY_3 (0x239Eu) /* Output Endpoint_3: Y-byte count */\r
8810 #define OFS_USBOEPBBAY_3 (0x239Du) /* Output Endpoint_3: Y-buffer base addr. */\r
8811 //#define Spare_O (0x239Cu) /* Not used */\r
8812 //#define Spare_O (0x239Bu) /* Not used */\r
8813 #define OFS_USBOEPBCTX_3 (0x239Au) /* Output Endpoint_3: X-byte count */\r
8814 #define OFS_USBOEPBBAX_3 (0x2399u) /* Output Endpoint_3: X-buffer base addr. */\r
8815 #define OFS_USBOEPCNF_3 (0x2398u) /* Output Endpoint_3: Configuration */\r
8816 #define OFS_USBOEPSIZXY_2 (0x2397u) /* Output Endpoint_2: X/Y-buffer size */\r
8817 #define OFS_USBOEPBCTY_2 (0x2396u) /* Output Endpoint_2: Y-byte count */\r
8818 #define OFS_USBOEPBBAY_2 (0x2395u) /* Output Endpoint_2: Y-buffer base addr. */\r
8819 //#define Spare_O (0x2394u) /* Not used */\r
8820 //#define Spare_O (0x2393u) /* Not used */\r
8821 #define OFS_USBOEPBCTX_2 (0x2392u) /* Output Endpoint_2: X-byte count */\r
8822 #define OFS_USBOEPBBAX_2 (0x2391u) /* Output Endpoint_2: X-buffer base addr. */\r
8823 #define OFS_USBOEPCNF_2 (0x2390u) /* Output Endpoint_2: Configuration */\r
8824 #define OFS_USBOEPSIZXY_1 (0x238Fu) /* Output Endpoint_1: X/Y-buffer size */\r
8825 #define OFS_USBOEPBCTY_1 (0x238Eu) /* Output Endpoint_1: Y-byte count */\r
8826 #define OFS_USBOEPBBAY_1 (0x238Du) /* Output Endpoint_1: Y-buffer base addr. */\r
8827 //#define Spare_O (0x238Cu) /* Not used */\r
8828 //#define Spare_O (0x238Bu) /* Not used */\r
8829 #define OFS_USBOEPBCTX_1 (0x238Au) /* Output Endpoint_1: X-byte count */\r
8830 #define OFS_USBOEPBBAX_1 (0x2389u) /* Output Endpoint_1: X-buffer base addr. */\r
8831 #define OFS_USBOEPCNF_1 (0x2388u) /* Output Endpoint_1: Configuration */\r
8832 #define OFS_USBSUBLK (0x2380u) /* Setup Packet Block */\r
8833 #define OFS_USBIEP0BUF (0x2378u) /* Input endpoint_0 buffer */\r
8834 #define OFS_USBOEP0BUF (0x2370u) /* Output endpoint_0 buffer */\r
8835 #define OFS_USBTOPBUFF (0x236Fu) /* Top of buffer space */\r
8836 // (1904 Bytes) /* Buffer space */\r
8837 #define OFS_USBSTABUFF (0x1C00u) /* Start of buffer space */\r
8838 \r
8839 /* USBIEPCNF_n Control Bits */\r
8840 /* USBOEPCNF_n Control Bits */\r
8841 //#define RESERVED (0x0001u) /* USB - */\r
8842 //#define RESERVED (0x0001u) /* USB - */\r
8843 #define DBUF (0x0010u) /* USB - Double Buffer Enable */\r
8844 //#define RESERVED (0x0040u) /* USB - */\r
8845 \r
8846 /* USBIEPBCNT_n Control Bits */\r
8847 /* USBOEPBCNT_n Control Bits */\r
8848 #define CNT4 (0x0010u) /* USB - Byte Count Bit 3 */\r
8849 #define CNT5 (0x0020u) /* USB - Byte Count Bit 3 */\r
8850 #define CNT6 (0x0040u) /* USB - Byte Count Bit 3 */\r
8851 #endif\r
8852 /************************************************************\r
8853 * USCI Ax\r
8854 ************************************************************/\r
8855 #ifdef __MSP430_HAS_USCI_Ax__ /* Definition to show that Module is available */\r
8856 \r
8857 #define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */\r
8858 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0\r
8859 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1\r
8860 #define OFS_UCAxCTL0 (0x0001u)\r
8861 #define OFS_UCAxCTL1 (0x0000u)\r
8862 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */\r
8863 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */\r
8864 #define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */\r
8865 #define OFS_UCAxBRW_L OFS_UCAxBRW\r
8866 #define OFS_UCAxBRW_H OFS_UCAxBRW+1\r
8867 #define OFS_UCAxBR0 (0x0006u)\r
8868 #define OFS_UCAxBR1 (0x0007u)\r
8869 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */\r
8870 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */\r
8871 #define OFS_UCAxMCTL (0x0008u) /* USCI Ax Modulation Control */\r
8872 #define OFS_UCAxSTAT (0x000Au) /* USCI Ax Status Register */\r
8873 #define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */\r
8874 #define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */\r
8875 #define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */\r
8876 #define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */\r
8877 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL\r
8878 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1\r
8879 #define OFS_UCAxIRTCTL (0x0012u)\r
8880 #define OFS_UCAxIRRCTL (0x0013u)\r
8881 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */\r
8882 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */\r
8883 #define OFS_UCAxICTL (0x001Cu) /* USCI Ax Interrupt Enable Register */\r
8884 #define OFS_UCAxICTL_L OFS_UCAxICTL\r
8885 #define OFS_UCAxICTL_H OFS_UCAxICTL+1\r
8886 #define OFS_UCAxIE (0x001Cu)\r
8887 #define OFS_UCAxIFG (0x001Du)\r
8888 #define UCAxIE UCAxICTL_L /* USCI Ax Interrupt Enable Register */\r
8889 #define UCAxIFG UCAxICTL_H /* USCI Ax Interrupt Flags Register */\r
8890 #define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */\r
8891 \r
8892 #define OFS_UCAxCTLW0__SPI (0x0000u)\r
8893 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI\r
8894 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1\r
8895 #define OFS_UCAxCTL0__SPI (0x0001u)\r
8896 #define OFS_UCAxCTL1__SPI (0x0000u)\r
8897 #define OFS_UCAxBRW__SPI (0x0006u)\r
8898 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI\r
8899 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1\r
8900 #define OFS_UCAxBR0__SPI (0x0006u)\r
8901 #define OFS_UCAxBR1__SPI (0x0007u)\r
8902 #define OFS_UCAxMCTL__SPI (0x0008u)\r
8903 #define OFS_UCAxSTAT__SPI (0x000Au)\r
8904 #define OFS_UCAxRXBUF__SPI (0x000Cu)\r
8905 #define OFS_UCAxTXBUF__SPI (0x000Eu)\r
8906 #define OFS_UCAxICTL__SPI (0x001Cu)\r
8907 #define OFS_UCAxICTL__SPI_L OFS_UCAxICTL__SPI\r
8908 #define OFS_UCAxICTL__SPI_H OFS_UCAxICTL__SPI+1\r
8909 #define OFS_UCAxIE__SPI (0x001Cu)\r
8910 #define OFS_UCAxIFG__SPI (0x001Du)\r
8911 #define OFS_UCAxIV__SPI (0x001Eu)\r
8912 \r
8913 #endif\r
8914 /************************************************************\r
8915 * USCI Bx\r
8916 ************************************************************/\r
8917 #ifdef __MSP430_HAS_USCI_Bx__ /* Definition to show that Module is available */\r
8918 \r
8919 #define OFS_UCBxCTLW0__SPI (0x0000u)\r
8920 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI\r
8921 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1\r
8922 #define OFS_UCBxCTL0__SPI (0x0001u)\r
8923 #define OFS_UCBxCTL1__SPI (0x0000u)\r
8924 #define OFS_UCBxBRW__SPI (0x0006u)\r
8925 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI\r
8926 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1\r
8927 #define OFS_UCBxBR0__SPI (0x0006u)\r
8928 #define OFS_UCBxBR1__SPI (0x0007u)\r
8929 #define OFS_UCBxSTAT__SPI (0x000Au)\r
8930 #define OFS_UCBxRXBUF__SPI (0x000Cu)\r
8931 #define OFS_UCBxTXBUF__SPI (0x000Eu)\r
8932 #define OFS_UCBxICTL__SPI (0x001Cu)\r
8933 #define OFS_UCBxICTL__SPI_L OFS_UCBxICTL__SPI\r
8934 #define OFS_UCBxICTL__SPI_H OFS_UCBxICTL__SPI+1\r
8935 #define OFS_UCBxIE__SPI (0x001Cu)\r
8936 #define OFS_UCBxIFG__SPI (0x001Du)\r
8937 #define OFS_UCBxIV__SPI (0x001Eu)\r
8938 \r
8939 #define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */\r
8940 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0\r
8941 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1\r
8942 #define OFS_UCBxCTL0 (0x0001u)\r
8943 #define OFS_UCBxCTL1 (0x0000u)\r
8944 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */\r
8945 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */\r
8946 #define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */\r
8947 #define OFS_UCBxBRW_L OFS_UCBxBRW\r
8948 #define OFS_UCBxBRW_H OFS_UCBxBRW+1\r
8949 #define OFS_UCBxBR0 (0x0006u)\r
8950 #define OFS_UCBxBR1 (0x0007u)\r
8951 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */\r
8952 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */\r
8953 #define OFS_UCBxSTAT (0x000Au) /* USCI Bx Status Register */\r
8954 #define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */\r
8955 #define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */\r
8956 #define OFS_UCBxI2COA (0x0010u) /* USCI Bx I2C Own Address */\r
8957 #define OFS_UCBxI2COA_L OFS_UCBxI2COA\r
8958 #define OFS_UCBxI2COA_H OFS_UCBxI2COA+1\r
8959 #define OFS_UCBxI2CSA (0x0012u) /* USCI Bx I2C Slave Address */\r
8960 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA\r
8961 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1\r
8962 #define OFS_UCBxICTL (0x001Cu) /* USCI Bx Interrupt Enable Register */\r
8963 #define OFS_UCBxICTL_L OFS_UCBxICTL\r
8964 #define OFS_UCBxICTL_H OFS_UCBxICTL+1\r
8965 #define OFS_UCBxIE (0x001Cu)\r
8966 #define OFS_UCBxIFG (0x001Du)\r
8967 #define UCBxIE UCBxICTL_L /* USCI Bx Interrupt Enable Register */\r
8968 #define UCBxIFG UCBxICTL_H /* USCI Bx Interrupt Flags Register */\r
8969 #define OFS_UCBxIV (0x001Eu) /* USCI Bx Interrupt Vector Register */\r
8970 \r
8971 #endif\r
8972 #if (defined(__MSP430_HAS_USCI_Ax__) || defined(__MSP430_HAS_USCI_Bx__))\r
8973 \r
8974 // UCAxCTL0 UART-Mode Control Bits\r
8975 #define UCPEN (0x80) /* Async. Mode: Parity enable */\r
8976 #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */\r
8977 #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
8978 #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
8979 #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */\r
8980 #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */\r
8981 #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */\r
8982 #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
8983 \r
8984 // UCxxCTL0 SPI-Mode Control Bits\r
8985 #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */\r
8986 #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */\r
8987 #define UCMST (0x08) /* Sync. Mode: Master Select */\r
8988 \r
8989 // UCBxCTL0 I2C-Mode Control Bits\r
8990 #define UCA10 (0x80) /* 10-bit Address Mode */\r
8991 #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */\r
8992 #define UCMM (0x20) /* Multi-Master Environment */\r
8993 //#define res (0x10) /* reserved */\r
8994 #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */\r
8995 #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */\r
8996 #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */\r
8997 #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */\r
8998 \r
8999 // UCAxCTL1 UART-Mode Control Bits\r
9000 #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */\r
9001 #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */\r
9002 #define UCRXEIE (0x20) /* RX Error interrupt enable */\r
9003 #define UCBRKIE (0x10) /* Break interrupt enable */\r
9004 #define UCDORM (0x08) /* Dormant (Sleep) Mode */\r
9005 #define UCTXADDR (0x04) /* Send next Data as Address */\r
9006 #define UCTXBRK (0x02) /* Send next Data as Break */\r
9007 #define UCSWRST (0x01) /* USCI Software Reset */\r
9008 \r
9009 // UCxxCTL1 SPI-Mode Control Bits\r
9010 //#define res (0x20) /* reserved */\r
9011 //#define res (0x10) /* reserved */\r
9012 //#define res (0x08) /* reserved */\r
9013 //#define res (0x04) /* reserved */\r
9014 //#define res (0x02) /* reserved */\r
9015 \r
9016 // UCBxCTL1 I2C-Mode Control Bits\r
9017 //#define res (0x20) /* reserved */\r
9018 #define UCTR (0x10) /* Transmit/Receive Select/Flag */\r
9019 #define UCTXNACK (0x08) /* Transmit NACK */\r
9020 #define UCTXSTP (0x04) /* Transmit STOP */\r
9021 #define UCTXSTT (0x02) /* Transmit START */\r
9022 #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */\r
9023 #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */\r
9024 #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */\r
9025 #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */\r
9026 #define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */\r
9027 #define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */\r
9028 #define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */\r
9029 \r
9030 /* UCAxMCTL Control Bits */\r
9031 #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */\r
9032 #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */\r
9033 #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */\r
9034 #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */\r
9035 #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */\r
9036 #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */\r
9037 #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */\r
9038 #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */\r
9039 \r
9040 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */\r
9041 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */\r
9042 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */\r
9043 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */\r
9044 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */\r
9045 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */\r
9046 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */\r
9047 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */\r
9048 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */\r
9049 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */\r
9050 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */\r
9051 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */\r
9052 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */\r
9053 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */\r
9054 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */\r
9055 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */\r
9056 \r
9057 #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */\r
9058 #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */\r
9059 #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */\r
9060 #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */\r
9061 #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */\r
9062 #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */\r
9063 #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */\r
9064 #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */\r
9065 \r
9066 /* UCAxSTAT Control Bits */\r
9067 #define UCLISTEN (0x80) /* USCI Listen mode */\r
9068 #define UCFE (0x40) /* USCI Frame Error Flag */\r
9069 #define UCOE (0x20) /* USCI Overrun Error Flag */\r
9070 #define UCPE (0x10) /* USCI Parity Error Flag */\r
9071 #define UCBRK (0x08) /* USCI Break received */\r
9072 #define UCRXERR (0x04) /* USCI RX Error Flag */\r
9073 #define UCADDR (0x02) /* USCI Address received Flag */\r
9074 #define UCBUSY (0x01) /* USCI Busy Flag */\r
9075 #define UCIDLE (0x02) /* USCI Idle line detected Flag */\r
9076 \r
9077 /* UCBxSTAT Control Bits */\r
9078 #define UCSCLLOW (0x40) /* SCL low */\r
9079 #define UCGC (0x20) /* General Call address received Flag */\r
9080 #define UCBBUSY (0x10) /* Bus Busy Flag */\r
9081 \r
9082 /* UCAxIRTCTL Control Bits */\r
9083 #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */\r
9084 #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */\r
9085 #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */\r
9086 #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */\r
9087 #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */\r
9088 #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */\r
9089 #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */\r
9090 #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */\r
9091 \r
9092 /* UCAxIRRCTL Control Bits */\r
9093 #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */\r
9094 #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */\r
9095 #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */\r
9096 #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */\r
9097 #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */\r
9098 #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */\r
9099 #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */\r
9100 #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */\r
9101 \r
9102 /* UCAxABCTL Control Bits */\r
9103 //#define res (0x80) /* reserved */\r
9104 //#define res (0x40) /* reserved */\r
9105 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */\r
9106 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */\r
9107 #define UCSTOE (0x08) /* Sync-Field Timeout error */\r
9108 #define UCBTOE (0x04) /* Break Timeout error */\r
9109 //#define res (0x02) /* reserved */\r
9110 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */\r
9111 \r
9112 /* UCBxI2COA Control Bits */\r
9113 #define UCGCEN (0x8000u) /* I2C General Call enable */\r
9114 #define UCOA9 (0x0200u) /* I2C Own Address 9 */\r
9115 #define UCOA8 (0x0100u) /* I2C Own Address 8 */\r
9116 #define UCOA7 (0x0080u) /* I2C Own Address 7 */\r
9117 #define UCOA6 (0x0040u) /* I2C Own Address 6 */\r
9118 #define UCOA5 (0x0020u) /* I2C Own Address 5 */\r
9119 #define UCOA4 (0x0010u) /* I2C Own Address 4 */\r
9120 #define UCOA3 (0x0008u) /* I2C Own Address 3 */\r
9121 #define UCOA2 (0x0004u) /* I2C Own Address 2 */\r
9122 #define UCOA1 (0x0002u) /* I2C Own Address 1 */\r
9123 #define UCOA0 (0x0001u) /* I2C Own Address 0 */\r
9124 \r
9125 /* UCBxI2COA Control Bits */\r
9126 #define UCOA7_L (0x0080u) /* I2C Own Address 7 */\r
9127 #define UCOA6_L (0x0040u) /* I2C Own Address 6 */\r
9128 #define UCOA5_L (0x0020u) /* I2C Own Address 5 */\r
9129 #define UCOA4_L (0x0010u) /* I2C Own Address 4 */\r
9130 #define UCOA3_L (0x0008u) /* I2C Own Address 3 */\r
9131 #define UCOA2_L (0x0004u) /* I2C Own Address 2 */\r
9132 #define UCOA1_L (0x0002u) /* I2C Own Address 1 */\r
9133 #define UCOA0_L (0x0001u) /* I2C Own Address 0 */\r
9134 \r
9135 /* UCBxI2COA Control Bits */\r
9136 #define UCGCEN_H (0x0080u) /* I2C General Call enable */\r
9137 #define UCOA9_H (0x0002u) /* I2C Own Address 9 */\r
9138 #define UCOA8_H (0x0001u) /* I2C Own Address 8 */\r
9139 \r
9140 /* UCBxI2CSA Control Bits */\r
9141 #define UCSA9 (0x0200u) /* I2C Slave Address 9 */\r
9142 #define UCSA8 (0x0100u) /* I2C Slave Address 8 */\r
9143 #define UCSA7 (0x0080u) /* I2C Slave Address 7 */\r
9144 #define UCSA6 (0x0040u) /* I2C Slave Address 6 */\r
9145 #define UCSA5 (0x0020u) /* I2C Slave Address 5 */\r
9146 #define UCSA4 (0x0010u) /* I2C Slave Address 4 */\r
9147 #define UCSA3 (0x0008u) /* I2C Slave Address 3 */\r
9148 #define UCSA2 (0x0004u) /* I2C Slave Address 2 */\r
9149 #define UCSA1 (0x0002u) /* I2C Slave Address 1 */\r
9150 #define UCSA0 (0x0001u) /* I2C Slave Address 0 */\r
9151 \r
9152 /* UCBxI2CSA Control Bits */\r
9153 #define UCSA7_L (0x0080u) /* I2C Slave Address 7 */\r
9154 #define UCSA6_L (0x0040u) /* I2C Slave Address 6 */\r
9155 #define UCSA5_L (0x0020u) /* I2C Slave Address 5 */\r
9156 #define UCSA4_L (0x0010u) /* I2C Slave Address 4 */\r
9157 #define UCSA3_L (0x0008u) /* I2C Slave Address 3 */\r
9158 #define UCSA2_L (0x0004u) /* I2C Slave Address 2 */\r
9159 #define UCSA1_L (0x0002u) /* I2C Slave Address 1 */\r
9160 #define UCSA0_L (0x0001u) /* I2C Slave Address 0 */\r
9161 \r
9162 /* UCBxI2CSA Control Bits */\r
9163 #define UCSA9_H (0x0002u) /* I2C Slave Address 9 */\r
9164 #define UCSA8_H (0x0001u) /* I2C Slave Address 8 */\r
9165 \r
9166 /* UCAxIE Control Bits */\r
9167 #define UCTXIE (0x0002u) /* USCI Transmit Interrupt Enable */\r
9168 #define UCRXIE (0x0001u) /* USCI Receive Interrupt Enable */\r
9169 \r
9170 /* UCAxIE Control Bits */\r
9171 #define UCTXIE_L (0x0002u) /* USCI Transmit Interrupt Enable */\r
9172 #define UCRXIE_L (0x0001u) /* USCI Receive Interrupt Enable */\r
9173 \r
9174 /* UCBxIE Control Bits */\r
9175 #define UCNACKIE (0x0020u) /* NACK Condition interrupt enable */\r
9176 #define UCALIE (0x0010u) /* Arbitration Lost interrupt enable */\r
9177 #define UCSTPIE (0x0008u) /* STOP Condition interrupt enable */\r
9178 #define UCSTTIE (0x0004u) /* START Condition interrupt enable */\r
9179 #define UCTXIE (0x0002u) /* USCI Transmit Interrupt Enable */\r
9180 #define UCRXIE (0x0001u) /* USCI Receive Interrupt Enable */\r
9181 \r
9182 /* UCBxIE Control Bits */\r
9183 #define UCNACKIE_L (0x0020u) /* NACK Condition interrupt enable */\r
9184 #define UCALIE_L (0x0010u) /* Arbitration Lost interrupt enable */\r
9185 #define UCSTPIE_L (0x0008u) /* STOP Condition interrupt enable */\r
9186 #define UCSTTIE_L (0x0004u) /* START Condition interrupt enable */\r
9187 #define UCTXIE_L (0x0002u) /* USCI Transmit Interrupt Enable */\r
9188 #define UCRXIE_L (0x0001u) /* USCI Receive Interrupt Enable */\r
9189 \r
9190 /* UCAxIFG Control Bits */\r
9191 #define UCTXIFG (0x0002u) /* USCI Transmit Interrupt Flag */\r
9192 #define UCRXIFG (0x0001u) /* USCI Receive Interrupt Flag */\r
9193 \r
9194 /* UCAxIFG Control Bits */\r
9195 #define UCTXIFG_L (0x0002u) /* USCI Transmit Interrupt Flag */\r
9196 #define UCRXIFG_L (0x0001u) /* USCI Receive Interrupt Flag */\r
9197 \r
9198 /* UCBxIFG Control Bits */\r
9199 #define UCNACKIFG (0x0020u) /* NAK Condition interrupt Flag */\r
9200 #define UCALIFG (0x0010u) /* Arbitration Lost interrupt Flag */\r
9201 #define UCSTPIFG (0x0008u) /* STOP Condition interrupt Flag */\r
9202 #define UCSTTIFG (0x0004u) /* START Condition interrupt Flag */\r
9203 #define UCTXIFG (0x0002u) /* USCI Transmit Interrupt Flag */\r
9204 #define UCRXIFG (0x0001u) /* USCI Receive Interrupt Flag */\r
9205 \r
9206 /* UCBxIFG Control Bits */\r
9207 #define UCNACKIFG_L (0x0020u) /* NAK Condition interrupt Flag */\r
9208 #define UCALIFG_L (0x0010u) /* Arbitration Lost interrupt Flag */\r
9209 #define UCSTPIFG_L (0x0008u) /* STOP Condition interrupt Flag */\r
9210 #define UCSTTIFG_L (0x0004u) /* START Condition interrupt Flag */\r
9211 #define UCTXIFG_L (0x0002u) /* USCI Transmit Interrupt Flag */\r
9212 #define UCRXIFG_L (0x0001u) /* USCI Receive Interrupt Flag */\r
9213 \r
9214 /* USCI Definitions */\r
9215 #define USCI_NONE (0x0000u) /* No Interrupt pending */\r
9216 #define USCI_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
9217 #define USCI_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
9218 #define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */\r
9219 #define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */\r
9220 #define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/\r
9221 #define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/\r
9222 #define USCI_I2C_UCRXIFG (0x000Au) /* USCI I2C Mode: UCRXIFG */\r
9223 #define USCI_I2C_UCTXIFG (0x000Cu) /* USCI I2C Mode: UCTXIFG */\r
9224 \r
9225 #endif\r
9226 /************************************************************\r
9227 * USCI Ax\r
9228 ************************************************************/\r
9229 #ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */\r
9230 \r
9231 #define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */\r
9232 #define OFS_UCAxCTLW0_L OFS_UCAxCTLW0\r
9233 #define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1\r
9234 #define OFS_UCAxCTL0 (0x0001u)\r
9235 #define OFS_UCAxCTL1 (0x0000u)\r
9236 #define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */\r
9237 #define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */\r
9238 #define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */\r
9239 #define OFS_UCAxCTLW1_L OFS_UCAxCTLW1\r
9240 #define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1\r
9241 #define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */\r
9242 #define OFS_UCAxBRW_L OFS_UCAxBRW\r
9243 #define OFS_UCAxBRW_H OFS_UCAxBRW+1\r
9244 #define OFS_UCAxBR0 (0x0006u)\r
9245 #define OFS_UCAxBR1 (0x0007u)\r
9246 #define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */\r
9247 #define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */\r
9248 #define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */\r
9249 #define OFS_UCAxMCTLW_L OFS_UCAxMCTLW\r
9250 #define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1\r
9251 #define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */\r
9252 #define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */\r
9253 #define OFS_UCAxRXBUF_L OFS_UCAxRXBUF\r
9254 #define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1\r
9255 #define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */\r
9256 #define OFS_UCAxTXBUF_L OFS_UCAxTXBUF\r
9257 #define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1\r
9258 #define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */\r
9259 #define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */\r
9260 #define OFS_UCAxIRCTL_L OFS_UCAxIRCTL\r
9261 #define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1\r
9262 #define OFS_UCAxIRTCTL (0x0012u)\r
9263 #define OFS_UCAxIRRCTL (0x0013u)\r
9264 #define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */\r
9265 #define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */\r
9266 #define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */\r
9267 #define OFS_UCAxIE_L OFS_UCAxIE\r
9268 #define OFS_UCAxIE_H OFS_UCAxIE+1\r
9269 #define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */\r
9270 #define OFS_UCAxIFG_L OFS_UCAxIFG\r
9271 #define OFS_UCAxIFG_H OFS_UCAxIFG+1\r
9272 #define OFS_UCAxIE__UART (0x001Au)\r
9273 #define OFS_UCAxIE__UART_L OFS_UCAxIE__UART\r
9274 #define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1\r
9275 #define OFS_UCAxIFG__UART (0x001Cu)\r
9276 #define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART\r
9277 #define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1\r
9278 #define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */\r
9279 \r
9280 #define OFS_UCAxCTLW0__SPI (0x0000u)\r
9281 #define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI\r
9282 #define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1\r
9283 #define OFS_UCAxCTL0__SPI (0x0001u)\r
9284 #define OFS_UCAxCTL1__SPI (0x0000u)\r
9285 #define OFS_UCAxBRW__SPI (0x0006u)\r
9286 #define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI\r
9287 #define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1\r
9288 #define OFS_UCAxBR0__SPI (0x0006u)\r
9289 #define OFS_UCAxBR1__SPI (0x0007u)\r
9290 #define OFS_UCAxSTATW__SPI (0x000Au)\r
9291 #define OFS_UCAxRXBUF__SPI (0x000Cu)\r
9292 #define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI\r
9293 #define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1\r
9294 #define OFS_UCAxTXBUF__SPI (0x000Eu)\r
9295 #define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI\r
9296 #define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1\r
9297 #define OFS_UCAxIE__SPI (0x001Au)\r
9298 #define OFS_UCAxIFG__SPI (0x001Cu)\r
9299 #define OFS_UCAxIV__SPI (0x001Eu)\r
9300 \r
9301 #endif\r
9302 /************************************************************\r
9303 * USCI Bx\r
9304 ************************************************************/\r
9305 #ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */\r
9306 \r
9307 #define OFS_UCBxCTLW0__SPI (0x0000u)\r
9308 #define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI\r
9309 #define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1\r
9310 #define OFS_UCBxCTL0__SPI (0x0001u)\r
9311 #define OFS_UCBxCTL1__SPI (0x0000u)\r
9312 #define OFS_UCBxBRW__SPI (0x0006u)\r
9313 #define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI\r
9314 #define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1\r
9315 #define OFS_UCBxBR0__SPI (0x0006u)\r
9316 #define OFS_UCBxBR1__SPI (0x0007u)\r
9317 #define OFS_UCBxSTATW__SPI (0x0008u)\r
9318 #define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI\r
9319 #define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1\r
9320 #define OFS_UCBxRXBUF__SPI (0x000Cu)\r
9321 #define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI\r
9322 #define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1\r
9323 #define OFS_UCBxTXBUF__SPI (0x000Eu)\r
9324 #define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI\r
9325 #define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1\r
9326 #define OFS_UCBxIE__SPI (0x002Au)\r
9327 #define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI\r
9328 #define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1\r
9329 #define OFS_UCBxIFG__SPI (0x002Cu)\r
9330 #define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI\r
9331 #define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1\r
9332 #define OFS_UCBxIV__SPI (0x002Eu)\r
9333 \r
9334 #define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */\r
9335 #define OFS_UCBxCTLW0_L OFS_UCBxCTLW0\r
9336 #define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1\r
9337 #define OFS_UCBxCTL0 (0x0001u)\r
9338 #define OFS_UCBxCTL1 (0x0000u)\r
9339 #define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */\r
9340 #define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */\r
9341 #define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */\r
9342 #define OFS_UCBxCTLW1_L OFS_UCBxCTLW1\r
9343 #define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1\r
9344 #define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */\r
9345 #define OFS_UCBxBRW_L OFS_UCBxBRW\r
9346 #define OFS_UCBxBRW_H OFS_UCBxBRW+1\r
9347 #define OFS_UCBxBR0 (0x0006u)\r
9348 #define OFS_UCBxBR1 (0x0007u)\r
9349 #define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */\r
9350 #define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */\r
9351 #define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */\r
9352 #define OFS_UCBxSTATW_L OFS_UCBxSTATW\r
9353 #define OFS_UCBxSTATW_H OFS_UCBxSTATW+1\r
9354 #define OFS_UCBxSTATW__I2C (0x0008u)\r
9355 #define OFS_UCBxSTAT__I2C (0x0008u)\r
9356 #define OFS_UCBxBCNT__I2C (0x0009u)\r
9357 #define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */\r
9358 #define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */\r
9359 #define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */\r
9360 #define OFS_UCBxTBCNT_L OFS_UCBxTBCNT\r
9361 #define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1\r
9362 #define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */\r
9363 #define OFS_UCBxRXBUF_L OFS_UCBxRXBUF\r
9364 #define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1\r
9365 #define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */\r
9366 #define OFS_UCBxTXBUF_L OFS_UCBxTXBUF\r
9367 #define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1\r
9368 #define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */\r
9369 #define OFS_UCBxI2COA0_L OFS_UCBxI2COA0\r
9370 #define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1\r
9371 #define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */\r
9372 #define OFS_UCBxI2COA1_L OFS_UCBxI2COA1\r
9373 #define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1\r
9374 #define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */\r
9375 #define OFS_UCBxI2COA2_L OFS_UCBxI2COA2\r
9376 #define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1\r
9377 #define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */\r
9378 #define OFS_UCBxI2COA3_L OFS_UCBxI2COA3\r
9379 #define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1\r
9380 #define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */\r
9381 #define OFS_UCBxADDRX_L OFS_UCBxADDRX\r
9382 #define OFS_UCBxADDRX_H OFS_UCBxADDRX+1\r
9383 #define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */\r
9384 #define OFS_UCBxADDMASK_L OFS_UCBxADDMASK\r
9385 #define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1\r
9386 #define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */\r
9387 #define OFS_UCBxI2CSA_L OFS_UCBxI2CSA\r
9388 #define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1\r
9389 #define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */\r
9390 #define OFS_UCBxIE_L OFS_UCBxIE\r
9391 #define OFS_UCBxIE_H OFS_UCBxIE+1\r
9392 #define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */\r
9393 #define OFS_UCBxIFG_L OFS_UCBxIFG\r
9394 #define OFS_UCBxIFG_H OFS_UCBxIFG+1\r
9395 #define OFS_UCBxIE__I2C (0x002Au)\r
9396 #define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C\r
9397 #define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1\r
9398 #define OFS_UCBxIFG__I2C (0x002Cu)\r
9399 #define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C\r
9400 #define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1\r
9401 #define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */\r
9402 \r
9403 #endif\r
9404 #if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))\r
9405 \r
9406 // UCAxCTLW0 UART-Mode Control Bits\r
9407 #define UCPEN (0x8000u) /* Async. Mode: Parity enable */\r
9408 #define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */\r
9409 #define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
9410 #define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
9411 #define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */\r
9412 #define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */\r
9413 #define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */\r
9414 #define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
9415 #define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */\r
9416 #define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */\r
9417 #define UCRXEIE (0x0020u) /* RX Error interrupt enable */\r
9418 #define UCBRKIE (0x0010u) /* Break interrupt enable */\r
9419 #define UCDORM (0x0008u) /* Dormant (Sleep) Mode */\r
9420 #define UCTXADDR (0x0004u) /* Send next Data as Address */\r
9421 #define UCTXBRK (0x0002u) /* Send next Data as Break */\r
9422 #define UCSWRST (0x0001u) /* USCI Software Reset */\r
9423 \r
9424 // UCAxCTLW0 UART-Mode Control Bits\r
9425 #define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */\r
9426 #define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */\r
9427 #define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */\r
9428 #define UCBRKIE_L (0x0010u) /* Break interrupt enable */\r
9429 #define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */\r
9430 #define UCTXADDR_L (0x0004u) /* Send next Data as Address */\r
9431 #define UCTXBRK_L (0x0002u) /* Send next Data as Break */\r
9432 #define UCSWRST_L (0x0001u) /* USCI Software Reset */\r
9433 \r
9434 // UCAxCTLW0 UART-Mode Control Bits\r
9435 #define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */\r
9436 #define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */\r
9437 #define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
9438 #define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
9439 #define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */\r
9440 #define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */\r
9441 #define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */\r
9442 #define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
9443 \r
9444 // UCxxCTLW0 SPI-Mode Control Bits\r
9445 #define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */\r
9446 #define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */\r
9447 #define UCMST (0x0800u) /* Sync. Mode: Master Select */\r
9448 //#define res (0x0020u) /* reserved */\r
9449 //#define res (0x0010u) /* reserved */\r
9450 //#define res (0x0008u) /* reserved */\r
9451 //#define res (0x0004u) /* reserved */\r
9452 #define UCSTEM (0x0002u) /* USCI STE Mode */\r
9453 \r
9454 // UCBxCTLW0 I2C-Mode Control Bits\r
9455 #define UCA10 (0x8000u) /* 10-bit Address Mode */\r
9456 #define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */\r
9457 #define UCMM (0x2000u) /* Multi-Master Environment */\r
9458 //#define res (0x1000u) /* reserved */\r
9459 //#define res (0x0100u) /* reserved */\r
9460 #define UCTXACK (0x0020u) /* Transmit ACK */\r
9461 #define UCTR (0x0010u) /* Transmit/Receive Select/Flag */\r
9462 #define UCTXNACK (0x0008u) /* Transmit NACK */\r
9463 #define UCTXSTP (0x0004u) /* Transmit STOP */\r
9464 #define UCTXSTT (0x0002u) /* Transmit START */\r
9465 \r
9466 // UCBxCTLW0 I2C-Mode Control Bits\r
9467 //#define res (0x1000u) /* reserved */\r
9468 //#define res (0x0100u) /* reserved */\r
9469 #define UCTXACK_L (0x0020u) /* Transmit ACK */\r
9470 #define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */\r
9471 #define UCTXNACK_L (0x0008u) /* Transmit NACK */\r
9472 #define UCTXSTP_L (0x0004u) /* Transmit STOP */\r
9473 #define UCTXSTT_L (0x0002u) /* Transmit START */\r
9474 \r
9475 // UCBxCTLW0 I2C-Mode Control Bits\r
9476 #define UCA10_H (0x0080u) /* 10-bit Address Mode */\r
9477 #define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */\r
9478 #define UCMM_H (0x0020u) /* Multi-Master Environment */\r
9479 //#define res (0x1000u) /* reserved */\r
9480 //#define res (0x0100u) /* reserved */\r
9481 \r
9482 #define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */\r
9483 #define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */\r
9484 #define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */\r
9485 #define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */\r
9486 \r
9487 #define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */\r
9488 #define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */\r
9489 #define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */\r
9490 #define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */\r
9491 #define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */\r
9492 #define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */\r
9493 #define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */\r
9494 \r
9495 // UCAxCTLW1 UART-Mode Control Bits\r
9496 #define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */\r
9497 #define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */\r
9498 \r
9499 // UCAxCTLW1 UART-Mode Control Bits\r
9500 #define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */\r
9501 #define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */\r
9502 \r
9503 // UCBxCTLW1 I2C-Mode Control Bits\r
9504 #define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */\r
9505 #define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */\r
9506 #define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */\r
9507 #define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */\r
9508 #define UCSWACK (0x0010u) /* USCI Software controlled ACK */\r
9509 #define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */\r
9510 #define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */\r
9511 #define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */\r
9512 #define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */\r
9513 \r
9514 // UCBxCTLW1 I2C-Mode Control Bits\r
9515 #define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */\r
9516 #define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */\r
9517 #define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */\r
9518 #define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */\r
9519 #define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */\r
9520 #define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */\r
9521 #define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */\r
9522 #define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */\r
9523 \r
9524 // UCBxCTLW1 I2C-Mode Control Bits\r
9525 #define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */\r
9526 \r
9527 #define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */\r
9528 #define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */\r
9529 #define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */\r
9530 #define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */\r
9531 \r
9532 #define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */\r
9533 #define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */\r
9534 #define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */\r
9535 #define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */\r
9536 \r
9537 #define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */\r
9538 #define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */\r
9539 #define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */\r
9540 #define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */\r
9541 \r
9542 /* UCAxMCTLW Control Bits */\r
9543 #define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */\r
9544 #define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */\r
9545 #define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */\r
9546 #define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */\r
9547 #define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */\r
9548 #define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */\r
9549 #define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */\r
9550 #define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */\r
9551 #define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */\r
9552 #define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */\r
9553 #define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */\r
9554 #define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */\r
9555 #define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */\r
9556 \r
9557 /* UCAxMCTLW Control Bits */\r
9558 #define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */\r
9559 #define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */\r
9560 #define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */\r
9561 #define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */\r
9562 #define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */\r
9563 \r
9564 /* UCAxMCTLW Control Bits */\r
9565 #define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */\r
9566 #define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */\r
9567 #define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */\r
9568 #define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */\r
9569 #define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */\r
9570 #define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */\r
9571 #define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */\r
9572 #define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */\r
9573 \r
9574 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */\r
9575 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */\r
9576 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */\r
9577 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */\r
9578 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */\r
9579 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */\r
9580 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */\r
9581 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */\r
9582 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */\r
9583 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */\r
9584 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */\r
9585 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */\r
9586 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */\r
9587 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */\r
9588 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */\r
9589 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */\r
9590 \r
9591 /* UCAxSTATW Control Bits */\r
9592 #define UCLISTEN (0x0080u) /* USCI Listen mode */\r
9593 #define UCFE (0x0040u) /* USCI Frame Error Flag */\r
9594 #define UCOE (0x0020u) /* USCI Overrun Error Flag */\r
9595 #define UCPE (0x0010u) /* USCI Parity Error Flag */\r
9596 #define UCBRK (0x0008u) /* USCI Break received */\r
9597 #define UCRXERR (0x0004u) /* USCI RX Error Flag */\r
9598 #define UCADDR (0x0002u) /* USCI Address received Flag */\r
9599 #define UCBUSY (0x0001u) /* USCI Busy Flag */\r
9600 #define UCIDLE (0x0002u) /* USCI Idle line detected Flag */\r
9601 \r
9602 /* UCBxSTATW I2C Control Bits */\r
9603 #define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */\r
9604 #define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */\r
9605 #define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */\r
9606 #define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */\r
9607 #define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */\r
9608 #define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */\r
9609 #define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */\r
9610 #define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */\r
9611 #define UCSCLLOW (0x0040u) /* SCL low */\r
9612 #define UCGC (0x0020u) /* General Call address received Flag */\r
9613 #define UCBBUSY (0x0010u) /* Bus Busy Flag */\r
9614 \r
9615 /* UCBxTBCNT I2C Control Bits */\r
9616 #define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */\r
9617 #define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */\r
9618 #define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */\r
9619 #define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */\r
9620 #define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */\r
9621 #define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */\r
9622 #define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */\r
9623 #define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */\r
9624 \r
9625 /* UCAxIRCTL Control Bits */\r
9626 #define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */\r
9627 #define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */\r
9628 #define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */\r
9629 #define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */\r
9630 #define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */\r
9631 #define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */\r
9632 #define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */\r
9633 #define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */\r
9634 #define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */\r
9635 #define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */\r
9636 #define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */\r
9637 #define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */\r
9638 #define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */\r
9639 #define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */\r
9640 #define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */\r
9641 #define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */\r
9642 \r
9643 /* UCAxIRCTL Control Bits */\r
9644 #define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */\r
9645 #define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */\r
9646 #define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */\r
9647 #define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */\r
9648 #define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */\r
9649 #define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */\r
9650 #define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */\r
9651 #define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */\r
9652 \r
9653 /* UCAxIRCTL Control Bits */\r
9654 #define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */\r
9655 #define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */\r
9656 #define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */\r
9657 #define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */\r
9658 #define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */\r
9659 #define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */\r
9660 #define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */\r
9661 #define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */\r
9662 \r
9663 /* UCAxABCTL Control Bits */\r
9664 //#define res (0x80) /* reserved */\r
9665 //#define res (0x40) /* reserved */\r
9666 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */\r
9667 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */\r
9668 #define UCSTOE (0x08) /* Sync-Field Timeout error */\r
9669 #define UCBTOE (0x04) /* Break Timeout error */\r
9670 //#define res (0x02) /* reserved */\r
9671 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */\r
9672 \r
9673 /* UCBxI2COA0 Control Bits */\r
9674 #define UCGCEN (0x8000u) /* I2C General Call enable */\r
9675 #define UCOAEN (0x0400u) /* I2C Own Address enable */\r
9676 #define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */\r
9677 #define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */\r
9678 #define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */\r
9679 #define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */\r
9680 #define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */\r
9681 #define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */\r
9682 #define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */\r
9683 #define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */\r
9684 #define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */\r
9685 #define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */\r
9686 \r
9687 /* UCBxI2COA0 Control Bits */\r
9688 #define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */\r
9689 #define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */\r
9690 #define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */\r
9691 #define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */\r
9692 #define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */\r
9693 #define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */\r
9694 #define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */\r
9695 #define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */\r
9696 \r
9697 /* UCBxI2COA0 Control Bits */\r
9698 #define UCGCEN_H (0x0080u) /* I2C General Call enable */\r
9699 #define UCOAEN_H (0x0004u) /* I2C Own Address enable */\r
9700 #define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */\r
9701 #define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */\r
9702 \r
9703 /* UCBxI2COAx Control Bits */\r
9704 #define UCOAEN (0x0400u) /* I2C Own Address enable */\r
9705 #define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */\r
9706 #define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */\r
9707 #define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */\r
9708 #define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */\r
9709 #define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */\r
9710 #define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */\r
9711 #define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */\r
9712 #define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */\r
9713 #define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */\r
9714 #define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */\r
9715 \r
9716 /* UCBxI2COAx Control Bits */\r
9717 #define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */\r
9718 #define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */\r
9719 #define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */\r
9720 #define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */\r
9721 #define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */\r
9722 #define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */\r
9723 #define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */\r
9724 #define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */\r
9725 \r
9726 /* UCBxI2COAx Control Bits */\r
9727 #define UCOAEN_H (0x0004u) /* I2C Own Address enable */\r
9728 #define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */\r
9729 #define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */\r
9730 \r
9731 /* UCBxADDRX Control Bits */\r
9732 #define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */\r
9733 #define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */\r
9734 #define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */\r
9735 #define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */\r
9736 #define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */\r
9737 #define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */\r
9738 #define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */\r
9739 #define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */\r
9740 #define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */\r
9741 #define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */\r
9742 \r
9743 /* UCBxADDRX Control Bits */\r
9744 #define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */\r
9745 #define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */\r
9746 #define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */\r
9747 #define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */\r
9748 #define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */\r
9749 #define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */\r
9750 #define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */\r
9751 #define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */\r
9752 \r
9753 /* UCBxADDRX Control Bits */\r
9754 #define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */\r
9755 #define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */\r
9756 \r
9757 /* UCBxADDMASK Control Bits */\r
9758 #define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */\r
9759 #define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */\r
9760 #define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */\r
9761 #define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */\r
9762 #define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */\r
9763 #define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */\r
9764 #define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */\r
9765 #define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */\r
9766 #define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */\r
9767 #define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */\r
9768 \r
9769 /* UCBxADDMASK Control Bits */\r
9770 #define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */\r
9771 #define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */\r
9772 #define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */\r
9773 #define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */\r
9774 #define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */\r
9775 #define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */\r
9776 #define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */\r
9777 #define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */\r
9778 \r
9779 /* UCBxADDMASK Control Bits */\r
9780 #define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */\r
9781 #define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */\r
9782 \r
9783 /* UCBxI2CSA Control Bits */\r
9784 #define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */\r
9785 #define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */\r
9786 #define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */\r
9787 #define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */\r
9788 #define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */\r
9789 #define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */\r
9790 #define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */\r
9791 #define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */\r
9792 #define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */\r
9793 #define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */\r
9794 \r
9795 /* UCBxI2CSA Control Bits */\r
9796 #define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */\r
9797 #define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */\r
9798 #define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */\r
9799 #define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */\r
9800 #define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */\r
9801 #define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */\r
9802 #define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */\r
9803 #define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */\r
9804 \r
9805 /* UCBxI2CSA Control Bits */\r
9806 #define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */\r
9807 #define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */\r
9808 \r
9809 /* UCAxIE UART Control Bits */\r
9810 #define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */\r
9811 #define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */\r
9812 #define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */\r
9813 #define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */\r
9814 \r
9815 /* UCAxIE/UCBxIE SPI Control Bits */\r
9816 \r
9817 /* UCBxIE I2C Control Bits */\r
9818 #define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */\r
9819 #define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */\r
9820 #define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */\r
9821 #define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */\r
9822 #define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */\r
9823 #define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */\r
9824 #define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */\r
9825 #define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */\r
9826 #define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */\r
9827 #define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */\r
9828 #define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */\r
9829 #define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */\r
9830 #define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */\r
9831 #define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */\r
9832 #define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */\r
9833 \r
9834 /* UCAxIFG UART Control Bits */\r
9835 #define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */\r
9836 #define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */\r
9837 #define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */\r
9838 #define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */\r
9839 \r
9840 /* UCAxIFG/UCBxIFG SPI Control Bits */\r
9841 #define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */\r
9842 #define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */\r
9843 \r
9844 /* UCBxIFG Control Bits */\r
9845 #define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */\r
9846 #define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */\r
9847 #define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */\r
9848 #define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */\r
9849 #define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */\r
9850 #define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */\r
9851 #define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */\r
9852 #define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */\r
9853 #define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */\r
9854 #define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */\r
9855 #define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */\r
9856 #define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */\r
9857 #define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */\r
9858 #define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */\r
9859 #define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */\r
9860 \r
9861 /* USCI UART Definitions */\r
9862 #define USCI_NONE (0x0000u) /* No Interrupt pending */\r
9863 #define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
9864 #define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
9865 #define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */\r
9866 #define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */\r
9867 \r
9868 /* USCI SPI Definitions */\r
9869 #define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
9870 #define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
9871 \r
9872 /* USCI I2C Definitions */\r
9873 #define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */\r
9874 #define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */\r
9875 #define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/\r
9876 #define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/\r
9877 #define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */\r
9878 #define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */\r
9879 #define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */\r
9880 #define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */\r
9881 #define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */\r
9882 #define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */\r
9883 #define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */\r
9884 #define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */\r
9885 #define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */\r
9886 #define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */\r
9887 #define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */\r
9888 \r
9889 #endif\r
9890 /************************************************************\r
9891 * WATCHDOG TIMER A\r
9892 ************************************************************/\r
9893 #ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */\r
9894 \r
9895 #define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */\r
9896 #define OFS_WDTCTL_L OFS_WDTCTL\r
9897 #define OFS_WDTCTL_H OFS_WDTCTL+1\r
9898 /* The bit names have been prefixed with "WDT" */\r
9899 /* WDTCTL Control Bits */\r
9900 #define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */\r
9901 #define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */\r
9902 #define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */\r
9903 #define WDTCNTCL (0x0008u) /* WDT - Timer Clear */\r
9904 #define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */\r
9905 #define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */\r
9906 #define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */\r
9907 #define WDTHOLD (0x0080u) /* WDT - Timer hold */\r
9908 \r
9909 /* WDTCTL Control Bits */\r
9910 #define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */\r
9911 #define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */\r
9912 #define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */\r
9913 #define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */\r
9914 #define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */\r
9915 #define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */\r
9916 #define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */\r
9917 #define WDTHOLD_L (0x0080u) /* WDT - Timer hold */\r
9918 \r
9919 #define WDTPW (0x5A00u)\r
9920 \r
9921 #define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
9922 #define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
9923 #define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
9924 #define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
9925 #define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
9926 #define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
9927 #define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
9928 #define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
9929 #define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
9930 #define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
9931 #define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
9932 #define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
9933 #define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
9934 #define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
9935 #define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
9936 #define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
9937 \r
9938 #define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
9939 #define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
9940 #define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
9941 #define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */\r
9942 #define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
9943 #define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
9944 #define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
9945 \r
9946 /* WDT-interval times [1ms] coded with Bits 0-2 */\r
9947 /* WDT is clocked by fSMCLK (assumed 1MHz) */\r
9948 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
9949 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
9950 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
9951 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
9952 /* WDT is clocked by fACLK (assumed 32KHz) */\r
9953 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */\r
9954 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */\r
9955 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */\r
9956 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */\r
9957 /* Watchdog mode -> reset after expired time */\r
9958 /* WDT is clocked by fSMCLK (assumed 1MHz) */\r
9959 #define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
9960 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
9961 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
9962 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
9963 /* WDT is clocked by fACLK (assumed 32KHz) */\r
9964 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */\r
9965 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */\r
9966 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */\r
9967 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */\r
9968 \r
9969 #endif\r
9970 \r
9971 /************************************************************\r
9972 * TLV Descriptors\r
9973 ************************************************************/\r
9974 #define __MSP430_HAS_TLV__ /* Definition to show that Module is available */\r
9975 #define TLV_BASE __MSP430_BASEADDRESS_TLV__\r
9976 \r
9977 #define TLV_START (0x1A08u) /* Start Address of the TLV structure */\r
9978 #define TLV_END (0x1AFFu) /* End Address of the TLV structure */\r
9979 \r
9980 #define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */\r
9981 #define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */\r
9982 #define TLV_Reserved3 (0x03) /* Future usage */\r
9983 #define TLV_Reserved4 (0x04) /* Future usage */\r
9984 #define TLV_BLANK (0x05) /* Blank descriptor */\r
9985 #define TLV_Reserved6 (0x06) /* Future usage */\r
9986 #define TLV_Reserved7 (0x07) /* Serial Number */\r
9987 #define TLV_DIERECORD (0x08) /* Die Record */\r
9988 #define TLV_ADCCAL (0x11) /* ADC12 calibration */\r
9989 #define TLV_ADC12CAL (0x11) /* ADC12 calibration */\r
9990 #define TLV_REFCAL (0x12) /* REF calibration */\r
9991 #define TLV_ADC10CAL (0x13) /* ADC10 calibration */\r
9992 #define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */\r
9993 #define TLV_TAGEXT (0xFE) /* Tag extender */\r
9994 #define TLV_TAGEND (0xFF) /* Tag End of Table */\r
9995 \r
9996 /************************************************************\r
9997 * Interrupt Vectors (offset from 0xFF80)\r
9998 ************************************************************/\r
9999 \r
10000 \r
10001 /************************************************************\r
10002 * End of Modules\r
10003 ************************************************************/\r
10004 #pragma language=default\r
10005 \r
10006 #endif /* #ifndef __msp430F5XX_F6XXGENERIC */\r
10007 \r